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chisel-verilog-pairs

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Generate the Verilog code corresponding to this FIRRTL code module PE_510 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_254 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_510( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_254 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_18 : input clock : Clock input reset : Reset output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}}, resp : { `3` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `2` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `1` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, `0` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<14> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_lo = cat(_decoded_orMatrixOutputs_T, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node decoded_invMatrixOutputs_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 1, 0) node _decoded_T_1 = bits(_decoded_T, 0, 0) node _decoded_T_2 = bits(_decoded_T, 1, 1) node _decoded_T_3 = cat(_decoded_T_1, _decoded_T_2) node _decoded_T_4 = bits(decoded_plaOutput, 3, 2) node _decoded_T_5 = bits(_decoded_T_4, 0, 0) node _decoded_T_6 = bits(_decoded_T_4, 1, 1) node _decoded_T_7 = cat(_decoded_T_5, _decoded_T_6) node decoded = cat(_decoded_T_3, _decoded_T_7) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T connect io.resp.`0`.vc_sel.`2`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<14> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_invInputs_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_plaInput_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_6_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_8_3) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_4) node _decoded_orMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_3_2) node _decoded_orMatrixOutputs_T_2 = orr(_decoded_orMatrixOutputs_T_1) node _decoded_orMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_4 = orr(_decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_lo_1 = cat(_decoded_orMatrixOutputs_T_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_1 = cat(_decoded_orMatrixOutputs_T_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs_1, 3, 3) node decoded_invMatrixOutputs_lo_1 = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_1 = cat(_decoded_invMatrixOutputs_T_7, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_8 = bits(decoded_plaOutput_1, 1, 0) node _decoded_T_9 = bits(_decoded_T_8, 0, 0) node _decoded_T_10 = bits(_decoded_T_8, 1, 1) node _decoded_T_11 = cat(_decoded_T_9, _decoded_T_10) node _decoded_T_12 = bits(decoded_plaOutput_1, 3, 2) node _decoded_T_13 = bits(_decoded_T_12, 0, 0) node _decoded_T_14 = bits(_decoded_T_12, 1, 1) node _decoded_T_15 = cat(_decoded_T_13, _decoded_T_14) node decoded_1 = cat(_decoded_T_11, _decoded_T_15) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T connect io.resp.`1`.vc_sel.`2`[0], UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<14> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<4> node decoded_orMatrixOutputs_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_2, 3, 3) node decoded_invMatrixOutputs_lo_2 = cat(_decoded_invMatrixOutputs_T_9, _decoded_invMatrixOutputs_T_8) node decoded_invMatrixOutputs_hi_2 = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_16 = bits(decoded_plaOutput_2, 1, 0) node _decoded_T_17 = bits(_decoded_T_16, 0, 0) node _decoded_T_18 = bits(_decoded_T_16, 1, 1) node _decoded_T_19 = cat(_decoded_T_17, _decoded_T_18) node _decoded_T_20 = bits(decoded_plaOutput_2, 3, 2) node _decoded_T_21 = bits(_decoded_T_20, 0, 0) node _decoded_T_22 = bits(_decoded_T_20, 1, 1) node _decoded_T_23 = cat(_decoded_T_21, _decoded_T_22) node decoded_2 = cat(_decoded_T_19, _decoded_T_23) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T connect io.resp.`2`.vc_sel.`2`[0], UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h1) node addr_lo_3 = cat(io.req.`3`.bits.flow.egress_node, io.req.`3`.bits.flow.egress_node_id) node addr_hi_hi_3 = cat(io.req.`3`.bits.flow.vnet_id, io.req.`3`.bits.flow.ingress_node) node addr_hi_3 = cat(addr_hi_hi_3, io.req.`3`.bits.flow.ingress_node_id) node _addr_T_3 = cat(addr_hi_3, addr_lo_3) node addr_3 = cat(io.req.`3`.bits.src_virt_id, _addr_T_3) wire decoded_plaInput_3 : UInt<14> node decoded_invInputs_3 = not(decoded_plaInput_3) wire decoded_plaOutput_3 : UInt<4> node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_invInputs_3, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_plaInput_3, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput_3, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs_3, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_3, 13, 13) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput_3, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_plaInput_3, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput_3, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs_3, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_invInputs_3, 13, 13) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_3, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_3, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_plaInput_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_plaInput_3, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_3, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs_3, 13, 13) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_3, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_3, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_plaInput_3, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_3, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_3, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_3, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput_3, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_3, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_3, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_3, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs_3, 13, 13) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_8) node _decoded_orMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_1_2_1, decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_6 = orr(_decoded_orMatrixOutputs_T_5) node _decoded_orMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_8 = orr(_decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_lo_3 = cat(_decoded_orMatrixOutputs_T_6, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_3 = cat(_decoded_orMatrixOutputs_T_8, UInt<1>(0h0)) node decoded_orMatrixOutputs_3 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_3, 0, 0) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_3, 1, 1) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_3, 2, 2) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_3, 3, 3) node decoded_invMatrixOutputs_lo_3 = cat(_decoded_invMatrixOutputs_T_13, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_hi_3 = cat(_decoded_invMatrixOutputs_T_15, _decoded_invMatrixOutputs_T_14) node decoded_invMatrixOutputs_3 = cat(decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3) connect decoded_plaOutput_3, decoded_invMatrixOutputs_3 connect decoded_plaInput_3, addr_3 node _decoded_T_24 = bits(decoded_plaOutput_3, 1, 0) node _decoded_T_25 = bits(_decoded_T_24, 0, 0) node _decoded_T_26 = bits(_decoded_T_24, 1, 1) node _decoded_T_27 = cat(_decoded_T_25, _decoded_T_26) node _decoded_T_28 = bits(decoded_plaOutput_3, 3, 2) node _decoded_T_29 = bits(_decoded_T_28, 0, 0) node _decoded_T_30 = bits(_decoded_T_28, 1, 1) node _decoded_T_31 = cat(_decoded_T_29, _decoded_T_30) node decoded_3 = cat(_decoded_T_27, _decoded_T_31) node _io_resp_3_vc_sel_0_0_T = bits(decoded_3, 0, 0) connect io.resp.`3`.vc_sel.`0`[0], _io_resp_3_vc_sel_0_0_T node _io_resp_3_vc_sel_0_1_T = bits(decoded_3, 1, 1) connect io.resp.`3`.vc_sel.`0`[1], _io_resp_3_vc_sel_0_1_T node _io_resp_3_vc_sel_1_0_T = bits(decoded_3, 2, 2) connect io.resp.`3`.vc_sel.`1`[0], _io_resp_3_vc_sel_1_0_T node _io_resp_3_vc_sel_1_1_T = bits(decoded_3, 3, 3) connect io.resp.`3`.vc_sel.`1`[1], _io_resp_3_vc_sel_1_1_T connect io.resp.`3`.vc_sel.`2`[0], UInt<1>(0h0) extmodule plusarg_reader_44 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20	module RouteComputer_18( // @[RouteComputer.scala:29:7] input [3:0] io_req_3_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1 // @[RouteComputer.scala:40:14] ); wire [12:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [12:0] decoded_invInputs_1 = ~{io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [2:0] _GEN = ~(io_req_3_bits_flow_egress_node[3:1]); // @[pla.scala:78:21] assign io_resp_3_vc_sel_1_0 = \|{&{io_req_3_bits_flow_egress_node[1], io_req_3_bits_flow_egress_node[2], _GEN[2]}, &{io_req_3_bits_flow_egress_node[1], _GEN[1], io_req_3_bits_flow_egress_node[3]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_0 = \|{&{_GEN[0], io_req_3_bits_flow_egress_node[2], _GEN[2]}, &{_GEN[0], _GEN[1], io_req_3_bits_flow_egress_node[3]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_0 = \|{&{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12]}, &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_0 = \|{&{decoded_invInputs_1[0], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12]}, &{decoded_invInputs_1[0], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_0 = &{decoded_invInputs[0], decoded_invInputs[7], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12]}; // @[pla.scala:78:21, :91:29, :98:{53,70}] assign io_resp_0_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_65 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_65( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_386 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_386( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module PE_21 : input clock : Clock input reset : Reset output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_d : { bits : UInt<32>}, out_a : { bits : UInt<32>}, out_b : { bits : UInt<32>}, out_c : { bits : UInt<32>}, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<4>, out_id : UInt<4>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_5 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : { bits : UInt<32>}, clock reg c2 : { bits : UInt<32>}, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a.bits, io.in_a.bits reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node io_out_c_self_rec_rawIn_sign = bits(c1.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn = bits(c1.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn = bits(c1.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn = eq(io_out_c_self_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn = eq(io_out_c_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T = bits(io_out_c_self_rec_rawIn_fractIn, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_1 = bits(io_out_c_self_rec_rawIn_fractIn, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_2 = bits(io_out_c_self_rec_rawIn_fractIn, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_3 = bits(io_out_c_self_rec_rawIn_fractIn, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_4 = bits(io_out_c_self_rec_rawIn_fractIn, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_5 = bits(io_out_c_self_rec_rawIn_fractIn, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_6 = bits(io_out_c_self_rec_rawIn_fractIn, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_7 = bits(io_out_c_self_rec_rawIn_fractIn, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_8 = bits(io_out_c_self_rec_rawIn_fractIn, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_9 = bits(io_out_c_self_rec_rawIn_fractIn, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_10 = bits(io_out_c_self_rec_rawIn_fractIn, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_11 = bits(io_out_c_self_rec_rawIn_fractIn, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_12 = bits(io_out_c_self_rec_rawIn_fractIn, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_13 = bits(io_out_c_self_rec_rawIn_fractIn, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_14 = bits(io_out_c_self_rec_rawIn_fractIn, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_15 = bits(io_out_c_self_rec_rawIn_fractIn, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_16 = bits(io_out_c_self_rec_rawIn_fractIn, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_17 = bits(io_out_c_self_rec_rawIn_fractIn, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_18 = bits(io_out_c_self_rec_rawIn_fractIn, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_19 = bits(io_out_c_self_rec_rawIn_fractIn, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_20 = bits(io_out_c_self_rec_rawIn_fractIn, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_21 = bits(io_out_c_self_rec_rawIn_fractIn, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_22 = bits(io_out_c_self_rec_rawIn_fractIn, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_23 = mux(_io_out_c_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_24 = mux(_io_out_c_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_23) node _io_out_c_self_rec_rawIn_normDist_T_25 = mux(_io_out_c_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_24) node _io_out_c_self_rec_rawIn_normDist_T_26 = mux(_io_out_c_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_25) node _io_out_c_self_rec_rawIn_normDist_T_27 = mux(_io_out_c_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_26) node _io_out_c_self_rec_rawIn_normDist_T_28 = mux(_io_out_c_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_27) node _io_out_c_self_rec_rawIn_normDist_T_29 = mux(_io_out_c_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_28) node _io_out_c_self_rec_rawIn_normDist_T_30 = mux(_io_out_c_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_29) node _io_out_c_self_rec_rawIn_normDist_T_31 = mux(_io_out_c_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_30) node _io_out_c_self_rec_rawIn_normDist_T_32 = mux(_io_out_c_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_31) node _io_out_c_self_rec_rawIn_normDist_T_33 = mux(_io_out_c_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_32) node _io_out_c_self_rec_rawIn_normDist_T_34 = mux(_io_out_c_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_33) node _io_out_c_self_rec_rawIn_normDist_T_35 = mux(_io_out_c_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_34) node _io_out_c_self_rec_rawIn_normDist_T_36 = mux(_io_out_c_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_35) node _io_out_c_self_rec_rawIn_normDist_T_37 = mux(_io_out_c_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_36) node _io_out_c_self_rec_rawIn_normDist_T_38 = mux(_io_out_c_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_37) node _io_out_c_self_rec_rawIn_normDist_T_39 = mux(_io_out_c_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_38) node _io_out_c_self_rec_rawIn_normDist_T_40 = mux(_io_out_c_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_39) node _io_out_c_self_rec_rawIn_normDist_T_41 = mux(_io_out_c_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_40) node _io_out_c_self_rec_rawIn_normDist_T_42 = mux(_io_out_c_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_41) node _io_out_c_self_rec_rawIn_normDist_T_43 = mux(_io_out_c_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_42) node io_out_c_self_rec_rawIn_normDist = mux(_io_out_c_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_43) node _io_out_c_self_rec_rawIn_subnormFract_T = dshl(io_out_c_self_rec_rawIn_fractIn, io_out_c_self_rec_rawIn_normDist) node _io_out_c_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_c_self_rec_rawIn_subnormFract_T, 21, 0) node io_out_c_self_rec_rawIn_subnormFract = shl(_io_out_c_self_rec_rawIn_subnormFract_T_1, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T = xor(io_out_c_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, _io_out_c_self_rec_rawIn_adjustedExp_T, io_out_c_self_rec_rawIn_expIn) node _io_out_c_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_2) node _io_out_c_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_1, _io_out_c_self_rec_rawIn_adjustedExp_T_3) node io_out_c_self_rec_rawIn_adjustedExp = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_4, 1) node io_out_c_self_rec_rawIn_isZero = and(io_out_c_self_rec_rawIn_isZeroExpIn, io_out_c_self_rec_rawIn_isZeroFractIn) node _io_out_c_self_rec_rawIn_isSpecial_T = bits(io_out_c_self_rec_rawIn_adjustedExp, 8, 7) node io_out_c_self_rec_rawIn_isSpecial = eq(_io_out_c_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T = eq(io_out_c_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_1 = and(io_out_c_self_rec_rawIn_isSpecial, _io_out_c_self_rec_rawIn_out_isNaN_T) connect io_out_c_self_rec_rawIn.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_1 node _io_out_c_self_rec_rawIn_out_isInf_T = and(io_out_c_self_rec_rawIn_isSpecial, io_out_c_self_rec_rawIn_isZeroFractIn) connect io_out_c_self_rec_rawIn.isInf, _io_out_c_self_rec_rawIn_out_isInf_T connect io_out_c_self_rec_rawIn.isZero, io_out_c_self_rec_rawIn_isZero connect io_out_c_self_rec_rawIn.sign, io_out_c_self_rec_rawIn_sign node _io_out_c_self_rec_rawIn_out_sExp_T = bits(io_out_c_self_rec_rawIn_adjustedExp, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T) connect io_out_c_self_rec_rawIn.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_1 node _io_out_c_self_rec_rawIn_out_sig_T = eq(io_out_c_self_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T) node _io_out_c_self_rec_rawIn_out_sig_T_2 = mux(io_out_c_self_rec_rawIn_isZeroExpIn, io_out_c_self_rec_rawIn_subnormFract, io_out_c_self_rec_rawIn_fractIn) node _io_out_c_self_rec_rawIn_out_sig_T_3 = cat(_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2) connect io_out_c_self_rec_rawIn.sig, _io_out_c_self_rec_rawIn_out_sig_T_3 node _io_out_c_self_rec_T = bits(io_out_c_self_rec_rawIn.sExp, 8, 6) node _io_out_c_self_rec_T_1 = mux(io_out_c_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_c_self_rec_T) node _io_out_c_self_rec_T_2 = mux(io_out_c_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_3 = or(_io_out_c_self_rec_T_1, _io_out_c_self_rec_T_2) node _io_out_c_self_rec_T_4 = cat(io_out_c_self_rec_rawIn.sign, _io_out_c_self_rec_T_3) node _io_out_c_self_rec_T_5 = bits(io_out_c_self_rec_rawIn.sExp, 5, 0) node _io_out_c_self_rec_T_6 = cat(_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5) node _io_out_c_self_rec_T_7 = bits(io_out_c_self_rec_rawIn.sig, 22, 0) node io_out_c_self_rec = cat(_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7) wire io_out_c_shift_exp : UInt<8> node _io_out_c_shift_exp_T = sub(UInt<7>(0h7f), shift_offset) node _io_out_c_shift_exp_T_1 = tail(_io_out_c_shift_exp_T, 1) connect io_out_c_shift_exp, _io_out_c_shift_exp_T_1 node io_out_c_shift_fn_hi = cat(UInt<1>(0h0), io_out_c_shift_exp) node io_out_c_shift_fn = cat(io_out_c_shift_fn_hi, UInt<23>(0h0)) node io_out_c_shift_rec_rawIn_sign = bits(io_out_c_shift_fn, 31, 31) node io_out_c_shift_rec_rawIn_expIn = bits(io_out_c_shift_fn, 30, 23) node io_out_c_shift_rec_rawIn_fractIn = bits(io_out_c_shift_fn, 22, 0) node io_out_c_shift_rec_rawIn_isZeroExpIn = eq(io_out_c_shift_rec_rawIn_expIn, UInt<1>(0h0)) node io_out_c_shift_rec_rawIn_isZeroFractIn = eq(io_out_c_shift_rec_rawIn_fractIn, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_normDist_T = bits(io_out_c_shift_rec_rawIn_fractIn, 0, 0) node _io_out_c_shift_rec_rawIn_normDist_T_1 = bits(io_out_c_shift_rec_rawIn_fractIn, 1, 1) node _io_out_c_shift_rec_rawIn_normDist_T_2 = bits(io_out_c_shift_rec_rawIn_fractIn, 2, 2) node _io_out_c_shift_rec_rawIn_normDist_T_3 = bits(io_out_c_shift_rec_rawIn_fractIn, 3, 3) node _io_out_c_shift_rec_rawIn_normDist_T_4 = bits(io_out_c_shift_rec_rawIn_fractIn, 4, 4) node _io_out_c_shift_rec_rawIn_normDist_T_5 = bits(io_out_c_shift_rec_rawIn_fractIn, 5, 5) node _io_out_c_shift_rec_rawIn_normDist_T_6 = bits(io_out_c_shift_rec_rawIn_fractIn, 6, 6) node _io_out_c_shift_rec_rawIn_normDist_T_7 = bits(io_out_c_shift_rec_rawIn_fractIn, 7, 7) node _io_out_c_shift_rec_rawIn_normDist_T_8 = bits(io_out_c_shift_rec_rawIn_fractIn, 8, 8) node _io_out_c_shift_rec_rawIn_normDist_T_9 = bits(io_out_c_shift_rec_rawIn_fractIn, 9, 9) node _io_out_c_shift_rec_rawIn_normDist_T_10 = bits(io_out_c_shift_rec_rawIn_fractIn, 10, 10) node _io_out_c_shift_rec_rawIn_normDist_T_11 = bits(io_out_c_shift_rec_rawIn_fractIn, 11, 11) node _io_out_c_shift_rec_rawIn_normDist_T_12 = bits(io_out_c_shift_rec_rawIn_fractIn, 12, 12) node _io_out_c_shift_rec_rawIn_normDist_T_13 = bits(io_out_c_shift_rec_rawIn_fractIn, 13, 13) node _io_out_c_shift_rec_rawIn_normDist_T_14 = bits(io_out_c_shift_rec_rawIn_fractIn, 14, 14) node _io_out_c_shift_rec_rawIn_normDist_T_15 = bits(io_out_c_shift_rec_rawIn_fractIn, 15, 15) node _io_out_c_shift_rec_rawIn_normDist_T_16 = bits(io_out_c_shift_rec_rawIn_fractIn, 16, 16) node _io_out_c_shift_rec_rawIn_normDist_T_17 = bits(io_out_c_shift_rec_rawIn_fractIn, 17, 17) node _io_out_c_shift_rec_rawIn_normDist_T_18 = bits(io_out_c_shift_rec_rawIn_fractIn, 18, 18) node _io_out_c_shift_rec_rawIn_normDist_T_19 = bits(io_out_c_shift_rec_rawIn_fractIn, 19, 19) node _io_out_c_shift_rec_rawIn_normDist_T_20 = bits(io_out_c_shift_rec_rawIn_fractIn, 20, 20) node _io_out_c_shift_rec_rawIn_normDist_T_21 = bits(io_out_c_shift_rec_rawIn_fractIn, 21, 21) node _io_out_c_shift_rec_rawIn_normDist_T_22 = bits(io_out_c_shift_rec_rawIn_fractIn, 22, 22) node _io_out_c_shift_rec_rawIn_normDist_T_23 = mux(_io_out_c_shift_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_shift_rec_rawIn_normDist_T_24 = mux(_io_out_c_shift_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_c_shift_rec_rawIn_normDist_T_23) node _io_out_c_shift_rec_rawIn_normDist_T_25 = mux(_io_out_c_shift_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_c_shift_rec_rawIn_normDist_T_24) node _io_out_c_shift_rec_rawIn_normDist_T_26 = mux(_io_out_c_shift_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_c_shift_rec_rawIn_normDist_T_25) node _io_out_c_shift_rec_rawIn_normDist_T_27 = mux(_io_out_c_shift_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_c_shift_rec_rawIn_normDist_T_26) node _io_out_c_shift_rec_rawIn_normDist_T_28 = mux(_io_out_c_shift_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_c_shift_rec_rawIn_normDist_T_27) node _io_out_c_shift_rec_rawIn_normDist_T_29 = mux(_io_out_c_shift_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_c_shift_rec_rawIn_normDist_T_28) node _io_out_c_shift_rec_rawIn_normDist_T_30 = mux(_io_out_c_shift_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_c_shift_rec_rawIn_normDist_T_29) node _io_out_c_shift_rec_rawIn_normDist_T_31 = mux(_io_out_c_shift_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_c_shift_rec_rawIn_normDist_T_30) node _io_out_c_shift_rec_rawIn_normDist_T_32 = mux(_io_out_c_shift_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_c_shift_rec_rawIn_normDist_T_31) node _io_out_c_shift_rec_rawIn_normDist_T_33 = mux(_io_out_c_shift_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_c_shift_rec_rawIn_normDist_T_32) node _io_out_c_shift_rec_rawIn_normDist_T_34 = mux(_io_out_c_shift_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_c_shift_rec_rawIn_normDist_T_33) node _io_out_c_shift_rec_rawIn_normDist_T_35 = mux(_io_out_c_shift_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_c_shift_rec_rawIn_normDist_T_34) node _io_out_c_shift_rec_rawIn_normDist_T_36 = mux(_io_out_c_shift_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_c_shift_rec_rawIn_normDist_T_35) node _io_out_c_shift_rec_rawIn_normDist_T_37 = mux(_io_out_c_shift_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_c_shift_rec_rawIn_normDist_T_36) node _io_out_c_shift_rec_rawIn_normDist_T_38 = mux(_io_out_c_shift_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_c_shift_rec_rawIn_normDist_T_37) node _io_out_c_shift_rec_rawIn_normDist_T_39 = mux(_io_out_c_shift_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_c_shift_rec_rawIn_normDist_T_38) node _io_out_c_shift_rec_rawIn_normDist_T_40 = mux(_io_out_c_shift_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_c_shift_rec_rawIn_normDist_T_39) node _io_out_c_shift_rec_rawIn_normDist_T_41 = mux(_io_out_c_shift_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_c_shift_rec_rawIn_normDist_T_40) node _io_out_c_shift_rec_rawIn_normDist_T_42 = mux(_io_out_c_shift_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_c_shift_rec_rawIn_normDist_T_41) node _io_out_c_shift_rec_rawIn_normDist_T_43 = mux(_io_out_c_shift_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_c_shift_rec_rawIn_normDist_T_42) node io_out_c_shift_rec_rawIn_normDist = mux(_io_out_c_shift_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_c_shift_rec_rawIn_normDist_T_43) node _io_out_c_shift_rec_rawIn_subnormFract_T = dshl(io_out_c_shift_rec_rawIn_fractIn, io_out_c_shift_rec_rawIn_normDist) node _io_out_c_shift_rec_rawIn_subnormFract_T_1 = bits(_io_out_c_shift_rec_rawIn_subnormFract_T, 21, 0) node io_out_c_shift_rec_rawIn_subnormFract = shl(_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1) node _io_out_c_shift_rec_rawIn_adjustedExp_T = xor(io_out_c_shift_rec_rawIn_normDist, UInt<9>(0h1ff)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, _io_out_c_shift_rec_rawIn_adjustedExp_T, io_out_c_shift_rec_rawIn_expIn) node _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_c_shift_rec_rawIn_adjustedExp_T_2) node _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = add(_io_out_c_shift_rec_rawIn_adjustedExp_T_1, _io_out_c_shift_rec_rawIn_adjustedExp_T_3) node io_out_c_shift_rec_rawIn_adjustedExp = tail(_io_out_c_shift_rec_rawIn_adjustedExp_T_4, 1) node io_out_c_shift_rec_rawIn_isZero = and(io_out_c_shift_rec_rawIn_isZeroExpIn, io_out_c_shift_rec_rawIn_isZeroFractIn) node _io_out_c_shift_rec_rawIn_isSpecial_T = bits(io_out_c_shift_rec_rawIn_adjustedExp, 8, 7) node io_out_c_shift_rec_rawIn_isSpecial = eq(_io_out_c_shift_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_shift_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_shift_rec_rawIn_out_isNaN_T = eq(io_out_c_shift_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = and(io_out_c_shift_rec_rawIn_isSpecial, _io_out_c_shift_rec_rawIn_out_isNaN_T) connect io_out_c_shift_rec_rawIn.isNaN, _io_out_c_shift_rec_rawIn_out_isNaN_T_1 node _io_out_c_shift_rec_rawIn_out_isInf_T = and(io_out_c_shift_rec_rawIn_isSpecial, io_out_c_shift_rec_rawIn_isZeroFractIn) connect io_out_c_shift_rec_rawIn.isInf, _io_out_c_shift_rec_rawIn_out_isInf_T connect io_out_c_shift_rec_rawIn.isZero, io_out_c_shift_rec_rawIn_isZero connect io_out_c_shift_rec_rawIn.sign, io_out_c_shift_rec_rawIn_sign node _io_out_c_shift_rec_rawIn_out_sExp_T = bits(io_out_c_shift_rec_rawIn_adjustedExp, 8, 0) node _io_out_c_shift_rec_rawIn_out_sExp_T_1 = cvt(_io_out_c_shift_rec_rawIn_out_sExp_T) connect io_out_c_shift_rec_rawIn.sExp, _io_out_c_shift_rec_rawIn_out_sExp_T_1 node _io_out_c_shift_rec_rawIn_out_sig_T = eq(io_out_c_shift_rec_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_shift_rec_rawIn_out_sig_T) node _io_out_c_shift_rec_rawIn_out_sig_T_2 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn, io_out_c_shift_rec_rawIn_subnormFract, io_out_c_shift_rec_rawIn_fractIn) node _io_out_c_shift_rec_rawIn_out_sig_T_3 = cat(_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2) connect io_out_c_shift_rec_rawIn.sig, _io_out_c_shift_rec_rawIn_out_sig_T_3 node _io_out_c_shift_rec_T = bits(io_out_c_shift_rec_rawIn.sExp, 8, 6) node _io_out_c_shift_rec_T_1 = mux(io_out_c_shift_rec_rawIn.isZero, UInt<3>(0h0), _io_out_c_shift_rec_T) node _io_out_c_shift_rec_T_2 = mux(io_out_c_shift_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_shift_rec_T_3 = or(_io_out_c_shift_rec_T_1, _io_out_c_shift_rec_T_2) node _io_out_c_shift_rec_T_4 = cat(io_out_c_shift_rec_rawIn.sign, _io_out_c_shift_rec_T_3) node _io_out_c_shift_rec_T_5 = bits(io_out_c_shift_rec_rawIn.sExp, 5, 0) node _io_out_c_shift_rec_T_6 = cat(_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5) node _io_out_c_shift_rec_T_7 = bits(io_out_c_shift_rec_rawIn.sig, 22, 0) node io_out_c_shift_rec = cat(_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7) node _io_out_c_T = neq(io_out_c_shift_exp, UInt<1>(0h0)) node _io_out_c_T_1 = asUInt(reset) node _io_out_c_T_2 = eq(_io_out_c_T_1, UInt<1>(0h0)) when _io_out_c_T_2 : node _io_out_c_T_3 = eq(_io_out_c_T, UInt<1>(0h0)) when _io_out_c_T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: scaling by denormalized numbers is not currently supported\n at Arithmetic.scala:447 assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n") : io_out_c_printf assert(clock, _io_out_c_T, UInt<1>(0h1), "") : io_out_c_assert inst io_out_c_muladder of MulRecFN_34 connect io_out_c_muladder.io.roundingMode, UInt<3>(0h0) connect io_out_c_muladder.io.detectTininess, UInt<1>(0h1) connect io_out_c_muladder.io.a, io_out_c_self_rec connect io_out_c_muladder.io.b, io_out_c_shift_rec wire io_out_c_result : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp = bits(io_out_c_muladder.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T = bits(io_out_c_result_bits_rawIn_exp, 8, 6) node io_out_c_result_bits_rawIn_isZero = eq(_io_out_c_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T = bits(io_out_c_result_bits_rawIn_exp, 8, 7) node io_out_c_result_bits_rawIn_isSpecial = eq(_io_out_c_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T = bits(io_out_c_result_bits_rawIn_exp, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_1 = and(io_out_c_result_bits_rawIn_isSpecial, _io_out_c_result_bits_rawIn_out_isNaN_T) connect io_out_c_result_bits_rawIn.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_1 node _io_out_c_result_bits_rawIn_out_isInf_T = bits(io_out_c_result_bits_rawIn_exp, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_1 = eq(_io_out_c_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_2 = and(io_out_c_result_bits_rawIn_isSpecial, _io_out_c_result_bits_rawIn_out_isInf_T_1) connect io_out_c_result_bits_rawIn.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_2 connect io_out_c_result_bits_rawIn.isZero, io_out_c_result_bits_rawIn_isZero node _io_out_c_result_bits_rawIn_out_sign_T = bits(io_out_c_muladder.io.out, 32, 32) connect io_out_c_result_bits_rawIn.sign, _io_out_c_result_bits_rawIn_out_sign_T node _io_out_c_result_bits_rawIn_out_sExp_T = cvt(io_out_c_result_bits_rawIn_exp) connect io_out_c_result_bits_rawIn.sExp, _io_out_c_result_bits_rawIn_out_sExp_T node _io_out_c_result_bits_rawIn_out_sig_T = eq(io_out_c_result_bits_rawIn_isZero, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T) node _io_out_c_result_bits_rawIn_out_sig_T_2 = bits(io_out_c_muladder.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_3 = cat(_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2) connect io_out_c_result_bits_rawIn.sig, _io_out_c_result_bits_rawIn_out_sig_T_3 node io_out_c_result_bits_isSubnormal = lt(io_out_c_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T = bits(io_out_c_result_bits_rawIn.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T) node io_out_c_result_bits_denormShiftDist = tail(_io_out_c_result_bits_denormShiftDist_T_1, 1) node _io_out_c_result_bits_denormFract_T = shr(io_out_c_result_bits_rawIn.sig, 1) node _io_out_c_result_bits_denormFract_T_1 = dshr(_io_out_c_result_bits_denormFract_T, io_out_c_result_bits_denormShiftDist) node io_out_c_result_bits_denormFract = bits(_io_out_c_result_bits_denormFract_T_1, 22, 0) node _io_out_c_result_bits_expOut_T = bits(io_out_c_result_bits_rawIn.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_1 = sub(_io_out_c_result_bits_expOut_T, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_2 = tail(_io_out_c_result_bits_expOut_T_1, 1) node _io_out_c_result_bits_expOut_T_3 = mux(io_out_c_result_bits_isSubnormal, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_2) node _io_out_c_result_bits_expOut_T_4 = or(io_out_c_result_bits_rawIn.isNaN, io_out_c_result_bits_rawIn.isInf) node _io_out_c_result_bits_expOut_T_5 = mux(_io_out_c_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut = or(_io_out_c_result_bits_expOut_T_3, _io_out_c_result_bits_expOut_T_5) node _io_out_c_result_bits_fractOut_T = bits(io_out_c_result_bits_rawIn.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_1 = mux(io_out_c_result_bits_rawIn.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T) node io_out_c_result_bits_fractOut = mux(io_out_c_result_bits_isSubnormal, io_out_c_result_bits_denormFract, _io_out_c_result_bits_fractOut_T_1) node io_out_c_result_bits_hi = cat(io_out_c_result_bits_rawIn.sign, io_out_c_result_bits_expOut) node _io_out_c_result_bits_T = cat(io_out_c_result_bits_hi, io_out_c_result_bits_fractOut) connect io_out_c_result.bits, _io_out_c_result_bits_T node io_out_c_self_rec_rawIn_sign_1 = bits(io_out_c_result.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_1 = bits(io_out_c_result.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_1 = bits(io_out_c_result.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_1 = eq(io_out_c_self_rec_rawIn_expIn_1, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_1 = eq(io_out_c_self_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_44 = bits(io_out_c_self_rec_rawIn_fractIn_1, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_45 = bits(io_out_c_self_rec_rawIn_fractIn_1, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_46 = bits(io_out_c_self_rec_rawIn_fractIn_1, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_47 = bits(io_out_c_self_rec_rawIn_fractIn_1, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_48 = bits(io_out_c_self_rec_rawIn_fractIn_1, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_49 = bits(io_out_c_self_rec_rawIn_fractIn_1, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_50 = bits(io_out_c_self_rec_rawIn_fractIn_1, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_51 = bits(io_out_c_self_rec_rawIn_fractIn_1, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_52 = bits(io_out_c_self_rec_rawIn_fractIn_1, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_53 = bits(io_out_c_self_rec_rawIn_fractIn_1, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_54 = bits(io_out_c_self_rec_rawIn_fractIn_1, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_55 = bits(io_out_c_self_rec_rawIn_fractIn_1, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_56 = bits(io_out_c_self_rec_rawIn_fractIn_1, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_57 = bits(io_out_c_self_rec_rawIn_fractIn_1, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_58 = bits(io_out_c_self_rec_rawIn_fractIn_1, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_59 = bits(io_out_c_self_rec_rawIn_fractIn_1, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_60 = bits(io_out_c_self_rec_rawIn_fractIn_1, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_61 = bits(io_out_c_self_rec_rawIn_fractIn_1, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_62 = bits(io_out_c_self_rec_rawIn_fractIn_1, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_63 = bits(io_out_c_self_rec_rawIn_fractIn_1, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_64 = bits(io_out_c_self_rec_rawIn_fractIn_1, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_65 = bits(io_out_c_self_rec_rawIn_fractIn_1, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_66 = bits(io_out_c_self_rec_rawIn_fractIn_1, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_67 = mux(_io_out_c_self_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_68 = mux(_io_out_c_self_rec_rawIn_normDist_T_46, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_67) node _io_out_c_self_rec_rawIn_normDist_T_69 = mux(_io_out_c_self_rec_rawIn_normDist_T_47, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_68) node _io_out_c_self_rec_rawIn_normDist_T_70 = mux(_io_out_c_self_rec_rawIn_normDist_T_48, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_69) node _io_out_c_self_rec_rawIn_normDist_T_71 = mux(_io_out_c_self_rec_rawIn_normDist_T_49, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_70) node _io_out_c_self_rec_rawIn_normDist_T_72 = mux(_io_out_c_self_rec_rawIn_normDist_T_50, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_71) node _io_out_c_self_rec_rawIn_normDist_T_73 = mux(_io_out_c_self_rec_rawIn_normDist_T_51, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_72) node _io_out_c_self_rec_rawIn_normDist_T_74 = mux(_io_out_c_self_rec_rawIn_normDist_T_52, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_73) node _io_out_c_self_rec_rawIn_normDist_T_75 = mux(_io_out_c_self_rec_rawIn_normDist_T_53, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_74) node _io_out_c_self_rec_rawIn_normDist_T_76 = mux(_io_out_c_self_rec_rawIn_normDist_T_54, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_75) node _io_out_c_self_rec_rawIn_normDist_T_77 = mux(_io_out_c_self_rec_rawIn_normDist_T_55, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_76) node _io_out_c_self_rec_rawIn_normDist_T_78 = mux(_io_out_c_self_rec_rawIn_normDist_T_56, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_77) node _io_out_c_self_rec_rawIn_normDist_T_79 = mux(_io_out_c_self_rec_rawIn_normDist_T_57, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_78) node _io_out_c_self_rec_rawIn_normDist_T_80 = mux(_io_out_c_self_rec_rawIn_normDist_T_58, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_79) node _io_out_c_self_rec_rawIn_normDist_T_81 = mux(_io_out_c_self_rec_rawIn_normDist_T_59, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_80) node _io_out_c_self_rec_rawIn_normDist_T_82 = mux(_io_out_c_self_rec_rawIn_normDist_T_60, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_81) node _io_out_c_self_rec_rawIn_normDist_T_83 = mux(_io_out_c_self_rec_rawIn_normDist_T_61, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_82) node _io_out_c_self_rec_rawIn_normDist_T_84 = mux(_io_out_c_self_rec_rawIn_normDist_T_62, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_83) node _io_out_c_self_rec_rawIn_normDist_T_85 = mux(_io_out_c_self_rec_rawIn_normDist_T_63, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_84) node _io_out_c_self_rec_rawIn_normDist_T_86 = mux(_io_out_c_self_rec_rawIn_normDist_T_64, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_85) node _io_out_c_self_rec_rawIn_normDist_T_87 = mux(_io_out_c_self_rec_rawIn_normDist_T_65, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_86) node io_out_c_self_rec_rawIn_normDist_1 = mux(_io_out_c_self_rec_rawIn_normDist_T_66, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_87) node _io_out_c_self_rec_rawIn_subnormFract_T_2 = dshl(io_out_c_self_rec_rawIn_fractIn_1, io_out_c_self_rec_rawIn_normDist_1) node _io_out_c_self_rec_rawIn_subnormFract_T_3 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_2, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_1 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_3, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_5 = xor(io_out_c_self_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_6 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, _io_out_c_self_rec_rawIn_adjustedExp_T_5, io_out_c_self_rec_rawIn_expIn_1) node _io_out_c_self_rec_rawIn_adjustedExp_T_7 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_7) node _io_out_c_self_rec_rawIn_adjustedExp_T_9 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_6, _io_out_c_self_rec_rawIn_adjustedExp_T_8) node io_out_c_self_rec_rawIn_adjustedExp_1 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_9, 1) node io_out_c_self_rec_rawIn_isZero_1 = and(io_out_c_self_rec_rawIn_isZeroExpIn_1, io_out_c_self_rec_rawIn_isZeroFractIn_1) node _io_out_c_self_rec_rawIn_isSpecial_T_1 = bits(io_out_c_self_rec_rawIn_adjustedExp_1, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_1 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_2 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_3 = and(io_out_c_self_rec_rawIn_isSpecial_1, _io_out_c_self_rec_rawIn_out_isNaN_T_2) connect io_out_c_self_rec_rawIn_1.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_3 node _io_out_c_self_rec_rawIn_out_isInf_T_1 = and(io_out_c_self_rec_rawIn_isSpecial_1, io_out_c_self_rec_rawIn_isZeroFractIn_1) connect io_out_c_self_rec_rawIn_1.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_1 connect io_out_c_self_rec_rawIn_1.isZero, io_out_c_self_rec_rawIn_isZero_1 connect io_out_c_self_rec_rawIn_1.sign, io_out_c_self_rec_rawIn_sign_1 node _io_out_c_self_rec_rawIn_out_sExp_T_2 = bits(io_out_c_self_rec_rawIn_adjustedExp_1, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_3 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_2) connect io_out_c_self_rec_rawIn_1.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_3 node _io_out_c_self_rec_rawIn_out_sig_T_4 = eq(io_out_c_self_rec_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_4) node _io_out_c_self_rec_rawIn_out_sig_T_6 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_1, io_out_c_self_rec_rawIn_subnormFract_1, io_out_c_self_rec_rawIn_fractIn_1) node _io_out_c_self_rec_rawIn_out_sig_T_7 = cat(_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6) connect io_out_c_self_rec_rawIn_1.sig, _io_out_c_self_rec_rawIn_out_sig_T_7 node _io_out_c_self_rec_T_8 = bits(io_out_c_self_rec_rawIn_1.sExp, 8, 6) node _io_out_c_self_rec_T_9 = mux(io_out_c_self_rec_rawIn_1.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_8) node _io_out_c_self_rec_T_10 = mux(io_out_c_self_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_11 = or(_io_out_c_self_rec_T_9, _io_out_c_self_rec_T_10) node _io_out_c_self_rec_T_12 = cat(io_out_c_self_rec_rawIn_1.sign, _io_out_c_self_rec_T_11) node _io_out_c_self_rec_T_13 = bits(io_out_c_self_rec_rawIn_1.sExp, 5, 0) node _io_out_c_self_rec_T_14 = cat(_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13) node _io_out_c_self_rec_T_15 = bits(io_out_c_self_rec_rawIn_1.sig, 22, 0) node io_out_c_self_rec_1 = cat(_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15) inst io_out_c_resizer of RecFNToRecFN_176 connect io_out_c_resizer.io.in, io_out_c_self_rec_1 connect io_out_c_resizer.io.roundingMode, UInt<3>(0h0) connect io_out_c_resizer.io.detectTininess, UInt<1>(0h1) wire io_out_c_result_1 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_1 = bits(io_out_c_resizer.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_1 = bits(io_out_c_result_bits_rawIn_exp_1, 8, 6) node io_out_c_result_bits_rawIn_isZero_1 = eq(_io_out_c_result_bits_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_1 = bits(io_out_c_result_bits_rawIn_exp_1, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_1 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_2 = bits(io_out_c_result_bits_rawIn_exp_1, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_3 = and(io_out_c_result_bits_rawIn_isSpecial_1, _io_out_c_result_bits_rawIn_out_isNaN_T_2) connect io_out_c_result_bits_rawIn_1.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_3 node _io_out_c_result_bits_rawIn_out_isInf_T_3 = bits(io_out_c_result_bits_rawIn_exp_1, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_4 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_5 = and(io_out_c_result_bits_rawIn_isSpecial_1, _io_out_c_result_bits_rawIn_out_isInf_T_4) connect io_out_c_result_bits_rawIn_1.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_5 connect io_out_c_result_bits_rawIn_1.isZero, io_out_c_result_bits_rawIn_isZero_1 node _io_out_c_result_bits_rawIn_out_sign_T_1 = bits(io_out_c_resizer.io.out, 32, 32) connect io_out_c_result_bits_rawIn_1.sign, _io_out_c_result_bits_rawIn_out_sign_T_1 node _io_out_c_result_bits_rawIn_out_sExp_T_1 = cvt(io_out_c_result_bits_rawIn_exp_1) connect io_out_c_result_bits_rawIn_1.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_1 node _io_out_c_result_bits_rawIn_out_sig_T_4 = eq(io_out_c_result_bits_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_4) node _io_out_c_result_bits_rawIn_out_sig_T_6 = bits(io_out_c_resizer.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_7 = cat(_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6) connect io_out_c_result_bits_rawIn_1.sig, _io_out_c_result_bits_rawIn_out_sig_T_7 node io_out_c_result_bits_isSubnormal_1 = lt(io_out_c_result_bits_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_2 = bits(io_out_c_result_bits_rawIn_1.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_2) node io_out_c_result_bits_denormShiftDist_1 = tail(_io_out_c_result_bits_denormShiftDist_T_3, 1) node _io_out_c_result_bits_denormFract_T_2 = shr(io_out_c_result_bits_rawIn_1.sig, 1) node _io_out_c_result_bits_denormFract_T_3 = dshr(_io_out_c_result_bits_denormFract_T_2, io_out_c_result_bits_denormShiftDist_1) node io_out_c_result_bits_denormFract_1 = bits(_io_out_c_result_bits_denormFract_T_3, 22, 0) node _io_out_c_result_bits_expOut_T_6 = bits(io_out_c_result_bits_rawIn_1.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_7 = sub(_io_out_c_result_bits_expOut_T_6, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_8 = tail(_io_out_c_result_bits_expOut_T_7, 1) node _io_out_c_result_bits_expOut_T_9 = mux(io_out_c_result_bits_isSubnormal_1, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_8) node _io_out_c_result_bits_expOut_T_10 = or(io_out_c_result_bits_rawIn_1.isNaN, io_out_c_result_bits_rawIn_1.isInf) node _io_out_c_result_bits_expOut_T_11 = mux(_io_out_c_result_bits_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_1 = or(_io_out_c_result_bits_expOut_T_9, _io_out_c_result_bits_expOut_T_11) node _io_out_c_result_bits_fractOut_T_2 = bits(io_out_c_result_bits_rawIn_1.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_3 = mux(io_out_c_result_bits_rawIn_1.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_2) node io_out_c_result_bits_fractOut_1 = mux(io_out_c_result_bits_isSubnormal_1, io_out_c_result_bits_denormFract_1, _io_out_c_result_bits_fractOut_T_3) node io_out_c_result_bits_hi_1 = cat(io_out_c_result_bits_rawIn_1.sign, io_out_c_result_bits_expOut_1) node _io_out_c_result_bits_T_1 = cat(io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1) connect io_out_c_result_1.bits, _io_out_c_result_bits_T_1 connect io.out_c, io_out_c_result_1 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_1 : UInt<32> connect _mac_unit_io_in_b_WIRE_1, io.in_b.bits node _mac_unit_io_in_b_T = bits(_mac_unit_io_in_b_WIRE_1, 31, 0) connect _mac_unit_io_in_b_WIRE.bits, _mac_unit_io_in_b_T connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE.bits connect mac_unit.io.in_c.bits, c2.bits connect c2, mac_unit.io.out_d node c1_self_rec_rawIn_sign = bits(io.in_d.bits, 31, 31) node c1_self_rec_rawIn_expIn = bits(io.in_d.bits, 30, 23) node c1_self_rec_rawIn_fractIn = bits(io.in_d.bits, 22, 0) node c1_self_rec_rawIn_isZeroExpIn = eq(c1_self_rec_rawIn_expIn, UInt<1>(0h0)) node c1_self_rec_rawIn_isZeroFractIn = eq(c1_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _c1_self_rec_rawIn_normDist_T = bits(c1_self_rec_rawIn_fractIn, 0, 0) node _c1_self_rec_rawIn_normDist_T_1 = bits(c1_self_rec_rawIn_fractIn, 1, 1) node _c1_self_rec_rawIn_normDist_T_2 = bits(c1_self_rec_rawIn_fractIn, 2, 2) node _c1_self_rec_rawIn_normDist_T_3 = bits(c1_self_rec_rawIn_fractIn, 3, 3) node _c1_self_rec_rawIn_normDist_T_4 = bits(c1_self_rec_rawIn_fractIn, 4, 4) node _c1_self_rec_rawIn_normDist_T_5 = bits(c1_self_rec_rawIn_fractIn, 5, 5) node _c1_self_rec_rawIn_normDist_T_6 = bits(c1_self_rec_rawIn_fractIn, 6, 6) node _c1_self_rec_rawIn_normDist_T_7 = bits(c1_self_rec_rawIn_fractIn, 7, 7) node _c1_self_rec_rawIn_normDist_T_8 = bits(c1_self_rec_rawIn_fractIn, 8, 8) node _c1_self_rec_rawIn_normDist_T_9 = bits(c1_self_rec_rawIn_fractIn, 9, 9) node _c1_self_rec_rawIn_normDist_T_10 = bits(c1_self_rec_rawIn_fractIn, 10, 10) node _c1_self_rec_rawIn_normDist_T_11 = bits(c1_self_rec_rawIn_fractIn, 11, 11) node _c1_self_rec_rawIn_normDist_T_12 = bits(c1_self_rec_rawIn_fractIn, 12, 12) node _c1_self_rec_rawIn_normDist_T_13 = bits(c1_self_rec_rawIn_fractIn, 13, 13) node _c1_self_rec_rawIn_normDist_T_14 = bits(c1_self_rec_rawIn_fractIn, 14, 14) node _c1_self_rec_rawIn_normDist_T_15 = bits(c1_self_rec_rawIn_fractIn, 15, 15) node _c1_self_rec_rawIn_normDist_T_16 = bits(c1_self_rec_rawIn_fractIn, 16, 16) node _c1_self_rec_rawIn_normDist_T_17 = bits(c1_self_rec_rawIn_fractIn, 17, 17) node _c1_self_rec_rawIn_normDist_T_18 = bits(c1_self_rec_rawIn_fractIn, 18, 18) node _c1_self_rec_rawIn_normDist_T_19 = bits(c1_self_rec_rawIn_fractIn, 19, 19) node _c1_self_rec_rawIn_normDist_T_20 = bits(c1_self_rec_rawIn_fractIn, 20, 20) node _c1_self_rec_rawIn_normDist_T_21 = bits(c1_self_rec_rawIn_fractIn, 21, 21) node _c1_self_rec_rawIn_normDist_T_22 = bits(c1_self_rec_rawIn_fractIn, 22, 22) node _c1_self_rec_rawIn_normDist_T_23 = mux(_c1_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _c1_self_rec_rawIn_normDist_T_24 = mux(_c1_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _c1_self_rec_rawIn_normDist_T_23) node _c1_self_rec_rawIn_normDist_T_25 = mux(_c1_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _c1_self_rec_rawIn_normDist_T_24) node _c1_self_rec_rawIn_normDist_T_26 = mux(_c1_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _c1_self_rec_rawIn_normDist_T_25) node _c1_self_rec_rawIn_normDist_T_27 = mux(_c1_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _c1_self_rec_rawIn_normDist_T_26) node _c1_self_rec_rawIn_normDist_T_28 = mux(_c1_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _c1_self_rec_rawIn_normDist_T_27) node _c1_self_rec_rawIn_normDist_T_29 = mux(_c1_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _c1_self_rec_rawIn_normDist_T_28) node _c1_self_rec_rawIn_normDist_T_30 = mux(_c1_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _c1_self_rec_rawIn_normDist_T_29) node _c1_self_rec_rawIn_normDist_T_31 = mux(_c1_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _c1_self_rec_rawIn_normDist_T_30) node _c1_self_rec_rawIn_normDist_T_32 = mux(_c1_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _c1_self_rec_rawIn_normDist_T_31) node _c1_self_rec_rawIn_normDist_T_33 = mux(_c1_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _c1_self_rec_rawIn_normDist_T_32) node _c1_self_rec_rawIn_normDist_T_34 = mux(_c1_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _c1_self_rec_rawIn_normDist_T_33) node _c1_self_rec_rawIn_normDist_T_35 = mux(_c1_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _c1_self_rec_rawIn_normDist_T_34) node _c1_self_rec_rawIn_normDist_T_36 = mux(_c1_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _c1_self_rec_rawIn_normDist_T_35) node _c1_self_rec_rawIn_normDist_T_37 = mux(_c1_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _c1_self_rec_rawIn_normDist_T_36) node _c1_self_rec_rawIn_normDist_T_38 = mux(_c1_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _c1_self_rec_rawIn_normDist_T_37) node _c1_self_rec_rawIn_normDist_T_39 = mux(_c1_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _c1_self_rec_rawIn_normDist_T_38) node _c1_self_rec_rawIn_normDist_T_40 = mux(_c1_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _c1_self_rec_rawIn_normDist_T_39) node _c1_self_rec_rawIn_normDist_T_41 = mux(_c1_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _c1_self_rec_rawIn_normDist_T_40) node _c1_self_rec_rawIn_normDist_T_42 = mux(_c1_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _c1_self_rec_rawIn_normDist_T_41) node _c1_self_rec_rawIn_normDist_T_43 = mux(_c1_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _c1_self_rec_rawIn_normDist_T_42) node c1_self_rec_rawIn_normDist = mux(_c1_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _c1_self_rec_rawIn_normDist_T_43) node _c1_self_rec_rawIn_subnormFract_T = dshl(c1_self_rec_rawIn_fractIn, c1_self_rec_rawIn_normDist) node _c1_self_rec_rawIn_subnormFract_T_1 = bits(_c1_self_rec_rawIn_subnormFract_T, 21, 0) node c1_self_rec_rawIn_subnormFract = shl(_c1_self_rec_rawIn_subnormFract_T_1, 1) node _c1_self_rec_rawIn_adjustedExp_T = xor(c1_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _c1_self_rec_rawIn_adjustedExp_T_1 = mux(c1_self_rec_rawIn_isZeroExpIn, _c1_self_rec_rawIn_adjustedExp_T, c1_self_rec_rawIn_expIn) node _c1_self_rec_rawIn_adjustedExp_T_2 = mux(c1_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _c1_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _c1_self_rec_rawIn_adjustedExp_T_2) node _c1_self_rec_rawIn_adjustedExp_T_4 = add(_c1_self_rec_rawIn_adjustedExp_T_1, _c1_self_rec_rawIn_adjustedExp_T_3) node c1_self_rec_rawIn_adjustedExp = tail(_c1_self_rec_rawIn_adjustedExp_T_4, 1) node c1_self_rec_rawIn_isZero = and(c1_self_rec_rawIn_isZeroExpIn, c1_self_rec_rawIn_isZeroFractIn) node _c1_self_rec_rawIn_isSpecial_T = bits(c1_self_rec_rawIn_adjustedExp, 8, 7) node c1_self_rec_rawIn_isSpecial = eq(_c1_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire c1_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c1_self_rec_rawIn_out_isNaN_T = eq(c1_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _c1_self_rec_rawIn_out_isNaN_T_1 = and(c1_self_rec_rawIn_isSpecial, _c1_self_rec_rawIn_out_isNaN_T) connect c1_self_rec_rawIn.isNaN, _c1_self_rec_rawIn_out_isNaN_T_1 node _c1_self_rec_rawIn_out_isInf_T = and(c1_self_rec_rawIn_isSpecial, c1_self_rec_rawIn_isZeroFractIn) connect c1_self_rec_rawIn.isInf, _c1_self_rec_rawIn_out_isInf_T connect c1_self_rec_rawIn.isZero, c1_self_rec_rawIn_isZero connect c1_self_rec_rawIn.sign, c1_self_rec_rawIn_sign node _c1_self_rec_rawIn_out_sExp_T = bits(c1_self_rec_rawIn_adjustedExp, 8, 0) node _c1_self_rec_rawIn_out_sExp_T_1 = cvt(_c1_self_rec_rawIn_out_sExp_T) connect c1_self_rec_rawIn.sExp, _c1_self_rec_rawIn_out_sExp_T_1 node _c1_self_rec_rawIn_out_sig_T = eq(c1_self_rec_rawIn_isZero, UInt<1>(0h0)) node _c1_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c1_self_rec_rawIn_out_sig_T) node _c1_self_rec_rawIn_out_sig_T_2 = mux(c1_self_rec_rawIn_isZeroExpIn, c1_self_rec_rawIn_subnormFract, c1_self_rec_rawIn_fractIn) node _c1_self_rec_rawIn_out_sig_T_3 = cat(_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2) connect c1_self_rec_rawIn.sig, _c1_self_rec_rawIn_out_sig_T_3 node _c1_self_rec_T = bits(c1_self_rec_rawIn.sExp, 8, 6) node _c1_self_rec_T_1 = mux(c1_self_rec_rawIn.isZero, UInt<3>(0h0), _c1_self_rec_T) node _c1_self_rec_T_2 = mux(c1_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _c1_self_rec_T_3 = or(_c1_self_rec_T_1, _c1_self_rec_T_2) node _c1_self_rec_T_4 = cat(c1_self_rec_rawIn.sign, _c1_self_rec_T_3) node _c1_self_rec_T_5 = bits(c1_self_rec_rawIn.sExp, 5, 0) node _c1_self_rec_T_6 = cat(_c1_self_rec_T_4, _c1_self_rec_T_5) node _c1_self_rec_T_7 = bits(c1_self_rec_rawIn.sig, 22, 0) node c1_self_rec = cat(_c1_self_rec_T_6, _c1_self_rec_T_7) inst c1_resizer of RecFNToRecFN_177 connect c1_resizer.io.in, c1_self_rec connect c1_resizer.io.roundingMode, UInt<3>(0h0) connect c1_resizer.io.detectTininess, UInt<1>(0h1) wire c1_result : { bits : UInt<32>} node c1_result_bits_rawIn_exp = bits(c1_resizer.io.out, 31, 23) node _c1_result_bits_rawIn_isZero_T = bits(c1_result_bits_rawIn_exp, 8, 6) node c1_result_bits_rawIn_isZero = eq(_c1_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _c1_result_bits_rawIn_isSpecial_T = bits(c1_result_bits_rawIn_exp, 8, 7) node c1_result_bits_rawIn_isSpecial = eq(_c1_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire c1_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c1_result_bits_rawIn_out_isNaN_T = bits(c1_result_bits_rawIn_exp, 6, 6) node _c1_result_bits_rawIn_out_isNaN_T_1 = and(c1_result_bits_rawIn_isSpecial, _c1_result_bits_rawIn_out_isNaN_T) connect c1_result_bits_rawIn.isNaN, _c1_result_bits_rawIn_out_isNaN_T_1 node _c1_result_bits_rawIn_out_isInf_T = bits(c1_result_bits_rawIn_exp, 6, 6) node _c1_result_bits_rawIn_out_isInf_T_1 = eq(_c1_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _c1_result_bits_rawIn_out_isInf_T_2 = and(c1_result_bits_rawIn_isSpecial, _c1_result_bits_rawIn_out_isInf_T_1) connect c1_result_bits_rawIn.isInf, _c1_result_bits_rawIn_out_isInf_T_2 connect c1_result_bits_rawIn.isZero, c1_result_bits_rawIn_isZero node _c1_result_bits_rawIn_out_sign_T = bits(c1_resizer.io.out, 32, 32) connect c1_result_bits_rawIn.sign, _c1_result_bits_rawIn_out_sign_T node _c1_result_bits_rawIn_out_sExp_T = cvt(c1_result_bits_rawIn_exp) connect c1_result_bits_rawIn.sExp, _c1_result_bits_rawIn_out_sExp_T node _c1_result_bits_rawIn_out_sig_T = eq(c1_result_bits_rawIn_isZero, UInt<1>(0h0)) node _c1_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c1_result_bits_rawIn_out_sig_T) node _c1_result_bits_rawIn_out_sig_T_2 = bits(c1_resizer.io.out, 22, 0) node _c1_result_bits_rawIn_out_sig_T_3 = cat(_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2) connect c1_result_bits_rawIn.sig, _c1_result_bits_rawIn_out_sig_T_3 node c1_result_bits_isSubnormal = lt(c1_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _c1_result_bits_denormShiftDist_T = bits(c1_result_bits_rawIn.sExp, 4, 0) node _c1_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _c1_result_bits_denormShiftDist_T) node c1_result_bits_denormShiftDist = tail(_c1_result_bits_denormShiftDist_T_1, 1) node _c1_result_bits_denormFract_T = shr(c1_result_bits_rawIn.sig, 1) node _c1_result_bits_denormFract_T_1 = dshr(_c1_result_bits_denormFract_T, c1_result_bits_denormShiftDist) node c1_result_bits_denormFract = bits(_c1_result_bits_denormFract_T_1, 22, 0) node _c1_result_bits_expOut_T = bits(c1_result_bits_rawIn.sExp, 7, 0) node _c1_result_bits_expOut_T_1 = sub(_c1_result_bits_expOut_T, UInt<8>(0h81)) node _c1_result_bits_expOut_T_2 = tail(_c1_result_bits_expOut_T_1, 1) node _c1_result_bits_expOut_T_3 = mux(c1_result_bits_isSubnormal, UInt<1>(0h0), _c1_result_bits_expOut_T_2) node _c1_result_bits_expOut_T_4 = or(c1_result_bits_rawIn.isNaN, c1_result_bits_rawIn.isInf) node _c1_result_bits_expOut_T_5 = mux(_c1_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node c1_result_bits_expOut = or(_c1_result_bits_expOut_T_3, _c1_result_bits_expOut_T_5) node _c1_result_bits_fractOut_T = bits(c1_result_bits_rawIn.sig, 22, 0) node _c1_result_bits_fractOut_T_1 = mux(c1_result_bits_rawIn.isInf, UInt<1>(0h0), _c1_result_bits_fractOut_T) node c1_result_bits_fractOut = mux(c1_result_bits_isSubnormal, c1_result_bits_denormFract, _c1_result_bits_fractOut_T_1) node c1_result_bits_hi = cat(c1_result_bits_rawIn.sign, c1_result_bits_expOut) node _c1_result_bits_T = cat(c1_result_bits_hi, c1_result_bits_fractOut) connect c1_result.bits, _c1_result_bits_T connect c1, c1_result else : node io_out_c_self_rec_rawIn_sign_2 = bits(c2.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_2 = bits(c2.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_2 = bits(c2.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_2 = eq(io_out_c_self_rec_rawIn_expIn_2, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_2 = eq(io_out_c_self_rec_rawIn_fractIn_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_88 = bits(io_out_c_self_rec_rawIn_fractIn_2, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_89 = bits(io_out_c_self_rec_rawIn_fractIn_2, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_90 = bits(io_out_c_self_rec_rawIn_fractIn_2, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_91 = bits(io_out_c_self_rec_rawIn_fractIn_2, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_92 = bits(io_out_c_self_rec_rawIn_fractIn_2, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_93 = bits(io_out_c_self_rec_rawIn_fractIn_2, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_94 = bits(io_out_c_self_rec_rawIn_fractIn_2, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_95 = bits(io_out_c_self_rec_rawIn_fractIn_2, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_96 = bits(io_out_c_self_rec_rawIn_fractIn_2, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_97 = bits(io_out_c_self_rec_rawIn_fractIn_2, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_98 = bits(io_out_c_self_rec_rawIn_fractIn_2, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_99 = bits(io_out_c_self_rec_rawIn_fractIn_2, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_100 = bits(io_out_c_self_rec_rawIn_fractIn_2, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_101 = bits(io_out_c_self_rec_rawIn_fractIn_2, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_102 = bits(io_out_c_self_rec_rawIn_fractIn_2, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_103 = bits(io_out_c_self_rec_rawIn_fractIn_2, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_104 = bits(io_out_c_self_rec_rawIn_fractIn_2, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_105 = bits(io_out_c_self_rec_rawIn_fractIn_2, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_106 = bits(io_out_c_self_rec_rawIn_fractIn_2, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_107 = bits(io_out_c_self_rec_rawIn_fractIn_2, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_108 = bits(io_out_c_self_rec_rawIn_fractIn_2, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_109 = bits(io_out_c_self_rec_rawIn_fractIn_2, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_110 = bits(io_out_c_self_rec_rawIn_fractIn_2, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_111 = mux(_io_out_c_self_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_112 = mux(_io_out_c_self_rec_rawIn_normDist_T_90, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_111) node _io_out_c_self_rec_rawIn_normDist_T_113 = mux(_io_out_c_self_rec_rawIn_normDist_T_91, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_112) node _io_out_c_self_rec_rawIn_normDist_T_114 = mux(_io_out_c_self_rec_rawIn_normDist_T_92, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_113) node _io_out_c_self_rec_rawIn_normDist_T_115 = mux(_io_out_c_self_rec_rawIn_normDist_T_93, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_114) node _io_out_c_self_rec_rawIn_normDist_T_116 = mux(_io_out_c_self_rec_rawIn_normDist_T_94, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_115) node _io_out_c_self_rec_rawIn_normDist_T_117 = mux(_io_out_c_self_rec_rawIn_normDist_T_95, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_116) node _io_out_c_self_rec_rawIn_normDist_T_118 = mux(_io_out_c_self_rec_rawIn_normDist_T_96, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_117) node _io_out_c_self_rec_rawIn_normDist_T_119 = mux(_io_out_c_self_rec_rawIn_normDist_T_97, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_118) node _io_out_c_self_rec_rawIn_normDist_T_120 = mux(_io_out_c_self_rec_rawIn_normDist_T_98, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_119) node _io_out_c_self_rec_rawIn_normDist_T_121 = mux(_io_out_c_self_rec_rawIn_normDist_T_99, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_120) node _io_out_c_self_rec_rawIn_normDist_T_122 = mux(_io_out_c_self_rec_rawIn_normDist_T_100, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_121) node _io_out_c_self_rec_rawIn_normDist_T_123 = mux(_io_out_c_self_rec_rawIn_normDist_T_101, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_122) node _io_out_c_self_rec_rawIn_normDist_T_124 = mux(_io_out_c_self_rec_rawIn_normDist_T_102, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_123) node _io_out_c_self_rec_rawIn_normDist_T_125 = mux(_io_out_c_self_rec_rawIn_normDist_T_103, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_124) node _io_out_c_self_rec_rawIn_normDist_T_126 = mux(_io_out_c_self_rec_rawIn_normDist_T_104, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_125) node _io_out_c_self_rec_rawIn_normDist_T_127 = mux(_io_out_c_self_rec_rawIn_normDist_T_105, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_126) node _io_out_c_self_rec_rawIn_normDist_T_128 = mux(_io_out_c_self_rec_rawIn_normDist_T_106, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_127) node _io_out_c_self_rec_rawIn_normDist_T_129 = mux(_io_out_c_self_rec_rawIn_normDist_T_107, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_128) node _io_out_c_self_rec_rawIn_normDist_T_130 = mux(_io_out_c_self_rec_rawIn_normDist_T_108, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_129) node _io_out_c_self_rec_rawIn_normDist_T_131 = mux(_io_out_c_self_rec_rawIn_normDist_T_109, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_130) node io_out_c_self_rec_rawIn_normDist_2 = mux(_io_out_c_self_rec_rawIn_normDist_T_110, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_131) node _io_out_c_self_rec_rawIn_subnormFract_T_4 = dshl(io_out_c_self_rec_rawIn_fractIn_2, io_out_c_self_rec_rawIn_normDist_2) node _io_out_c_self_rec_rawIn_subnormFract_T_5 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_4, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_2 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_5, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_10 = xor(io_out_c_self_rec_rawIn_normDist_2, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_11 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, _io_out_c_self_rec_rawIn_adjustedExp_T_10, io_out_c_self_rec_rawIn_expIn_2) node _io_out_c_self_rec_rawIn_adjustedExp_T_12 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_12) node _io_out_c_self_rec_rawIn_adjustedExp_T_14 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_11, _io_out_c_self_rec_rawIn_adjustedExp_T_13) node io_out_c_self_rec_rawIn_adjustedExp_2 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_14, 1) node io_out_c_self_rec_rawIn_isZero_2 = and(io_out_c_self_rec_rawIn_isZeroExpIn_2, io_out_c_self_rec_rawIn_isZeroFractIn_2) node _io_out_c_self_rec_rawIn_isSpecial_T_2 = bits(io_out_c_self_rec_rawIn_adjustedExp_2, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_2 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_4 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_5 = and(io_out_c_self_rec_rawIn_isSpecial_2, _io_out_c_self_rec_rawIn_out_isNaN_T_4) connect io_out_c_self_rec_rawIn_2.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_5 node _io_out_c_self_rec_rawIn_out_isInf_T_2 = and(io_out_c_self_rec_rawIn_isSpecial_2, io_out_c_self_rec_rawIn_isZeroFractIn_2) connect io_out_c_self_rec_rawIn_2.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_2 connect io_out_c_self_rec_rawIn_2.isZero, io_out_c_self_rec_rawIn_isZero_2 connect io_out_c_self_rec_rawIn_2.sign, io_out_c_self_rec_rawIn_sign_2 node _io_out_c_self_rec_rawIn_out_sExp_T_4 = bits(io_out_c_self_rec_rawIn_adjustedExp_2, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_5 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_4) connect io_out_c_self_rec_rawIn_2.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_5 node _io_out_c_self_rec_rawIn_out_sig_T_8 = eq(io_out_c_self_rec_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_8) node _io_out_c_self_rec_rawIn_out_sig_T_10 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_2, io_out_c_self_rec_rawIn_subnormFract_2, io_out_c_self_rec_rawIn_fractIn_2) node _io_out_c_self_rec_rawIn_out_sig_T_11 = cat(_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10) connect io_out_c_self_rec_rawIn_2.sig, _io_out_c_self_rec_rawIn_out_sig_T_11 node _io_out_c_self_rec_T_16 = bits(io_out_c_self_rec_rawIn_2.sExp, 8, 6) node _io_out_c_self_rec_T_17 = mux(io_out_c_self_rec_rawIn_2.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_16) node _io_out_c_self_rec_T_18 = mux(io_out_c_self_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_19 = or(_io_out_c_self_rec_T_17, _io_out_c_self_rec_T_18) node _io_out_c_self_rec_T_20 = cat(io_out_c_self_rec_rawIn_2.sign, _io_out_c_self_rec_T_19) node _io_out_c_self_rec_T_21 = bits(io_out_c_self_rec_rawIn_2.sExp, 5, 0) node _io_out_c_self_rec_T_22 = cat(_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21) node _io_out_c_self_rec_T_23 = bits(io_out_c_self_rec_rawIn_2.sig, 22, 0) node io_out_c_self_rec_2 = cat(_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23) wire io_out_c_shift_exp_1 : UInt<8> node _io_out_c_shift_exp_T_2 = sub(UInt<7>(0h7f), shift_offset) node _io_out_c_shift_exp_T_3 = tail(_io_out_c_shift_exp_T_2, 1) connect io_out_c_shift_exp_1, _io_out_c_shift_exp_T_3 node io_out_c_shift_fn_hi_1 = cat(UInt<1>(0h0), io_out_c_shift_exp_1) node io_out_c_shift_fn_1 = cat(io_out_c_shift_fn_hi_1, UInt<23>(0h0)) node io_out_c_shift_rec_rawIn_sign_1 = bits(io_out_c_shift_fn_1, 31, 31) node io_out_c_shift_rec_rawIn_expIn_1 = bits(io_out_c_shift_fn_1, 30, 23) node io_out_c_shift_rec_rawIn_fractIn_1 = bits(io_out_c_shift_fn_1, 22, 0) node io_out_c_shift_rec_rawIn_isZeroExpIn_1 = eq(io_out_c_shift_rec_rawIn_expIn_1, UInt<1>(0h0)) node io_out_c_shift_rec_rawIn_isZeroFractIn_1 = eq(io_out_c_shift_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_normDist_T_44 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 0, 0) node _io_out_c_shift_rec_rawIn_normDist_T_45 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 1, 1) node _io_out_c_shift_rec_rawIn_normDist_T_46 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 2, 2) node _io_out_c_shift_rec_rawIn_normDist_T_47 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 3, 3) node _io_out_c_shift_rec_rawIn_normDist_T_48 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 4, 4) node _io_out_c_shift_rec_rawIn_normDist_T_49 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 5, 5) node _io_out_c_shift_rec_rawIn_normDist_T_50 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 6, 6) node _io_out_c_shift_rec_rawIn_normDist_T_51 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 7, 7) node _io_out_c_shift_rec_rawIn_normDist_T_52 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 8, 8) node _io_out_c_shift_rec_rawIn_normDist_T_53 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 9, 9) node _io_out_c_shift_rec_rawIn_normDist_T_54 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 10, 10) node _io_out_c_shift_rec_rawIn_normDist_T_55 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 11, 11) node _io_out_c_shift_rec_rawIn_normDist_T_56 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 12, 12) node _io_out_c_shift_rec_rawIn_normDist_T_57 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 13, 13) node _io_out_c_shift_rec_rawIn_normDist_T_58 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 14, 14) node _io_out_c_shift_rec_rawIn_normDist_T_59 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 15, 15) node _io_out_c_shift_rec_rawIn_normDist_T_60 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 16, 16) node _io_out_c_shift_rec_rawIn_normDist_T_61 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 17, 17) node _io_out_c_shift_rec_rawIn_normDist_T_62 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 18, 18) node _io_out_c_shift_rec_rawIn_normDist_T_63 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 19, 19) node _io_out_c_shift_rec_rawIn_normDist_T_64 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 20, 20) node _io_out_c_shift_rec_rawIn_normDist_T_65 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 21, 21) node _io_out_c_shift_rec_rawIn_normDist_T_66 = bits(io_out_c_shift_rec_rawIn_fractIn_1, 22, 22) node _io_out_c_shift_rec_rawIn_normDist_T_67 = mux(_io_out_c_shift_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_shift_rec_rawIn_normDist_T_68 = mux(_io_out_c_shift_rec_rawIn_normDist_T_46, UInt<5>(0h14), _io_out_c_shift_rec_rawIn_normDist_T_67) node _io_out_c_shift_rec_rawIn_normDist_T_69 = mux(_io_out_c_shift_rec_rawIn_normDist_T_47, UInt<5>(0h13), _io_out_c_shift_rec_rawIn_normDist_T_68) node _io_out_c_shift_rec_rawIn_normDist_T_70 = mux(_io_out_c_shift_rec_rawIn_normDist_T_48, UInt<5>(0h12), _io_out_c_shift_rec_rawIn_normDist_T_69) node _io_out_c_shift_rec_rawIn_normDist_T_71 = mux(_io_out_c_shift_rec_rawIn_normDist_T_49, UInt<5>(0h11), _io_out_c_shift_rec_rawIn_normDist_T_70) node _io_out_c_shift_rec_rawIn_normDist_T_72 = mux(_io_out_c_shift_rec_rawIn_normDist_T_50, UInt<5>(0h10), _io_out_c_shift_rec_rawIn_normDist_T_71) node _io_out_c_shift_rec_rawIn_normDist_T_73 = mux(_io_out_c_shift_rec_rawIn_normDist_T_51, UInt<4>(0hf), _io_out_c_shift_rec_rawIn_normDist_T_72) node _io_out_c_shift_rec_rawIn_normDist_T_74 = mux(_io_out_c_shift_rec_rawIn_normDist_T_52, UInt<4>(0he), _io_out_c_shift_rec_rawIn_normDist_T_73) node _io_out_c_shift_rec_rawIn_normDist_T_75 = mux(_io_out_c_shift_rec_rawIn_normDist_T_53, UInt<4>(0hd), _io_out_c_shift_rec_rawIn_normDist_T_74) node _io_out_c_shift_rec_rawIn_normDist_T_76 = mux(_io_out_c_shift_rec_rawIn_normDist_T_54, UInt<4>(0hc), _io_out_c_shift_rec_rawIn_normDist_T_75) node _io_out_c_shift_rec_rawIn_normDist_T_77 = mux(_io_out_c_shift_rec_rawIn_normDist_T_55, UInt<4>(0hb), _io_out_c_shift_rec_rawIn_normDist_T_76) node _io_out_c_shift_rec_rawIn_normDist_T_78 = mux(_io_out_c_shift_rec_rawIn_normDist_T_56, UInt<4>(0ha), _io_out_c_shift_rec_rawIn_normDist_T_77) node _io_out_c_shift_rec_rawIn_normDist_T_79 = mux(_io_out_c_shift_rec_rawIn_normDist_T_57, UInt<4>(0h9), _io_out_c_shift_rec_rawIn_normDist_T_78) node _io_out_c_shift_rec_rawIn_normDist_T_80 = mux(_io_out_c_shift_rec_rawIn_normDist_T_58, UInt<4>(0h8), _io_out_c_shift_rec_rawIn_normDist_T_79) node _io_out_c_shift_rec_rawIn_normDist_T_81 = mux(_io_out_c_shift_rec_rawIn_normDist_T_59, UInt<3>(0h7), _io_out_c_shift_rec_rawIn_normDist_T_80) node _io_out_c_shift_rec_rawIn_normDist_T_82 = mux(_io_out_c_shift_rec_rawIn_normDist_T_60, UInt<3>(0h6), _io_out_c_shift_rec_rawIn_normDist_T_81) node _io_out_c_shift_rec_rawIn_normDist_T_83 = mux(_io_out_c_shift_rec_rawIn_normDist_T_61, UInt<3>(0h5), _io_out_c_shift_rec_rawIn_normDist_T_82) node _io_out_c_shift_rec_rawIn_normDist_T_84 = mux(_io_out_c_shift_rec_rawIn_normDist_T_62, UInt<3>(0h4), _io_out_c_shift_rec_rawIn_normDist_T_83) node _io_out_c_shift_rec_rawIn_normDist_T_85 = mux(_io_out_c_shift_rec_rawIn_normDist_T_63, UInt<2>(0h3), _io_out_c_shift_rec_rawIn_normDist_T_84) node _io_out_c_shift_rec_rawIn_normDist_T_86 = mux(_io_out_c_shift_rec_rawIn_normDist_T_64, UInt<2>(0h2), _io_out_c_shift_rec_rawIn_normDist_T_85) node _io_out_c_shift_rec_rawIn_normDist_T_87 = mux(_io_out_c_shift_rec_rawIn_normDist_T_65, UInt<1>(0h1), _io_out_c_shift_rec_rawIn_normDist_T_86) node io_out_c_shift_rec_rawIn_normDist_1 = mux(_io_out_c_shift_rec_rawIn_normDist_T_66, UInt<1>(0h0), _io_out_c_shift_rec_rawIn_normDist_T_87) node _io_out_c_shift_rec_rawIn_subnormFract_T_2 = dshl(io_out_c_shift_rec_rawIn_fractIn_1, io_out_c_shift_rec_rawIn_normDist_1) node _io_out_c_shift_rec_rawIn_subnormFract_T_3 = bits(_io_out_c_shift_rec_rawIn_subnormFract_T_2, 21, 0) node io_out_c_shift_rec_rawIn_subnormFract_1 = shl(_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1) node _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = xor(io_out_c_shift_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, _io_out_c_shift_rec_rawIn_adjustedExp_T_5, io_out_c_shift_rec_rawIn_expIn_1) node _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _io_out_c_shift_rec_rawIn_adjustedExp_T_7) node _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = add(_io_out_c_shift_rec_rawIn_adjustedExp_T_6, _io_out_c_shift_rec_rawIn_adjustedExp_T_8) node io_out_c_shift_rec_rawIn_adjustedExp_1 = tail(_io_out_c_shift_rec_rawIn_adjustedExp_T_9, 1) node io_out_c_shift_rec_rawIn_isZero_1 = and(io_out_c_shift_rec_rawIn_isZeroExpIn_1, io_out_c_shift_rec_rawIn_isZeroFractIn_1) node _io_out_c_shift_rec_rawIn_isSpecial_T_1 = bits(io_out_c_shift_rec_rawIn_adjustedExp_1, 8, 7) node io_out_c_shift_rec_rawIn_isSpecial_1 = eq(_io_out_c_shift_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_c_shift_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = eq(io_out_c_shift_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = and(io_out_c_shift_rec_rawIn_isSpecial_1, _io_out_c_shift_rec_rawIn_out_isNaN_T_2) connect io_out_c_shift_rec_rawIn_1.isNaN, _io_out_c_shift_rec_rawIn_out_isNaN_T_3 node _io_out_c_shift_rec_rawIn_out_isInf_T_1 = and(io_out_c_shift_rec_rawIn_isSpecial_1, io_out_c_shift_rec_rawIn_isZeroFractIn_1) connect io_out_c_shift_rec_rawIn_1.isInf, _io_out_c_shift_rec_rawIn_out_isInf_T_1 connect io_out_c_shift_rec_rawIn_1.isZero, io_out_c_shift_rec_rawIn_isZero_1 connect io_out_c_shift_rec_rawIn_1.sign, io_out_c_shift_rec_rawIn_sign_1 node _io_out_c_shift_rec_rawIn_out_sExp_T_2 = bits(io_out_c_shift_rec_rawIn_adjustedExp_1, 8, 0) node _io_out_c_shift_rec_rawIn_out_sExp_T_3 = cvt(_io_out_c_shift_rec_rawIn_out_sExp_T_2) connect io_out_c_shift_rec_rawIn_1.sExp, _io_out_c_shift_rec_rawIn_out_sExp_T_3 node _io_out_c_shift_rec_rawIn_out_sig_T_4 = eq(io_out_c_shift_rec_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_c_shift_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_c_shift_rec_rawIn_out_sig_T_4) node _io_out_c_shift_rec_rawIn_out_sig_T_6 = mux(io_out_c_shift_rec_rawIn_isZeroExpIn_1, io_out_c_shift_rec_rawIn_subnormFract_1, io_out_c_shift_rec_rawIn_fractIn_1) node _io_out_c_shift_rec_rawIn_out_sig_T_7 = cat(_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6) connect io_out_c_shift_rec_rawIn_1.sig, _io_out_c_shift_rec_rawIn_out_sig_T_7 node _io_out_c_shift_rec_T_8 = bits(io_out_c_shift_rec_rawIn_1.sExp, 8, 6) node _io_out_c_shift_rec_T_9 = mux(io_out_c_shift_rec_rawIn_1.isZero, UInt<3>(0h0), _io_out_c_shift_rec_T_8) node _io_out_c_shift_rec_T_10 = mux(io_out_c_shift_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_shift_rec_T_11 = or(_io_out_c_shift_rec_T_9, _io_out_c_shift_rec_T_10) node _io_out_c_shift_rec_T_12 = cat(io_out_c_shift_rec_rawIn_1.sign, _io_out_c_shift_rec_T_11) node _io_out_c_shift_rec_T_13 = bits(io_out_c_shift_rec_rawIn_1.sExp, 5, 0) node _io_out_c_shift_rec_T_14 = cat(_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13) node _io_out_c_shift_rec_T_15 = bits(io_out_c_shift_rec_rawIn_1.sig, 22, 0) node io_out_c_shift_rec_1 = cat(_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15) node _io_out_c_T_4 = neq(io_out_c_shift_exp_1, UInt<1>(0h0)) node _io_out_c_T_5 = asUInt(reset) node _io_out_c_T_6 = eq(_io_out_c_T_5, UInt<1>(0h0)) when _io_out_c_T_6 : node _io_out_c_T_7 = eq(_io_out_c_T_4, UInt<1>(0h0)) when _io_out_c_T_7 : printf(clock, UInt<1>(0h1), "Assertion failed: scaling by denormalized numbers is not currently supported\n at Arithmetic.scala:447 assert(shift_exp =/= 0.U, \"scaling by denormalized numbers is not currently supported\")\n") : io_out_c_printf_1 assert(clock, _io_out_c_T_4, UInt<1>(0h1), "") : io_out_c_assert_1 inst io_out_c_muladder_1 of MulRecFN_35 connect io_out_c_muladder_1.io.roundingMode, UInt<3>(0h0) connect io_out_c_muladder_1.io.detectTininess, UInt<1>(0h1) connect io_out_c_muladder_1.io.a, io_out_c_self_rec_2 connect io_out_c_muladder_1.io.b, io_out_c_shift_rec_1 wire io_out_c_result_2 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_2 = bits(io_out_c_muladder_1.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_2 = bits(io_out_c_result_bits_rawIn_exp_2, 8, 6) node io_out_c_result_bits_rawIn_isZero_2 = eq(_io_out_c_result_bits_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_2 = bits(io_out_c_result_bits_rawIn_exp_2, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_2 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_4 = bits(io_out_c_result_bits_rawIn_exp_2, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_5 = and(io_out_c_result_bits_rawIn_isSpecial_2, _io_out_c_result_bits_rawIn_out_isNaN_T_4) connect io_out_c_result_bits_rawIn_2.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_5 node _io_out_c_result_bits_rawIn_out_isInf_T_6 = bits(io_out_c_result_bits_rawIn_exp_2, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_7 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_8 = and(io_out_c_result_bits_rawIn_isSpecial_2, _io_out_c_result_bits_rawIn_out_isInf_T_7) connect io_out_c_result_bits_rawIn_2.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_8 connect io_out_c_result_bits_rawIn_2.isZero, io_out_c_result_bits_rawIn_isZero_2 node _io_out_c_result_bits_rawIn_out_sign_T_2 = bits(io_out_c_muladder_1.io.out, 32, 32) connect io_out_c_result_bits_rawIn_2.sign, _io_out_c_result_bits_rawIn_out_sign_T_2 node _io_out_c_result_bits_rawIn_out_sExp_T_2 = cvt(io_out_c_result_bits_rawIn_exp_2) connect io_out_c_result_bits_rawIn_2.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_2 node _io_out_c_result_bits_rawIn_out_sig_T_8 = eq(io_out_c_result_bits_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_8) node _io_out_c_result_bits_rawIn_out_sig_T_10 = bits(io_out_c_muladder_1.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_11 = cat(_io_out_c_result_bits_rawIn_out_sig_T_9, _io_out_c_result_bits_rawIn_out_sig_T_10) connect io_out_c_result_bits_rawIn_2.sig, _io_out_c_result_bits_rawIn_out_sig_T_11 node io_out_c_result_bits_isSubnormal_2 = lt(io_out_c_result_bits_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_4 = bits(io_out_c_result_bits_rawIn_2.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_4) node io_out_c_result_bits_denormShiftDist_2 = tail(_io_out_c_result_bits_denormShiftDist_T_5, 1) node _io_out_c_result_bits_denormFract_T_4 = shr(io_out_c_result_bits_rawIn_2.sig, 1) node _io_out_c_result_bits_denormFract_T_5 = dshr(_io_out_c_result_bits_denormFract_T_4, io_out_c_result_bits_denormShiftDist_2) node io_out_c_result_bits_denormFract_2 = bits(_io_out_c_result_bits_denormFract_T_5, 22, 0) node _io_out_c_result_bits_expOut_T_12 = bits(io_out_c_result_bits_rawIn_2.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_13 = sub(_io_out_c_result_bits_expOut_T_12, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_14 = tail(_io_out_c_result_bits_expOut_T_13, 1) node _io_out_c_result_bits_expOut_T_15 = mux(io_out_c_result_bits_isSubnormal_2, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_14) node _io_out_c_result_bits_expOut_T_16 = or(io_out_c_result_bits_rawIn_2.isNaN, io_out_c_result_bits_rawIn_2.isInf) node _io_out_c_result_bits_expOut_T_17 = mux(_io_out_c_result_bits_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_2 = or(_io_out_c_result_bits_expOut_T_15, _io_out_c_result_bits_expOut_T_17) node _io_out_c_result_bits_fractOut_T_4 = bits(io_out_c_result_bits_rawIn_2.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_5 = mux(io_out_c_result_bits_rawIn_2.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_4) node io_out_c_result_bits_fractOut_2 = mux(io_out_c_result_bits_isSubnormal_2, io_out_c_result_bits_denormFract_2, _io_out_c_result_bits_fractOut_T_5) node io_out_c_result_bits_hi_2 = cat(io_out_c_result_bits_rawIn_2.sign, io_out_c_result_bits_expOut_2) node _io_out_c_result_bits_T_2 = cat(io_out_c_result_bits_hi_2, io_out_c_result_bits_fractOut_2) connect io_out_c_result_2.bits, _io_out_c_result_bits_T_2 node io_out_c_self_rec_rawIn_sign_3 = bits(io_out_c_result_2.bits, 31, 31) node io_out_c_self_rec_rawIn_expIn_3 = bits(io_out_c_result_2.bits, 30, 23) node io_out_c_self_rec_rawIn_fractIn_3 = bits(io_out_c_result_2.bits, 22, 0) node io_out_c_self_rec_rawIn_isZeroExpIn_3 = eq(io_out_c_self_rec_rawIn_expIn_3, UInt<1>(0h0)) node io_out_c_self_rec_rawIn_isZeroFractIn_3 = eq(io_out_c_self_rec_rawIn_fractIn_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_normDist_T_132 = bits(io_out_c_self_rec_rawIn_fractIn_3, 0, 0) node _io_out_c_self_rec_rawIn_normDist_T_133 = bits(io_out_c_self_rec_rawIn_fractIn_3, 1, 1) node _io_out_c_self_rec_rawIn_normDist_T_134 = bits(io_out_c_self_rec_rawIn_fractIn_3, 2, 2) node _io_out_c_self_rec_rawIn_normDist_T_135 = bits(io_out_c_self_rec_rawIn_fractIn_3, 3, 3) node _io_out_c_self_rec_rawIn_normDist_T_136 = bits(io_out_c_self_rec_rawIn_fractIn_3, 4, 4) node _io_out_c_self_rec_rawIn_normDist_T_137 = bits(io_out_c_self_rec_rawIn_fractIn_3, 5, 5) node _io_out_c_self_rec_rawIn_normDist_T_138 = bits(io_out_c_self_rec_rawIn_fractIn_3, 6, 6) node _io_out_c_self_rec_rawIn_normDist_T_139 = bits(io_out_c_self_rec_rawIn_fractIn_3, 7, 7) node _io_out_c_self_rec_rawIn_normDist_T_140 = bits(io_out_c_self_rec_rawIn_fractIn_3, 8, 8) node _io_out_c_self_rec_rawIn_normDist_T_141 = bits(io_out_c_self_rec_rawIn_fractIn_3, 9, 9) node _io_out_c_self_rec_rawIn_normDist_T_142 = bits(io_out_c_self_rec_rawIn_fractIn_3, 10, 10) node _io_out_c_self_rec_rawIn_normDist_T_143 = bits(io_out_c_self_rec_rawIn_fractIn_3, 11, 11) node _io_out_c_self_rec_rawIn_normDist_T_144 = bits(io_out_c_self_rec_rawIn_fractIn_3, 12, 12) node _io_out_c_self_rec_rawIn_normDist_T_145 = bits(io_out_c_self_rec_rawIn_fractIn_3, 13, 13) node _io_out_c_self_rec_rawIn_normDist_T_146 = bits(io_out_c_self_rec_rawIn_fractIn_3, 14, 14) node _io_out_c_self_rec_rawIn_normDist_T_147 = bits(io_out_c_self_rec_rawIn_fractIn_3, 15, 15) node _io_out_c_self_rec_rawIn_normDist_T_148 = bits(io_out_c_self_rec_rawIn_fractIn_3, 16, 16) node _io_out_c_self_rec_rawIn_normDist_T_149 = bits(io_out_c_self_rec_rawIn_fractIn_3, 17, 17) node _io_out_c_self_rec_rawIn_normDist_T_150 = bits(io_out_c_self_rec_rawIn_fractIn_3, 18, 18) node _io_out_c_self_rec_rawIn_normDist_T_151 = bits(io_out_c_self_rec_rawIn_fractIn_3, 19, 19) node _io_out_c_self_rec_rawIn_normDist_T_152 = bits(io_out_c_self_rec_rawIn_fractIn_3, 20, 20) node _io_out_c_self_rec_rawIn_normDist_T_153 = bits(io_out_c_self_rec_rawIn_fractIn_3, 21, 21) node _io_out_c_self_rec_rawIn_normDist_T_154 = bits(io_out_c_self_rec_rawIn_fractIn_3, 22, 22) node _io_out_c_self_rec_rawIn_normDist_T_155 = mux(_io_out_c_self_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16)) node _io_out_c_self_rec_rawIn_normDist_T_156 = mux(_io_out_c_self_rec_rawIn_normDist_T_134, UInt<5>(0h14), _io_out_c_self_rec_rawIn_normDist_T_155) node _io_out_c_self_rec_rawIn_normDist_T_157 = mux(_io_out_c_self_rec_rawIn_normDist_T_135, UInt<5>(0h13), _io_out_c_self_rec_rawIn_normDist_T_156) node _io_out_c_self_rec_rawIn_normDist_T_158 = mux(_io_out_c_self_rec_rawIn_normDist_T_136, UInt<5>(0h12), _io_out_c_self_rec_rawIn_normDist_T_157) node _io_out_c_self_rec_rawIn_normDist_T_159 = mux(_io_out_c_self_rec_rawIn_normDist_T_137, UInt<5>(0h11), _io_out_c_self_rec_rawIn_normDist_T_158) node _io_out_c_self_rec_rawIn_normDist_T_160 = mux(_io_out_c_self_rec_rawIn_normDist_T_138, UInt<5>(0h10), _io_out_c_self_rec_rawIn_normDist_T_159) node _io_out_c_self_rec_rawIn_normDist_T_161 = mux(_io_out_c_self_rec_rawIn_normDist_T_139, UInt<4>(0hf), _io_out_c_self_rec_rawIn_normDist_T_160) node _io_out_c_self_rec_rawIn_normDist_T_162 = mux(_io_out_c_self_rec_rawIn_normDist_T_140, UInt<4>(0he), _io_out_c_self_rec_rawIn_normDist_T_161) node _io_out_c_self_rec_rawIn_normDist_T_163 = mux(_io_out_c_self_rec_rawIn_normDist_T_141, UInt<4>(0hd), _io_out_c_self_rec_rawIn_normDist_T_162) node _io_out_c_self_rec_rawIn_normDist_T_164 = mux(_io_out_c_self_rec_rawIn_normDist_T_142, UInt<4>(0hc), _io_out_c_self_rec_rawIn_normDist_T_163) node _io_out_c_self_rec_rawIn_normDist_T_165 = mux(_io_out_c_self_rec_rawIn_normDist_T_143, UInt<4>(0hb), _io_out_c_self_rec_rawIn_normDist_T_164) node _io_out_c_self_rec_rawIn_normDist_T_166 = mux(_io_out_c_self_rec_rawIn_normDist_T_144, UInt<4>(0ha), _io_out_c_self_rec_rawIn_normDist_T_165) node _io_out_c_self_rec_rawIn_normDist_T_167 = mux(_io_out_c_self_rec_rawIn_normDist_T_145, UInt<4>(0h9), _io_out_c_self_rec_rawIn_normDist_T_166) node _io_out_c_self_rec_rawIn_normDist_T_168 = mux(_io_out_c_self_rec_rawIn_normDist_T_146, UInt<4>(0h8), _io_out_c_self_rec_rawIn_normDist_T_167) node _io_out_c_self_rec_rawIn_normDist_T_169 = mux(_io_out_c_self_rec_rawIn_normDist_T_147, UInt<3>(0h7), _io_out_c_self_rec_rawIn_normDist_T_168) node _io_out_c_self_rec_rawIn_normDist_T_170 = mux(_io_out_c_self_rec_rawIn_normDist_T_148, UInt<3>(0h6), _io_out_c_self_rec_rawIn_normDist_T_169) node _io_out_c_self_rec_rawIn_normDist_T_171 = mux(_io_out_c_self_rec_rawIn_normDist_T_149, UInt<3>(0h5), _io_out_c_self_rec_rawIn_normDist_T_170) node _io_out_c_self_rec_rawIn_normDist_T_172 = mux(_io_out_c_self_rec_rawIn_normDist_T_150, UInt<3>(0h4), _io_out_c_self_rec_rawIn_normDist_T_171) node _io_out_c_self_rec_rawIn_normDist_T_173 = mux(_io_out_c_self_rec_rawIn_normDist_T_151, UInt<2>(0h3), _io_out_c_self_rec_rawIn_normDist_T_172) node _io_out_c_self_rec_rawIn_normDist_T_174 = mux(_io_out_c_self_rec_rawIn_normDist_T_152, UInt<2>(0h2), _io_out_c_self_rec_rawIn_normDist_T_173) node _io_out_c_self_rec_rawIn_normDist_T_175 = mux(_io_out_c_self_rec_rawIn_normDist_T_153, UInt<1>(0h1), _io_out_c_self_rec_rawIn_normDist_T_174) node io_out_c_self_rec_rawIn_normDist_3 = mux(_io_out_c_self_rec_rawIn_normDist_T_154, UInt<1>(0h0), _io_out_c_self_rec_rawIn_normDist_T_175) node _io_out_c_self_rec_rawIn_subnormFract_T_6 = dshl(io_out_c_self_rec_rawIn_fractIn_3, io_out_c_self_rec_rawIn_normDist_3) node _io_out_c_self_rec_rawIn_subnormFract_T_7 = bits(_io_out_c_self_rec_rawIn_subnormFract_T_6, 21, 0) node io_out_c_self_rec_rawIn_subnormFract_3 = shl(_io_out_c_self_rec_rawIn_subnormFract_T_7, 1) node _io_out_c_self_rec_rawIn_adjustedExp_T_15 = xor(io_out_c_self_rec_rawIn_normDist_3, UInt<9>(0h1ff)) node _io_out_c_self_rec_rawIn_adjustedExp_T_16 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, _io_out_c_self_rec_rawIn_adjustedExp_T_15, io_out_c_self_rec_rawIn_expIn_3) node _io_out_c_self_rec_rawIn_adjustedExp_T_17 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1)) node _io_out_c_self_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _io_out_c_self_rec_rawIn_adjustedExp_T_17) node _io_out_c_self_rec_rawIn_adjustedExp_T_19 = add(_io_out_c_self_rec_rawIn_adjustedExp_T_16, _io_out_c_self_rec_rawIn_adjustedExp_T_18) node io_out_c_self_rec_rawIn_adjustedExp_3 = tail(_io_out_c_self_rec_rawIn_adjustedExp_T_19, 1) node io_out_c_self_rec_rawIn_isZero_3 = and(io_out_c_self_rec_rawIn_isZeroExpIn_3, io_out_c_self_rec_rawIn_isZeroFractIn_3) node _io_out_c_self_rec_rawIn_isSpecial_T_3 = bits(io_out_c_self_rec_rawIn_adjustedExp_3, 8, 7) node io_out_c_self_rec_rawIn_isSpecial_3 = eq(_io_out_c_self_rec_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire io_out_c_self_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_self_rec_rawIn_out_isNaN_T_6 = eq(io_out_c_self_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_isNaN_T_7 = and(io_out_c_self_rec_rawIn_isSpecial_3, _io_out_c_self_rec_rawIn_out_isNaN_T_6) connect io_out_c_self_rec_rawIn_3.isNaN, _io_out_c_self_rec_rawIn_out_isNaN_T_7 node _io_out_c_self_rec_rawIn_out_isInf_T_3 = and(io_out_c_self_rec_rawIn_isSpecial_3, io_out_c_self_rec_rawIn_isZeroFractIn_3) connect io_out_c_self_rec_rawIn_3.isInf, _io_out_c_self_rec_rawIn_out_isInf_T_3 connect io_out_c_self_rec_rawIn_3.isZero, io_out_c_self_rec_rawIn_isZero_3 connect io_out_c_self_rec_rawIn_3.sign, io_out_c_self_rec_rawIn_sign_3 node _io_out_c_self_rec_rawIn_out_sExp_T_6 = bits(io_out_c_self_rec_rawIn_adjustedExp_3, 8, 0) node _io_out_c_self_rec_rawIn_out_sExp_T_7 = cvt(_io_out_c_self_rec_rawIn_out_sExp_T_6) connect io_out_c_self_rec_rawIn_3.sExp, _io_out_c_self_rec_rawIn_out_sExp_T_7 node _io_out_c_self_rec_rawIn_out_sig_T_12 = eq(io_out_c_self_rec_rawIn_isZero_3, UInt<1>(0h0)) node _io_out_c_self_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _io_out_c_self_rec_rawIn_out_sig_T_12) node _io_out_c_self_rec_rawIn_out_sig_T_14 = mux(io_out_c_self_rec_rawIn_isZeroExpIn_3, io_out_c_self_rec_rawIn_subnormFract_3, io_out_c_self_rec_rawIn_fractIn_3) node _io_out_c_self_rec_rawIn_out_sig_T_15 = cat(_io_out_c_self_rec_rawIn_out_sig_T_13, _io_out_c_self_rec_rawIn_out_sig_T_14) connect io_out_c_self_rec_rawIn_3.sig, _io_out_c_self_rec_rawIn_out_sig_T_15 node _io_out_c_self_rec_T_24 = bits(io_out_c_self_rec_rawIn_3.sExp, 8, 6) node _io_out_c_self_rec_T_25 = mux(io_out_c_self_rec_rawIn_3.isZero, UInt<3>(0h0), _io_out_c_self_rec_T_24) node _io_out_c_self_rec_T_26 = mux(io_out_c_self_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _io_out_c_self_rec_T_27 = or(_io_out_c_self_rec_T_25, _io_out_c_self_rec_T_26) node _io_out_c_self_rec_T_28 = cat(io_out_c_self_rec_rawIn_3.sign, _io_out_c_self_rec_T_27) node _io_out_c_self_rec_T_29 = bits(io_out_c_self_rec_rawIn_3.sExp, 5, 0) node _io_out_c_self_rec_T_30 = cat(_io_out_c_self_rec_T_28, _io_out_c_self_rec_T_29) node _io_out_c_self_rec_T_31 = bits(io_out_c_self_rec_rawIn_3.sig, 22, 0) node io_out_c_self_rec_3 = cat(_io_out_c_self_rec_T_30, _io_out_c_self_rec_T_31) inst io_out_c_resizer_1 of RecFNToRecFN_178 connect io_out_c_resizer_1.io.in, io_out_c_self_rec_3 connect io_out_c_resizer_1.io.roundingMode, UInt<3>(0h0) connect io_out_c_resizer_1.io.detectTininess, UInt<1>(0h1) wire io_out_c_result_3 : { bits : UInt<32>} node io_out_c_result_bits_rawIn_exp_3 = bits(io_out_c_resizer_1.io.out, 31, 23) node _io_out_c_result_bits_rawIn_isZero_T_3 = bits(io_out_c_result_bits_rawIn_exp_3, 8, 6) node io_out_c_result_bits_rawIn_isZero_3 = eq(_io_out_c_result_bits_rawIn_isZero_T_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_isSpecial_T_3 = bits(io_out_c_result_bits_rawIn_exp_3, 8, 7) node io_out_c_result_bits_rawIn_isSpecial_3 = eq(_io_out_c_result_bits_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire io_out_c_result_bits_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_c_result_bits_rawIn_out_isNaN_T_6 = bits(io_out_c_result_bits_rawIn_exp_3, 6, 6) node _io_out_c_result_bits_rawIn_out_isNaN_T_7 = and(io_out_c_result_bits_rawIn_isSpecial_3, _io_out_c_result_bits_rawIn_out_isNaN_T_6) connect io_out_c_result_bits_rawIn_3.isNaN, _io_out_c_result_bits_rawIn_out_isNaN_T_7 node _io_out_c_result_bits_rawIn_out_isInf_T_9 = bits(io_out_c_result_bits_rawIn_exp_3, 6, 6) node _io_out_c_result_bits_rawIn_out_isInf_T_10 = eq(_io_out_c_result_bits_rawIn_out_isInf_T_9, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_isInf_T_11 = and(io_out_c_result_bits_rawIn_isSpecial_3, _io_out_c_result_bits_rawIn_out_isInf_T_10) connect io_out_c_result_bits_rawIn_3.isInf, _io_out_c_result_bits_rawIn_out_isInf_T_11 connect io_out_c_result_bits_rawIn_3.isZero, io_out_c_result_bits_rawIn_isZero_3 node _io_out_c_result_bits_rawIn_out_sign_T_3 = bits(io_out_c_resizer_1.io.out, 32, 32) connect io_out_c_result_bits_rawIn_3.sign, _io_out_c_result_bits_rawIn_out_sign_T_3 node _io_out_c_result_bits_rawIn_out_sExp_T_3 = cvt(io_out_c_result_bits_rawIn_exp_3) connect io_out_c_result_bits_rawIn_3.sExp, _io_out_c_result_bits_rawIn_out_sExp_T_3 node _io_out_c_result_bits_rawIn_out_sig_T_12 = eq(io_out_c_result_bits_rawIn_isZero_3, UInt<1>(0h0)) node _io_out_c_result_bits_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _io_out_c_result_bits_rawIn_out_sig_T_12) node _io_out_c_result_bits_rawIn_out_sig_T_14 = bits(io_out_c_resizer_1.io.out, 22, 0) node _io_out_c_result_bits_rawIn_out_sig_T_15 = cat(_io_out_c_result_bits_rawIn_out_sig_T_13, _io_out_c_result_bits_rawIn_out_sig_T_14) connect io_out_c_result_bits_rawIn_3.sig, _io_out_c_result_bits_rawIn_out_sig_T_15 node io_out_c_result_bits_isSubnormal_3 = lt(io_out_c_result_bits_rawIn_3.sExp, asSInt(UInt<9>(0h82))) node _io_out_c_result_bits_denormShiftDist_T_6 = bits(io_out_c_result_bits_rawIn_3.sExp, 4, 0) node _io_out_c_result_bits_denormShiftDist_T_7 = sub(UInt<1>(0h1), _io_out_c_result_bits_denormShiftDist_T_6) node io_out_c_result_bits_denormShiftDist_3 = tail(_io_out_c_result_bits_denormShiftDist_T_7, 1) node _io_out_c_result_bits_denormFract_T_6 = shr(io_out_c_result_bits_rawIn_3.sig, 1) node _io_out_c_result_bits_denormFract_T_7 = dshr(_io_out_c_result_bits_denormFract_T_6, io_out_c_result_bits_denormShiftDist_3) node io_out_c_result_bits_denormFract_3 = bits(_io_out_c_result_bits_denormFract_T_7, 22, 0) node _io_out_c_result_bits_expOut_T_18 = bits(io_out_c_result_bits_rawIn_3.sExp, 7, 0) node _io_out_c_result_bits_expOut_T_19 = sub(_io_out_c_result_bits_expOut_T_18, UInt<8>(0h81)) node _io_out_c_result_bits_expOut_T_20 = tail(_io_out_c_result_bits_expOut_T_19, 1) node _io_out_c_result_bits_expOut_T_21 = mux(io_out_c_result_bits_isSubnormal_3, UInt<1>(0h0), _io_out_c_result_bits_expOut_T_20) node _io_out_c_result_bits_expOut_T_22 = or(io_out_c_result_bits_rawIn_3.isNaN, io_out_c_result_bits_rawIn_3.isInf) node _io_out_c_result_bits_expOut_T_23 = mux(_io_out_c_result_bits_expOut_T_22, UInt<8>(0hff), UInt<8>(0h0)) node io_out_c_result_bits_expOut_3 = or(_io_out_c_result_bits_expOut_T_21, _io_out_c_result_bits_expOut_T_23) node _io_out_c_result_bits_fractOut_T_6 = bits(io_out_c_result_bits_rawIn_3.sig, 22, 0) node _io_out_c_result_bits_fractOut_T_7 = mux(io_out_c_result_bits_rawIn_3.isInf, UInt<1>(0h0), _io_out_c_result_bits_fractOut_T_6) node io_out_c_result_bits_fractOut_3 = mux(io_out_c_result_bits_isSubnormal_3, io_out_c_result_bits_denormFract_3, _io_out_c_result_bits_fractOut_T_7) node io_out_c_result_bits_hi_3 = cat(io_out_c_result_bits_rawIn_3.sign, io_out_c_result_bits_expOut_3) node _io_out_c_result_bits_T_3 = cat(io_out_c_result_bits_hi_3, io_out_c_result_bits_fractOut_3) connect io_out_c_result_3.bits, _io_out_c_result_bits_T_3 connect io.out_c, io_out_c_result_3 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_2 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_3 : UInt<32> connect _mac_unit_io_in_b_WIRE_3, io.in_b.bits node _mac_unit_io_in_b_T_1 = bits(_mac_unit_io_in_b_WIRE_3, 31, 0) connect _mac_unit_io_in_b_WIRE_2.bits, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_2.bits connect mac_unit.io.in_c.bits, c1.bits connect c1, mac_unit.io.out_d node c2_self_rec_rawIn_sign = bits(io.in_d.bits, 31, 31) node c2_self_rec_rawIn_expIn = bits(io.in_d.bits, 30, 23) node c2_self_rec_rawIn_fractIn = bits(io.in_d.bits, 22, 0) node c2_self_rec_rawIn_isZeroExpIn = eq(c2_self_rec_rawIn_expIn, UInt<1>(0h0)) node c2_self_rec_rawIn_isZeroFractIn = eq(c2_self_rec_rawIn_fractIn, UInt<1>(0h0)) node _c2_self_rec_rawIn_normDist_T = bits(c2_self_rec_rawIn_fractIn, 0, 0) node _c2_self_rec_rawIn_normDist_T_1 = bits(c2_self_rec_rawIn_fractIn, 1, 1) node _c2_self_rec_rawIn_normDist_T_2 = bits(c2_self_rec_rawIn_fractIn, 2, 2) node _c2_self_rec_rawIn_normDist_T_3 = bits(c2_self_rec_rawIn_fractIn, 3, 3) node _c2_self_rec_rawIn_normDist_T_4 = bits(c2_self_rec_rawIn_fractIn, 4, 4) node _c2_self_rec_rawIn_normDist_T_5 = bits(c2_self_rec_rawIn_fractIn, 5, 5) node _c2_self_rec_rawIn_normDist_T_6 = bits(c2_self_rec_rawIn_fractIn, 6, 6) node _c2_self_rec_rawIn_normDist_T_7 = bits(c2_self_rec_rawIn_fractIn, 7, 7) node _c2_self_rec_rawIn_normDist_T_8 = bits(c2_self_rec_rawIn_fractIn, 8, 8) node _c2_self_rec_rawIn_normDist_T_9 = bits(c2_self_rec_rawIn_fractIn, 9, 9) node _c2_self_rec_rawIn_normDist_T_10 = bits(c2_self_rec_rawIn_fractIn, 10, 10) node _c2_self_rec_rawIn_normDist_T_11 = bits(c2_self_rec_rawIn_fractIn, 11, 11) node _c2_self_rec_rawIn_normDist_T_12 = bits(c2_self_rec_rawIn_fractIn, 12, 12) node _c2_self_rec_rawIn_normDist_T_13 = bits(c2_self_rec_rawIn_fractIn, 13, 13) node _c2_self_rec_rawIn_normDist_T_14 = bits(c2_self_rec_rawIn_fractIn, 14, 14) node _c2_self_rec_rawIn_normDist_T_15 = bits(c2_self_rec_rawIn_fractIn, 15, 15) node _c2_self_rec_rawIn_normDist_T_16 = bits(c2_self_rec_rawIn_fractIn, 16, 16) node _c2_self_rec_rawIn_normDist_T_17 = bits(c2_self_rec_rawIn_fractIn, 17, 17) node _c2_self_rec_rawIn_normDist_T_18 = bits(c2_self_rec_rawIn_fractIn, 18, 18) node _c2_self_rec_rawIn_normDist_T_19 = bits(c2_self_rec_rawIn_fractIn, 19, 19) node _c2_self_rec_rawIn_normDist_T_20 = bits(c2_self_rec_rawIn_fractIn, 20, 20) node _c2_self_rec_rawIn_normDist_T_21 = bits(c2_self_rec_rawIn_fractIn, 21, 21) node _c2_self_rec_rawIn_normDist_T_22 = bits(c2_self_rec_rawIn_fractIn, 22, 22) node _c2_self_rec_rawIn_normDist_T_23 = mux(_c2_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _c2_self_rec_rawIn_normDist_T_24 = mux(_c2_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _c2_self_rec_rawIn_normDist_T_23) node _c2_self_rec_rawIn_normDist_T_25 = mux(_c2_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _c2_self_rec_rawIn_normDist_T_24) node _c2_self_rec_rawIn_normDist_T_26 = mux(_c2_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _c2_self_rec_rawIn_normDist_T_25) node _c2_self_rec_rawIn_normDist_T_27 = mux(_c2_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _c2_self_rec_rawIn_normDist_T_26) node _c2_self_rec_rawIn_normDist_T_28 = mux(_c2_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _c2_self_rec_rawIn_normDist_T_27) node _c2_self_rec_rawIn_normDist_T_29 = mux(_c2_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _c2_self_rec_rawIn_normDist_T_28) node _c2_self_rec_rawIn_normDist_T_30 = mux(_c2_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _c2_self_rec_rawIn_normDist_T_29) node _c2_self_rec_rawIn_normDist_T_31 = mux(_c2_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _c2_self_rec_rawIn_normDist_T_30) node _c2_self_rec_rawIn_normDist_T_32 = mux(_c2_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _c2_self_rec_rawIn_normDist_T_31) node _c2_self_rec_rawIn_normDist_T_33 = mux(_c2_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _c2_self_rec_rawIn_normDist_T_32) node _c2_self_rec_rawIn_normDist_T_34 = mux(_c2_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _c2_self_rec_rawIn_normDist_T_33) node _c2_self_rec_rawIn_normDist_T_35 = mux(_c2_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _c2_self_rec_rawIn_normDist_T_34) node _c2_self_rec_rawIn_normDist_T_36 = mux(_c2_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _c2_self_rec_rawIn_normDist_T_35) node _c2_self_rec_rawIn_normDist_T_37 = mux(_c2_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _c2_self_rec_rawIn_normDist_T_36) node _c2_self_rec_rawIn_normDist_T_38 = mux(_c2_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _c2_self_rec_rawIn_normDist_T_37) node _c2_self_rec_rawIn_normDist_T_39 = mux(_c2_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _c2_self_rec_rawIn_normDist_T_38) node _c2_self_rec_rawIn_normDist_T_40 = mux(_c2_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _c2_self_rec_rawIn_normDist_T_39) node _c2_self_rec_rawIn_normDist_T_41 = mux(_c2_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _c2_self_rec_rawIn_normDist_T_40) node _c2_self_rec_rawIn_normDist_T_42 = mux(_c2_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _c2_self_rec_rawIn_normDist_T_41) node _c2_self_rec_rawIn_normDist_T_43 = mux(_c2_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _c2_self_rec_rawIn_normDist_T_42) node c2_self_rec_rawIn_normDist = mux(_c2_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _c2_self_rec_rawIn_normDist_T_43) node _c2_self_rec_rawIn_subnormFract_T = dshl(c2_self_rec_rawIn_fractIn, c2_self_rec_rawIn_normDist) node _c2_self_rec_rawIn_subnormFract_T_1 = bits(_c2_self_rec_rawIn_subnormFract_T, 21, 0) node c2_self_rec_rawIn_subnormFract = shl(_c2_self_rec_rawIn_subnormFract_T_1, 1) node _c2_self_rec_rawIn_adjustedExp_T = xor(c2_self_rec_rawIn_normDist, UInt<9>(0h1ff)) node _c2_self_rec_rawIn_adjustedExp_T_1 = mux(c2_self_rec_rawIn_isZeroExpIn, _c2_self_rec_rawIn_adjustedExp_T, c2_self_rec_rawIn_expIn) node _c2_self_rec_rawIn_adjustedExp_T_2 = mux(c2_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _c2_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _c2_self_rec_rawIn_adjustedExp_T_2) node _c2_self_rec_rawIn_adjustedExp_T_4 = add(_c2_self_rec_rawIn_adjustedExp_T_1, _c2_self_rec_rawIn_adjustedExp_T_3) node c2_self_rec_rawIn_adjustedExp = tail(_c2_self_rec_rawIn_adjustedExp_T_4, 1) node c2_self_rec_rawIn_isZero = and(c2_self_rec_rawIn_isZeroExpIn, c2_self_rec_rawIn_isZeroFractIn) node _c2_self_rec_rawIn_isSpecial_T = bits(c2_self_rec_rawIn_adjustedExp, 8, 7) node c2_self_rec_rawIn_isSpecial = eq(_c2_self_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire c2_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c2_self_rec_rawIn_out_isNaN_T = eq(c2_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _c2_self_rec_rawIn_out_isNaN_T_1 = and(c2_self_rec_rawIn_isSpecial, _c2_self_rec_rawIn_out_isNaN_T) connect c2_self_rec_rawIn.isNaN, _c2_self_rec_rawIn_out_isNaN_T_1 node _c2_self_rec_rawIn_out_isInf_T = and(c2_self_rec_rawIn_isSpecial, c2_self_rec_rawIn_isZeroFractIn) connect c2_self_rec_rawIn.isInf, _c2_self_rec_rawIn_out_isInf_T connect c2_self_rec_rawIn.isZero, c2_self_rec_rawIn_isZero connect c2_self_rec_rawIn.sign, c2_self_rec_rawIn_sign node _c2_self_rec_rawIn_out_sExp_T = bits(c2_self_rec_rawIn_adjustedExp, 8, 0) node _c2_self_rec_rawIn_out_sExp_T_1 = cvt(_c2_self_rec_rawIn_out_sExp_T) connect c2_self_rec_rawIn.sExp, _c2_self_rec_rawIn_out_sExp_T_1 node _c2_self_rec_rawIn_out_sig_T = eq(c2_self_rec_rawIn_isZero, UInt<1>(0h0)) node _c2_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c2_self_rec_rawIn_out_sig_T) node _c2_self_rec_rawIn_out_sig_T_2 = mux(c2_self_rec_rawIn_isZeroExpIn, c2_self_rec_rawIn_subnormFract, c2_self_rec_rawIn_fractIn) node _c2_self_rec_rawIn_out_sig_T_3 = cat(_c2_self_rec_rawIn_out_sig_T_1, _c2_self_rec_rawIn_out_sig_T_2) connect c2_self_rec_rawIn.sig, _c2_self_rec_rawIn_out_sig_T_3 node _c2_self_rec_T = bits(c2_self_rec_rawIn.sExp, 8, 6) node _c2_self_rec_T_1 = mux(c2_self_rec_rawIn.isZero, UInt<3>(0h0), _c2_self_rec_T) node _c2_self_rec_T_2 = mux(c2_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _c2_self_rec_T_3 = or(_c2_self_rec_T_1, _c2_self_rec_T_2) node _c2_self_rec_T_4 = cat(c2_self_rec_rawIn.sign, _c2_self_rec_T_3) node _c2_self_rec_T_5 = bits(c2_self_rec_rawIn.sExp, 5, 0) node _c2_self_rec_T_6 = cat(_c2_self_rec_T_4, _c2_self_rec_T_5) node _c2_self_rec_T_7 = bits(c2_self_rec_rawIn.sig, 22, 0) node c2_self_rec = cat(_c2_self_rec_T_6, _c2_self_rec_T_7) inst c2_resizer of RecFNToRecFN_179 connect c2_resizer.io.in, c2_self_rec connect c2_resizer.io.roundingMode, UInt<3>(0h0) connect c2_resizer.io.detectTininess, UInt<1>(0h1) wire c2_result : { bits : UInt<32>} node c2_result_bits_rawIn_exp = bits(c2_resizer.io.out, 31, 23) node _c2_result_bits_rawIn_isZero_T = bits(c2_result_bits_rawIn_exp, 8, 6) node c2_result_bits_rawIn_isZero = eq(_c2_result_bits_rawIn_isZero_T, UInt<1>(0h0)) node _c2_result_bits_rawIn_isSpecial_T = bits(c2_result_bits_rawIn_exp, 8, 7) node c2_result_bits_rawIn_isSpecial = eq(_c2_result_bits_rawIn_isSpecial_T, UInt<2>(0h3)) wire c2_result_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _c2_result_bits_rawIn_out_isNaN_T = bits(c2_result_bits_rawIn_exp, 6, 6) node _c2_result_bits_rawIn_out_isNaN_T_1 = and(c2_result_bits_rawIn_isSpecial, _c2_result_bits_rawIn_out_isNaN_T) connect c2_result_bits_rawIn.isNaN, _c2_result_bits_rawIn_out_isNaN_T_1 node _c2_result_bits_rawIn_out_isInf_T = bits(c2_result_bits_rawIn_exp, 6, 6) node _c2_result_bits_rawIn_out_isInf_T_1 = eq(_c2_result_bits_rawIn_out_isInf_T, UInt<1>(0h0)) node _c2_result_bits_rawIn_out_isInf_T_2 = and(c2_result_bits_rawIn_isSpecial, _c2_result_bits_rawIn_out_isInf_T_1) connect c2_result_bits_rawIn.isInf, _c2_result_bits_rawIn_out_isInf_T_2 connect c2_result_bits_rawIn.isZero, c2_result_bits_rawIn_isZero node _c2_result_bits_rawIn_out_sign_T = bits(c2_resizer.io.out, 32, 32) connect c2_result_bits_rawIn.sign, _c2_result_bits_rawIn_out_sign_T node _c2_result_bits_rawIn_out_sExp_T = cvt(c2_result_bits_rawIn_exp) connect c2_result_bits_rawIn.sExp, _c2_result_bits_rawIn_out_sExp_T node _c2_result_bits_rawIn_out_sig_T = eq(c2_result_bits_rawIn_isZero, UInt<1>(0h0)) node _c2_result_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _c2_result_bits_rawIn_out_sig_T) node _c2_result_bits_rawIn_out_sig_T_2 = bits(c2_resizer.io.out, 22, 0) node _c2_result_bits_rawIn_out_sig_T_3 = cat(_c2_result_bits_rawIn_out_sig_T_1, _c2_result_bits_rawIn_out_sig_T_2) connect c2_result_bits_rawIn.sig, _c2_result_bits_rawIn_out_sig_T_3 node c2_result_bits_isSubnormal = lt(c2_result_bits_rawIn.sExp, asSInt(UInt<9>(0h82))) node _c2_result_bits_denormShiftDist_T = bits(c2_result_bits_rawIn.sExp, 4, 0) node _c2_result_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _c2_result_bits_denormShiftDist_T) node c2_result_bits_denormShiftDist = tail(_c2_result_bits_denormShiftDist_T_1, 1) node _c2_result_bits_denormFract_T = shr(c2_result_bits_rawIn.sig, 1) node _c2_result_bits_denormFract_T_1 = dshr(_c2_result_bits_denormFract_T, c2_result_bits_denormShiftDist) node c2_result_bits_denormFract = bits(_c2_result_bits_denormFract_T_1, 22, 0) node _c2_result_bits_expOut_T = bits(c2_result_bits_rawIn.sExp, 7, 0) node _c2_result_bits_expOut_T_1 = sub(_c2_result_bits_expOut_T, UInt<8>(0h81)) node _c2_result_bits_expOut_T_2 = tail(_c2_result_bits_expOut_T_1, 1) node _c2_result_bits_expOut_T_3 = mux(c2_result_bits_isSubnormal, UInt<1>(0h0), _c2_result_bits_expOut_T_2) node _c2_result_bits_expOut_T_4 = or(c2_result_bits_rawIn.isNaN, c2_result_bits_rawIn.isInf) node _c2_result_bits_expOut_T_5 = mux(_c2_result_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node c2_result_bits_expOut = or(_c2_result_bits_expOut_T_3, _c2_result_bits_expOut_T_5) node _c2_result_bits_fractOut_T = bits(c2_result_bits_rawIn.sig, 22, 0) node _c2_result_bits_fractOut_T_1 = mux(c2_result_bits_rawIn.isInf, UInt<1>(0h0), _c2_result_bits_fractOut_T) node c2_result_bits_fractOut = mux(c2_result_bits_isSubnormal, c2_result_bits_denormFract, _c2_result_bits_fractOut_T_1) node c2_result_bits_hi = cat(c2_result_bits_rawIn.sign, c2_result_bits_expOut) node _c2_result_bits_T = cat(c2_result_bits_hi, c2_result_bits_fractOut) connect c2_result.bits, _c2_result_bits_T connect c2, c2_result else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_4 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_5 : UInt<32> connect _mac_unit_io_in_b_WIRE_5, c2.bits node _mac_unit_io_in_b_T_2 = bits(_mac_unit_io_in_b_WIRE_5, 31, 0) connect _mac_unit_io_in_b_WIRE_4.bits, _mac_unit_io_in_b_T_2 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_4.bits connect mac_unit.io.in_c.bits, io.in_b.bits connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_6 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_7 : UInt<32> connect _mac_unit_io_in_b_WIRE_7, c1.bits node _mac_unit_io_in_b_T_3 = bits(_mac_unit_io_in_b_WIRE_7, 31, 0) connect _mac_unit_io_in_b_WIRE_6.bits, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_6.bits connect mac_unit.io.in_c.bits, io.in_b.bits connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c.bits invalidate io.out_b.bits wire _mac_unit_io_in_b_WIRE_8 : { bits : UInt<32>} wire _mac_unit_io_in_b_WIRE_9 : UInt<32> connect _mac_unit_io_in_b_WIRE_9, io.in_b.bits node _mac_unit_io_in_b_T_4 = bits(_mac_unit_io_in_b_WIRE_9, 31, 0) connect _mac_unit_io_in_b_WIRE_8.bits, _mac_unit_io_in_b_T_4 connect mac_unit.io.in_b.bits, _mac_unit_io_in_b_WIRE_8.bits connect mac_unit.io.in_c.bits, c2.bits node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b.bits invalidate mac_unit.io.in_c.bits	module PE_21( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [31:0] io_in_a_bits, // @[PE.scala:35:14] input [31:0] io_in_b_bits, // @[PE.scala:35:14] input [31:0] io_in_d_bits, // @[PE.scala:35:14] output [31:0] io_out_a_bits, // @[PE.scala:35:14] output [31:0] io_out_b_bits, // @[PE.scala:35:14] output [31:0] io_out_c_bits, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [3:0] io_in_id, // @[PE.scala:35:14] output [3:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire c2_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire c1_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_shift_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire io_out_c_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [32:0] _c2_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_1_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_1_io_out; // @[Arithmetic.scala:450:30] wire [32:0] _c1_resizer_io_out; // @[Arithmetic.scala:486:29] wire [32:0] _io_out_c_resizer_io_out; // @[Arithmetic.scala:500:29] wire [32:0] _io_out_c_muladder_io_out; // @[Arithmetic.scala:450:30] wire [31:0] _mac_unit_io_out_d_bits; // @[PE.scala:64:24] wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:31:7] wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:31:7] wire [31:0] io_in_d_bits_0 = io_in_d_bits; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [3:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire _io_out_c_T_1 = reset; // @[Arithmetic.scala:447:15] wire _io_out_c_T_5 = reset; // @[Arithmetic.scala:447:15] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [31:0] io_out_a_bits_0 = io_in_a_bits_0; // @[PE.scala:31:7] wire [31:0] _mac_unit_io_in_b_WIRE_1 = io_in_b_bits_0; // @[PE.scala:31:7, :106:37] wire [31:0] _mac_unit_io_in_b_WIRE_3 = io_in_b_bits_0; // @[PE.scala:31:7, :113:37] wire [31:0] _mac_unit_io_in_b_WIRE_9 = io_in_b_bits_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [3:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [31:0] io_out_b_bits_0; // @[PE.scala:31:7] wire [31:0] io_out_c_bits_0; // @[PE.scala:31:7] reg [31:0] c1_bits; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_WIRE_7 = c1_bits; // @[PE.scala:70:15, :127:38] reg [31:0] c2_bits; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_WIRE_5 = c2_bits; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire io_out_c_self_rec_rawIn_sign = c1_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_sign_0 = io_out_c_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn = c1_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn = c1_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn = io_out_c_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn = io_out_c_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T = io_out_c_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_1 = io_out_c_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_2 = io_out_c_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_3 = io_out_c_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_4 = io_out_c_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_5 = io_out_c_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_6 = io_out_c_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_7 = io_out_c_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_8 = io_out_c_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_9 = io_out_c_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_10 = io_out_c_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_11 = io_out_c_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_12 = io_out_c_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_13 = io_out_c_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_14 = io_out_c_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_15 = io_out_c_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_16 = io_out_c_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_17 = io_out_c_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_18 = io_out_c_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_19 = io_out_c_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_20 = io_out_c_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_21 = io_out_c_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_22 = io_out_c_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_23 = _io_out_c_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_24 = _io_out_c_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_25 = _io_out_c_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_26 = _io_out_c_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_27 = _io_out_c_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_28 = _io_out_c_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_29 = _io_out_c_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_30 = _io_out_c_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_31 = _io_out_c_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_32 = _io_out_c_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_33 = _io_out_c_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_34 = _io_out_c_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_35 = _io_out_c_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_36 = _io_out_c_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_37 = _io_out_c_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_38 = _io_out_c_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_39 = _io_out_c_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_40 = _io_out_c_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_41 = _io_out_c_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_42 = _io_out_c_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_43 = _io_out_c_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist = _io_out_c_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T = {31'h0, io_out_c_self_rec_rawIn_fractIn} << io_out_c_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_1 = _io_out_c_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract = {_io_out_c_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_1 = io_out_c_self_rec_rawIn_isZeroExpIn ? _io_out_c_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp = _io_out_c_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T = io_out_c_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero = io_out_c_self_rec_rawIn_isZeroExpIn & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_isZero_0 = io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T = io_out_c_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial = &_io_out_c_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_2 = io_out_c_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T = ~io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_1 = io_out_c_self_rec_rawIn_isSpecial & _io_out_c_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T = io_out_c_self_rec_rawIn_isSpecial & io_out_c_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_isInf = _io_out_c_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T = ~io_out_c_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_2 = io_out_c_self_rec_rawIn_isZeroExpIn ? io_out_c_self_rec_rawIn_subnormFract : io_out_c_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_3 = {_io_out_c_self_rec_rawIn_out_sig_T_1, _io_out_c_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_sig = _io_out_c_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T = io_out_c_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_1 = io_out_c_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_3 = {_io_out_c_self_rec_T_1[2:1], _io_out_c_self_rec_T_1[0] \| _io_out_c_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_4 = {io_out_c_self_rec_rawIn_sign_0, _io_out_c_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_5 = io_out_c_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_6 = {_io_out_c_self_rec_T_4, _io_out_c_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_7 = io_out_c_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec = {_io_out_c_self_rec_T_6, _io_out_c_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp; // @[Arithmetic.scala:442:29] wire [7:0] _GEN = 8'h7F - {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _io_out_c_shift_exp_T; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T = _GEN; // @[Arithmetic.scala:443:34] wire [7:0] _io_out_c_shift_exp_T_2; // @[Arithmetic.scala:443:34] assign _io_out_c_shift_exp_T_2 = _GEN; // @[Arithmetic.scala:443:34] wire [6:0] _io_out_c_shift_exp_T_1 = _io_out_c_shift_exp_T[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp = {1'h0, _io_out_c_shift_exp_T_1}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi = {1'h0, io_out_c_shift_exp}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn = {io_out_c_shift_fn_hi, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign = io_out_c_shift_fn[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_sign_0 = io_out_c_shift_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn = io_out_c_shift_fn[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn = io_out_c_shift_fn[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn = io_out_c_shift_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn = io_out_c_shift_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T = io_out_c_shift_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_1 = io_out_c_shift_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_2 = io_out_c_shift_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_3 = io_out_c_shift_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_4 = io_out_c_shift_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_5 = io_out_c_shift_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_6 = io_out_c_shift_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_7 = io_out_c_shift_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_8 = io_out_c_shift_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_9 = io_out_c_shift_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_10 = io_out_c_shift_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_11 = io_out_c_shift_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_12 = io_out_c_shift_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_13 = io_out_c_shift_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_14 = io_out_c_shift_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_15 = io_out_c_shift_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_16 = io_out_c_shift_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_17 = io_out_c_shift_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_18 = io_out_c_shift_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_19 = io_out_c_shift_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_20 = io_out_c_shift_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_21 = io_out_c_shift_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_22 = io_out_c_shift_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_23 = _io_out_c_shift_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_24 = _io_out_c_shift_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_25 = _io_out_c_shift_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_26 = _io_out_c_shift_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_27 = _io_out_c_shift_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_28 = _io_out_c_shift_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_29 = _io_out_c_shift_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_30 = _io_out_c_shift_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_31 = _io_out_c_shift_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_32 = _io_out_c_shift_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_33 = _io_out_c_shift_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_34 = _io_out_c_shift_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_35 = _io_out_c_shift_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_36 = _io_out_c_shift_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_37 = _io_out_c_shift_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_38 = _io_out_c_shift_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_39 = _io_out_c_shift_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_40 = _io_out_c_shift_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_41 = _io_out_c_shift_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_42 = _io_out_c_shift_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_43 = _io_out_c_shift_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist = _io_out_c_shift_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T = {31'h0, io_out_c_shift_rec_rawIn_fractIn} << io_out_c_shift_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_1 = _io_out_c_shift_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract = {_io_out_c_shift_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_c_shift_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_1 = io_out_c_shift_rec_rawIn_isZeroExpIn ? _io_out_c_shift_rec_rawIn_adjustedExp_T : {1'h0, io_out_c_shift_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp = _io_out_c_shift_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T = io_out_c_shift_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero = io_out_c_shift_rec_rawIn_isZeroExpIn & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_isZero_0 = io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T = io_out_c_shift_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial = &_io_out_c_shift_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_2 = io_out_c_shift_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T = ~io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_1 = io_out_c_shift_rec_rawIn_isSpecial & _io_out_c_shift_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T = io_out_c_shift_rec_rawIn_isSpecial & io_out_c_shift_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T = ~io_out_c_shift_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_2 = io_out_c_shift_rec_rawIn_isZeroExpIn ? io_out_c_shift_rec_rawIn_subnormFract : io_out_c_shift_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_3 = {_io_out_c_shift_rec_rawIn_out_sig_T_1, _io_out_c_shift_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_sig = _io_out_c_shift_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T = io_out_c_shift_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_1 = io_out_c_shift_rec_rawIn_isZero_0 ? 3'h0 : _io_out_c_shift_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_3 = {_io_out_c_shift_rec_T_1[2:1], _io_out_c_shift_rec_T_1[0] \| _io_out_c_shift_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_4 = {io_out_c_shift_rec_rawIn_sign_0, _io_out_c_shift_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_5 = io_out_c_shift_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_6 = {_io_out_c_shift_rec_T_4, _io_out_c_shift_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_7 = io_out_c_shift_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec = {_io_out_c_shift_rec_T_6, _io_out_c_shift_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T = \|io_out_c_shift_exp; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_2 = ~_io_out_c_T_1; // @[Arithmetic.scala:447:15] wire _io_out_c_T_3 = ~_io_out_c_T; // @[Arithmetic.scala:447:{15,26}] wire [31:0] _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_bits; // @[Arithmetic.scala:458:26] wire [8:0] io_out_c_result_bits_rawIn_exp = _io_out_c_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T = io_out_c_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero = _io_out_c_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_isZero_0 = io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T = io_out_c_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial = &_io_out_c_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T = io_out_c_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_1 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_1 = ~_io_out_c_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_2 = io_out_c_result_bits_rawIn_isSpecial & _io_out_c_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T = _io_out_c_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_sign = _io_out_c_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T = {1'h0, io_out_c_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_sExp = _io_out_c_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T = ~io_out_c_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_2 = _io_out_c_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_3 = {_io_out_c_result_bits_rawIn_out_sig_T_1, _io_out_c_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_sig = _io_out_c_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal = $signed(io_out_c_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T = io_out_c_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist = _io_out_c_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T = io_out_c_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_1 = _io_out_c_result_bits_denormFract_T >> io_out_c_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract = _io_out_c_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T = io_out_c_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_1 = {1'h0, _io_out_c_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_2 = _io_out_c_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_3 = io_out_c_result_bits_isSubnormal ? 8'h0 : _io_out_c_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_4 = io_out_c_result_bits_rawIn_isNaN \| io_out_c_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_5 = {8{_io_out_c_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut = _io_out_c_result_bits_expOut_T_3 \| _io_out_c_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T = io_out_c_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_1 = io_out_c_result_bits_rawIn_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut = io_out_c_result_bits_isSubnormal ? io_out_c_result_bits_denormFract : _io_out_c_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi = {io_out_c_result_bits_rawIn_sign, io_out_c_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T = {io_out_c_result_bits_hi, io_out_c_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_bits = _io_out_c_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_1 = io_out_c_result_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_1_sign = io_out_c_self_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_1 = io_out_c_result_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_1 = io_out_c_result_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_1 = io_out_c_self_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_1 = io_out_c_self_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_44 = io_out_c_self_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_45 = io_out_c_self_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_46 = io_out_c_self_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_47 = io_out_c_self_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_48 = io_out_c_self_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_49 = io_out_c_self_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_50 = io_out_c_self_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_51 = io_out_c_self_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_52 = io_out_c_self_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_53 = io_out_c_self_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_54 = io_out_c_self_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_55 = io_out_c_self_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_56 = io_out_c_self_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_57 = io_out_c_self_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_58 = io_out_c_self_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_59 = io_out_c_self_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_60 = io_out_c_self_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_61 = io_out_c_self_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_62 = io_out_c_self_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_63 = io_out_c_self_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_64 = io_out_c_self_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_65 = io_out_c_self_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_66 = io_out_c_self_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_67 = _io_out_c_self_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_68 = _io_out_c_self_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_69 = _io_out_c_self_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_70 = _io_out_c_self_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_71 = _io_out_c_self_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_72 = _io_out_c_self_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_73 = _io_out_c_self_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_74 = _io_out_c_self_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_75 = _io_out_c_self_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_76 = _io_out_c_self_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_77 = _io_out_c_self_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_78 = _io_out_c_self_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_79 = _io_out_c_self_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_80 = _io_out_c_self_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_81 = _io_out_c_self_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_82 = _io_out_c_self_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_83 = _io_out_c_self_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_84 = _io_out_c_self_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_85 = _io_out_c_self_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_86 = _io_out_c_self_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_87 = _io_out_c_self_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_1 = _io_out_c_self_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_self_rec_rawIn_fractIn_1} << io_out_c_self_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_3 = _io_out_c_self_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_1 = {_io_out_c_self_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? _io_out_c_self_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_self_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_7 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_1 = _io_out_c_self_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_2 = io_out_c_self_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_1 = io_out_c_self_rec_rawIn_isZeroExpIn_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_1_isZero = io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_1 = io_out_c_self_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_1 = &_io_out_c_self_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_10 = io_out_c_self_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_2 = ~io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_3 = io_out_c_self_rec_rawIn_isSpecial_1 & _io_out_c_self_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_1_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_1 = io_out_c_self_rec_rawIn_isSpecial_1 & io_out_c_self_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_1_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_1_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_4 = ~io_out_c_self_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_6 = io_out_c_self_rec_rawIn_isZeroExpIn_1 ? io_out_c_self_rec_rawIn_subnormFract_1 : io_out_c_self_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_7 = {_io_out_c_self_rec_rawIn_out_sig_T_5, _io_out_c_self_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_1_sig = _io_out_c_self_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_8 = io_out_c_self_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_9 = io_out_c_self_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_self_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_11 = {_io_out_c_self_rec_T_9[2:1], _io_out_c_self_rec_T_9[0] \| _io_out_c_self_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_12 = {io_out_c_self_rec_rawIn_1_sign, _io_out_c_self_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_13 = io_out_c_self_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_14 = {_io_out_c_self_rec_T_12, _io_out_c_self_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_15 = io_out_c_self_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_1 = {_io_out_c_self_rec_T_14, _io_out_c_self_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] io_out_c_result_1_bits; // @[Arithmetic.scala:505:26] wire [8:0] io_out_c_result_bits_rawIn_exp_1 = _io_out_c_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _io_out_c_result_bits_rawIn_isZero_T_1 = io_out_c_result_bits_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_c_result_bits_rawIn_isZero_1 = _io_out_c_result_bits_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_c_result_bits_rawIn_1_isZero = io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_c_result_bits_rawIn_isSpecial_T_1 = io_out_c_result_bits_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_c_result_bits_rawIn_isSpecial_1 = &_io_out_c_result_bits_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_c_result_bits_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_c_result_bits_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_c_result_bits_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_c_result_bits_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_c_result_bits_rawIn_out_isNaN_T_2 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_c_result_bits_rawIn_out_isInf_T_3 = io_out_c_result_bits_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_c_result_bits_rawIn_out_isNaN_T_3 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_c_result_bits_rawIn_1_isNaN = _io_out_c_result_bits_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_c_result_bits_rawIn_out_isInf_T_4 = ~_io_out_c_result_bits_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_c_result_bits_rawIn_out_isInf_T_5 = io_out_c_result_bits_rawIn_isSpecial_1 & _io_out_c_result_bits_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_c_result_bits_rawIn_1_isInf = _io_out_c_result_bits_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_c_result_bits_rawIn_out_sign_T_1 = _io_out_c_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign io_out_c_result_bits_rawIn_1_sign = _io_out_c_result_bits_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_c_result_bits_rawIn_out_sExp_T_1 = {1'h0, io_out_c_result_bits_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_c_result_bits_rawIn_1_sExp = _io_out_c_result_bits_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_c_result_bits_rawIn_out_sig_T_4 = ~io_out_c_result_bits_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_c_result_bits_rawIn_out_sig_T_5 = {1'h0, _io_out_c_result_bits_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_c_result_bits_rawIn_out_sig_T_6 = _io_out_c_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _io_out_c_result_bits_rawIn_out_sig_T_7 = {_io_out_c_result_bits_rawIn_out_sig_T_5, _io_out_c_result_bits_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_c_result_bits_rawIn_1_sig = _io_out_c_result_bits_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_c_result_bits_isSubnormal_1 = $signed(io_out_c_result_bits_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_c_result_bits_denormShiftDist_T_2 = io_out_c_result_bits_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_c_result_bits_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_c_result_bits_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_c_result_bits_denormShiftDist_1 = _io_out_c_result_bits_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_c_result_bits_denormFract_T_2 = io_out_c_result_bits_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_c_result_bits_denormFract_T_3 = _io_out_c_result_bits_denormFract_T_2 >> io_out_c_result_bits_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_c_result_bits_denormFract_1 = _io_out_c_result_bits_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_c_result_bits_expOut_T_6 = io_out_c_result_bits_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_c_result_bits_expOut_T_7 = {1'h0, _io_out_c_result_bits_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_c_result_bits_expOut_T_8 = _io_out_c_result_bits_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_c_result_bits_expOut_T_9 = io_out_c_result_bits_isSubnormal_1 ? 8'h0 : _io_out_c_result_bits_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_c_result_bits_expOut_T_10 = io_out_c_result_bits_rawIn_1_isNaN \| io_out_c_result_bits_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_c_result_bits_expOut_T_11 = {8{_io_out_c_result_bits_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_c_result_bits_expOut_1 = _io_out_c_result_bits_expOut_T_9 \| _io_out_c_result_bits_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_c_result_bits_fractOut_T_2 = io_out_c_result_bits_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_c_result_bits_fractOut_T_3 = io_out_c_result_bits_rawIn_1_isInf ? 23'h0 : _io_out_c_result_bits_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_c_result_bits_fractOut_1 = io_out_c_result_bits_isSubnormal_1 ? io_out_c_result_bits_denormFract_1 : _io_out_c_result_bits_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_c_result_bits_hi_1 = {io_out_c_result_bits_rawIn_1_sign, io_out_c_result_bits_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] assign _io_out_c_result_bits_T_1 = {io_out_c_result_bits_hi_1, io_out_c_result_bits_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] assign io_out_c_result_1_bits = _io_out_c_result_bits_T_1; // @[fNFromRecFN.scala:66:12] wire [31:0] _mac_unit_io_in_b_T; // @[PE.scala:106:37] assign _mac_unit_io_in_b_T = _mac_unit_io_in_b_WIRE_1; // @[PE.scala:106:37] wire [31:0] _mac_unit_io_in_b_WIRE_bits = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire c1_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c2_self_rec_rawIn_sign = io_in_d_bits_0[31]; // @[rawFloatFromFN.scala:44:18] wire c1_self_rec_rawIn_sign_0 = c1_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] c1_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [7:0] c2_self_rec_rawIn_expIn = io_in_d_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] c1_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire [22:0] c2_self_rec_rawIn_fractIn = io_in_d_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21] wire c1_self_rec_rawIn_isZeroExpIn = c1_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire c1_self_rec_rawIn_isZeroFractIn = c1_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _c1_self_rec_rawIn_normDist_T = c1_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_1 = c1_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_2 = c1_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_3 = c1_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_4 = c1_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_5 = c1_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_6 = c1_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_7 = c1_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_8 = c1_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_9 = c1_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_10 = c1_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_11 = c1_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_12 = c1_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_13 = c1_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_14 = c1_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_15 = c1_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_16 = c1_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_17 = c1_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_18 = c1_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_19 = c1_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_20 = c1_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_21 = c1_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _c1_self_rec_rawIn_normDist_T_22 = c1_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _c1_self_rec_rawIn_normDist_T_23 = _c1_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_24 = _c1_self_rec_rawIn_normDist_T_2 ? 5'h14 : _c1_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_25 = _c1_self_rec_rawIn_normDist_T_3 ? 5'h13 : _c1_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_26 = _c1_self_rec_rawIn_normDist_T_4 ? 5'h12 : _c1_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_27 = _c1_self_rec_rawIn_normDist_T_5 ? 5'h11 : _c1_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_28 = _c1_self_rec_rawIn_normDist_T_6 ? 5'h10 : _c1_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_29 = _c1_self_rec_rawIn_normDist_T_7 ? 5'hF : _c1_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_30 = _c1_self_rec_rawIn_normDist_T_8 ? 5'hE : _c1_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_31 = _c1_self_rec_rawIn_normDist_T_9 ? 5'hD : _c1_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_32 = _c1_self_rec_rawIn_normDist_T_10 ? 5'hC : _c1_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_33 = _c1_self_rec_rawIn_normDist_T_11 ? 5'hB : _c1_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_34 = _c1_self_rec_rawIn_normDist_T_12 ? 5'hA : _c1_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_35 = _c1_self_rec_rawIn_normDist_T_13 ? 5'h9 : _c1_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_36 = _c1_self_rec_rawIn_normDist_T_14 ? 5'h8 : _c1_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_37 = _c1_self_rec_rawIn_normDist_T_15 ? 5'h7 : _c1_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_38 = _c1_self_rec_rawIn_normDist_T_16 ? 5'h6 : _c1_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_39 = _c1_self_rec_rawIn_normDist_T_17 ? 5'h5 : _c1_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_40 = _c1_self_rec_rawIn_normDist_T_18 ? 5'h4 : _c1_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_41 = _c1_self_rec_rawIn_normDist_T_19 ? 5'h3 : _c1_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_42 = _c1_self_rec_rawIn_normDist_T_20 ? 5'h2 : _c1_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _c1_self_rec_rawIn_normDist_T_43 = _c1_self_rec_rawIn_normDist_T_21 ? 5'h1 : _c1_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] c1_self_rec_rawIn_normDist = _c1_self_rec_rawIn_normDist_T_22 ? 5'h0 : _c1_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _c1_self_rec_rawIn_subnormFract_T = {31'h0, c1_self_rec_rawIn_fractIn} << c1_self_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _c1_self_rec_rawIn_subnormFract_T_1 = _c1_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] c1_self_rec_rawIn_subnormFract = {_c1_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T = {4'hF, ~c1_self_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _c1_self_rec_rawIn_adjustedExp_T_1 = c1_self_rec_rawIn_isZeroExpIn ? _c1_self_rec_rawIn_adjustedExp_T : {1'h0, c1_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _c1_self_rec_rawIn_adjustedExp_T_2 = c1_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _c1_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _c1_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _c1_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _c1_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _c1_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] c1_self_rec_rawIn_adjustedExp = _c1_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _c1_self_rec_rawIn_out_sExp_T = c1_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire c1_self_rec_rawIn_isZero = c1_self_rec_rawIn_isZeroExpIn & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire c1_self_rec_rawIn_isZero_0 = c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _c1_self_rec_rawIn_isSpecial_T = c1_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire c1_self_rec_rawIn_isSpecial = &_c1_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _c1_self_rec_T_2 = c1_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire c1_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] c1_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] c1_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _c1_self_rec_rawIn_out_isNaN_T = ~c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _c1_self_rec_rawIn_out_isNaN_T_1 = c1_self_rec_rawIn_isSpecial & _c1_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign c1_self_rec_rawIn_isNaN = _c1_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _c1_self_rec_rawIn_out_isInf_T = c1_self_rec_rawIn_isSpecial & c1_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign c1_self_rec_rawIn_isInf = _c1_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _c1_self_rec_rawIn_out_sExp_T_1 = {1'h0, _c1_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign c1_self_rec_rawIn_sExp = _c1_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _c1_self_rec_rawIn_out_sig_T = ~c1_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _c1_self_rec_rawIn_out_sig_T_1 = {1'h0, _c1_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _c1_self_rec_rawIn_out_sig_T_2 = c1_self_rec_rawIn_isZeroExpIn ? c1_self_rec_rawIn_subnormFract : c1_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _c1_self_rec_rawIn_out_sig_T_3 = {_c1_self_rec_rawIn_out_sig_T_1, _c1_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign c1_self_rec_rawIn_sig = _c1_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _c1_self_rec_T = c1_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _c1_self_rec_T_1 = c1_self_rec_rawIn_isZero_0 ? 3'h0 : _c1_self_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _c1_self_rec_T_3 = {_c1_self_rec_T_1[2:1], _c1_self_rec_T_1[0] \| _c1_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _c1_self_rec_T_4 = {c1_self_rec_rawIn_sign_0, _c1_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _c1_self_rec_T_5 = c1_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _c1_self_rec_T_6 = {_c1_self_rec_T_4, _c1_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _c1_self_rec_T_7 = c1_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] c1_self_rec = {_c1_self_rec_T_6, _c1_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire [31:0] c1_result_bits; // @[Arithmetic.scala:491:26] wire [8:0] c1_result_bits_rawIn_exp = _c1_resizer_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _c1_result_bits_rawIn_isZero_T = c1_result_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire c1_result_bits_rawIn_isZero = _c1_result_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire c1_result_bits_rawIn_isZero_0 = c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _c1_result_bits_rawIn_isSpecial_T = c1_result_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire c1_result_bits_rawIn_isSpecial = &_c1_result_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire c1_result_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire c1_result_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] c1_result_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] c1_result_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _c1_result_bits_rawIn_out_isNaN_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _c1_result_bits_rawIn_out_isInf_T = c1_result_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _c1_result_bits_rawIn_out_isNaN_T_1 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign c1_result_bits_rawIn_isNaN = _c1_result_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _c1_result_bits_rawIn_out_isInf_T_1 = ~_c1_result_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _c1_result_bits_rawIn_out_isInf_T_2 = c1_result_bits_rawIn_isSpecial & _c1_result_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign c1_result_bits_rawIn_isInf = _c1_result_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _c1_result_bits_rawIn_out_sign_T = _c1_resizer_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign c1_result_bits_rawIn_sign = _c1_result_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _c1_result_bits_rawIn_out_sExp_T = {1'h0, c1_result_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign c1_result_bits_rawIn_sExp = _c1_result_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _c1_result_bits_rawIn_out_sig_T = ~c1_result_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _c1_result_bits_rawIn_out_sig_T_1 = {1'h0, _c1_result_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _c1_result_bits_rawIn_out_sig_T_2 = _c1_resizer_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _c1_result_bits_rawIn_out_sig_T_3 = {_c1_result_bits_rawIn_out_sig_T_1, _c1_result_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign c1_result_bits_rawIn_sig = _c1_result_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire c1_result_bits_isSubnormal = $signed(c1_result_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _c1_result_bits_denormShiftDist_T = c1_result_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _c1_result_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _c1_result_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] c1_result_bits_denormShiftDist = _c1_result_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _c1_result_bits_denormFract_T = c1_result_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _c1_result_bits_denormFract_T_1 = _c1_result_bits_denormFract_T >> c1_result_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] c1_result_bits_denormFract = _c1_result_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _c1_result_bits_expOut_T = c1_result_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _c1_result_bits_expOut_T_1 = {1'h0, _c1_result_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _c1_result_bits_expOut_T_2 = _c1_result_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _c1_result_bits_expOut_T_3 = c1_result_bits_isSubnormal ? 8'h0 : _c1_result_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _c1_result_bits_expOut_T_4 = c1_result_bits_rawIn_isNaN \| c1_result_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _c1_result_bits_expOut_T_5 = {8{_c1_result_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] c1_result_bits_expOut = _c1_result_bits_expOut_T_3 \| _c1_result_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _c1_result_bits_fractOut_T = c1_result_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _c1_result_bits_fractOut_T_1 = c1_result_bits_rawIn_isInf ? 23'h0 : _c1_result_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] c1_result_bits_fractOut = c1_result_bits_isSubnormal ? c1_result_bits_denormFract : _c1_result_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] c1_result_bits_hi = {c1_result_bits_rawIn_sign, c1_result_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23] assign _c1_result_bits_T = {c1_result_bits_hi, c1_result_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] assign c1_result_bits = _c1_result_bits_T; // @[fNFromRecFN.scala:66:12] wire io_out_c_self_rec_rawIn_sign_2 = c2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_self_rec_rawIn_2_sign = io_out_c_self_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_self_rec_rawIn_expIn_2 = c2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_self_rec_rawIn_fractIn_2 = c2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_self_rec_rawIn_isZeroExpIn_2 = io_out_c_self_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_self_rec_rawIn_isZeroFractIn_2 = io_out_c_self_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_self_rec_rawIn_normDist_T_88 = io_out_c_self_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_89 = io_out_c_self_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_90 = io_out_c_self_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_91 = io_out_c_self_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_92 = io_out_c_self_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_93 = io_out_c_self_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_94 = io_out_c_self_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_95 = io_out_c_self_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_96 = io_out_c_self_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_97 = io_out_c_self_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_98 = io_out_c_self_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_99 = io_out_c_self_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_100 = io_out_c_self_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_101 = io_out_c_self_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_102 = io_out_c_self_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_103 = io_out_c_self_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_104 = io_out_c_self_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_105 = io_out_c_self_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_106 = io_out_c_self_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_107 = io_out_c_self_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_108 = io_out_c_self_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_109 = io_out_c_self_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_self_rec_rawIn_normDist_T_110 = io_out_c_self_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_111 = _io_out_c_self_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_112 = _io_out_c_self_rec_rawIn_normDist_T_90 ? 5'h14 : _io_out_c_self_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_113 = _io_out_c_self_rec_rawIn_normDist_T_91 ? 5'h13 : _io_out_c_self_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_114 = _io_out_c_self_rec_rawIn_normDist_T_92 ? 5'h12 : _io_out_c_self_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_115 = _io_out_c_self_rec_rawIn_normDist_T_93 ? 5'h11 : _io_out_c_self_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_116 = _io_out_c_self_rec_rawIn_normDist_T_94 ? 5'h10 : _io_out_c_self_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_117 = _io_out_c_self_rec_rawIn_normDist_T_95 ? 5'hF : _io_out_c_self_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_118 = _io_out_c_self_rec_rawIn_normDist_T_96 ? 5'hE : _io_out_c_self_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_119 = _io_out_c_self_rec_rawIn_normDist_T_97 ? 5'hD : _io_out_c_self_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_120 = _io_out_c_self_rec_rawIn_normDist_T_98 ? 5'hC : _io_out_c_self_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_121 = _io_out_c_self_rec_rawIn_normDist_T_99 ? 5'hB : _io_out_c_self_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_122 = _io_out_c_self_rec_rawIn_normDist_T_100 ? 5'hA : _io_out_c_self_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_123 = _io_out_c_self_rec_rawIn_normDist_T_101 ? 5'h9 : _io_out_c_self_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_124 = _io_out_c_self_rec_rawIn_normDist_T_102 ? 5'h8 : _io_out_c_self_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_125 = _io_out_c_self_rec_rawIn_normDist_T_103 ? 5'h7 : _io_out_c_self_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_126 = _io_out_c_self_rec_rawIn_normDist_T_104 ? 5'h6 : _io_out_c_self_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_127 = _io_out_c_self_rec_rawIn_normDist_T_105 ? 5'h5 : _io_out_c_self_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_128 = _io_out_c_self_rec_rawIn_normDist_T_106 ? 5'h4 : _io_out_c_self_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_129 = _io_out_c_self_rec_rawIn_normDist_T_107 ? 5'h3 : _io_out_c_self_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_130 = _io_out_c_self_rec_rawIn_normDist_T_108 ? 5'h2 : _io_out_c_self_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _io_out_c_self_rec_rawIn_normDist_T_131 = _io_out_c_self_rec_rawIn_normDist_T_109 ? 5'h1 : _io_out_c_self_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] io_out_c_self_rec_rawIn_normDist_2 = _io_out_c_self_rec_rawIn_normDist_T_110 ? 5'h0 : _io_out_c_self_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _io_out_c_self_rec_rawIn_subnormFract_T_4 = {31'h0, io_out_c_self_rec_rawIn_fractIn_2} << io_out_c_self_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _io_out_c_self_rec_rawIn_subnormFract_T_5 = _io_out_c_self_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_self_rec_rawIn_subnormFract_2 = {_io_out_c_self_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_10 = {4'hF, ~io_out_c_self_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_self_rec_rawIn_adjustedExp_T_11 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? _io_out_c_self_rec_rawIn_adjustedExp_T_10 : {1'h0, io_out_c_self_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_self_rec_rawIn_adjustedExp_T_12 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_self_rec_rawIn_adjustedExp_T_13 = {6'h20, _io_out_c_self_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_self_rec_rawIn_adjustedExp_T_14 = {1'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_11} + {2'h0, _io_out_c_self_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_self_rec_rawIn_adjustedExp_2 = _io_out_c_self_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_self_rec_rawIn_out_sExp_T_4 = io_out_c_self_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_self_rec_rawIn_isZero_2 = io_out_c_self_rec_rawIn_isZeroExpIn_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_self_rec_rawIn_2_isZero = io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_self_rec_rawIn_isSpecial_T_2 = io_out_c_self_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_self_rec_rawIn_isSpecial_2 = &_io_out_c_self_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_self_rec_T_18 = io_out_c_self_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire io_out_c_self_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_self_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_self_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_self_rec_rawIn_out_isNaN_T_4 = ~io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_self_rec_rawIn_out_isNaN_T_5 = io_out_c_self_rec_rawIn_isSpecial_2 & _io_out_c_self_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_self_rec_rawIn_2_isNaN = _io_out_c_self_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_self_rec_rawIn_out_isInf_T_2 = io_out_c_self_rec_rawIn_isSpecial_2 & io_out_c_self_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_self_rec_rawIn_2_isInf = _io_out_c_self_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_self_rec_rawIn_out_sExp_T_5 = {1'h0, _io_out_c_self_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_self_rec_rawIn_2_sExp = _io_out_c_self_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_self_rec_rawIn_out_sig_T_8 = ~io_out_c_self_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_self_rec_rawIn_out_sig_T_9 = {1'h0, _io_out_c_self_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_self_rec_rawIn_out_sig_T_10 = io_out_c_self_rec_rawIn_isZeroExpIn_2 ? io_out_c_self_rec_rawIn_subnormFract_2 : io_out_c_self_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_self_rec_rawIn_out_sig_T_11 = {_io_out_c_self_rec_rawIn_out_sig_T_9, _io_out_c_self_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_self_rec_rawIn_2_sig = _io_out_c_self_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_self_rec_T_16 = io_out_c_self_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_self_rec_T_17 = io_out_c_self_rec_rawIn_2_isZero ? 3'h0 : _io_out_c_self_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_self_rec_T_19 = {_io_out_c_self_rec_T_17[2:1], _io_out_c_self_rec_T_17[0] \| _io_out_c_self_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_self_rec_T_20 = {io_out_c_self_rec_rawIn_2_sign, _io_out_c_self_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_self_rec_T_21 = io_out_c_self_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_self_rec_T_22 = {_io_out_c_self_rec_T_20, _io_out_c_self_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_self_rec_T_23 = io_out_c_self_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_self_rec_2 = {_io_out_c_self_rec_T_22, _io_out_c_self_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [7:0] io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29] wire [6:0] _io_out_c_shift_exp_T_3 = _io_out_c_shift_exp_T_2[6:0]; // @[Arithmetic.scala:443:34] assign io_out_c_shift_exp_1 = {1'h0, _io_out_c_shift_exp_T_3}; // @[Arithmetic.scala:442:29, :443:{19,34}] wire [8:0] io_out_c_shift_fn_hi_1 = {1'h0, io_out_c_shift_exp_1}; // @[Arithmetic.scala:442:29, :444:27] wire [31:0] io_out_c_shift_fn_1 = {io_out_c_shift_fn_hi_1, 23'h0}; // @[Arithmetic.scala:444:27] wire io_out_c_shift_rec_rawIn_sign_1 = io_out_c_shift_fn_1[31]; // @[rawFloatFromFN.scala:44:18] wire io_out_c_shift_rec_rawIn_1_sign = io_out_c_shift_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] io_out_c_shift_rec_rawIn_expIn_1 = io_out_c_shift_fn_1[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] io_out_c_shift_rec_rawIn_fractIn_1 = io_out_c_shift_fn_1[22:0]; // @[rawFloatFromFN.scala:46:21] wire io_out_c_shift_rec_rawIn_isZeroExpIn_1 = io_out_c_shift_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire io_out_c_shift_rec_rawIn_isZeroFractIn_1 = io_out_c_shift_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _io_out_c_shift_rec_rawIn_normDist_T_44 = io_out_c_shift_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_45 = io_out_c_shift_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_46 = io_out_c_shift_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_47 = io_out_c_shift_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_48 = io_out_c_shift_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_49 = io_out_c_shift_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_50 = io_out_c_shift_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_51 = io_out_c_shift_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_52 = io_out_c_shift_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_53 = io_out_c_shift_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_54 = io_out_c_shift_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_55 = io_out_c_shift_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_56 = io_out_c_shift_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_57 = io_out_c_shift_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_58 = io_out_c_shift_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_59 = io_out_c_shift_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_60 = io_out_c_shift_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_61 = io_out_c_shift_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_62 = io_out_c_shift_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_63 = io_out_c_shift_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_64 = io_out_c_shift_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_65 = io_out_c_shift_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _io_out_c_shift_rec_rawIn_normDist_T_66 = io_out_c_shift_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_67 = _io_out_c_shift_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_68 = _io_out_c_shift_rec_rawIn_normDist_T_46 ? 5'h14 : _io_out_c_shift_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_69 = _io_out_c_shift_rec_rawIn_normDist_T_47 ? 5'h13 : _io_out_c_shift_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_70 = _io_out_c_shift_rec_rawIn_normDist_T_48 ? 5'h12 : _io_out_c_shift_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_71 = _io_out_c_shift_rec_rawIn_normDist_T_49 ? 5'h11 : _io_out_c_shift_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_72 = _io_out_c_shift_rec_rawIn_normDist_T_50 ? 5'h10 : _io_out_c_shift_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_73 = _io_out_c_shift_rec_rawIn_normDist_T_51 ? 5'hF : _io_out_c_shift_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_74 = _io_out_c_shift_rec_rawIn_normDist_T_52 ? 5'hE : _io_out_c_shift_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_75 = _io_out_c_shift_rec_rawIn_normDist_T_53 ? 5'hD : _io_out_c_shift_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_76 = _io_out_c_shift_rec_rawIn_normDist_T_54 ? 5'hC : _io_out_c_shift_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_77 = _io_out_c_shift_rec_rawIn_normDist_T_55 ? 5'hB : _io_out_c_shift_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_78 = _io_out_c_shift_rec_rawIn_normDist_T_56 ? 5'hA : _io_out_c_shift_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_79 = _io_out_c_shift_rec_rawIn_normDist_T_57 ? 5'h9 : _io_out_c_shift_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_80 = _io_out_c_shift_rec_rawIn_normDist_T_58 ? 5'h8 : _io_out_c_shift_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_81 = _io_out_c_shift_rec_rawIn_normDist_T_59 ? 5'h7 : _io_out_c_shift_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_82 = _io_out_c_shift_rec_rawIn_normDist_T_60 ? 5'h6 : _io_out_c_shift_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_83 = _io_out_c_shift_rec_rawIn_normDist_T_61 ? 5'h5 : _io_out_c_shift_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_84 = _io_out_c_shift_rec_rawIn_normDist_T_62 ? 5'h4 : _io_out_c_shift_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_85 = _io_out_c_shift_rec_rawIn_normDist_T_63 ? 5'h3 : _io_out_c_shift_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_86 = _io_out_c_shift_rec_rawIn_normDist_T_64 ? 5'h2 : _io_out_c_shift_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _io_out_c_shift_rec_rawIn_normDist_T_87 = _io_out_c_shift_rec_rawIn_normDist_T_65 ? 5'h1 : _io_out_c_shift_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] io_out_c_shift_rec_rawIn_normDist_1 = _io_out_c_shift_rec_rawIn_normDist_T_66 ? 5'h0 : _io_out_c_shift_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _io_out_c_shift_rec_rawIn_subnormFract_T_2 = {31'h0, io_out_c_shift_rec_rawIn_fractIn_1} << io_out_c_shift_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _io_out_c_shift_rec_rawIn_subnormFract_T_3 = _io_out_c_shift_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] io_out_c_shift_rec_rawIn_subnormFract_1 = {_io_out_c_shift_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_5 = {4'hF, ~io_out_c_shift_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? _io_out_c_shift_rec_rawIn_adjustedExp_T_5 : {1'h0, io_out_c_shift_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_7 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_8 = {6'h20, _io_out_c_shift_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _io_out_c_shift_rec_rawIn_adjustedExp_T_9 = {1'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_6} + {2'h0, _io_out_c_shift_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] io_out_c_shift_rec_rawIn_adjustedExp_1 = _io_out_c_shift_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _io_out_c_shift_rec_rawIn_out_sExp_T_2 = io_out_c_shift_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire io_out_c_shift_rec_rawIn_isZero_1 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire io_out_c_shift_rec_rawIn_1_isZero = io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _io_out_c_shift_rec_rawIn_isSpecial_T_1 = io_out_c_shift_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire io_out_c_shift_rec_rawIn_isSpecial_1 = &_io_out_c_shift_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _io_out_c_shift_rec_T_10 = io_out_c_shift_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire io_out_c_shift_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] io_out_c_shift_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] io_out_c_shift_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _io_out_c_shift_rec_rawIn_out_isNaN_T_2 = ~io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _io_out_c_shift_rec_rawIn_out_isNaN_T_3 = io_out_c_shift_rec_rawIn_isSpecial_1 & _io_out_c_shift_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign io_out_c_shift_rec_rawIn_1_isNaN = _io_out_c_shift_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _io_out_c_shift_rec_rawIn_out_isInf_T_1 = io_out_c_shift_rec_rawIn_isSpecial_1 & io_out_c_shift_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign io_out_c_shift_rec_rawIn_1_isInf = _io_out_c_shift_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _io_out_c_shift_rec_rawIn_out_sExp_T_3 = {1'h0, _io_out_c_shift_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign io_out_c_shift_rec_rawIn_1_sExp = _io_out_c_shift_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _io_out_c_shift_rec_rawIn_out_sig_T_4 = ~io_out_c_shift_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _io_out_c_shift_rec_rawIn_out_sig_T_5 = {1'h0, _io_out_c_shift_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _io_out_c_shift_rec_rawIn_out_sig_T_6 = io_out_c_shift_rec_rawIn_isZeroExpIn_1 ? io_out_c_shift_rec_rawIn_subnormFract_1 : io_out_c_shift_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _io_out_c_shift_rec_rawIn_out_sig_T_7 = {_io_out_c_shift_rec_rawIn_out_sig_T_5, _io_out_c_shift_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign io_out_c_shift_rec_rawIn_1_sig = _io_out_c_shift_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _io_out_c_shift_rec_T_8 = io_out_c_shift_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _io_out_c_shift_rec_T_9 = io_out_c_shift_rec_rawIn_1_isZero ? 3'h0 : _io_out_c_shift_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _io_out_c_shift_rec_T_11 = {_io_out_c_shift_rec_T_9[2:1], _io_out_c_shift_rec_T_9[0] \| _io_out_c_shift_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _io_out_c_shift_rec_T_12 = {io_out_c_shift_rec_rawIn_1_sign, _io_out_c_shift_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _io_out_c_shift_rec_T_13 = io_out_c_shift_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _io_out_c_shift_rec_T_14 = {_io_out_c_shift_rec_T_12, _io_out_c_shift_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _io_out_c_shift_rec_T_15 = io_out_c_shift_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] io_out_c_shift_rec_1 = {_io_out_c_shift_rec_T_14, _io_out_c_shift_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire _io_out_c_T_4 = \|io_out_c_shift_exp_1; // @[Arithmetic.scala:442:29, :447:26] wire _io_out_c_T_6 = ~_io_out_c_T_5; // @[Arithmetic.scala:447:15] wire _io_out_c_T_7 = ~_io_out_c_T_4; // @[Arithmetic.scala:447:{15,26}]
Generate the Verilog code corresponding to this FIRRTL code module LevelGateway_2 : input clock : Clock input reset : Reset output io : { flip interrupt : UInt<1>, plic : { valid : UInt<1>, flip ready : UInt<1>, flip complete : UInt<1>}} regreset inFlight : UInt<1>, clock, reset, UInt<1>(0h0) node _T = and(io.interrupt, io.plic.ready) when _T : connect inFlight, UInt<1>(0h1) when io.plic.complete : connect inFlight, UInt<1>(0h0) node _io_plic_valid_T = eq(inFlight, UInt<1>(0h0)) node _io_plic_valid_T_1 = and(io.interrupt, _io_plic_valid_T) connect io.plic.valid, _io_plic_valid_T_1	module LevelGateway_2( // @[Plic.scala:31:7] input clock, // @[Plic.scala:31:7] input reset, // @[Plic.scala:31:7] input io_interrupt, // @[Plic.scala:32:14] output io_plic_valid, // @[Plic.scala:32:14] input io_plic_ready, // @[Plic.scala:32:14] input io_plic_complete // @[Plic.scala:32:14] ); wire io_interrupt_0 = io_interrupt; // @[Plic.scala:31:7] wire io_plic_ready_0 = io_plic_ready; // @[Plic.scala:31:7] wire io_plic_complete_0 = io_plic_complete; // @[Plic.scala:31:7] wire _io_plic_valid_T_1; // @[Plic.scala:40:33] wire io_plic_valid_0; // @[Plic.scala:31:7] reg inFlight; // @[Plic.scala:37:25] wire _io_plic_valid_T = ~inFlight; // @[Plic.scala:37:25, :40:36] assign _io_plic_valid_T_1 = io_interrupt_0 & _io_plic_valid_T; // @[Plic.scala:31:7, :40:{33,36}] assign io_plic_valid_0 = _io_plic_valid_T_1; // @[Plic.scala:31:7, :40:33] always @(posedge clock) begin // @[Plic.scala:31:7] if (reset) // @[Plic.scala:31:7] inFlight <= 1'h0; // @[Plic.scala:37:25] else // @[Plic.scala:31:7] inFlight <= ~io_plic_complete_0 & (io_interrupt_0 & io_plic_ready_0 \| inFlight); // @[Plic.scala:31:7, :37:25, :38:{22,40,51}, :39:{27,38}] always @(posedge) assign io_plic_valid = io_plic_valid_0; // @[Plic.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_60 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0) node _source_ok_T = shr(io.in.a.bits.source, 11) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits = bits(_uncommonBits_T, 10, 0) node _T_4 = shr(io.in.a.bits.source, 11) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<11>(0h40f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0) node _T_24 = shr(io.in.a.bits.source, 11) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<9>(0h100))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<9>(0h100))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0) node _T_86 = shr(io.in.a.bits.source, 11) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<9>(0h100))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<9>(0h100))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0) node _T_152 = shr(io.in.a.bits.source, 11) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<9>(0h100))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0) node _T_199 = shr(io.in.a.bits.source, 11) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<9>(0h100))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0) node _T_240 = shr(io.in.a.bits.source, 11) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<9>(0h100))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0) node _T_283 = shr(io.in.a.bits.source, 11) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<9>(0h100))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0) node _T_321 = shr(io.in.a.bits.source, 11) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<9>(0h100))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0) node _T_359 = shr(io.in.a.bits.source, 11) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<9>(0h100))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 11) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h0), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<14>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<14>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1040> connect a_set, UInt<1040>(0h0) wire a_set_wo_ready : UInt<1040> connect a_set_wo_ready, UInt<1040>(0h0) wire a_opcodes_set : UInt<4160> connect a_opcodes_set, UInt<4160>(0h0) wire a_sizes_set : UInt<4160> connect a_sizes_set, UInt<4160>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1040> connect d_clr, UInt<1040>(0h0) wire d_clr_wo_ready : UInt<1040> connect d_clr_wo_ready, UInt<1040>(0h0) wire d_opcodes_clr : UInt<4160> connect d_opcodes_clr, UInt<4160>(0h0) wire d_sizes_clr : UInt<4160> connect d_sizes_clr, UInt<4160>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_123 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0) regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<11>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<11>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1040> connect c_set, UInt<1040>(0h0) wire c_set_wo_ready : UInt<1040> connect c_set_wo_ready, UInt<1040>(0h0) wire c_opcodes_set : UInt<4160> connect c_opcodes_set, UInt<4160>(0h0) wire c_sizes_set : UInt<4160> connect c_sizes_set, UInt<4160>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<14>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<11>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<11>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<11>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<11>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1040> connect d_clr_1, UInt<1040>(0h0) wire d_clr_wo_ready_1 : UInt<1040> connect d_clr_wo_ready_1, UInt<1040>(0h0) wire d_opcodes_clr_1 : UInt<4160> connect d_opcodes_clr_1, UInt<4160>(0h0) wire d_sizes_clr_1 : UInt<4160> connect d_sizes_clr_1, UInt<4160>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<11>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<11>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<11>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<11>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_124 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/fft-generator/src/main/scala/Tail.scala:150:58)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<11>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_60( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire [2047:0] _GEN = {2037'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [2047:0] _GEN_2 = {2037'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_213 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_213( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_72 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_148 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_72( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_148 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TileClockGater : input clock : Clock input reset : Reset output auto : { flip clock_gater_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_gater_in_0 : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_gater_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}} wire clock_gaterOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterOut.member.allClocks_uncore.reset invalidate clock_gaterOut.member.allClocks_uncore.clock wire clock_gaterIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterIn.member.allClocks_uncore.reset invalidate clock_gaterIn.member.allClocks_uncore.clock connect clock_gaterOut, clock_gaterIn wire clock_gaterIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clock_gaterIn_1.d.bits.corrupt invalidate clock_gaterIn_1.d.bits.data invalidate clock_gaterIn_1.d.bits.denied invalidate clock_gaterIn_1.d.bits.sink invalidate clock_gaterIn_1.d.bits.source invalidate clock_gaterIn_1.d.bits.size invalidate clock_gaterIn_1.d.bits.param invalidate clock_gaterIn_1.d.bits.opcode invalidate clock_gaterIn_1.d.valid invalidate clock_gaterIn_1.d.ready invalidate clock_gaterIn_1.a.bits.corrupt invalidate clock_gaterIn_1.a.bits.data invalidate clock_gaterIn_1.a.bits.mask invalidate clock_gaterIn_1.a.bits.address invalidate clock_gaterIn_1.a.bits.source invalidate clock_gaterIn_1.a.bits.size invalidate clock_gaterIn_1.a.bits.param invalidate clock_gaterIn_1.a.bits.opcode invalidate clock_gaterIn_1.a.valid invalidate clock_gaterIn_1.a.ready inst monitor of TLMonitor_117 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, clock_gaterIn_1.d.bits.corrupt connect monitor.io.in.d.bits.data, clock_gaterIn_1.d.bits.data connect monitor.io.in.d.bits.denied, clock_gaterIn_1.d.bits.denied connect monitor.io.in.d.bits.sink, clock_gaterIn_1.d.bits.sink connect monitor.io.in.d.bits.source, clock_gaterIn_1.d.bits.source connect monitor.io.in.d.bits.size, clock_gaterIn_1.d.bits.size connect monitor.io.in.d.bits.param, clock_gaterIn_1.d.bits.param connect monitor.io.in.d.bits.opcode, clock_gaterIn_1.d.bits.opcode connect monitor.io.in.d.valid, clock_gaterIn_1.d.valid connect monitor.io.in.d.ready, clock_gaterIn_1.d.ready connect monitor.io.in.a.bits.corrupt, clock_gaterIn_1.a.bits.corrupt connect monitor.io.in.a.bits.data, clock_gaterIn_1.a.bits.data connect monitor.io.in.a.bits.mask, clock_gaterIn_1.a.bits.mask connect monitor.io.in.a.bits.address, clock_gaterIn_1.a.bits.address connect monitor.io.in.a.bits.source, clock_gaterIn_1.a.bits.source connect monitor.io.in.a.bits.size, clock_gaterIn_1.a.bits.size connect monitor.io.in.a.bits.param, clock_gaterIn_1.a.bits.param connect monitor.io.in.a.bits.opcode, clock_gaterIn_1.a.bits.opcode connect monitor.io.in.a.valid, clock_gaterIn_1.a.valid connect monitor.io.in.a.ready, clock_gaterIn_1.a.ready connect auto.clock_gater_out, clock_gaterOut connect clock_gaterIn, auto.clock_gater_in_0 connect clock_gaterIn_1, auto.clock_gater_in_1 inst regs_0 of AsyncResetRegVec_w1_i1 connect regs_0.clock, clock connect regs_0.reset, clock_gaterIn.member.allClocks_uncore.reset connect clock_gaterOut.member.allClocks_uncore, clock_gaterIn.member.allClocks_uncore wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(clock_gaterIn_1.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(clock_gaterIn_1.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, clock_gaterIn_1.a.bits.data connect in.bits.mask, clock_gaterIn_1.a.bits.mask connect in.bits.extra.tlrr_extra.source, clock_gaterIn_1.a.bits.source connect in.bits.extra.tlrr_extra.size, clock_gaterIn_1.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect regs_0.io.en, out_f_woready connect regs_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(regs_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, clock_gaterIn_1.a.valid connect clock_gaterIn_1.a.ready, in.ready connect clock_gaterIn_1.d.valid, out.valid connect out.ready, clock_gaterIn_1.d.ready wire clock_gaterIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect clock_gaterIn_d_bits_d.opcode, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.param, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect clock_gaterIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect clock_gaterIn_d_bits_d.sink, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.denied, UInt<1>(0h0) invalidate clock_gaterIn_d_bits_d.data connect clock_gaterIn_d_bits_d.corrupt, UInt<1>(0h0) connect clock_gaterIn_1.d.bits.corrupt, clock_gaterIn_d_bits_d.corrupt connect clock_gaterIn_1.d.bits.data, clock_gaterIn_d_bits_d.data connect clock_gaterIn_1.d.bits.denied, clock_gaterIn_d_bits_d.denied connect clock_gaterIn_1.d.bits.sink, clock_gaterIn_d_bits_d.sink connect clock_gaterIn_1.d.bits.source, clock_gaterIn_d_bits_d.source connect clock_gaterIn_1.d.bits.size, clock_gaterIn_d_bits_d.size connect clock_gaterIn_1.d.bits.param, clock_gaterIn_d_bits_d.param connect clock_gaterIn_1.d.bits.opcode, clock_gaterIn_d_bits_d.opcode connect clock_gaterIn_1.d.bits.data, out.bits.data node _clock_gaterIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect clock_gaterIn_1.d.bits.opcode, _clock_gaterIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_282 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_283 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TileClockGater( // @[TileClockGater.scala:27:25] input clock, // @[TileClockGater.scala:27:25] input reset, // @[TileClockGater.scala:27:25] output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25] ); wire _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _regs_0_io_q; // @[TileClockGater.scala:33:53] wire in_bits_read = auto_clock_gater_in_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_1 = auto_clock_gater_in_1_a_bits_address[11:3] == 9'h0; // @[RegisterRouter.scala:75:19, :87:24] assign _out_wofireMux_T_1 = ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] wire [2:0] monitor_io_in_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] TLMonitor_117 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_clock_gater_in_1_d_ready), .io_in_a_valid (auto_clock_gater_in_1_a_valid), .io_in_a_bits_opcode (auto_clock_gater_in_1_a_bits_opcode), .io_in_a_bits_param (auto_clock_gater_in_1_a_bits_param), .io_in_a_bits_size (auto_clock_gater_in_1_a_bits_size), .io_in_a_bits_source (auto_clock_gater_in_1_a_bits_source), .io_in_a_bits_address (auto_clock_gater_in_1_a_bits_address), .io_in_a_bits_mask (auto_clock_gater_in_1_a_bits_mask), .io_in_a_bits_corrupt (auto_clock_gater_in_1_a_bits_corrupt), .io_in_d_ready (auto_clock_gater_in_1_d_ready), .io_in_d_valid (auto_clock_gater_in_1_a_valid), .io_in_d_bits_opcode (monitor_io_in_d_bits_opcode), // @[RegisterRouter.scala:105:19] .io_in_d_bits_size (auto_clock_gater_in_1_a_bits_size), .io_in_d_bits_source (auto_clock_gater_in_1_a_bits_source) ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53] .clock (clock), .reset (auto_clock_gater_in_0_member_allClocks_uncore_reset), .io_d (auto_clock_gater_in_1_a_bits_data[0]), // @[RegisterRouter.scala:87:24] .io_q (_regs_0_io_q), .io_en (auto_clock_gater_in_1_a_valid & auto_clock_gater_in_1_d_ready & _out_wofireMux_T_1 & _out_T_1 & auto_clock_gater_in_1_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ); // @[TileClockGater.scala:33:53] assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_opcode = monitor_io_in_d_bits_opcode; // @[RegisterRouter.scala:105:19] assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_data = {63'h0, _out_T_1 & _regs_0_io_q}; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_330 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_330( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_23 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_23( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_16 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_16( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN \| ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN \| ~_T_12 \| p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_170 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_302 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_170( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_302 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4_1 : input clock : Clock input reset : Reset output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, axi4yank_out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst axi4yank of AXI4UserYanker_1 connect axi4yank.clock, clock connect axi4yank.reset, reset inst axi4index of AXI4IdIndexer_1 connect axi4index.clock, clock connect axi4index.reset, reset inst tl2axi4 of TLToAXI4_1 connect tl2axi4.clock, clock connect tl2axi4.reset, reset inst widget of TLWidthWidget8_14 connect widget.clock, clock connect widget.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect axi4yank.auto.in, axi4index.auto.out connect axi4index.auto.in, tl2axi4.auto.out connect tl2axi4.auto.in, widget.auto.anon_out connect auto.tl_out, tlOut connect tlIn, auto.tl_in connect axi4yank.auto.out.r, auto.axi4yank_out.r connect auto.axi4yank_out.ar.bits, axi4yank.auto.out.ar.bits connect auto.axi4yank_out.ar.valid, axi4yank.auto.out.ar.valid connect axi4yank.auto.out.ar.ready, auto.axi4yank_out.ar.ready connect axi4yank.auto.out.b, auto.axi4yank_out.b connect auto.axi4yank_out.w.bits, axi4yank.auto.out.w.bits connect auto.axi4yank_out.w.valid, axi4yank.auto.out.w.valid connect axi4yank.auto.out.w.ready, auto.axi4yank_out.w.ready connect auto.axi4yank_out.aw.bits, axi4yank.auto.out.aw.bits connect auto.axi4yank_out.aw.valid, axi4yank.auto.out.aw.valid connect axi4yank.auto.out.aw.ready, auto.axi4yank_out.aw.ready connect widget.auto.anon_in, auto.widget_anon_in	module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4_1( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_widget_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_widget_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_widget_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_axi4yank_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_axi4yank_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_axi4yank_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_axi4yank_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_axi4yank_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_axi4yank_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_axi4yank_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_axi4yank_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_axi4yank_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_axi4yank_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_axi4yank_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_axi4yank_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_axi4yank_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_axi4yank_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_axi4yank_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_axi4yank_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_axi4yank_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_axi4yank_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_axi4yank_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_axi4yank_out_r_bits_last, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _tl2axi4_auto_out_aw_valid; // @[ToAXI4.scala:301:29] wire [5:0] _tl2axi4_auto_out_aw_bits_id; // @[ToAXI4.scala:301:29] wire [31:0] _tl2axi4_auto_out_aw_bits_addr; // @[ToAXI4.scala:301:29] wire [7:0] _tl2axi4_auto_out_aw_bits_len; // @[ToAXI4.scala:301:29] wire [2:0] _tl2axi4_auto_out_aw_bits_size; // @[ToAXI4.scala:301:29] wire [1:0] _tl2axi4_auto_out_aw_bits_burst; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_aw_bits_lock; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_aw_bits_cache; // @[ToAXI4.scala:301:29] wire [2:0] _tl2axi4_auto_out_aw_bits_prot; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_aw_bits_qos; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_aw_bits_echo_tl_state_size; // @[ToAXI4.scala:301:29] wire [5:0] _tl2axi4_auto_out_aw_bits_echo_tl_state_source; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_w_valid; // @[ToAXI4.scala:301:29] wire [63:0] _tl2axi4_auto_out_w_bits_data; // @[ToAXI4.scala:301:29] wire [7:0] _tl2axi4_auto_out_w_bits_strb; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_w_bits_last; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_b_ready; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_ar_valid; // @[ToAXI4.scala:301:29] wire [5:0] _tl2axi4_auto_out_ar_bits_id; // @[ToAXI4.scala:301:29] wire [31:0] _tl2axi4_auto_out_ar_bits_addr; // @[ToAXI4.scala:301:29] wire [7:0] _tl2axi4_auto_out_ar_bits_len; // @[ToAXI4.scala:301:29] wire [2:0] _tl2axi4_auto_out_ar_bits_size; // @[ToAXI4.scala:301:29] wire [1:0] _tl2axi4_auto_out_ar_bits_burst; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_ar_bits_lock; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_ar_bits_cache; // @[ToAXI4.scala:301:29] wire [2:0] _tl2axi4_auto_out_ar_bits_prot; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_ar_bits_qos; // @[ToAXI4.scala:301:29] wire [3:0] _tl2axi4_auto_out_ar_bits_echo_tl_state_size; // @[ToAXI4.scala:301:29] wire [5:0] _tl2axi4_auto_out_ar_bits_echo_tl_state_source; // @[ToAXI4.scala:301:29] wire _tl2axi4_auto_out_r_ready; // @[ToAXI4.scala:301:29] wire _axi4index_auto_in_aw_ready; // @[IdIndexer.scala:108:31] wire _axi4index_auto_in_w_ready; // @[IdIndexer.scala:108:31] wire _axi4index_auto_in_b_valid; // @[IdIndexer.scala:108:31] wire [5:0] _axi4index_auto_in_b_bits_id; // @[IdIndexer.scala:108:31] wire [1:0] _axi4index_auto_in_b_bits_resp; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_in_b_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31] wire [5:0] _axi4index_auto_in_b_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31] wire _axi4index_auto_in_ar_ready; // @[IdIndexer.scala:108:31] wire _axi4index_auto_in_r_valid; // @[IdIndexer.scala:108:31] wire [5:0] _axi4index_auto_in_r_bits_id; // @[IdIndexer.scala:108:31] wire [63:0] _axi4index_auto_in_r_bits_data; // @[IdIndexer.scala:108:31] wire [1:0] _axi4index_auto_in_r_bits_resp; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_in_r_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31] wire [5:0] _axi4index_auto_in_r_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31] wire _axi4index_auto_in_r_bits_last; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_aw_valid; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_aw_bits_id; // @[IdIndexer.scala:108:31] wire [31:0] _axi4index_auto_out_aw_bits_addr; // @[IdIndexer.scala:108:31] wire [7:0] _axi4index_auto_out_aw_bits_len; // @[IdIndexer.scala:108:31] wire [2:0] _axi4index_auto_out_aw_bits_size; // @[IdIndexer.scala:108:31] wire [1:0] _axi4index_auto_out_aw_bits_burst; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_aw_bits_lock; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_aw_bits_cache; // @[IdIndexer.scala:108:31] wire [2:0] _axi4index_auto_out_aw_bits_prot; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_aw_bits_qos; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31] wire [5:0] _axi4index_auto_out_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31] wire [1:0] _axi4index_auto_out_aw_bits_echo_extra_id; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_w_valid; // @[IdIndexer.scala:108:31] wire [63:0] _axi4index_auto_out_w_bits_data; // @[IdIndexer.scala:108:31] wire [7:0] _axi4index_auto_out_w_bits_strb; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_w_bits_last; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_b_ready; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_ar_valid; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_ar_bits_id; // @[IdIndexer.scala:108:31] wire [31:0] _axi4index_auto_out_ar_bits_addr; // @[IdIndexer.scala:108:31] wire [7:0] _axi4index_auto_out_ar_bits_len; // @[IdIndexer.scala:108:31] wire [2:0] _axi4index_auto_out_ar_bits_size; // @[IdIndexer.scala:108:31] wire [1:0] _axi4index_auto_out_ar_bits_burst; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_ar_bits_lock; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_ar_bits_cache; // @[IdIndexer.scala:108:31] wire [2:0] _axi4index_auto_out_ar_bits_prot; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_ar_bits_qos; // @[IdIndexer.scala:108:31] wire [3:0] _axi4index_auto_out_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31] wire [5:0] _axi4index_auto_out_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31] wire [1:0] _axi4index_auto_out_ar_bits_echo_extra_id; // @[IdIndexer.scala:108:31] wire _axi4index_auto_out_r_ready; // @[IdIndexer.scala:108:31] wire _axi4yank_auto_in_aw_ready; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_w_ready; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_b_valid; // @[UserYanker.scala:125:30] wire [3:0] _axi4yank_auto_in_b_bits_id; // @[UserYanker.scala:125:30] wire [1:0] _axi4yank_auto_in_b_bits_resp; // @[UserYanker.scala:125:30] wire [3:0] _axi4yank_auto_in_b_bits_echo_tl_state_size; // @[UserYanker.scala:125:30] wire [5:0] _axi4yank_auto_in_b_bits_echo_tl_state_source; // @[UserYanker.scala:125:30] wire [1:0] _axi4yank_auto_in_b_bits_echo_extra_id; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_ar_ready; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_r_valid; // @[UserYanker.scala:125:30] wire [3:0] _axi4yank_auto_in_r_bits_id; // @[UserYanker.scala:125:30] wire [63:0] _axi4yank_auto_in_r_bits_data; // @[UserYanker.scala:125:30] wire [1:0] _axi4yank_auto_in_r_bits_resp; // @[UserYanker.scala:125:30] wire [3:0] _axi4yank_auto_in_r_bits_echo_tl_state_size; // @[UserYanker.scala:125:30] wire [5:0] _axi4yank_auto_in_r_bits_echo_tl_state_source; // @[UserYanker.scala:125:30] wire [1:0] _axi4yank_auto_in_r_bits_echo_extra_id; // @[UserYanker.scala:125:30] wire _axi4yank_auto_in_r_bits_last; // @[UserYanker.scala:125:30] AXI4UserYanker axi4yank ( // @[UserYanker.scala:125:30] .clock (clock), .reset (reset), .auto_in_aw_ready (_axi4yank_auto_in_aw_ready), .auto_in_aw_valid (_axi4index_auto_out_aw_valid), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_id (_axi4index_auto_out_aw_bits_id), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_addr (_axi4index_auto_out_aw_bits_addr), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_len (_axi4index_auto_out_aw_bits_len), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_size (_axi4index_auto_out_aw_bits_size), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_burst (_axi4index_auto_out_aw_bits_burst), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_lock (_axi4index_auto_out_aw_bits_lock), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_cache (_axi4index_auto_out_aw_bits_cache), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_prot (_axi4index_auto_out_aw_bits_prot), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_qos (_axi4index_auto_out_aw_bits_qos), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_echo_tl_state_size (_axi4index_auto_out_aw_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_echo_tl_state_source (_axi4index_auto_out_aw_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31] .auto_in_aw_bits_echo_extra_id (_axi4index_auto_out_aw_bits_echo_extra_id), // @[IdIndexer.scala:108:31] .auto_in_w_ready (_axi4yank_auto_in_w_ready), .auto_in_w_valid (_axi4index_auto_out_w_valid), // @[IdIndexer.scala:108:31] .auto_in_w_bits_data (_axi4index_auto_out_w_bits_data), // @[IdIndexer.scala:108:31] .auto_in_w_bits_strb (_axi4index_auto_out_w_bits_strb), // @[IdIndexer.scala:108:31] .auto_in_w_bits_last (_axi4index_auto_out_w_bits_last), // @[IdIndexer.scala:108:31] .auto_in_b_ready (_axi4index_auto_out_b_ready), // @[IdIndexer.scala:108:31] .auto_in_b_valid (_axi4yank_auto_in_b_valid), .auto_in_b_bits_id (_axi4yank_auto_in_b_bits_id), .auto_in_b_bits_resp (_axi4yank_auto_in_b_bits_resp), .auto_in_b_bits_echo_tl_state_size (_axi4yank_auto_in_b_bits_echo_tl_state_size), .auto_in_b_bits_echo_tl_state_source (_axi4yank_auto_in_b_bits_echo_tl_state_source), .auto_in_b_bits_echo_extra_id (_axi4yank_auto_in_b_bits_echo_extra_id), .auto_in_ar_ready (_axi4yank_auto_in_ar_ready), .auto_in_ar_valid (_axi4index_auto_out_ar_valid), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_id (_axi4index_auto_out_ar_bits_id), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_addr (_axi4index_auto_out_ar_bits_addr), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_len (_axi4index_auto_out_ar_bits_len), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_size (_axi4index_auto_out_ar_bits_size), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_burst (_axi4index_auto_out_ar_bits_burst), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_lock (_axi4index_auto_out_ar_bits_lock), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_cache (_axi4index_auto_out_ar_bits_cache), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_prot (_axi4index_auto_out_ar_bits_prot), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_qos (_axi4index_auto_out_ar_bits_qos), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_echo_tl_state_size (_axi4index_auto_out_ar_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_echo_tl_state_source (_axi4index_auto_out_ar_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31] .auto_in_ar_bits_echo_extra_id (_axi4index_auto_out_ar_bits_echo_extra_id), // @[IdIndexer.scala:108:31] .auto_in_r_ready (_axi4index_auto_out_r_ready), // @[IdIndexer.scala:108:31] .auto_in_r_valid (_axi4yank_auto_in_r_valid), .auto_in_r_bits_id (_axi4yank_auto_in_r_bits_id), .auto_in_r_bits_data (_axi4yank_auto_in_r_bits_data), .auto_in_r_bits_resp (_axi4yank_auto_in_r_bits_resp), .auto_in_r_bits_echo_tl_state_size (_axi4yank_auto_in_r_bits_echo_tl_state_size), .auto_in_r_bits_echo_tl_state_source (_axi4yank_auto_in_r_bits_echo_tl_state_source), .auto_in_r_bits_echo_extra_id (_axi4yank_auto_in_r_bits_echo_extra_id), .auto_in_r_bits_last (_axi4yank_auto_in_r_bits_last), .auto_out_aw_ready (auto_axi4yank_out_aw_ready), .auto_out_aw_valid (auto_axi4yank_out_aw_valid), .auto_out_aw_bits_id (auto_axi4yank_out_aw_bits_id), .auto_out_aw_bits_addr (auto_axi4yank_out_aw_bits_addr), .auto_out_aw_bits_len (auto_axi4yank_out_aw_bits_len), .auto_out_aw_bits_size (auto_axi4yank_out_aw_bits_size), .auto_out_aw_bits_burst (auto_axi4yank_out_aw_bits_burst), .auto_out_aw_bits_lock (auto_axi4yank_out_aw_bits_lock), .auto_out_aw_bits_cache (auto_axi4yank_out_aw_bits_cache), .auto_out_aw_bits_prot (auto_axi4yank_out_aw_bits_prot), .auto_out_aw_bits_qos (auto_axi4yank_out_aw_bits_qos), .auto_out_w_ready (auto_axi4yank_out_w_ready), .auto_out_w_valid (auto_axi4yank_out_w_valid), .auto_out_w_bits_data (auto_axi4yank_out_w_bits_data), .auto_out_w_bits_strb (auto_axi4yank_out_w_bits_strb), .auto_out_w_bits_last (auto_axi4yank_out_w_bits_last), .auto_out_b_ready (auto_axi4yank_out_b_ready), .auto_out_b_valid (auto_axi4yank_out_b_valid), .auto_out_b_bits_id (auto_axi4yank_out_b_bits_id), .auto_out_b_bits_resp (auto_axi4yank_out_b_bits_resp), .auto_out_ar_ready (auto_axi4yank_out_ar_ready), .auto_out_ar_valid (auto_axi4yank_out_ar_valid), .auto_out_ar_bits_id (auto_axi4yank_out_ar_bits_id), .auto_out_ar_bits_addr (auto_axi4yank_out_ar_bits_addr), .auto_out_ar_bits_len (auto_axi4yank_out_ar_bits_len), .auto_out_ar_bits_size (auto_axi4yank_out_ar_bits_size), .auto_out_ar_bits_burst (auto_axi4yank_out_ar_bits_burst), .auto_out_ar_bits_lock (auto_axi4yank_out_ar_bits_lock), .auto_out_ar_bits_cache (auto_axi4yank_out_ar_bits_cache), .auto_out_ar_bits_prot (auto_axi4yank_out_ar_bits_prot), .auto_out_ar_bits_qos (auto_axi4yank_out_ar_bits_qos), .auto_out_r_ready (auto_axi4yank_out_r_ready), .auto_out_r_valid (auto_axi4yank_out_r_valid), .auto_out_r_bits_id (auto_axi4yank_out_r_bits_id), .auto_out_r_bits_data (auto_axi4yank_out_r_bits_data), .auto_out_r_bits_resp (auto_axi4yank_out_r_bits_resp), .auto_out_r_bits_last (auto_axi4yank_out_r_bits_last) ); // @[UserYanker.scala:125:30] AXI4IdIndexer axi4index ( // @[IdIndexer.scala:108:31] .auto_in_aw_ready (_axi4index_auto_in_aw_ready), .auto_in_aw_valid (_tl2axi4_auto_out_aw_valid), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_id (_tl2axi4_auto_out_aw_bits_id), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_addr (_tl2axi4_auto_out_aw_bits_addr), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_len (_tl2axi4_auto_out_aw_bits_len), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_size (_tl2axi4_auto_out_aw_bits_size), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_burst (_tl2axi4_auto_out_aw_bits_burst), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_lock (_tl2axi4_auto_out_aw_bits_lock), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_cache (_tl2axi4_auto_out_aw_bits_cache), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_prot (_tl2axi4_auto_out_aw_bits_prot), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_qos (_tl2axi4_auto_out_aw_bits_qos), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_echo_tl_state_size (_tl2axi4_auto_out_aw_bits_echo_tl_state_size), // @[ToAXI4.scala:301:29] .auto_in_aw_bits_echo_tl_state_source (_tl2axi4_auto_out_aw_bits_echo_tl_state_source), // @[ToAXI4.scala:301:29] .auto_in_w_ready (_axi4index_auto_in_w_ready), .auto_in_w_valid (_tl2axi4_auto_out_w_valid), // @[ToAXI4.scala:301:29] .auto_in_w_bits_data (_tl2axi4_auto_out_w_bits_data), // @[ToAXI4.scala:301:29] .auto_in_w_bits_strb (_tl2axi4_auto_out_w_bits_strb), // @[ToAXI4.scala:301:29] .auto_in_w_bits_last (_tl2axi4_auto_out_w_bits_last), // @[ToAXI4.scala:301:29] .auto_in_b_ready (_tl2axi4_auto_out_b_ready), // @[ToAXI4.scala:301:29] .auto_in_b_valid (_axi4index_auto_in_b_valid), .auto_in_b_bits_id (_axi4index_auto_in_b_bits_id), .auto_in_b_bits_resp (_axi4index_auto_in_b_bits_resp), .auto_in_b_bits_echo_tl_state_size (_axi4index_auto_in_b_bits_echo_tl_state_size), .auto_in_b_bits_echo_tl_state_source (_axi4index_auto_in_b_bits_echo_tl_state_source), .auto_in_ar_ready (_axi4index_auto_in_ar_ready), .auto_in_ar_valid (_tl2axi4_auto_out_ar_valid), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_id (_tl2axi4_auto_out_ar_bits_id), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_addr (_tl2axi4_auto_out_ar_bits_addr), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_len (_tl2axi4_auto_out_ar_bits_len), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_size (_tl2axi4_auto_out_ar_bits_size), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_burst (_tl2axi4_auto_out_ar_bits_burst), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_lock (_tl2axi4_auto_out_ar_bits_lock), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_cache (_tl2axi4_auto_out_ar_bits_cache), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_prot (_tl2axi4_auto_out_ar_bits_prot), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_qos (_tl2axi4_auto_out_ar_bits_qos), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_echo_tl_state_size (_tl2axi4_auto_out_ar_bits_echo_tl_state_size), // @[ToAXI4.scala:301:29] .auto_in_ar_bits_echo_tl_state_source (_tl2axi4_auto_out_ar_bits_echo_tl_state_source), // @[ToAXI4.scala:301:29] .auto_in_r_ready (_tl2axi4_auto_out_r_ready), // @[ToAXI4.scala:301:29] .auto_in_r_valid (_axi4index_auto_in_r_valid), .auto_in_r_bits_id (_axi4index_auto_in_r_bits_id), .auto_in_r_bits_data (_axi4index_auto_in_r_bits_data), .auto_in_r_bits_resp (_axi4index_auto_in_r_bits_resp), .auto_in_r_bits_echo_tl_state_size (_axi4index_auto_in_r_bits_echo_tl_state_size), .auto_in_r_bits_echo_tl_state_source (_axi4index_auto_in_r_bits_echo_tl_state_source), .auto_in_r_bits_last (_axi4index_auto_in_r_bits_last), .auto_out_aw_ready (_axi4yank_auto_in_aw_ready), // @[UserYanker.scala:125:30] .auto_out_aw_valid (_axi4index_auto_out_aw_valid), .auto_out_aw_bits_id (_axi4index_auto_out_aw_bits_id), .auto_out_aw_bits_addr (_axi4index_auto_out_aw_bits_addr), .auto_out_aw_bits_len (_axi4index_auto_out_aw_bits_len), .auto_out_aw_bits_size (_axi4index_auto_out_aw_bits_size), .auto_out_aw_bits_burst (_axi4index_auto_out_aw_bits_burst), .auto_out_aw_bits_lock (_axi4index_auto_out_aw_bits_lock), .auto_out_aw_bits_cache (_axi4index_auto_out_aw_bits_cache), .auto_out_aw_bits_prot (_axi4index_auto_out_aw_bits_prot), .auto_out_aw_bits_qos (_axi4index_auto_out_aw_bits_qos), .auto_out_aw_bits_echo_tl_state_size (_axi4index_auto_out_aw_bits_echo_tl_state_size), .auto_out_aw_bits_echo_tl_state_source (_axi4index_auto_out_aw_bits_echo_tl_state_source), .auto_out_aw_bits_echo_extra_id (_axi4index_auto_out_aw_bits_echo_extra_id), .auto_out_w_ready (_axi4yank_auto_in_w_ready), // @[UserYanker.scala:125:30] .auto_out_w_valid (_axi4index_auto_out_w_valid), .auto_out_w_bits_data (_axi4index_auto_out_w_bits_data), .auto_out_w_bits_strb (_axi4index_auto_out_w_bits_strb), .auto_out_w_bits_last (_axi4index_auto_out_w_bits_last), .auto_out_b_ready (_axi4index_auto_out_b_ready), .auto_out_b_valid (_axi4yank_auto_in_b_valid), // @[UserYanker.scala:125:30] .auto_out_b_bits_id (_axi4yank_auto_in_b_bits_id), // @[UserYanker.scala:125:30] .auto_out_b_bits_resp (_axi4yank_auto_in_b_bits_resp), // @[UserYanker.scala:125:30] .auto_out_b_bits_echo_tl_state_size (_axi4yank_auto_in_b_bits_echo_tl_state_size), // @[UserYanker.scala:125:30] .auto_out_b_bits_echo_tl_state_source (_axi4yank_auto_in_b_bits_echo_tl_state_source), // @[UserYanker.scala:125:30] .auto_out_b_bits_echo_extra_id (_axi4yank_auto_in_b_bits_echo_extra_id), // @[UserYanker.scala:125:30] .auto_out_ar_ready (_axi4yank_auto_in_ar_ready), // @[UserYanker.scala:125:30] .auto_out_ar_valid (_axi4index_auto_out_ar_valid), .auto_out_ar_bits_id (_axi4index_auto_out_ar_bits_id), .auto_out_ar_bits_addr (_axi4index_auto_out_ar_bits_addr), .auto_out_ar_bits_len (_axi4index_auto_out_ar_bits_len), .auto_out_ar_bits_size (_axi4index_auto_out_ar_bits_size), .auto_out_ar_bits_burst (_axi4index_auto_out_ar_bits_burst), .auto_out_ar_bits_lock (_axi4index_auto_out_ar_bits_lock), .auto_out_ar_bits_cache (_axi4index_auto_out_ar_bits_cache), .auto_out_ar_bits_prot (_axi4index_auto_out_ar_bits_prot), .auto_out_ar_bits_qos (_axi4index_auto_out_ar_bits_qos), .auto_out_ar_bits_echo_tl_state_size (_axi4index_auto_out_ar_bits_echo_tl_state_size), .auto_out_ar_bits_echo_tl_state_source (_axi4index_auto_out_ar_bits_echo_tl_state_source), .auto_out_ar_bits_echo_extra_id (_axi4index_auto_out_ar_bits_echo_extra_id), .auto_out_r_ready (_axi4index_auto_out_r_ready), .auto_out_r_valid (_axi4yank_auto_in_r_valid), // @[UserYanker.scala:125:30] .auto_out_r_bits_id (_axi4yank_auto_in_r_bits_id), // @[UserYanker.scala:125:30] .auto_out_r_bits_data (_axi4yank_auto_in_r_bits_data), // @[UserYanker.scala:125:30] .auto_out_r_bits_resp (_axi4yank_auto_in_r_bits_resp), // @[UserYanker.scala:125:30] .auto_out_r_bits_echo_tl_state_size (_axi4yank_auto_in_r_bits_echo_tl_state_size), // @[UserYanker.scala:125:30] .auto_out_r_bits_echo_tl_state_source (_axi4yank_auto_in_r_bits_echo_tl_state_source), // @[UserYanker.scala:125:30] .auto_out_r_bits_echo_extra_id (_axi4yank_auto_in_r_bits_echo_extra_id), // @[UserYanker.scala:125:30] .auto_out_r_bits_last (_axi4yank_auto_in_r_bits_last) // @[UserYanker.scala:125:30] ); // @[IdIndexer.scala:108:31] TLToAXI4_1 tl2axi4 ( // @[ToAXI4.scala:301:29] .clock (clock), .reset (reset), .auto_in_a_ready (auto_widget_anon_in_a_ready), .auto_in_a_valid (auto_widget_anon_in_a_valid), .auto_in_a_bits_opcode (auto_widget_anon_in_a_bits_opcode), .auto_in_a_bits_param (auto_widget_anon_in_a_bits_param), .auto_in_a_bits_size (auto_widget_anon_in_a_bits_size), .auto_in_a_bits_source (auto_widget_anon_in_a_bits_source), .auto_in_a_bits_address (auto_widget_anon_in_a_bits_address), .auto_in_a_bits_mask (auto_widget_anon_in_a_bits_mask), .auto_in_a_bits_data (auto_widget_anon_in_a_bits_data), .auto_in_a_bits_corrupt (auto_widget_anon_in_a_bits_corrupt), .auto_in_d_ready (auto_widget_anon_in_d_ready), .auto_in_d_valid (auto_widget_anon_in_d_valid), .auto_in_d_bits_opcode (auto_widget_anon_in_d_bits_opcode), .auto_in_d_bits_size (auto_widget_anon_in_d_bits_size), .auto_in_d_bits_source (auto_widget_anon_in_d_bits_source), .auto_in_d_bits_denied (auto_widget_anon_in_d_bits_denied), .auto_in_d_bits_data (auto_widget_anon_in_d_bits_data), .auto_in_d_bits_corrupt (auto_widget_anon_in_d_bits_corrupt), .auto_out_aw_ready (_axi4index_auto_in_aw_ready), // @[IdIndexer.scala:108:31] .auto_out_aw_valid (_tl2axi4_auto_out_aw_valid), .auto_out_aw_bits_id (_tl2axi4_auto_out_aw_bits_id), .auto_out_aw_bits_addr (_tl2axi4_auto_out_aw_bits_addr), .auto_out_aw_bits_len (_tl2axi4_auto_out_aw_bits_len), .auto_out_aw_bits_size (_tl2axi4_auto_out_aw_bits_size), .auto_out_aw_bits_burst (_tl2axi4_auto_out_aw_bits_burst), .auto_out_aw_bits_lock (_tl2axi4_auto_out_aw_bits_lock), .auto_out_aw_bits_cache (_tl2axi4_auto_out_aw_bits_cache), .auto_out_aw_bits_prot (_tl2axi4_auto_out_aw_bits_prot), .auto_out_aw_bits_qos (_tl2axi4_auto_out_aw_bits_qos), .auto_out_aw_bits_echo_tl_state_size (_tl2axi4_auto_out_aw_bits_echo_tl_state_size), .auto_out_aw_bits_echo_tl_state_source (_tl2axi4_auto_out_aw_bits_echo_tl_state_source), .auto_out_w_ready (_axi4index_auto_in_w_ready), // @[IdIndexer.scala:108:31] .auto_out_w_valid (_tl2axi4_auto_out_w_valid), .auto_out_w_bits_data (_tl2axi4_auto_out_w_bits_data), .auto_out_w_bits_strb (_tl2axi4_auto_out_w_bits_strb), .auto_out_w_bits_last (_tl2axi4_auto_out_w_bits_last), .auto_out_b_ready (_tl2axi4_auto_out_b_ready), .auto_out_b_valid (_axi4index_auto_in_b_valid), // @[IdIndexer.scala:108:31] .auto_out_b_bits_id (_axi4index_auto_in_b_bits_id), // @[IdIndexer.scala:108:31] .auto_out_b_bits_resp (_axi4index_auto_in_b_bits_resp), // @[IdIndexer.scala:108:31] .auto_out_b_bits_echo_tl_state_size (_axi4index_auto_in_b_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31] .auto_out_b_bits_echo_tl_state_source (_axi4index_auto_in_b_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31] .auto_out_ar_ready (_axi4index_auto_in_ar_ready), // @[IdIndexer.scala:108:31] .auto_out_ar_valid (_tl2axi4_auto_out_ar_valid), .auto_out_ar_bits_id (_tl2axi4_auto_out_ar_bits_id), .auto_out_ar_bits_addr (_tl2axi4_auto_out_ar_bits_addr), .auto_out_ar_bits_len (_tl2axi4_auto_out_ar_bits_len), .auto_out_ar_bits_size (_tl2axi4_auto_out_ar_bits_size), .auto_out_ar_bits_burst (_tl2axi4_auto_out_ar_bits_burst), .auto_out_ar_bits_lock (_tl2axi4_auto_out_ar_bits_lock), .auto_out_ar_bits_cache (_tl2axi4_auto_out_ar_bits_cache), .auto_out_ar_bits_prot (_tl2axi4_auto_out_ar_bits_prot), .auto_out_ar_bits_qos (_tl2axi4_auto_out_ar_bits_qos), .auto_out_ar_bits_echo_tl_state_size (_tl2axi4_auto_out_ar_bits_echo_tl_state_size), .auto_out_ar_bits_echo_tl_state_source (_tl2axi4_auto_out_ar_bits_echo_tl_state_source), .auto_out_r_ready (_tl2axi4_auto_out_r_ready), .auto_out_r_valid (_axi4index_auto_in_r_valid), // @[IdIndexer.scala:108:31] .auto_out_r_bits_id (_axi4index_auto_in_r_bits_id), // @[IdIndexer.scala:108:31] .auto_out_r_bits_data (_axi4index_auto_in_r_bits_data), // @[IdIndexer.scala:108:31] .auto_out_r_bits_resp (_axi4index_auto_in_r_bits_resp), // @[IdIndexer.scala:108:31] .auto_out_r_bits_echo_tl_state_size (_axi4index_auto_in_r_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31] .auto_out_r_bits_echo_tl_state_source (_axi4index_auto_in_r_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31] .auto_out_r_bits_last (_axi4index_auto_in_r_bits_last) // @[IdIndexer.scala:108:31] ); // @[ToAXI4.scala:301:29] assign auto_tl_in_a_ready = auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_valid = auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_opcode = auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_size = auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_source = auto_tl_out_d_bits_source; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_denied = auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_data = auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_corrupt = auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_valid = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_param = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_size = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_source = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_address = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_mask = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_data = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] assign auto_tl_out_d_ready = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_198 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_358 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_198( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_358 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AccumulatorScale : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { acc_read_resp : { data : SInt<32>[1][16], fromDMA : UInt<1>, scale : { bits : UInt<32>}, igelu_qb : SInt<32>, igelu_qc : SInt<32>, iexp_qln2 : SInt<32>, iexp_qln2_inv : SInt<32>, act : UInt<3>, acc_bank_id : UInt<2>}, mean : SInt<32>, max : SInt<32>, inv_stddev : { bits : UInt<32>}, inv_sum_exp : { bits : UInt<32>}}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { full_data : SInt<32>[1][16], data : SInt<8>[1][16], acc_bank_id : UInt<2>, fromDMA : UInt<1>}}} wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { full_data : SInt<32>[1][16], data : SInt<8>[1][16], acc_bank_id : UInt<2>, fromDMA : UInt<1>}} node _activated_data_e_act_T = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_1 = and(UInt<1>(0h1), _activated_data_e_act_T) node _activated_data_e_act_T_2 = geq(io.in.bits.acc_read_resp.data[0][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_3 = mux(_activated_data_e_act_T_2, io.in.bits.acc_read_resp.data[0][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_4 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_5 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_6 = and(_activated_data_e_act_T_4, _activated_data_e_act_T_5) node _activated_data_e_act_T_7 = sub(io.in.bits.acc_read_resp.data[0][0], io.in.bits.mean) node _activated_data_e_act_T_8 = tail(_activated_data_e_act_T_7, 1) node _activated_data_e_act_T_9 = asSInt(_activated_data_e_act_T_8) node _activated_data_e_act_T_10 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_11 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_12 = and(_activated_data_e_act_T_10, _activated_data_e_act_T_11) node _activated_data_e_act_q_sign_T = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[0][0]) node _activated_data_e_act_q_sign_T_1 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_2 = tail(_activated_data_e_act_q_sign_T_1, 1) node _activated_data_e_act_q_sign_T_3 = asSInt(_activated_data_e_act_q_sign_T_2) node activated_data_e_act_q_sign = mux(_activated_data_e_act_q_sign_T, _activated_data_e_act_q_sign_T_3, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[0][0]) node _activated_data_e_act_q_abs_T_1 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[0][0]) node _activated_data_e_act_q_abs_T_2 = tail(_activated_data_e_act_q_abs_T_1, 1) node _activated_data_e_act_q_abs_T_3 = asSInt(_activated_data_e_act_q_abs_T_2) node activated_data_e_act_q_abs = mux(_activated_data_e_act_q_abs_T, _activated_data_e_act_q_abs_T_3, io.in.bits.acc_read_resp.data[0][0]) node _activated_data_e_act_q_clipped_T = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_1 = tail(_activated_data_e_act_q_clipped_T, 1) node _activated_data_e_act_q_clipped_T_2 = asSInt(_activated_data_e_act_q_clipped_T_1) node _activated_data_e_act_q_clipped_T_3 = gt(activated_data_e_act_q_abs, _activated_data_e_act_q_clipped_T_2) node _activated_data_e_act_q_clipped_T_4 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_5 = tail(_activated_data_e_act_q_clipped_T_4, 1) node _activated_data_e_act_q_clipped_T_6 = asSInt(_activated_data_e_act_q_clipped_T_5) node activated_data_e_act_q_clipped = mux(_activated_data_e_act_q_clipped_T_3, _activated_data_e_act_q_clipped_T_6, activated_data_e_act_q_abs) node _activated_data_e_act_q_poly_T = add(activated_data_e_act_q_clipped, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_1 = tail(_activated_data_e_act_q_poly_T, 1) node _activated_data_e_act_q_poly_T_2 = asSInt(_activated_data_e_act_q_poly_T_1) node _activated_data_e_act_q_poly_T_3 = add(activated_data_e_act_q_clipped, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_4 = tail(_activated_data_e_act_q_poly_T_3, 1) node _activated_data_e_act_q_poly_T_5 = asSInt(_activated_data_e_act_q_poly_T_4) node _activated_data_e_act_q_poly_T_6 = mul(_activated_data_e_act_q_poly_T_2, _activated_data_e_act_q_poly_T_5) node _activated_data_e_act_q_poly_T_7 = add(_activated_data_e_act_q_poly_T_6, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_8 = tail(_activated_data_e_act_q_poly_T_7, 1) node _activated_data_e_act_q_poly_T_9 = asSInt(_activated_data_e_act_q_poly_T_8) node _activated_data_e_act_q_poly_T_10 = bits(_activated_data_e_act_q_poly_T_9, 31, 0) node activated_data_e_act_q_poly = asSInt(_activated_data_e_act_q_poly_T_10) node _activated_data_e_act_q_erf_T = mul(activated_data_e_act_q_sign, activated_data_e_act_q_poly) node _activated_data_e_act_q_erf_T_1 = bits(_activated_data_e_act_q_erf_T, 31, 0) node activated_data_e_act_q_erf = asSInt(_activated_data_e_act_q_erf_T_1) node _activated_data_e_act_T_13 = add(activated_data_e_act_q_erf, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_14 = tail(_activated_data_e_act_T_13, 1) node _activated_data_e_act_T_15 = asSInt(_activated_data_e_act_T_14) node _activated_data_e_act_T_16 = mul(io.in.bits.acc_read_resp.data[0][0], _activated_data_e_act_T_15) node _activated_data_e_act_T_17 = bits(_activated_data_e_act_T_16, 31, 0) node _activated_data_e_act_T_18 = asSInt(_activated_data_e_act_T_17) node _activated_data_e_act_T_19 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_20 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_21 = and(_activated_data_e_act_T_19, _activated_data_e_act_T_20) node _activated_data_e_act_T_22 = sub(io.in.bits.acc_read_resp.data[0][0], io.in.bits.max) node _activated_data_e_act_T_23 = tail(_activated_data_e_act_T_22, 1) node _activated_data_e_act_T_24 = asSInt(_activated_data_e_act_T_23) node _activated_data_e_act_neg_q_iexp_T = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_24) node _activated_data_e_act_neg_q_iexp_T_1 = tail(_activated_data_e_act_neg_q_iexp_T, 1) node activated_data_e_act_neg_q_iexp = asSInt(_activated_data_e_act_neg_q_iexp_T_1) node _activated_data_e_act_z_iexp_T = mul(activated_data_e_act_neg_q_iexp, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_1 = asUInt(_activated_data_e_act_z_iexp_T) node _activated_data_e_act_z_iexp_T_2 = shr(_activated_data_e_act_z_iexp_T_1, 16) wire activated_data_e_act_z_iexp : SInt<32> node _activated_data_e_act_z_iexp_T_3 = asSInt(_activated_data_e_act_z_iexp_T_2) connect activated_data_e_act_z_iexp, _activated_data_e_act_z_iexp_T_3 wire activated_data_e_act_z_iexp_saturated : SInt<32> node _activated_data_e_act_z_iexp_saturated_T = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_1 = bits(_activated_data_e_act_z_iexp_saturated_T, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_2 = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_3 = bits(_activated_data_e_act_z_iexp_saturated_T_2, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_4 = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_5 = bits(_activated_data_e_act_z_iexp_saturated_T_4, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_6 = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_7 = bits(_activated_data_e_act_z_iexp_saturated_T_6, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_8 = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_9 = bits(_activated_data_e_act_z_iexp_saturated_T_8, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_10 = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_11 = bits(_activated_data_e_act_z_iexp_saturated_T_10, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_12 = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_13 = bits(_activated_data_e_act_z_iexp_saturated_T_12, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_14 = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_15 = bits(_activated_data_e_act_z_iexp_saturated_T_14, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_16 = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_17 = bits(_activated_data_e_act_z_iexp_saturated_T_16, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_18 = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_19 = bits(_activated_data_e_act_z_iexp_saturated_T_18, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_20 = asUInt(activated_data_e_act_z_iexp) node _activated_data_e_act_z_iexp_saturated_T_21 = bits(_activated_data_e_act_z_iexp_saturated_T_20, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_22 = or(_activated_data_e_act_z_iexp_saturated_T_1, _activated_data_e_act_z_iexp_saturated_T_3) node _activated_data_e_act_z_iexp_saturated_T_23 = or(_activated_data_e_act_z_iexp_saturated_T_22, _activated_data_e_act_z_iexp_saturated_T_5) node _activated_data_e_act_z_iexp_saturated_T_24 = or(_activated_data_e_act_z_iexp_saturated_T_23, _activated_data_e_act_z_iexp_saturated_T_7) node _activated_data_e_act_z_iexp_saturated_T_25 = or(_activated_data_e_act_z_iexp_saturated_T_24, _activated_data_e_act_z_iexp_saturated_T_9) node _activated_data_e_act_z_iexp_saturated_T_26 = or(_activated_data_e_act_z_iexp_saturated_T_25, _activated_data_e_act_z_iexp_saturated_T_11) node _activated_data_e_act_z_iexp_saturated_T_27 = or(_activated_data_e_act_z_iexp_saturated_T_26, _activated_data_e_act_z_iexp_saturated_T_13) node _activated_data_e_act_z_iexp_saturated_T_28 = or(_activated_data_e_act_z_iexp_saturated_T_27, _activated_data_e_act_z_iexp_saturated_T_15) node _activated_data_e_act_z_iexp_saturated_T_29 = or(_activated_data_e_act_z_iexp_saturated_T_28, _activated_data_e_act_z_iexp_saturated_T_17) node _activated_data_e_act_z_iexp_saturated_T_30 = or(_activated_data_e_act_z_iexp_saturated_T_29, _activated_data_e_act_z_iexp_saturated_T_19) node _activated_data_e_act_z_iexp_saturated_T_31 = or(_activated_data_e_act_z_iexp_saturated_T_30, _activated_data_e_act_z_iexp_saturated_T_21) wire _activated_data_e_act_z_iexp_saturated_WIRE : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_32 = mux(_activated_data_e_act_z_iexp_saturated_T_31, _activated_data_e_act_z_iexp_saturated_WIRE, activated_data_e_act_z_iexp) connect activated_data_e_act_z_iexp_saturated, _activated_data_e_act_z_iexp_saturated_T_32 node _activated_data_e_act_qp_iexp_T = mul(activated_data_e_act_z_iexp, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_1 = add(_activated_data_e_act_qp_iexp_T, _activated_data_e_act_T_24) node _activated_data_e_act_qp_iexp_T_2 = tail(_activated_data_e_act_qp_iexp_T_1, 1) node _activated_data_e_act_qp_iexp_T_3 = asSInt(_activated_data_e_act_qp_iexp_T_2) node _activated_data_e_act_qp_iexp_T_4 = bits(_activated_data_e_act_qp_iexp_T_3, 31, 0) node activated_data_e_act_qp_iexp = asSInt(_activated_data_e_act_qp_iexp_T_4) node _activated_data_e_act_q_poly_iexp_T = add(activated_data_e_act_qp_iexp, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_1 = tail(_activated_data_e_act_q_poly_iexp_T, 1) node _activated_data_e_act_q_poly_iexp_T_2 = asSInt(_activated_data_e_act_q_poly_iexp_T_1) node _activated_data_e_act_q_poly_iexp_T_3 = add(activated_data_e_act_qp_iexp, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_4 = tail(_activated_data_e_act_q_poly_iexp_T_3, 1) node _activated_data_e_act_q_poly_iexp_T_5 = asSInt(_activated_data_e_act_q_poly_iexp_T_4) node _activated_data_e_act_q_poly_iexp_T_6 = mul(_activated_data_e_act_q_poly_iexp_T_2, _activated_data_e_act_q_poly_iexp_T_5) node _activated_data_e_act_q_poly_iexp_T_7 = add(_activated_data_e_act_q_poly_iexp_T_6, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_8 = tail(_activated_data_e_act_q_poly_iexp_T_7, 1) node _activated_data_e_act_q_poly_iexp_T_9 = asSInt(_activated_data_e_act_q_poly_iexp_T_8) node _activated_data_e_act_q_poly_iexp_T_10 = bits(_activated_data_e_act_q_poly_iexp_T_9, 31, 0) node activated_data_e_act_q_poly_iexp = asSInt(_activated_data_e_act_q_poly_iexp_T_10) node _activated_data_e_act_T_25 = asUInt(activated_data_e_act_q_poly_iexp) node _activated_data_e_act_T_26 = asUInt(activated_data_e_act_z_iexp_saturated) node _activated_data_e_act_T_27 = dshr(_activated_data_e_act_T_25, _activated_data_e_act_T_26) wire _activated_data_e_act_WIRE : SInt<32> node _activated_data_e_act_T_28 = asSInt(_activated_data_e_act_T_27) connect _activated_data_e_act_WIRE, _activated_data_e_act_T_28 node _activated_data_e_act_T_29 = mux(_activated_data_e_act_T_21, _activated_data_e_act_WIRE, io.in.bits.acc_read_resp.data[0][0]) node _activated_data_e_act_T_30 = mux(_activated_data_e_act_T_12, _activated_data_e_act_T_18, _activated_data_e_act_T_29) node _activated_data_e_act_T_31 = mux(_activated_data_e_act_T_6, _activated_data_e_act_T_9, _activated_data_e_act_T_30) node activated_data_e_act = mux(_activated_data_e_act_T_1, _activated_data_e_act_T_3, _activated_data_e_act_T_31) node _activated_data_e_scaled_T = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_1 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_2 = and(_activated_data_e_scaled_T, _activated_data_e_scaled_T_1) node _activated_data_e_scaled_T_3 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_4 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_5 = and(_activated_data_e_scaled_T_3, _activated_data_e_scaled_T_4) wire _activated_data_e_scaled_WIRE : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_1 : UInt<32> connect _activated_data_e_scaled_WIRE_1, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_6 = bits(_activated_data_e_scaled_WIRE_1, 31, 0) connect _activated_data_e_scaled_WIRE.bits, _activated_data_e_scaled_T_6 node _activated_data_e_scaled_T_7 = mux(_activated_data_e_scaled_T_5, _activated_data_e_scaled_WIRE, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_8 = mux(_activated_data_e_scaled_T_2, io.in.bits.inv_stddev, _activated_data_e_scaled_T_7) wire _activated_data_e_scaled_WIRE_2 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_3 : UInt<32> connect _activated_data_e_scaled_WIRE_3, _activated_data_e_scaled_T_8.bits node _activated_data_e_scaled_T_9 = bits(_activated_data_e_scaled_WIRE_3, 31, 0) connect _activated_data_e_scaled_WIRE_2.bits, _activated_data_e_scaled_T_9 node activated_data_e_scaled_f_rec_rawIn_sign = bits(_activated_data_e_scaled_WIRE_2.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn = bits(_activated_data_e_scaled_WIRE_2.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn = bits(_activated_data_e_scaled_WIRE_2.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn = eq(activated_data_e_scaled_f_rec_rawIn_expIn, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn = eq(activated_data_e_scaled_f_rec_rawIn_fractIn, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_1 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_2 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_3 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_4 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_5 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_6 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_7 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_8 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_9 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_10 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_11 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_12 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_13 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_14 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_15 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_16 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_17 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_18 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_19 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_20 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_21 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_22 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_23 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_24 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_2, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_23) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_25 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_3, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_24) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_26 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_4, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_25) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_27 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_5, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_26) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_28 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_6, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_27) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_29 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_7, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_28) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_30 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_8, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_29) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_31 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_9, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_30) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_32 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_10, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_31) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_33 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_11, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_32) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_34 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_12, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_33) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_35 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_13, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_34) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_36 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_14, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_35) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_37 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_15, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_36) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_38 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_16, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_37) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_39 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_17, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_38) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_40 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_18, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_39) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_41 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_19, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_40) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_42 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_20, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_41) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_43 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_21, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_42) node activated_data_e_scaled_f_rec_rawIn_normDist = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_22, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_43) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn, activated_data_e_scaled_f_rec_rawIn_normDist) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_1 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_1, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T = xor(activated_data_e_scaled_f_rec_rawIn_normDist, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_1 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T, activated_data_e_scaled_f_rec_rawIn_expIn) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_2 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_2) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_4 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_1, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_3) node activated_data_e_scaled_f_rec_rawIn_adjustedExp = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_4, 1) node activated_data_e_scaled_f_rec_rawIn_isZero = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_1 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T) connect activated_data_e_scaled_f_rec_rawIn.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_1 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T = and(activated_data_e_scaled_f_rec_rawIn_isSpecial, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn) connect activated_data_e_scaled_f_rec_rawIn.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T connect activated_data_e_scaled_f_rec_rawIn.isZero, activated_data_e_scaled_f_rec_rawIn_isZero connect activated_data_e_scaled_f_rec_rawIn.sign, activated_data_e_scaled_f_rec_rawIn_sign node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_1 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T) connect activated_data_e_scaled_f_rec_rawIn.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_1 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T = eq(activated_data_e_scaled_f_rec_rawIn_isZero, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_2 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn, activated_data_e_scaled_f_rec_rawIn_subnormFract, activated_data_e_scaled_f_rec_rawIn_fractIn) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_3 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_1, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_2) connect activated_data_e_scaled_f_rec_rawIn.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_3 node _activated_data_e_scaled_f_rec_T = bits(activated_data_e_scaled_f_rec_rawIn.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_1 = mux(activated_data_e_scaled_f_rec_rawIn.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T) node _activated_data_e_scaled_f_rec_T_2 = mux(activated_data_e_scaled_f_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_3 = or(_activated_data_e_scaled_f_rec_T_1, _activated_data_e_scaled_f_rec_T_2) node _activated_data_e_scaled_f_rec_T_4 = cat(activated_data_e_scaled_f_rec_rawIn.sign, _activated_data_e_scaled_f_rec_T_3) node _activated_data_e_scaled_f_rec_T_5 = bits(activated_data_e_scaled_f_rec_rawIn.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_6 = cat(_activated_data_e_scaled_f_rec_T_4, _activated_data_e_scaled_f_rec_T_5) node _activated_data_e_scaled_f_rec_T_7 = bits(activated_data_e_scaled_f_rec_rawIn.sig, 22, 0) node activated_data_e_scaled_f_rec = cat(_activated_data_e_scaled_f_rec_T_6, _activated_data_e_scaled_f_rec_T_7) inst activated_data_e_scaled_in_to_rec_fn of INToRecFN_i32_e8_s24 connect activated_data_e_scaled_in_to_rec_fn.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T = asUInt(activated_data_e_act) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE, _activated_data_e_scaled_in_to_rec_fn_io_in_T connect activated_data_e_scaled_in_to_rec_fn.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE connect activated_data_e_scaled_in_to_rec_fn.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder of MulAddRecFN_e8_s24_4 connect activated_data_e_scaled_muladder.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder.io.a, activated_data_e_scaled_in_to_rec_fn.io.out connect activated_data_e_scaled_muladder.io.b, activated_data_e_scaled_f_rec connect activated_data_e_scaled_muladder.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in of RecFNToIN_e8_s24_i32 connect activated_data_e_scaled_rec_fn_to_in.clock, clock connect activated_data_e_scaled_rec_fn_to_in.reset, reset connect activated_data_e_scaled_rec_fn_to_in.io.in, activated_data_e_scaled_muladder.io.out connect activated_data_e_scaled_rec_fn_to_in.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow = bits(activated_data_e_scaled_rec_fn_to_in.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp = bits(activated_data_e_scaled_rec_fn_to_in.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T = bits(activated_data_e_scaled_sign_exp, 8, 6) node activated_data_e_scaled_sign_isZero = eq(_activated_data_e_scaled_sign_isZero_T, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T = bits(activated_data_e_scaled_sign_exp, 8, 7) node activated_data_e_scaled_sign_isSpecial = eq(_activated_data_e_scaled_sign_isSpecial_T, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T = bits(activated_data_e_scaled_sign_exp, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_1 = and(activated_data_e_scaled_sign_isSpecial, _activated_data_e_scaled_sign_out_isNaN_T) connect activated_data_e_scaled_sign_out.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_1 node _activated_data_e_scaled_sign_out_isInf_T = bits(activated_data_e_scaled_sign_exp, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_1 = eq(_activated_data_e_scaled_sign_out_isInf_T, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_2 = and(activated_data_e_scaled_sign_isSpecial, _activated_data_e_scaled_sign_out_isInf_T_1) connect activated_data_e_scaled_sign_out.isInf, _activated_data_e_scaled_sign_out_isInf_T_2 connect activated_data_e_scaled_sign_out.isZero, activated_data_e_scaled_sign_isZero node _activated_data_e_scaled_sign_out_sign_T = bits(activated_data_e_scaled_rec_fn_to_in.io.in, 32, 32) connect activated_data_e_scaled_sign_out.sign, _activated_data_e_scaled_sign_out_sign_T node _activated_data_e_scaled_sign_out_sExp_T = cvt(activated_data_e_scaled_sign_exp) connect activated_data_e_scaled_sign_out.sExp, _activated_data_e_scaled_sign_out_sExp_T node _activated_data_e_scaled_sign_out_sig_T = eq(activated_data_e_scaled_sign_isZero, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_1 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T) node _activated_data_e_scaled_sign_out_sig_T_2 = bits(activated_data_e_scaled_rec_fn_to_in.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_3 = cat(_activated_data_e_scaled_sign_out_sig_T_1, _activated_data_e_scaled_sign_out_sig_T_2) connect activated_data_e_scaled_sign_out.sig, _activated_data_e_scaled_sign_out_sig_T_3 node activated_data_e_scaled_sat = mux(activated_data_e_scaled_sign_out.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_4 : SInt<32> node _activated_data_e_scaled_T_10 = asSInt(activated_data_e_scaled_rec_fn_to_in.io.out) connect _activated_data_e_scaled_WIRE_4, _activated_data_e_scaled_T_10 node activated_data_e_scaled = mux(activated_data_e_scaled_overflow, activated_data_e_scaled_sat, _activated_data_e_scaled_WIRE_4) node _activated_data_e_clipped_T = gt(activated_data_e_scaled, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_1 = lt(activated_data_e_scaled, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_2 = mux(_activated_data_e_clipped_T_1, asSInt(UInt<8>(0h80)), activated_data_e_scaled) node _activated_data_e_clipped_T_3 = mux(_activated_data_e_clipped_T, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_2) node _activated_data_e_clipped_T_4 = bits(_activated_data_e_clipped_T_3, 7, 0) node activated_data_e_clipped = asSInt(_activated_data_e_clipped_T_4) wire _activated_data_WIRE : SInt<8>[1] connect _activated_data_WIRE[0], activated_data_e_clipped node _activated_data_e_act_T_32 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_33 = and(UInt<1>(0h1), _activated_data_e_act_T_32) node _activated_data_e_act_T_34 = geq(io.in.bits.acc_read_resp.data[1][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_35 = mux(_activated_data_e_act_T_34, io.in.bits.acc_read_resp.data[1][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_36 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_37 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_38 = and(_activated_data_e_act_T_36, _activated_data_e_act_T_37) node _activated_data_e_act_T_39 = sub(io.in.bits.acc_read_resp.data[1][0], io.in.bits.mean) node _activated_data_e_act_T_40 = tail(_activated_data_e_act_T_39, 1) node _activated_data_e_act_T_41 = asSInt(_activated_data_e_act_T_40) node _activated_data_e_act_T_42 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_43 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_44 = and(_activated_data_e_act_T_42, _activated_data_e_act_T_43) node _activated_data_e_act_q_sign_T_4 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[1][0]) node _activated_data_e_act_q_sign_T_5 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_6 = tail(_activated_data_e_act_q_sign_T_5, 1) node _activated_data_e_act_q_sign_T_7 = asSInt(_activated_data_e_act_q_sign_T_6) node activated_data_e_act_q_sign_1 = mux(_activated_data_e_act_q_sign_T_4, _activated_data_e_act_q_sign_T_7, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_4 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[1][0]) node _activated_data_e_act_q_abs_T_5 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[1][0]) node _activated_data_e_act_q_abs_T_6 = tail(_activated_data_e_act_q_abs_T_5, 1) node _activated_data_e_act_q_abs_T_7 = asSInt(_activated_data_e_act_q_abs_T_6) node activated_data_e_act_q_abs_1 = mux(_activated_data_e_act_q_abs_T_4, _activated_data_e_act_q_abs_T_7, io.in.bits.acc_read_resp.data[1][0]) node _activated_data_e_act_q_clipped_T_7 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_8 = tail(_activated_data_e_act_q_clipped_T_7, 1) node _activated_data_e_act_q_clipped_T_9 = asSInt(_activated_data_e_act_q_clipped_T_8) node _activated_data_e_act_q_clipped_T_10 = gt(activated_data_e_act_q_abs_1, _activated_data_e_act_q_clipped_T_9) node _activated_data_e_act_q_clipped_T_11 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_12 = tail(_activated_data_e_act_q_clipped_T_11, 1) node _activated_data_e_act_q_clipped_T_13 = asSInt(_activated_data_e_act_q_clipped_T_12) node activated_data_e_act_q_clipped_1 = mux(_activated_data_e_act_q_clipped_T_10, _activated_data_e_act_q_clipped_T_13, activated_data_e_act_q_abs_1) node _activated_data_e_act_q_poly_T_11 = add(activated_data_e_act_q_clipped_1, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_12 = tail(_activated_data_e_act_q_poly_T_11, 1) node _activated_data_e_act_q_poly_T_13 = asSInt(_activated_data_e_act_q_poly_T_12) node _activated_data_e_act_q_poly_T_14 = add(activated_data_e_act_q_clipped_1, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_15 = tail(_activated_data_e_act_q_poly_T_14, 1) node _activated_data_e_act_q_poly_T_16 = asSInt(_activated_data_e_act_q_poly_T_15) node _activated_data_e_act_q_poly_T_17 = mul(_activated_data_e_act_q_poly_T_13, _activated_data_e_act_q_poly_T_16) node _activated_data_e_act_q_poly_T_18 = add(_activated_data_e_act_q_poly_T_17, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_19 = tail(_activated_data_e_act_q_poly_T_18, 1) node _activated_data_e_act_q_poly_T_20 = asSInt(_activated_data_e_act_q_poly_T_19) node _activated_data_e_act_q_poly_T_21 = bits(_activated_data_e_act_q_poly_T_20, 31, 0) node activated_data_e_act_q_poly_1 = asSInt(_activated_data_e_act_q_poly_T_21) node _activated_data_e_act_q_erf_T_2 = mul(activated_data_e_act_q_sign_1, activated_data_e_act_q_poly_1) node _activated_data_e_act_q_erf_T_3 = bits(_activated_data_e_act_q_erf_T_2, 31, 0) node activated_data_e_act_q_erf_1 = asSInt(_activated_data_e_act_q_erf_T_3) node _activated_data_e_act_T_45 = add(activated_data_e_act_q_erf_1, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_46 = tail(_activated_data_e_act_T_45, 1) node _activated_data_e_act_T_47 = asSInt(_activated_data_e_act_T_46) node _activated_data_e_act_T_48 = mul(io.in.bits.acc_read_resp.data[1][0], _activated_data_e_act_T_47) node _activated_data_e_act_T_49 = bits(_activated_data_e_act_T_48, 31, 0) node _activated_data_e_act_T_50 = asSInt(_activated_data_e_act_T_49) node _activated_data_e_act_T_51 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_52 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_53 = and(_activated_data_e_act_T_51, _activated_data_e_act_T_52) node _activated_data_e_act_T_54 = sub(io.in.bits.acc_read_resp.data[1][0], io.in.bits.max) node _activated_data_e_act_T_55 = tail(_activated_data_e_act_T_54, 1) node _activated_data_e_act_T_56 = asSInt(_activated_data_e_act_T_55) node _activated_data_e_act_neg_q_iexp_T_2 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_56) node _activated_data_e_act_neg_q_iexp_T_3 = tail(_activated_data_e_act_neg_q_iexp_T_2, 1) node activated_data_e_act_neg_q_iexp_1 = asSInt(_activated_data_e_act_neg_q_iexp_T_3) node _activated_data_e_act_z_iexp_T_4 = mul(activated_data_e_act_neg_q_iexp_1, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_5 = asUInt(_activated_data_e_act_z_iexp_T_4) node _activated_data_e_act_z_iexp_T_6 = shr(_activated_data_e_act_z_iexp_T_5, 16) wire activated_data_e_act_z_iexp_1 : SInt<32> node _activated_data_e_act_z_iexp_T_7 = asSInt(_activated_data_e_act_z_iexp_T_6) connect activated_data_e_act_z_iexp_1, _activated_data_e_act_z_iexp_T_7 wire activated_data_e_act_z_iexp_saturated_1 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_33 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_34 = bits(_activated_data_e_act_z_iexp_saturated_T_33, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_35 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_36 = bits(_activated_data_e_act_z_iexp_saturated_T_35, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_37 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_38 = bits(_activated_data_e_act_z_iexp_saturated_T_37, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_39 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_40 = bits(_activated_data_e_act_z_iexp_saturated_T_39, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_41 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_42 = bits(_activated_data_e_act_z_iexp_saturated_T_41, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_43 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_44 = bits(_activated_data_e_act_z_iexp_saturated_T_43, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_45 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_46 = bits(_activated_data_e_act_z_iexp_saturated_T_45, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_47 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_48 = bits(_activated_data_e_act_z_iexp_saturated_T_47, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_49 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_50 = bits(_activated_data_e_act_z_iexp_saturated_T_49, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_51 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_52 = bits(_activated_data_e_act_z_iexp_saturated_T_51, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_53 = asUInt(activated_data_e_act_z_iexp_1) node _activated_data_e_act_z_iexp_saturated_T_54 = bits(_activated_data_e_act_z_iexp_saturated_T_53, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_55 = or(_activated_data_e_act_z_iexp_saturated_T_34, _activated_data_e_act_z_iexp_saturated_T_36) node _activated_data_e_act_z_iexp_saturated_T_56 = or(_activated_data_e_act_z_iexp_saturated_T_55, _activated_data_e_act_z_iexp_saturated_T_38) node _activated_data_e_act_z_iexp_saturated_T_57 = or(_activated_data_e_act_z_iexp_saturated_T_56, _activated_data_e_act_z_iexp_saturated_T_40) node _activated_data_e_act_z_iexp_saturated_T_58 = or(_activated_data_e_act_z_iexp_saturated_T_57, _activated_data_e_act_z_iexp_saturated_T_42) node _activated_data_e_act_z_iexp_saturated_T_59 = or(_activated_data_e_act_z_iexp_saturated_T_58, _activated_data_e_act_z_iexp_saturated_T_44) node _activated_data_e_act_z_iexp_saturated_T_60 = or(_activated_data_e_act_z_iexp_saturated_T_59, _activated_data_e_act_z_iexp_saturated_T_46) node _activated_data_e_act_z_iexp_saturated_T_61 = or(_activated_data_e_act_z_iexp_saturated_T_60, _activated_data_e_act_z_iexp_saturated_T_48) node _activated_data_e_act_z_iexp_saturated_T_62 = or(_activated_data_e_act_z_iexp_saturated_T_61, _activated_data_e_act_z_iexp_saturated_T_50) node _activated_data_e_act_z_iexp_saturated_T_63 = or(_activated_data_e_act_z_iexp_saturated_T_62, _activated_data_e_act_z_iexp_saturated_T_52) node _activated_data_e_act_z_iexp_saturated_T_64 = or(_activated_data_e_act_z_iexp_saturated_T_63, _activated_data_e_act_z_iexp_saturated_T_54) wire _activated_data_e_act_z_iexp_saturated_WIRE_1 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_1, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_65 = mux(_activated_data_e_act_z_iexp_saturated_T_64, _activated_data_e_act_z_iexp_saturated_WIRE_1, activated_data_e_act_z_iexp_1) connect activated_data_e_act_z_iexp_saturated_1, _activated_data_e_act_z_iexp_saturated_T_65 node _activated_data_e_act_qp_iexp_T_5 = mul(activated_data_e_act_z_iexp_1, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_6 = add(_activated_data_e_act_qp_iexp_T_5, _activated_data_e_act_T_56) node _activated_data_e_act_qp_iexp_T_7 = tail(_activated_data_e_act_qp_iexp_T_6, 1) node _activated_data_e_act_qp_iexp_T_8 = asSInt(_activated_data_e_act_qp_iexp_T_7) node _activated_data_e_act_qp_iexp_T_9 = bits(_activated_data_e_act_qp_iexp_T_8, 31, 0) node activated_data_e_act_qp_iexp_1 = asSInt(_activated_data_e_act_qp_iexp_T_9) node _activated_data_e_act_q_poly_iexp_T_11 = add(activated_data_e_act_qp_iexp_1, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_12 = tail(_activated_data_e_act_q_poly_iexp_T_11, 1) node _activated_data_e_act_q_poly_iexp_T_13 = asSInt(_activated_data_e_act_q_poly_iexp_T_12) node _activated_data_e_act_q_poly_iexp_T_14 = add(activated_data_e_act_qp_iexp_1, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_15 = tail(_activated_data_e_act_q_poly_iexp_T_14, 1) node _activated_data_e_act_q_poly_iexp_T_16 = asSInt(_activated_data_e_act_q_poly_iexp_T_15) node _activated_data_e_act_q_poly_iexp_T_17 = mul(_activated_data_e_act_q_poly_iexp_T_13, _activated_data_e_act_q_poly_iexp_T_16) node _activated_data_e_act_q_poly_iexp_T_18 = add(_activated_data_e_act_q_poly_iexp_T_17, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_19 = tail(_activated_data_e_act_q_poly_iexp_T_18, 1) node _activated_data_e_act_q_poly_iexp_T_20 = asSInt(_activated_data_e_act_q_poly_iexp_T_19) node _activated_data_e_act_q_poly_iexp_T_21 = bits(_activated_data_e_act_q_poly_iexp_T_20, 31, 0) node activated_data_e_act_q_poly_iexp_1 = asSInt(_activated_data_e_act_q_poly_iexp_T_21) node _activated_data_e_act_T_57 = asUInt(activated_data_e_act_q_poly_iexp_1) node _activated_data_e_act_T_58 = asUInt(activated_data_e_act_z_iexp_saturated_1) node _activated_data_e_act_T_59 = dshr(_activated_data_e_act_T_57, _activated_data_e_act_T_58) wire _activated_data_e_act_WIRE_1 : SInt<32> node _activated_data_e_act_T_60 = asSInt(_activated_data_e_act_T_59) connect _activated_data_e_act_WIRE_1, _activated_data_e_act_T_60 node _activated_data_e_act_T_61 = mux(_activated_data_e_act_T_53, _activated_data_e_act_WIRE_1, io.in.bits.acc_read_resp.data[1][0]) node _activated_data_e_act_T_62 = mux(_activated_data_e_act_T_44, _activated_data_e_act_T_50, _activated_data_e_act_T_61) node _activated_data_e_act_T_63 = mux(_activated_data_e_act_T_38, _activated_data_e_act_T_41, _activated_data_e_act_T_62) node activated_data_e_act_1 = mux(_activated_data_e_act_T_33, _activated_data_e_act_T_35, _activated_data_e_act_T_63) node _activated_data_e_scaled_T_11 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_12 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_13 = and(_activated_data_e_scaled_T_11, _activated_data_e_scaled_T_12) node _activated_data_e_scaled_T_14 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_15 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_16 = and(_activated_data_e_scaled_T_14, _activated_data_e_scaled_T_15) wire _activated_data_e_scaled_WIRE_5 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_6 : UInt<32> connect _activated_data_e_scaled_WIRE_6, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_17 = bits(_activated_data_e_scaled_WIRE_6, 31, 0) connect _activated_data_e_scaled_WIRE_5.bits, _activated_data_e_scaled_T_17 node _activated_data_e_scaled_T_18 = mux(_activated_data_e_scaled_T_16, _activated_data_e_scaled_WIRE_5, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_19 = mux(_activated_data_e_scaled_T_13, io.in.bits.inv_stddev, _activated_data_e_scaled_T_18) wire _activated_data_e_scaled_WIRE_7 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_8 : UInt<32> connect _activated_data_e_scaled_WIRE_8, _activated_data_e_scaled_T_19.bits node _activated_data_e_scaled_T_20 = bits(_activated_data_e_scaled_WIRE_8, 31, 0) connect _activated_data_e_scaled_WIRE_7.bits, _activated_data_e_scaled_T_20 node activated_data_e_scaled_f_rec_rawIn_sign_1 = bits(_activated_data_e_scaled_WIRE_7.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_1 = bits(_activated_data_e_scaled_WIRE_7.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_1 = bits(_activated_data_e_scaled_WIRE_7.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_1, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_1, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_44 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_45 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_46 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_47 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_48 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_49 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_50 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_51 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_52 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_53 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_54 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_55 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_56 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_57 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_58 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_59 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_60 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_61 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_62 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_63 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_64 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_65 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_66 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_1, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_67 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_45, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_68 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_46, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_67) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_69 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_47, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_68) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_70 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_48, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_69) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_71 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_49, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_70) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_72 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_50, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_71) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_73 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_51, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_72) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_74 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_52, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_73) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_75 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_53, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_74) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_76 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_54, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_75) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_77 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_55, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_76) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_78 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_56, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_77) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_79 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_57, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_78) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_80 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_58, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_79) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_81 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_59, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_80) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_82 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_60, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_81) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_83 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_61, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_82) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_84 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_62, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_83) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_85 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_63, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_84) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_86 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_64, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_85) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_87 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_65, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_86) node activated_data_e_scaled_f_rec_rawIn_normDist_1 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_66, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_87) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_2 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_1, activated_data_e_scaled_f_rec_rawIn_normDist_1) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_3 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_2, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_1 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_3, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_5 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_1, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_6 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_5, activated_data_e_scaled_f_rec_rawIn_expIn_1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_7 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_7) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_9 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_6, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_8) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_1 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_9, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_1 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_1 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_1, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_1 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_2 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_3 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_1, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_2) connect activated_data_e_scaled_f_rec_rawIn_1.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_3 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_1 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_1, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1) connect activated_data_e_scaled_f_rec_rawIn_1.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_1 connect activated_data_e_scaled_f_rec_rawIn_1.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_1 connect activated_data_e_scaled_f_rec_rawIn_1.sign, activated_data_e_scaled_f_rec_rawIn_sign_1 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_2 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_1, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_3 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_2) connect activated_data_e_scaled_f_rec_rawIn_1.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_3 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_4 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_1, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_4) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_6 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1, activated_data_e_scaled_f_rec_rawIn_subnormFract_1, activated_data_e_scaled_f_rec_rawIn_fractIn_1) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_7 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_5, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_6) connect activated_data_e_scaled_f_rec_rawIn_1.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_7 node _activated_data_e_scaled_f_rec_T_8 = bits(activated_data_e_scaled_f_rec_rawIn_1.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_9 = mux(activated_data_e_scaled_f_rec_rawIn_1.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_8) node _activated_data_e_scaled_f_rec_T_10 = mux(activated_data_e_scaled_f_rec_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_11 = or(_activated_data_e_scaled_f_rec_T_9, _activated_data_e_scaled_f_rec_T_10) node _activated_data_e_scaled_f_rec_T_12 = cat(activated_data_e_scaled_f_rec_rawIn_1.sign, _activated_data_e_scaled_f_rec_T_11) node _activated_data_e_scaled_f_rec_T_13 = bits(activated_data_e_scaled_f_rec_rawIn_1.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_14 = cat(_activated_data_e_scaled_f_rec_T_12, _activated_data_e_scaled_f_rec_T_13) node _activated_data_e_scaled_f_rec_T_15 = bits(activated_data_e_scaled_f_rec_rawIn_1.sig, 22, 0) node activated_data_e_scaled_f_rec_1 = cat(_activated_data_e_scaled_f_rec_T_14, _activated_data_e_scaled_f_rec_T_15) inst activated_data_e_scaled_in_to_rec_fn_1 of INToRecFN_i32_e8_s24_1 connect activated_data_e_scaled_in_to_rec_fn_1.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_1 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_1 = asUInt(activated_data_e_act_1) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_1, _activated_data_e_scaled_in_to_rec_fn_io_in_T_1 connect activated_data_e_scaled_in_to_rec_fn_1.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_1 connect activated_data_e_scaled_in_to_rec_fn_1.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_1.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_1 of MulAddRecFN_e8_s24_5 connect activated_data_e_scaled_muladder_1.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_1.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_1.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_1.io.a, activated_data_e_scaled_in_to_rec_fn_1.io.out connect activated_data_e_scaled_muladder_1.io.b, activated_data_e_scaled_f_rec_1 connect activated_data_e_scaled_muladder_1.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_1 of RecFNToIN_e8_s24_i32_1 connect activated_data_e_scaled_rec_fn_to_in_1.clock, clock connect activated_data_e_scaled_rec_fn_to_in_1.reset, reset connect activated_data_e_scaled_rec_fn_to_in_1.io.in, activated_data_e_scaled_muladder_1.io.out connect activated_data_e_scaled_rec_fn_to_in_1.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_1.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_1 = bits(activated_data_e_scaled_rec_fn_to_in_1.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_1 = bits(activated_data_e_scaled_rec_fn_to_in_1.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_1 = bits(activated_data_e_scaled_sign_exp_1, 8, 6) node activated_data_e_scaled_sign_isZero_1 = eq(_activated_data_e_scaled_sign_isZero_T_1, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_1 = bits(activated_data_e_scaled_sign_exp_1, 8, 7) node activated_data_e_scaled_sign_isSpecial_1 = eq(_activated_data_e_scaled_sign_isSpecial_T_1, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_2 = bits(activated_data_e_scaled_sign_exp_1, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_3 = and(activated_data_e_scaled_sign_isSpecial_1, _activated_data_e_scaled_sign_out_isNaN_T_2) connect activated_data_e_scaled_sign_out_1.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_3 node _activated_data_e_scaled_sign_out_isInf_T_3 = bits(activated_data_e_scaled_sign_exp_1, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_4 = eq(_activated_data_e_scaled_sign_out_isInf_T_3, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_5 = and(activated_data_e_scaled_sign_isSpecial_1, _activated_data_e_scaled_sign_out_isInf_T_4) connect activated_data_e_scaled_sign_out_1.isInf, _activated_data_e_scaled_sign_out_isInf_T_5 connect activated_data_e_scaled_sign_out_1.isZero, activated_data_e_scaled_sign_isZero_1 node _activated_data_e_scaled_sign_out_sign_T_1 = bits(activated_data_e_scaled_rec_fn_to_in_1.io.in, 32, 32) connect activated_data_e_scaled_sign_out_1.sign, _activated_data_e_scaled_sign_out_sign_T_1 node _activated_data_e_scaled_sign_out_sExp_T_1 = cvt(activated_data_e_scaled_sign_exp_1) connect activated_data_e_scaled_sign_out_1.sExp, _activated_data_e_scaled_sign_out_sExp_T_1 node _activated_data_e_scaled_sign_out_sig_T_4 = eq(activated_data_e_scaled_sign_isZero_1, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_5 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_4) node _activated_data_e_scaled_sign_out_sig_T_6 = bits(activated_data_e_scaled_rec_fn_to_in_1.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_7 = cat(_activated_data_e_scaled_sign_out_sig_T_5, _activated_data_e_scaled_sign_out_sig_T_6) connect activated_data_e_scaled_sign_out_1.sig, _activated_data_e_scaled_sign_out_sig_T_7 node activated_data_e_scaled_sat_1 = mux(activated_data_e_scaled_sign_out_1.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_9 : SInt<32> node _activated_data_e_scaled_T_21 = asSInt(activated_data_e_scaled_rec_fn_to_in_1.io.out) connect _activated_data_e_scaled_WIRE_9, _activated_data_e_scaled_T_21 node activated_data_e_scaled_1 = mux(activated_data_e_scaled_overflow_1, activated_data_e_scaled_sat_1, _activated_data_e_scaled_WIRE_9) node _activated_data_e_clipped_T_5 = gt(activated_data_e_scaled_1, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_6 = lt(activated_data_e_scaled_1, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_7 = mux(_activated_data_e_clipped_T_6, asSInt(UInt<8>(0h80)), activated_data_e_scaled_1) node _activated_data_e_clipped_T_8 = mux(_activated_data_e_clipped_T_5, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_7) node _activated_data_e_clipped_T_9 = bits(_activated_data_e_clipped_T_8, 7, 0) node activated_data_e_clipped_1 = asSInt(_activated_data_e_clipped_T_9) wire _activated_data_WIRE_1 : SInt<8>[1] connect _activated_data_WIRE_1[0], activated_data_e_clipped_1 node _activated_data_e_act_T_64 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_65 = and(UInt<1>(0h1), _activated_data_e_act_T_64) node _activated_data_e_act_T_66 = geq(io.in.bits.acc_read_resp.data[2][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_67 = mux(_activated_data_e_act_T_66, io.in.bits.acc_read_resp.data[2][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_68 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_69 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_70 = and(_activated_data_e_act_T_68, _activated_data_e_act_T_69) node _activated_data_e_act_T_71 = sub(io.in.bits.acc_read_resp.data[2][0], io.in.bits.mean) node _activated_data_e_act_T_72 = tail(_activated_data_e_act_T_71, 1) node _activated_data_e_act_T_73 = asSInt(_activated_data_e_act_T_72) node _activated_data_e_act_T_74 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_75 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_76 = and(_activated_data_e_act_T_74, _activated_data_e_act_T_75) node _activated_data_e_act_q_sign_T_8 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[2][0]) node _activated_data_e_act_q_sign_T_9 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_10 = tail(_activated_data_e_act_q_sign_T_9, 1) node _activated_data_e_act_q_sign_T_11 = asSInt(_activated_data_e_act_q_sign_T_10) node activated_data_e_act_q_sign_2 = mux(_activated_data_e_act_q_sign_T_8, _activated_data_e_act_q_sign_T_11, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_8 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[2][0]) node _activated_data_e_act_q_abs_T_9 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[2][0]) node _activated_data_e_act_q_abs_T_10 = tail(_activated_data_e_act_q_abs_T_9, 1) node _activated_data_e_act_q_abs_T_11 = asSInt(_activated_data_e_act_q_abs_T_10) node activated_data_e_act_q_abs_2 = mux(_activated_data_e_act_q_abs_T_8, _activated_data_e_act_q_abs_T_11, io.in.bits.acc_read_resp.data[2][0]) node _activated_data_e_act_q_clipped_T_14 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_15 = tail(_activated_data_e_act_q_clipped_T_14, 1) node _activated_data_e_act_q_clipped_T_16 = asSInt(_activated_data_e_act_q_clipped_T_15) node _activated_data_e_act_q_clipped_T_17 = gt(activated_data_e_act_q_abs_2, _activated_data_e_act_q_clipped_T_16) node _activated_data_e_act_q_clipped_T_18 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_19 = tail(_activated_data_e_act_q_clipped_T_18, 1) node _activated_data_e_act_q_clipped_T_20 = asSInt(_activated_data_e_act_q_clipped_T_19) node activated_data_e_act_q_clipped_2 = mux(_activated_data_e_act_q_clipped_T_17, _activated_data_e_act_q_clipped_T_20, activated_data_e_act_q_abs_2) node _activated_data_e_act_q_poly_T_22 = add(activated_data_e_act_q_clipped_2, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_23 = tail(_activated_data_e_act_q_poly_T_22, 1) node _activated_data_e_act_q_poly_T_24 = asSInt(_activated_data_e_act_q_poly_T_23) node _activated_data_e_act_q_poly_T_25 = add(activated_data_e_act_q_clipped_2, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_26 = tail(_activated_data_e_act_q_poly_T_25, 1) node _activated_data_e_act_q_poly_T_27 = asSInt(_activated_data_e_act_q_poly_T_26) node _activated_data_e_act_q_poly_T_28 = mul(_activated_data_e_act_q_poly_T_24, _activated_data_e_act_q_poly_T_27) node _activated_data_e_act_q_poly_T_29 = add(_activated_data_e_act_q_poly_T_28, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_30 = tail(_activated_data_e_act_q_poly_T_29, 1) node _activated_data_e_act_q_poly_T_31 = asSInt(_activated_data_e_act_q_poly_T_30) node _activated_data_e_act_q_poly_T_32 = bits(_activated_data_e_act_q_poly_T_31, 31, 0) node activated_data_e_act_q_poly_2 = asSInt(_activated_data_e_act_q_poly_T_32) node _activated_data_e_act_q_erf_T_4 = mul(activated_data_e_act_q_sign_2, activated_data_e_act_q_poly_2) node _activated_data_e_act_q_erf_T_5 = bits(_activated_data_e_act_q_erf_T_4, 31, 0) node activated_data_e_act_q_erf_2 = asSInt(_activated_data_e_act_q_erf_T_5) node _activated_data_e_act_T_77 = add(activated_data_e_act_q_erf_2, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_78 = tail(_activated_data_e_act_T_77, 1) node _activated_data_e_act_T_79 = asSInt(_activated_data_e_act_T_78) node _activated_data_e_act_T_80 = mul(io.in.bits.acc_read_resp.data[2][0], _activated_data_e_act_T_79) node _activated_data_e_act_T_81 = bits(_activated_data_e_act_T_80, 31, 0) node _activated_data_e_act_T_82 = asSInt(_activated_data_e_act_T_81) node _activated_data_e_act_T_83 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_84 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_85 = and(_activated_data_e_act_T_83, _activated_data_e_act_T_84) node _activated_data_e_act_T_86 = sub(io.in.bits.acc_read_resp.data[2][0], io.in.bits.max) node _activated_data_e_act_T_87 = tail(_activated_data_e_act_T_86, 1) node _activated_data_e_act_T_88 = asSInt(_activated_data_e_act_T_87) node _activated_data_e_act_neg_q_iexp_T_4 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_88) node _activated_data_e_act_neg_q_iexp_T_5 = tail(_activated_data_e_act_neg_q_iexp_T_4, 1) node activated_data_e_act_neg_q_iexp_2 = asSInt(_activated_data_e_act_neg_q_iexp_T_5) node _activated_data_e_act_z_iexp_T_8 = mul(activated_data_e_act_neg_q_iexp_2, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_9 = asUInt(_activated_data_e_act_z_iexp_T_8) node _activated_data_e_act_z_iexp_T_10 = shr(_activated_data_e_act_z_iexp_T_9, 16) wire activated_data_e_act_z_iexp_2 : SInt<32> node _activated_data_e_act_z_iexp_T_11 = asSInt(_activated_data_e_act_z_iexp_T_10) connect activated_data_e_act_z_iexp_2, _activated_data_e_act_z_iexp_T_11 wire activated_data_e_act_z_iexp_saturated_2 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_66 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_67 = bits(_activated_data_e_act_z_iexp_saturated_T_66, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_68 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_69 = bits(_activated_data_e_act_z_iexp_saturated_T_68, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_70 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_71 = bits(_activated_data_e_act_z_iexp_saturated_T_70, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_72 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_73 = bits(_activated_data_e_act_z_iexp_saturated_T_72, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_74 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_75 = bits(_activated_data_e_act_z_iexp_saturated_T_74, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_76 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_77 = bits(_activated_data_e_act_z_iexp_saturated_T_76, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_78 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_79 = bits(_activated_data_e_act_z_iexp_saturated_T_78, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_80 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_81 = bits(_activated_data_e_act_z_iexp_saturated_T_80, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_82 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_83 = bits(_activated_data_e_act_z_iexp_saturated_T_82, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_84 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_85 = bits(_activated_data_e_act_z_iexp_saturated_T_84, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_86 = asUInt(activated_data_e_act_z_iexp_2) node _activated_data_e_act_z_iexp_saturated_T_87 = bits(_activated_data_e_act_z_iexp_saturated_T_86, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_88 = or(_activated_data_e_act_z_iexp_saturated_T_67, _activated_data_e_act_z_iexp_saturated_T_69) node _activated_data_e_act_z_iexp_saturated_T_89 = or(_activated_data_e_act_z_iexp_saturated_T_88, _activated_data_e_act_z_iexp_saturated_T_71) node _activated_data_e_act_z_iexp_saturated_T_90 = or(_activated_data_e_act_z_iexp_saturated_T_89, _activated_data_e_act_z_iexp_saturated_T_73) node _activated_data_e_act_z_iexp_saturated_T_91 = or(_activated_data_e_act_z_iexp_saturated_T_90, _activated_data_e_act_z_iexp_saturated_T_75) node _activated_data_e_act_z_iexp_saturated_T_92 = or(_activated_data_e_act_z_iexp_saturated_T_91, _activated_data_e_act_z_iexp_saturated_T_77) node _activated_data_e_act_z_iexp_saturated_T_93 = or(_activated_data_e_act_z_iexp_saturated_T_92, _activated_data_e_act_z_iexp_saturated_T_79) node _activated_data_e_act_z_iexp_saturated_T_94 = or(_activated_data_e_act_z_iexp_saturated_T_93, _activated_data_e_act_z_iexp_saturated_T_81) node _activated_data_e_act_z_iexp_saturated_T_95 = or(_activated_data_e_act_z_iexp_saturated_T_94, _activated_data_e_act_z_iexp_saturated_T_83) node _activated_data_e_act_z_iexp_saturated_T_96 = or(_activated_data_e_act_z_iexp_saturated_T_95, _activated_data_e_act_z_iexp_saturated_T_85) node _activated_data_e_act_z_iexp_saturated_T_97 = or(_activated_data_e_act_z_iexp_saturated_T_96, _activated_data_e_act_z_iexp_saturated_T_87) wire _activated_data_e_act_z_iexp_saturated_WIRE_2 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_2, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_98 = mux(_activated_data_e_act_z_iexp_saturated_T_97, _activated_data_e_act_z_iexp_saturated_WIRE_2, activated_data_e_act_z_iexp_2) connect activated_data_e_act_z_iexp_saturated_2, _activated_data_e_act_z_iexp_saturated_T_98 node _activated_data_e_act_qp_iexp_T_10 = mul(activated_data_e_act_z_iexp_2, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_11 = add(_activated_data_e_act_qp_iexp_T_10, _activated_data_e_act_T_88) node _activated_data_e_act_qp_iexp_T_12 = tail(_activated_data_e_act_qp_iexp_T_11, 1) node _activated_data_e_act_qp_iexp_T_13 = asSInt(_activated_data_e_act_qp_iexp_T_12) node _activated_data_e_act_qp_iexp_T_14 = bits(_activated_data_e_act_qp_iexp_T_13, 31, 0) node activated_data_e_act_qp_iexp_2 = asSInt(_activated_data_e_act_qp_iexp_T_14) node _activated_data_e_act_q_poly_iexp_T_22 = add(activated_data_e_act_qp_iexp_2, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_23 = tail(_activated_data_e_act_q_poly_iexp_T_22, 1) node _activated_data_e_act_q_poly_iexp_T_24 = asSInt(_activated_data_e_act_q_poly_iexp_T_23) node _activated_data_e_act_q_poly_iexp_T_25 = add(activated_data_e_act_qp_iexp_2, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_26 = tail(_activated_data_e_act_q_poly_iexp_T_25, 1) node _activated_data_e_act_q_poly_iexp_T_27 = asSInt(_activated_data_e_act_q_poly_iexp_T_26) node _activated_data_e_act_q_poly_iexp_T_28 = mul(_activated_data_e_act_q_poly_iexp_T_24, _activated_data_e_act_q_poly_iexp_T_27) node _activated_data_e_act_q_poly_iexp_T_29 = add(_activated_data_e_act_q_poly_iexp_T_28, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_30 = tail(_activated_data_e_act_q_poly_iexp_T_29, 1) node _activated_data_e_act_q_poly_iexp_T_31 = asSInt(_activated_data_e_act_q_poly_iexp_T_30) node _activated_data_e_act_q_poly_iexp_T_32 = bits(_activated_data_e_act_q_poly_iexp_T_31, 31, 0) node activated_data_e_act_q_poly_iexp_2 = asSInt(_activated_data_e_act_q_poly_iexp_T_32) node _activated_data_e_act_T_89 = asUInt(activated_data_e_act_q_poly_iexp_2) node _activated_data_e_act_T_90 = asUInt(activated_data_e_act_z_iexp_saturated_2) node _activated_data_e_act_T_91 = dshr(_activated_data_e_act_T_89, _activated_data_e_act_T_90) wire _activated_data_e_act_WIRE_2 : SInt<32> node _activated_data_e_act_T_92 = asSInt(_activated_data_e_act_T_91) connect _activated_data_e_act_WIRE_2, _activated_data_e_act_T_92 node _activated_data_e_act_T_93 = mux(_activated_data_e_act_T_85, _activated_data_e_act_WIRE_2, io.in.bits.acc_read_resp.data[2][0]) node _activated_data_e_act_T_94 = mux(_activated_data_e_act_T_76, _activated_data_e_act_T_82, _activated_data_e_act_T_93) node _activated_data_e_act_T_95 = mux(_activated_data_e_act_T_70, _activated_data_e_act_T_73, _activated_data_e_act_T_94) node activated_data_e_act_2 = mux(_activated_data_e_act_T_65, _activated_data_e_act_T_67, _activated_data_e_act_T_95) node _activated_data_e_scaled_T_22 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_23 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_24 = and(_activated_data_e_scaled_T_22, _activated_data_e_scaled_T_23) node _activated_data_e_scaled_T_25 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_26 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_27 = and(_activated_data_e_scaled_T_25, _activated_data_e_scaled_T_26) wire _activated_data_e_scaled_WIRE_10 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_11 : UInt<32> connect _activated_data_e_scaled_WIRE_11, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_28 = bits(_activated_data_e_scaled_WIRE_11, 31, 0) connect _activated_data_e_scaled_WIRE_10.bits, _activated_data_e_scaled_T_28 node _activated_data_e_scaled_T_29 = mux(_activated_data_e_scaled_T_27, _activated_data_e_scaled_WIRE_10, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_30 = mux(_activated_data_e_scaled_T_24, io.in.bits.inv_stddev, _activated_data_e_scaled_T_29) wire _activated_data_e_scaled_WIRE_12 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_13 : UInt<32> connect _activated_data_e_scaled_WIRE_13, _activated_data_e_scaled_T_30.bits node _activated_data_e_scaled_T_31 = bits(_activated_data_e_scaled_WIRE_13, 31, 0) connect _activated_data_e_scaled_WIRE_12.bits, _activated_data_e_scaled_T_31 node activated_data_e_scaled_f_rec_rawIn_sign_2 = bits(_activated_data_e_scaled_WIRE_12.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_2 = bits(_activated_data_e_scaled_WIRE_12.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_2 = bits(_activated_data_e_scaled_WIRE_12.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_2, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_2, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_88 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_89 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_90 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_91 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_92 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_93 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_94 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_95 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_96 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_97 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_98 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_99 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_100 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_101 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_102 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_103 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_104 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_105 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_106 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_107 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_108 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_109 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_110 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_2, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_111 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_89, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_112 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_90, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_111) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_113 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_91, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_112) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_114 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_92, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_113) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_115 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_93, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_114) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_116 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_94, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_115) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_117 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_95, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_116) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_118 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_96, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_117) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_119 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_97, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_118) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_120 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_98, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_119) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_121 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_99, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_120) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_122 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_100, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_121) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_123 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_101, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_122) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_124 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_102, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_123) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_125 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_103, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_124) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_126 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_104, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_125) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_127 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_105, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_126) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_128 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_106, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_127) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_129 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_107, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_128) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_130 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_108, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_129) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_131 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_109, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_130) node activated_data_e_scaled_f_rec_rawIn_normDist_2 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_110, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_131) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_4 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_2, activated_data_e_scaled_f_rec_rawIn_normDist_2) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_5 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_4, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_2 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_5, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_10 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_2, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_11 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_10, activated_data_e_scaled_f_rec_rawIn_expIn_2) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_12 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_13 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_12) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_14 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_11, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_13) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_2 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_14, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_2 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_2 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_2, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_2 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_4 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_5 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_2, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_4) connect activated_data_e_scaled_f_rec_rawIn_2.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_5 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_2 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_2, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2) connect activated_data_e_scaled_f_rec_rawIn_2.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_2 connect activated_data_e_scaled_f_rec_rawIn_2.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_2 connect activated_data_e_scaled_f_rec_rawIn_2.sign, activated_data_e_scaled_f_rec_rawIn_sign_2 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_4 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_2, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_5 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_4) connect activated_data_e_scaled_f_rec_rawIn_2.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_5 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_8 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_2, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_8) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_10 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2, activated_data_e_scaled_f_rec_rawIn_subnormFract_2, activated_data_e_scaled_f_rec_rawIn_fractIn_2) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_11 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_9, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_10) connect activated_data_e_scaled_f_rec_rawIn_2.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_11 node _activated_data_e_scaled_f_rec_T_16 = bits(activated_data_e_scaled_f_rec_rawIn_2.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_17 = mux(activated_data_e_scaled_f_rec_rawIn_2.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_16) node _activated_data_e_scaled_f_rec_T_18 = mux(activated_data_e_scaled_f_rec_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_19 = or(_activated_data_e_scaled_f_rec_T_17, _activated_data_e_scaled_f_rec_T_18) node _activated_data_e_scaled_f_rec_T_20 = cat(activated_data_e_scaled_f_rec_rawIn_2.sign, _activated_data_e_scaled_f_rec_T_19) node _activated_data_e_scaled_f_rec_T_21 = bits(activated_data_e_scaled_f_rec_rawIn_2.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_22 = cat(_activated_data_e_scaled_f_rec_T_20, _activated_data_e_scaled_f_rec_T_21) node _activated_data_e_scaled_f_rec_T_23 = bits(activated_data_e_scaled_f_rec_rawIn_2.sig, 22, 0) node activated_data_e_scaled_f_rec_2 = cat(_activated_data_e_scaled_f_rec_T_22, _activated_data_e_scaled_f_rec_T_23) inst activated_data_e_scaled_in_to_rec_fn_2 of INToRecFN_i32_e8_s24_2 connect activated_data_e_scaled_in_to_rec_fn_2.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_2 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_2 = asUInt(activated_data_e_act_2) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_2, _activated_data_e_scaled_in_to_rec_fn_io_in_T_2 connect activated_data_e_scaled_in_to_rec_fn_2.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_2 connect activated_data_e_scaled_in_to_rec_fn_2.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_2.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_2 of MulAddRecFN_e8_s24_6 connect activated_data_e_scaled_muladder_2.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_2.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_2.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_2.io.a, activated_data_e_scaled_in_to_rec_fn_2.io.out connect activated_data_e_scaled_muladder_2.io.b, activated_data_e_scaled_f_rec_2 connect activated_data_e_scaled_muladder_2.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_2 of RecFNToIN_e8_s24_i32_2 connect activated_data_e_scaled_rec_fn_to_in_2.clock, clock connect activated_data_e_scaled_rec_fn_to_in_2.reset, reset connect activated_data_e_scaled_rec_fn_to_in_2.io.in, activated_data_e_scaled_muladder_2.io.out connect activated_data_e_scaled_rec_fn_to_in_2.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_2.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_2 = bits(activated_data_e_scaled_rec_fn_to_in_2.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_2 = bits(activated_data_e_scaled_rec_fn_to_in_2.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_2 = bits(activated_data_e_scaled_sign_exp_2, 8, 6) node activated_data_e_scaled_sign_isZero_2 = eq(_activated_data_e_scaled_sign_isZero_T_2, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_2 = bits(activated_data_e_scaled_sign_exp_2, 8, 7) node activated_data_e_scaled_sign_isSpecial_2 = eq(_activated_data_e_scaled_sign_isSpecial_T_2, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_4 = bits(activated_data_e_scaled_sign_exp_2, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_5 = and(activated_data_e_scaled_sign_isSpecial_2, _activated_data_e_scaled_sign_out_isNaN_T_4) connect activated_data_e_scaled_sign_out_2.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_5 node _activated_data_e_scaled_sign_out_isInf_T_6 = bits(activated_data_e_scaled_sign_exp_2, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_7 = eq(_activated_data_e_scaled_sign_out_isInf_T_6, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_8 = and(activated_data_e_scaled_sign_isSpecial_2, _activated_data_e_scaled_sign_out_isInf_T_7) connect activated_data_e_scaled_sign_out_2.isInf, _activated_data_e_scaled_sign_out_isInf_T_8 connect activated_data_e_scaled_sign_out_2.isZero, activated_data_e_scaled_sign_isZero_2 node _activated_data_e_scaled_sign_out_sign_T_2 = bits(activated_data_e_scaled_rec_fn_to_in_2.io.in, 32, 32) connect activated_data_e_scaled_sign_out_2.sign, _activated_data_e_scaled_sign_out_sign_T_2 node _activated_data_e_scaled_sign_out_sExp_T_2 = cvt(activated_data_e_scaled_sign_exp_2) connect activated_data_e_scaled_sign_out_2.sExp, _activated_data_e_scaled_sign_out_sExp_T_2 node _activated_data_e_scaled_sign_out_sig_T_8 = eq(activated_data_e_scaled_sign_isZero_2, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_9 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_8) node _activated_data_e_scaled_sign_out_sig_T_10 = bits(activated_data_e_scaled_rec_fn_to_in_2.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_11 = cat(_activated_data_e_scaled_sign_out_sig_T_9, _activated_data_e_scaled_sign_out_sig_T_10) connect activated_data_e_scaled_sign_out_2.sig, _activated_data_e_scaled_sign_out_sig_T_11 node activated_data_e_scaled_sat_2 = mux(activated_data_e_scaled_sign_out_2.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_14 : SInt<32> node _activated_data_e_scaled_T_32 = asSInt(activated_data_e_scaled_rec_fn_to_in_2.io.out) connect _activated_data_e_scaled_WIRE_14, _activated_data_e_scaled_T_32 node activated_data_e_scaled_2 = mux(activated_data_e_scaled_overflow_2, activated_data_e_scaled_sat_2, _activated_data_e_scaled_WIRE_14) node _activated_data_e_clipped_T_10 = gt(activated_data_e_scaled_2, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_11 = lt(activated_data_e_scaled_2, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_12 = mux(_activated_data_e_clipped_T_11, asSInt(UInt<8>(0h80)), activated_data_e_scaled_2) node _activated_data_e_clipped_T_13 = mux(_activated_data_e_clipped_T_10, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_12) node _activated_data_e_clipped_T_14 = bits(_activated_data_e_clipped_T_13, 7, 0) node activated_data_e_clipped_2 = asSInt(_activated_data_e_clipped_T_14) wire _activated_data_WIRE_2 : SInt<8>[1] connect _activated_data_WIRE_2[0], activated_data_e_clipped_2 node _activated_data_e_act_T_96 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_97 = and(UInt<1>(0h1), _activated_data_e_act_T_96) node _activated_data_e_act_T_98 = geq(io.in.bits.acc_read_resp.data[3][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_99 = mux(_activated_data_e_act_T_98, io.in.bits.acc_read_resp.data[3][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_100 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_101 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_102 = and(_activated_data_e_act_T_100, _activated_data_e_act_T_101) node _activated_data_e_act_T_103 = sub(io.in.bits.acc_read_resp.data[3][0], io.in.bits.mean) node _activated_data_e_act_T_104 = tail(_activated_data_e_act_T_103, 1) node _activated_data_e_act_T_105 = asSInt(_activated_data_e_act_T_104) node _activated_data_e_act_T_106 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_107 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_108 = and(_activated_data_e_act_T_106, _activated_data_e_act_T_107) node _activated_data_e_act_q_sign_T_12 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[3][0]) node _activated_data_e_act_q_sign_T_13 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_14 = tail(_activated_data_e_act_q_sign_T_13, 1) node _activated_data_e_act_q_sign_T_15 = asSInt(_activated_data_e_act_q_sign_T_14) node activated_data_e_act_q_sign_3 = mux(_activated_data_e_act_q_sign_T_12, _activated_data_e_act_q_sign_T_15, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_12 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[3][0]) node _activated_data_e_act_q_abs_T_13 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[3][0]) node _activated_data_e_act_q_abs_T_14 = tail(_activated_data_e_act_q_abs_T_13, 1) node _activated_data_e_act_q_abs_T_15 = asSInt(_activated_data_e_act_q_abs_T_14) node activated_data_e_act_q_abs_3 = mux(_activated_data_e_act_q_abs_T_12, _activated_data_e_act_q_abs_T_15, io.in.bits.acc_read_resp.data[3][0]) node _activated_data_e_act_q_clipped_T_21 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_22 = tail(_activated_data_e_act_q_clipped_T_21, 1) node _activated_data_e_act_q_clipped_T_23 = asSInt(_activated_data_e_act_q_clipped_T_22) node _activated_data_e_act_q_clipped_T_24 = gt(activated_data_e_act_q_abs_3, _activated_data_e_act_q_clipped_T_23) node _activated_data_e_act_q_clipped_T_25 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_26 = tail(_activated_data_e_act_q_clipped_T_25, 1) node _activated_data_e_act_q_clipped_T_27 = asSInt(_activated_data_e_act_q_clipped_T_26) node activated_data_e_act_q_clipped_3 = mux(_activated_data_e_act_q_clipped_T_24, _activated_data_e_act_q_clipped_T_27, activated_data_e_act_q_abs_3) node _activated_data_e_act_q_poly_T_33 = add(activated_data_e_act_q_clipped_3, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_34 = tail(_activated_data_e_act_q_poly_T_33, 1) node _activated_data_e_act_q_poly_T_35 = asSInt(_activated_data_e_act_q_poly_T_34) node _activated_data_e_act_q_poly_T_36 = add(activated_data_e_act_q_clipped_3, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_37 = tail(_activated_data_e_act_q_poly_T_36, 1) node _activated_data_e_act_q_poly_T_38 = asSInt(_activated_data_e_act_q_poly_T_37) node _activated_data_e_act_q_poly_T_39 = mul(_activated_data_e_act_q_poly_T_35, _activated_data_e_act_q_poly_T_38) node _activated_data_e_act_q_poly_T_40 = add(_activated_data_e_act_q_poly_T_39, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_41 = tail(_activated_data_e_act_q_poly_T_40, 1) node _activated_data_e_act_q_poly_T_42 = asSInt(_activated_data_e_act_q_poly_T_41) node _activated_data_e_act_q_poly_T_43 = bits(_activated_data_e_act_q_poly_T_42, 31, 0) node activated_data_e_act_q_poly_3 = asSInt(_activated_data_e_act_q_poly_T_43) node _activated_data_e_act_q_erf_T_6 = mul(activated_data_e_act_q_sign_3, activated_data_e_act_q_poly_3) node _activated_data_e_act_q_erf_T_7 = bits(_activated_data_e_act_q_erf_T_6, 31, 0) node activated_data_e_act_q_erf_3 = asSInt(_activated_data_e_act_q_erf_T_7) node _activated_data_e_act_T_109 = add(activated_data_e_act_q_erf_3, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_110 = tail(_activated_data_e_act_T_109, 1) node _activated_data_e_act_T_111 = asSInt(_activated_data_e_act_T_110) node _activated_data_e_act_T_112 = mul(io.in.bits.acc_read_resp.data[3][0], _activated_data_e_act_T_111) node _activated_data_e_act_T_113 = bits(_activated_data_e_act_T_112, 31, 0) node _activated_data_e_act_T_114 = asSInt(_activated_data_e_act_T_113) node _activated_data_e_act_T_115 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_116 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_117 = and(_activated_data_e_act_T_115, _activated_data_e_act_T_116) node _activated_data_e_act_T_118 = sub(io.in.bits.acc_read_resp.data[3][0], io.in.bits.max) node _activated_data_e_act_T_119 = tail(_activated_data_e_act_T_118, 1) node _activated_data_e_act_T_120 = asSInt(_activated_data_e_act_T_119) node _activated_data_e_act_neg_q_iexp_T_6 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_120) node _activated_data_e_act_neg_q_iexp_T_7 = tail(_activated_data_e_act_neg_q_iexp_T_6, 1) node activated_data_e_act_neg_q_iexp_3 = asSInt(_activated_data_e_act_neg_q_iexp_T_7) node _activated_data_e_act_z_iexp_T_12 = mul(activated_data_e_act_neg_q_iexp_3, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_13 = asUInt(_activated_data_e_act_z_iexp_T_12) node _activated_data_e_act_z_iexp_T_14 = shr(_activated_data_e_act_z_iexp_T_13, 16) wire activated_data_e_act_z_iexp_3 : SInt<32> node _activated_data_e_act_z_iexp_T_15 = asSInt(_activated_data_e_act_z_iexp_T_14) connect activated_data_e_act_z_iexp_3, _activated_data_e_act_z_iexp_T_15 wire activated_data_e_act_z_iexp_saturated_3 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_99 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_100 = bits(_activated_data_e_act_z_iexp_saturated_T_99, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_101 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_102 = bits(_activated_data_e_act_z_iexp_saturated_T_101, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_103 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_104 = bits(_activated_data_e_act_z_iexp_saturated_T_103, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_105 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_106 = bits(_activated_data_e_act_z_iexp_saturated_T_105, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_107 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_108 = bits(_activated_data_e_act_z_iexp_saturated_T_107, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_109 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_110 = bits(_activated_data_e_act_z_iexp_saturated_T_109, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_111 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_112 = bits(_activated_data_e_act_z_iexp_saturated_T_111, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_113 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_114 = bits(_activated_data_e_act_z_iexp_saturated_T_113, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_115 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_116 = bits(_activated_data_e_act_z_iexp_saturated_T_115, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_117 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_118 = bits(_activated_data_e_act_z_iexp_saturated_T_117, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_119 = asUInt(activated_data_e_act_z_iexp_3) node _activated_data_e_act_z_iexp_saturated_T_120 = bits(_activated_data_e_act_z_iexp_saturated_T_119, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_121 = or(_activated_data_e_act_z_iexp_saturated_T_100, _activated_data_e_act_z_iexp_saturated_T_102) node _activated_data_e_act_z_iexp_saturated_T_122 = or(_activated_data_e_act_z_iexp_saturated_T_121, _activated_data_e_act_z_iexp_saturated_T_104) node _activated_data_e_act_z_iexp_saturated_T_123 = or(_activated_data_e_act_z_iexp_saturated_T_122, _activated_data_e_act_z_iexp_saturated_T_106) node _activated_data_e_act_z_iexp_saturated_T_124 = or(_activated_data_e_act_z_iexp_saturated_T_123, _activated_data_e_act_z_iexp_saturated_T_108) node _activated_data_e_act_z_iexp_saturated_T_125 = or(_activated_data_e_act_z_iexp_saturated_T_124, _activated_data_e_act_z_iexp_saturated_T_110) node _activated_data_e_act_z_iexp_saturated_T_126 = or(_activated_data_e_act_z_iexp_saturated_T_125, _activated_data_e_act_z_iexp_saturated_T_112) node _activated_data_e_act_z_iexp_saturated_T_127 = or(_activated_data_e_act_z_iexp_saturated_T_126, _activated_data_e_act_z_iexp_saturated_T_114) node _activated_data_e_act_z_iexp_saturated_T_128 = or(_activated_data_e_act_z_iexp_saturated_T_127, _activated_data_e_act_z_iexp_saturated_T_116) node _activated_data_e_act_z_iexp_saturated_T_129 = or(_activated_data_e_act_z_iexp_saturated_T_128, _activated_data_e_act_z_iexp_saturated_T_118) node _activated_data_e_act_z_iexp_saturated_T_130 = or(_activated_data_e_act_z_iexp_saturated_T_129, _activated_data_e_act_z_iexp_saturated_T_120) wire _activated_data_e_act_z_iexp_saturated_WIRE_3 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_3, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_131 = mux(_activated_data_e_act_z_iexp_saturated_T_130, _activated_data_e_act_z_iexp_saturated_WIRE_3, activated_data_e_act_z_iexp_3) connect activated_data_e_act_z_iexp_saturated_3, _activated_data_e_act_z_iexp_saturated_T_131 node _activated_data_e_act_qp_iexp_T_15 = mul(activated_data_e_act_z_iexp_3, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_16 = add(_activated_data_e_act_qp_iexp_T_15, _activated_data_e_act_T_120) node _activated_data_e_act_qp_iexp_T_17 = tail(_activated_data_e_act_qp_iexp_T_16, 1) node _activated_data_e_act_qp_iexp_T_18 = asSInt(_activated_data_e_act_qp_iexp_T_17) node _activated_data_e_act_qp_iexp_T_19 = bits(_activated_data_e_act_qp_iexp_T_18, 31, 0) node activated_data_e_act_qp_iexp_3 = asSInt(_activated_data_e_act_qp_iexp_T_19) node _activated_data_e_act_q_poly_iexp_T_33 = add(activated_data_e_act_qp_iexp_3, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_34 = tail(_activated_data_e_act_q_poly_iexp_T_33, 1) node _activated_data_e_act_q_poly_iexp_T_35 = asSInt(_activated_data_e_act_q_poly_iexp_T_34) node _activated_data_e_act_q_poly_iexp_T_36 = add(activated_data_e_act_qp_iexp_3, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_37 = tail(_activated_data_e_act_q_poly_iexp_T_36, 1) node _activated_data_e_act_q_poly_iexp_T_38 = asSInt(_activated_data_e_act_q_poly_iexp_T_37) node _activated_data_e_act_q_poly_iexp_T_39 = mul(_activated_data_e_act_q_poly_iexp_T_35, _activated_data_e_act_q_poly_iexp_T_38) node _activated_data_e_act_q_poly_iexp_T_40 = add(_activated_data_e_act_q_poly_iexp_T_39, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_41 = tail(_activated_data_e_act_q_poly_iexp_T_40, 1) node _activated_data_e_act_q_poly_iexp_T_42 = asSInt(_activated_data_e_act_q_poly_iexp_T_41) node _activated_data_e_act_q_poly_iexp_T_43 = bits(_activated_data_e_act_q_poly_iexp_T_42, 31, 0) node activated_data_e_act_q_poly_iexp_3 = asSInt(_activated_data_e_act_q_poly_iexp_T_43) node _activated_data_e_act_T_121 = asUInt(activated_data_e_act_q_poly_iexp_3) node _activated_data_e_act_T_122 = asUInt(activated_data_e_act_z_iexp_saturated_3) node _activated_data_e_act_T_123 = dshr(_activated_data_e_act_T_121, _activated_data_e_act_T_122) wire _activated_data_e_act_WIRE_3 : SInt<32> node _activated_data_e_act_T_124 = asSInt(_activated_data_e_act_T_123) connect _activated_data_e_act_WIRE_3, _activated_data_e_act_T_124 node _activated_data_e_act_T_125 = mux(_activated_data_e_act_T_117, _activated_data_e_act_WIRE_3, io.in.bits.acc_read_resp.data[3][0]) node _activated_data_e_act_T_126 = mux(_activated_data_e_act_T_108, _activated_data_e_act_T_114, _activated_data_e_act_T_125) node _activated_data_e_act_T_127 = mux(_activated_data_e_act_T_102, _activated_data_e_act_T_105, _activated_data_e_act_T_126) node activated_data_e_act_3 = mux(_activated_data_e_act_T_97, _activated_data_e_act_T_99, _activated_data_e_act_T_127) node _activated_data_e_scaled_T_33 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_34 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_35 = and(_activated_data_e_scaled_T_33, _activated_data_e_scaled_T_34) node _activated_data_e_scaled_T_36 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_37 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_38 = and(_activated_data_e_scaled_T_36, _activated_data_e_scaled_T_37) wire _activated_data_e_scaled_WIRE_15 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_16 : UInt<32> connect _activated_data_e_scaled_WIRE_16, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_39 = bits(_activated_data_e_scaled_WIRE_16, 31, 0) connect _activated_data_e_scaled_WIRE_15.bits, _activated_data_e_scaled_T_39 node _activated_data_e_scaled_T_40 = mux(_activated_data_e_scaled_T_38, _activated_data_e_scaled_WIRE_15, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_41 = mux(_activated_data_e_scaled_T_35, io.in.bits.inv_stddev, _activated_data_e_scaled_T_40) wire _activated_data_e_scaled_WIRE_17 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_18 : UInt<32> connect _activated_data_e_scaled_WIRE_18, _activated_data_e_scaled_T_41.bits node _activated_data_e_scaled_T_42 = bits(_activated_data_e_scaled_WIRE_18, 31, 0) connect _activated_data_e_scaled_WIRE_17.bits, _activated_data_e_scaled_T_42 node activated_data_e_scaled_f_rec_rawIn_sign_3 = bits(_activated_data_e_scaled_WIRE_17.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_3 = bits(_activated_data_e_scaled_WIRE_17.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_3 = bits(_activated_data_e_scaled_WIRE_17.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_3, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_3, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_132 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_133 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_134 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_135 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_136 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_137 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_138 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_139 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_140 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_141 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_142 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_143 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_144 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_145 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_146 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_147 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_148 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_149 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_150 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_151 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_152 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_153 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_154 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_3, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_155 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_133, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_156 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_134, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_155) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_157 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_135, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_156) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_158 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_136, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_157) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_159 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_137, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_158) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_160 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_138, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_159) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_161 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_139, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_160) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_162 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_140, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_161) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_163 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_141, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_162) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_164 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_142, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_163) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_165 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_143, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_164) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_166 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_144, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_165) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_167 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_145, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_166) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_168 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_146, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_167) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_169 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_147, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_168) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_170 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_148, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_169) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_171 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_149, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_170) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_172 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_150, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_171) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_173 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_151, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_172) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_174 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_152, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_173) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_175 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_153, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_174) node activated_data_e_scaled_f_rec_rawIn_normDist_3 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_154, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_175) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_6 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_3, activated_data_e_scaled_f_rec_rawIn_normDist_3) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_7 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_6, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_3 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_7, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_15 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_3, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_16 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_15, activated_data_e_scaled_f_rec_rawIn_expIn_3) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_17 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_18 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_17) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_19 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_16, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_18) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_3 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_19, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_3 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_3 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_3, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_3 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_3, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_6 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_7 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_3, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_6) connect activated_data_e_scaled_f_rec_rawIn_3.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_7 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_3 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_3, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3) connect activated_data_e_scaled_f_rec_rawIn_3.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_3 connect activated_data_e_scaled_f_rec_rawIn_3.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_3 connect activated_data_e_scaled_f_rec_rawIn_3.sign, activated_data_e_scaled_f_rec_rawIn_sign_3 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_6 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_3, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_7 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_6) connect activated_data_e_scaled_f_rec_rawIn_3.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_7 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_12 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_3, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_13 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_12) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_14 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3, activated_data_e_scaled_f_rec_rawIn_subnormFract_3, activated_data_e_scaled_f_rec_rawIn_fractIn_3) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_15 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_13, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_14) connect activated_data_e_scaled_f_rec_rawIn_3.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_15 node _activated_data_e_scaled_f_rec_T_24 = bits(activated_data_e_scaled_f_rec_rawIn_3.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_25 = mux(activated_data_e_scaled_f_rec_rawIn_3.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_24) node _activated_data_e_scaled_f_rec_T_26 = mux(activated_data_e_scaled_f_rec_rawIn_3.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_27 = or(_activated_data_e_scaled_f_rec_T_25, _activated_data_e_scaled_f_rec_T_26) node _activated_data_e_scaled_f_rec_T_28 = cat(activated_data_e_scaled_f_rec_rawIn_3.sign, _activated_data_e_scaled_f_rec_T_27) node _activated_data_e_scaled_f_rec_T_29 = bits(activated_data_e_scaled_f_rec_rawIn_3.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_30 = cat(_activated_data_e_scaled_f_rec_T_28, _activated_data_e_scaled_f_rec_T_29) node _activated_data_e_scaled_f_rec_T_31 = bits(activated_data_e_scaled_f_rec_rawIn_3.sig, 22, 0) node activated_data_e_scaled_f_rec_3 = cat(_activated_data_e_scaled_f_rec_T_30, _activated_data_e_scaled_f_rec_T_31) inst activated_data_e_scaled_in_to_rec_fn_3 of INToRecFN_i32_e8_s24_3 connect activated_data_e_scaled_in_to_rec_fn_3.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_3 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_3 = asUInt(activated_data_e_act_3) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_3, _activated_data_e_scaled_in_to_rec_fn_io_in_T_3 connect activated_data_e_scaled_in_to_rec_fn_3.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_3 connect activated_data_e_scaled_in_to_rec_fn_3.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_3.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_3 of MulAddRecFN_e8_s24_7 connect activated_data_e_scaled_muladder_3.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_3.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_3.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_3.io.a, activated_data_e_scaled_in_to_rec_fn_3.io.out connect activated_data_e_scaled_muladder_3.io.b, activated_data_e_scaled_f_rec_3 connect activated_data_e_scaled_muladder_3.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_3 of RecFNToIN_e8_s24_i32_3 connect activated_data_e_scaled_rec_fn_to_in_3.clock, clock connect activated_data_e_scaled_rec_fn_to_in_3.reset, reset connect activated_data_e_scaled_rec_fn_to_in_3.io.in, activated_data_e_scaled_muladder_3.io.out connect activated_data_e_scaled_rec_fn_to_in_3.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_3.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_3 = bits(activated_data_e_scaled_rec_fn_to_in_3.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_3 = bits(activated_data_e_scaled_rec_fn_to_in_3.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_3 = bits(activated_data_e_scaled_sign_exp_3, 8, 6) node activated_data_e_scaled_sign_isZero_3 = eq(_activated_data_e_scaled_sign_isZero_T_3, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_3 = bits(activated_data_e_scaled_sign_exp_3, 8, 7) node activated_data_e_scaled_sign_isSpecial_3 = eq(_activated_data_e_scaled_sign_isSpecial_T_3, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_3 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_6 = bits(activated_data_e_scaled_sign_exp_3, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_7 = and(activated_data_e_scaled_sign_isSpecial_3, _activated_data_e_scaled_sign_out_isNaN_T_6) connect activated_data_e_scaled_sign_out_3.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_7 node _activated_data_e_scaled_sign_out_isInf_T_9 = bits(activated_data_e_scaled_sign_exp_3, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_10 = eq(_activated_data_e_scaled_sign_out_isInf_T_9, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_11 = and(activated_data_e_scaled_sign_isSpecial_3, _activated_data_e_scaled_sign_out_isInf_T_10) connect activated_data_e_scaled_sign_out_3.isInf, _activated_data_e_scaled_sign_out_isInf_T_11 connect activated_data_e_scaled_sign_out_3.isZero, activated_data_e_scaled_sign_isZero_3 node _activated_data_e_scaled_sign_out_sign_T_3 = bits(activated_data_e_scaled_rec_fn_to_in_3.io.in, 32, 32) connect activated_data_e_scaled_sign_out_3.sign, _activated_data_e_scaled_sign_out_sign_T_3 node _activated_data_e_scaled_sign_out_sExp_T_3 = cvt(activated_data_e_scaled_sign_exp_3) connect activated_data_e_scaled_sign_out_3.sExp, _activated_data_e_scaled_sign_out_sExp_T_3 node _activated_data_e_scaled_sign_out_sig_T_12 = eq(activated_data_e_scaled_sign_isZero_3, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_13 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_12) node _activated_data_e_scaled_sign_out_sig_T_14 = bits(activated_data_e_scaled_rec_fn_to_in_3.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_15 = cat(_activated_data_e_scaled_sign_out_sig_T_13, _activated_data_e_scaled_sign_out_sig_T_14) connect activated_data_e_scaled_sign_out_3.sig, _activated_data_e_scaled_sign_out_sig_T_15 node activated_data_e_scaled_sat_3 = mux(activated_data_e_scaled_sign_out_3.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_19 : SInt<32> node _activated_data_e_scaled_T_43 = asSInt(activated_data_e_scaled_rec_fn_to_in_3.io.out) connect _activated_data_e_scaled_WIRE_19, _activated_data_e_scaled_T_43 node activated_data_e_scaled_3 = mux(activated_data_e_scaled_overflow_3, activated_data_e_scaled_sat_3, _activated_data_e_scaled_WIRE_19) node _activated_data_e_clipped_T_15 = gt(activated_data_e_scaled_3, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_16 = lt(activated_data_e_scaled_3, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_17 = mux(_activated_data_e_clipped_T_16, asSInt(UInt<8>(0h80)), activated_data_e_scaled_3) node _activated_data_e_clipped_T_18 = mux(_activated_data_e_clipped_T_15, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_17) node _activated_data_e_clipped_T_19 = bits(_activated_data_e_clipped_T_18, 7, 0) node activated_data_e_clipped_3 = asSInt(_activated_data_e_clipped_T_19) wire _activated_data_WIRE_3 : SInt<8>[1] connect _activated_data_WIRE_3[0], activated_data_e_clipped_3 node _activated_data_e_act_T_128 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_129 = and(UInt<1>(0h1), _activated_data_e_act_T_128) node _activated_data_e_act_T_130 = geq(io.in.bits.acc_read_resp.data[4][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_131 = mux(_activated_data_e_act_T_130, io.in.bits.acc_read_resp.data[4][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_132 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_133 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_134 = and(_activated_data_e_act_T_132, _activated_data_e_act_T_133) node _activated_data_e_act_T_135 = sub(io.in.bits.acc_read_resp.data[4][0], io.in.bits.mean) node _activated_data_e_act_T_136 = tail(_activated_data_e_act_T_135, 1) node _activated_data_e_act_T_137 = asSInt(_activated_data_e_act_T_136) node _activated_data_e_act_T_138 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_139 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_140 = and(_activated_data_e_act_T_138, _activated_data_e_act_T_139) node _activated_data_e_act_q_sign_T_16 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[4][0]) node _activated_data_e_act_q_sign_T_17 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_18 = tail(_activated_data_e_act_q_sign_T_17, 1) node _activated_data_e_act_q_sign_T_19 = asSInt(_activated_data_e_act_q_sign_T_18) node activated_data_e_act_q_sign_4 = mux(_activated_data_e_act_q_sign_T_16, _activated_data_e_act_q_sign_T_19, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_16 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[4][0]) node _activated_data_e_act_q_abs_T_17 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[4][0]) node _activated_data_e_act_q_abs_T_18 = tail(_activated_data_e_act_q_abs_T_17, 1) node _activated_data_e_act_q_abs_T_19 = asSInt(_activated_data_e_act_q_abs_T_18) node activated_data_e_act_q_abs_4 = mux(_activated_data_e_act_q_abs_T_16, _activated_data_e_act_q_abs_T_19, io.in.bits.acc_read_resp.data[4][0]) node _activated_data_e_act_q_clipped_T_28 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_29 = tail(_activated_data_e_act_q_clipped_T_28, 1) node _activated_data_e_act_q_clipped_T_30 = asSInt(_activated_data_e_act_q_clipped_T_29) node _activated_data_e_act_q_clipped_T_31 = gt(activated_data_e_act_q_abs_4, _activated_data_e_act_q_clipped_T_30) node _activated_data_e_act_q_clipped_T_32 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_33 = tail(_activated_data_e_act_q_clipped_T_32, 1) node _activated_data_e_act_q_clipped_T_34 = asSInt(_activated_data_e_act_q_clipped_T_33) node activated_data_e_act_q_clipped_4 = mux(_activated_data_e_act_q_clipped_T_31, _activated_data_e_act_q_clipped_T_34, activated_data_e_act_q_abs_4) node _activated_data_e_act_q_poly_T_44 = add(activated_data_e_act_q_clipped_4, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_45 = tail(_activated_data_e_act_q_poly_T_44, 1) node _activated_data_e_act_q_poly_T_46 = asSInt(_activated_data_e_act_q_poly_T_45) node _activated_data_e_act_q_poly_T_47 = add(activated_data_e_act_q_clipped_4, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_48 = tail(_activated_data_e_act_q_poly_T_47, 1) node _activated_data_e_act_q_poly_T_49 = asSInt(_activated_data_e_act_q_poly_T_48) node _activated_data_e_act_q_poly_T_50 = mul(_activated_data_e_act_q_poly_T_46, _activated_data_e_act_q_poly_T_49) node _activated_data_e_act_q_poly_T_51 = add(_activated_data_e_act_q_poly_T_50, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_52 = tail(_activated_data_e_act_q_poly_T_51, 1) node _activated_data_e_act_q_poly_T_53 = asSInt(_activated_data_e_act_q_poly_T_52) node _activated_data_e_act_q_poly_T_54 = bits(_activated_data_e_act_q_poly_T_53, 31, 0) node activated_data_e_act_q_poly_4 = asSInt(_activated_data_e_act_q_poly_T_54) node _activated_data_e_act_q_erf_T_8 = mul(activated_data_e_act_q_sign_4, activated_data_e_act_q_poly_4) node _activated_data_e_act_q_erf_T_9 = bits(_activated_data_e_act_q_erf_T_8, 31, 0) node activated_data_e_act_q_erf_4 = asSInt(_activated_data_e_act_q_erf_T_9) node _activated_data_e_act_T_141 = add(activated_data_e_act_q_erf_4, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_142 = tail(_activated_data_e_act_T_141, 1) node _activated_data_e_act_T_143 = asSInt(_activated_data_e_act_T_142) node _activated_data_e_act_T_144 = mul(io.in.bits.acc_read_resp.data[4][0], _activated_data_e_act_T_143) node _activated_data_e_act_T_145 = bits(_activated_data_e_act_T_144, 31, 0) node _activated_data_e_act_T_146 = asSInt(_activated_data_e_act_T_145) node _activated_data_e_act_T_147 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_148 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_149 = and(_activated_data_e_act_T_147, _activated_data_e_act_T_148) node _activated_data_e_act_T_150 = sub(io.in.bits.acc_read_resp.data[4][0], io.in.bits.max) node _activated_data_e_act_T_151 = tail(_activated_data_e_act_T_150, 1) node _activated_data_e_act_T_152 = asSInt(_activated_data_e_act_T_151) node _activated_data_e_act_neg_q_iexp_T_8 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_152) node _activated_data_e_act_neg_q_iexp_T_9 = tail(_activated_data_e_act_neg_q_iexp_T_8, 1) node activated_data_e_act_neg_q_iexp_4 = asSInt(_activated_data_e_act_neg_q_iexp_T_9) node _activated_data_e_act_z_iexp_T_16 = mul(activated_data_e_act_neg_q_iexp_4, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_17 = asUInt(_activated_data_e_act_z_iexp_T_16) node _activated_data_e_act_z_iexp_T_18 = shr(_activated_data_e_act_z_iexp_T_17, 16) wire activated_data_e_act_z_iexp_4 : SInt<32> node _activated_data_e_act_z_iexp_T_19 = asSInt(_activated_data_e_act_z_iexp_T_18) connect activated_data_e_act_z_iexp_4, _activated_data_e_act_z_iexp_T_19 wire activated_data_e_act_z_iexp_saturated_4 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_132 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_133 = bits(_activated_data_e_act_z_iexp_saturated_T_132, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_134 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_135 = bits(_activated_data_e_act_z_iexp_saturated_T_134, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_136 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_137 = bits(_activated_data_e_act_z_iexp_saturated_T_136, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_138 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_139 = bits(_activated_data_e_act_z_iexp_saturated_T_138, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_140 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_141 = bits(_activated_data_e_act_z_iexp_saturated_T_140, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_142 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_143 = bits(_activated_data_e_act_z_iexp_saturated_T_142, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_144 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_145 = bits(_activated_data_e_act_z_iexp_saturated_T_144, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_146 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_147 = bits(_activated_data_e_act_z_iexp_saturated_T_146, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_148 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_149 = bits(_activated_data_e_act_z_iexp_saturated_T_148, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_150 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_151 = bits(_activated_data_e_act_z_iexp_saturated_T_150, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_152 = asUInt(activated_data_e_act_z_iexp_4) node _activated_data_e_act_z_iexp_saturated_T_153 = bits(_activated_data_e_act_z_iexp_saturated_T_152, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_154 = or(_activated_data_e_act_z_iexp_saturated_T_133, _activated_data_e_act_z_iexp_saturated_T_135) node _activated_data_e_act_z_iexp_saturated_T_155 = or(_activated_data_e_act_z_iexp_saturated_T_154, _activated_data_e_act_z_iexp_saturated_T_137) node _activated_data_e_act_z_iexp_saturated_T_156 = or(_activated_data_e_act_z_iexp_saturated_T_155, _activated_data_e_act_z_iexp_saturated_T_139) node _activated_data_e_act_z_iexp_saturated_T_157 = or(_activated_data_e_act_z_iexp_saturated_T_156, _activated_data_e_act_z_iexp_saturated_T_141) node _activated_data_e_act_z_iexp_saturated_T_158 = or(_activated_data_e_act_z_iexp_saturated_T_157, _activated_data_e_act_z_iexp_saturated_T_143) node _activated_data_e_act_z_iexp_saturated_T_159 = or(_activated_data_e_act_z_iexp_saturated_T_158, _activated_data_e_act_z_iexp_saturated_T_145) node _activated_data_e_act_z_iexp_saturated_T_160 = or(_activated_data_e_act_z_iexp_saturated_T_159, _activated_data_e_act_z_iexp_saturated_T_147) node _activated_data_e_act_z_iexp_saturated_T_161 = or(_activated_data_e_act_z_iexp_saturated_T_160, _activated_data_e_act_z_iexp_saturated_T_149) node _activated_data_e_act_z_iexp_saturated_T_162 = or(_activated_data_e_act_z_iexp_saturated_T_161, _activated_data_e_act_z_iexp_saturated_T_151) node _activated_data_e_act_z_iexp_saturated_T_163 = or(_activated_data_e_act_z_iexp_saturated_T_162, _activated_data_e_act_z_iexp_saturated_T_153) wire _activated_data_e_act_z_iexp_saturated_WIRE_4 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_4, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_164 = mux(_activated_data_e_act_z_iexp_saturated_T_163, _activated_data_e_act_z_iexp_saturated_WIRE_4, activated_data_e_act_z_iexp_4) connect activated_data_e_act_z_iexp_saturated_4, _activated_data_e_act_z_iexp_saturated_T_164 node _activated_data_e_act_qp_iexp_T_20 = mul(activated_data_e_act_z_iexp_4, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_21 = add(_activated_data_e_act_qp_iexp_T_20, _activated_data_e_act_T_152) node _activated_data_e_act_qp_iexp_T_22 = tail(_activated_data_e_act_qp_iexp_T_21, 1) node _activated_data_e_act_qp_iexp_T_23 = asSInt(_activated_data_e_act_qp_iexp_T_22) node _activated_data_e_act_qp_iexp_T_24 = bits(_activated_data_e_act_qp_iexp_T_23, 31, 0) node activated_data_e_act_qp_iexp_4 = asSInt(_activated_data_e_act_qp_iexp_T_24) node _activated_data_e_act_q_poly_iexp_T_44 = add(activated_data_e_act_qp_iexp_4, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_45 = tail(_activated_data_e_act_q_poly_iexp_T_44, 1) node _activated_data_e_act_q_poly_iexp_T_46 = asSInt(_activated_data_e_act_q_poly_iexp_T_45) node _activated_data_e_act_q_poly_iexp_T_47 = add(activated_data_e_act_qp_iexp_4, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_48 = tail(_activated_data_e_act_q_poly_iexp_T_47, 1) node _activated_data_e_act_q_poly_iexp_T_49 = asSInt(_activated_data_e_act_q_poly_iexp_T_48) node _activated_data_e_act_q_poly_iexp_T_50 = mul(_activated_data_e_act_q_poly_iexp_T_46, _activated_data_e_act_q_poly_iexp_T_49) node _activated_data_e_act_q_poly_iexp_T_51 = add(_activated_data_e_act_q_poly_iexp_T_50, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_52 = tail(_activated_data_e_act_q_poly_iexp_T_51, 1) node _activated_data_e_act_q_poly_iexp_T_53 = asSInt(_activated_data_e_act_q_poly_iexp_T_52) node _activated_data_e_act_q_poly_iexp_T_54 = bits(_activated_data_e_act_q_poly_iexp_T_53, 31, 0) node activated_data_e_act_q_poly_iexp_4 = asSInt(_activated_data_e_act_q_poly_iexp_T_54) node _activated_data_e_act_T_153 = asUInt(activated_data_e_act_q_poly_iexp_4) node _activated_data_e_act_T_154 = asUInt(activated_data_e_act_z_iexp_saturated_4) node _activated_data_e_act_T_155 = dshr(_activated_data_e_act_T_153, _activated_data_e_act_T_154) wire _activated_data_e_act_WIRE_4 : SInt<32> node _activated_data_e_act_T_156 = asSInt(_activated_data_e_act_T_155) connect _activated_data_e_act_WIRE_4, _activated_data_e_act_T_156 node _activated_data_e_act_T_157 = mux(_activated_data_e_act_T_149, _activated_data_e_act_WIRE_4, io.in.bits.acc_read_resp.data[4][0]) node _activated_data_e_act_T_158 = mux(_activated_data_e_act_T_140, _activated_data_e_act_T_146, _activated_data_e_act_T_157) node _activated_data_e_act_T_159 = mux(_activated_data_e_act_T_134, _activated_data_e_act_T_137, _activated_data_e_act_T_158) node activated_data_e_act_4 = mux(_activated_data_e_act_T_129, _activated_data_e_act_T_131, _activated_data_e_act_T_159) node _activated_data_e_scaled_T_44 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_45 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_46 = and(_activated_data_e_scaled_T_44, _activated_data_e_scaled_T_45) node _activated_data_e_scaled_T_47 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_48 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_49 = and(_activated_data_e_scaled_T_47, _activated_data_e_scaled_T_48) wire _activated_data_e_scaled_WIRE_20 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_21 : UInt<32> connect _activated_data_e_scaled_WIRE_21, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_50 = bits(_activated_data_e_scaled_WIRE_21, 31, 0) connect _activated_data_e_scaled_WIRE_20.bits, _activated_data_e_scaled_T_50 node _activated_data_e_scaled_T_51 = mux(_activated_data_e_scaled_T_49, _activated_data_e_scaled_WIRE_20, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_52 = mux(_activated_data_e_scaled_T_46, io.in.bits.inv_stddev, _activated_data_e_scaled_T_51) wire _activated_data_e_scaled_WIRE_22 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_23 : UInt<32> connect _activated_data_e_scaled_WIRE_23, _activated_data_e_scaled_T_52.bits node _activated_data_e_scaled_T_53 = bits(_activated_data_e_scaled_WIRE_23, 31, 0) connect _activated_data_e_scaled_WIRE_22.bits, _activated_data_e_scaled_T_53 node activated_data_e_scaled_f_rec_rawIn_sign_4 = bits(_activated_data_e_scaled_WIRE_22.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_4 = bits(_activated_data_e_scaled_WIRE_22.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_4 = bits(_activated_data_e_scaled_WIRE_22.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_4, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_4, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_176 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_177 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_178 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_179 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_180 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_181 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_182 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_183 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_184 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_185 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_186 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_187 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_188 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_189 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_190 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_191 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_192 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_193 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_194 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_195 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_196 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_197 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_198 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_4, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_199 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_177, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_200 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_178, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_199) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_201 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_179, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_200) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_202 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_180, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_201) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_203 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_181, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_202) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_204 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_182, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_203) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_205 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_183, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_204) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_206 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_184, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_205) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_207 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_185, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_206) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_208 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_186, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_207) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_209 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_187, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_208) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_210 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_188, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_209) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_211 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_189, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_210) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_212 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_190, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_211) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_213 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_191, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_212) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_214 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_192, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_213) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_215 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_193, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_214) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_216 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_194, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_215) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_217 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_195, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_216) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_218 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_196, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_217) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_219 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_197, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_218) node activated_data_e_scaled_f_rec_rawIn_normDist_4 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_198, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_219) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_8 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_4, activated_data_e_scaled_f_rec_rawIn_normDist_4) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_9 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_8, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_4 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_9, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_20 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_4, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_21 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_20, activated_data_e_scaled_f_rec_rawIn_expIn_4) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_22 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_23 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_22) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_24 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_21, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_23) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_4 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_24, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_4 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_4 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_4, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_4 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_4, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_4 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_8 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_9 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_4, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_8) connect activated_data_e_scaled_f_rec_rawIn_4.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_9 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_4 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_4, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4) connect activated_data_e_scaled_f_rec_rawIn_4.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_4 connect activated_data_e_scaled_f_rec_rawIn_4.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_4 connect activated_data_e_scaled_f_rec_rawIn_4.sign, activated_data_e_scaled_f_rec_rawIn_sign_4 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_8 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_4, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_9 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_8) connect activated_data_e_scaled_f_rec_rawIn_4.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_9 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_16 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_4, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_17 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_16) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_18 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4, activated_data_e_scaled_f_rec_rawIn_subnormFract_4, activated_data_e_scaled_f_rec_rawIn_fractIn_4) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_19 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_17, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_18) connect activated_data_e_scaled_f_rec_rawIn_4.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_19 node _activated_data_e_scaled_f_rec_T_32 = bits(activated_data_e_scaled_f_rec_rawIn_4.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_33 = mux(activated_data_e_scaled_f_rec_rawIn_4.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_32) node _activated_data_e_scaled_f_rec_T_34 = mux(activated_data_e_scaled_f_rec_rawIn_4.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_35 = or(_activated_data_e_scaled_f_rec_T_33, _activated_data_e_scaled_f_rec_T_34) node _activated_data_e_scaled_f_rec_T_36 = cat(activated_data_e_scaled_f_rec_rawIn_4.sign, _activated_data_e_scaled_f_rec_T_35) node _activated_data_e_scaled_f_rec_T_37 = bits(activated_data_e_scaled_f_rec_rawIn_4.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_38 = cat(_activated_data_e_scaled_f_rec_T_36, _activated_data_e_scaled_f_rec_T_37) node _activated_data_e_scaled_f_rec_T_39 = bits(activated_data_e_scaled_f_rec_rawIn_4.sig, 22, 0) node activated_data_e_scaled_f_rec_4 = cat(_activated_data_e_scaled_f_rec_T_38, _activated_data_e_scaled_f_rec_T_39) inst activated_data_e_scaled_in_to_rec_fn_4 of INToRecFN_i32_e8_s24_4 connect activated_data_e_scaled_in_to_rec_fn_4.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_4 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_4 = asUInt(activated_data_e_act_4) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_4, _activated_data_e_scaled_in_to_rec_fn_io_in_T_4 connect activated_data_e_scaled_in_to_rec_fn_4.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_4 connect activated_data_e_scaled_in_to_rec_fn_4.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_4.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_4 of MulAddRecFN_e8_s24_8 connect activated_data_e_scaled_muladder_4.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_4.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_4.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_4.io.a, activated_data_e_scaled_in_to_rec_fn_4.io.out connect activated_data_e_scaled_muladder_4.io.b, activated_data_e_scaled_f_rec_4 connect activated_data_e_scaled_muladder_4.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_4 of RecFNToIN_e8_s24_i32_4 connect activated_data_e_scaled_rec_fn_to_in_4.clock, clock connect activated_data_e_scaled_rec_fn_to_in_4.reset, reset connect activated_data_e_scaled_rec_fn_to_in_4.io.in, activated_data_e_scaled_muladder_4.io.out connect activated_data_e_scaled_rec_fn_to_in_4.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_4.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_4 = bits(activated_data_e_scaled_rec_fn_to_in_4.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_4 = bits(activated_data_e_scaled_rec_fn_to_in_4.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_4 = bits(activated_data_e_scaled_sign_exp_4, 8, 6) node activated_data_e_scaled_sign_isZero_4 = eq(_activated_data_e_scaled_sign_isZero_T_4, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_4 = bits(activated_data_e_scaled_sign_exp_4, 8, 7) node activated_data_e_scaled_sign_isSpecial_4 = eq(_activated_data_e_scaled_sign_isSpecial_T_4, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_4 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_8 = bits(activated_data_e_scaled_sign_exp_4, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_9 = and(activated_data_e_scaled_sign_isSpecial_4, _activated_data_e_scaled_sign_out_isNaN_T_8) connect activated_data_e_scaled_sign_out_4.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_9 node _activated_data_e_scaled_sign_out_isInf_T_12 = bits(activated_data_e_scaled_sign_exp_4, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_13 = eq(_activated_data_e_scaled_sign_out_isInf_T_12, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_14 = and(activated_data_e_scaled_sign_isSpecial_4, _activated_data_e_scaled_sign_out_isInf_T_13) connect activated_data_e_scaled_sign_out_4.isInf, _activated_data_e_scaled_sign_out_isInf_T_14 connect activated_data_e_scaled_sign_out_4.isZero, activated_data_e_scaled_sign_isZero_4 node _activated_data_e_scaled_sign_out_sign_T_4 = bits(activated_data_e_scaled_rec_fn_to_in_4.io.in, 32, 32) connect activated_data_e_scaled_sign_out_4.sign, _activated_data_e_scaled_sign_out_sign_T_4 node _activated_data_e_scaled_sign_out_sExp_T_4 = cvt(activated_data_e_scaled_sign_exp_4) connect activated_data_e_scaled_sign_out_4.sExp, _activated_data_e_scaled_sign_out_sExp_T_4 node _activated_data_e_scaled_sign_out_sig_T_16 = eq(activated_data_e_scaled_sign_isZero_4, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_17 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_16) node _activated_data_e_scaled_sign_out_sig_T_18 = bits(activated_data_e_scaled_rec_fn_to_in_4.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_19 = cat(_activated_data_e_scaled_sign_out_sig_T_17, _activated_data_e_scaled_sign_out_sig_T_18) connect activated_data_e_scaled_sign_out_4.sig, _activated_data_e_scaled_sign_out_sig_T_19 node activated_data_e_scaled_sat_4 = mux(activated_data_e_scaled_sign_out_4.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_24 : SInt<32> node _activated_data_e_scaled_T_54 = asSInt(activated_data_e_scaled_rec_fn_to_in_4.io.out) connect _activated_data_e_scaled_WIRE_24, _activated_data_e_scaled_T_54 node activated_data_e_scaled_4 = mux(activated_data_e_scaled_overflow_4, activated_data_e_scaled_sat_4, _activated_data_e_scaled_WIRE_24) node _activated_data_e_clipped_T_20 = gt(activated_data_e_scaled_4, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_21 = lt(activated_data_e_scaled_4, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_22 = mux(_activated_data_e_clipped_T_21, asSInt(UInt<8>(0h80)), activated_data_e_scaled_4) node _activated_data_e_clipped_T_23 = mux(_activated_data_e_clipped_T_20, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_22) node _activated_data_e_clipped_T_24 = bits(_activated_data_e_clipped_T_23, 7, 0) node activated_data_e_clipped_4 = asSInt(_activated_data_e_clipped_T_24) wire _activated_data_WIRE_4 : SInt<8>[1] connect _activated_data_WIRE_4[0], activated_data_e_clipped_4 node _activated_data_e_act_T_160 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_161 = and(UInt<1>(0h1), _activated_data_e_act_T_160) node _activated_data_e_act_T_162 = geq(io.in.bits.acc_read_resp.data[5][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_163 = mux(_activated_data_e_act_T_162, io.in.bits.acc_read_resp.data[5][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_164 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_165 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_166 = and(_activated_data_e_act_T_164, _activated_data_e_act_T_165) node _activated_data_e_act_T_167 = sub(io.in.bits.acc_read_resp.data[5][0], io.in.bits.mean) node _activated_data_e_act_T_168 = tail(_activated_data_e_act_T_167, 1) node _activated_data_e_act_T_169 = asSInt(_activated_data_e_act_T_168) node _activated_data_e_act_T_170 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_171 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_172 = and(_activated_data_e_act_T_170, _activated_data_e_act_T_171) node _activated_data_e_act_q_sign_T_20 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[5][0]) node _activated_data_e_act_q_sign_T_21 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_22 = tail(_activated_data_e_act_q_sign_T_21, 1) node _activated_data_e_act_q_sign_T_23 = asSInt(_activated_data_e_act_q_sign_T_22) node activated_data_e_act_q_sign_5 = mux(_activated_data_e_act_q_sign_T_20, _activated_data_e_act_q_sign_T_23, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_20 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[5][0]) node _activated_data_e_act_q_abs_T_21 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[5][0]) node _activated_data_e_act_q_abs_T_22 = tail(_activated_data_e_act_q_abs_T_21, 1) node _activated_data_e_act_q_abs_T_23 = asSInt(_activated_data_e_act_q_abs_T_22) node activated_data_e_act_q_abs_5 = mux(_activated_data_e_act_q_abs_T_20, _activated_data_e_act_q_abs_T_23, io.in.bits.acc_read_resp.data[5][0]) node _activated_data_e_act_q_clipped_T_35 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_36 = tail(_activated_data_e_act_q_clipped_T_35, 1) node _activated_data_e_act_q_clipped_T_37 = asSInt(_activated_data_e_act_q_clipped_T_36) node _activated_data_e_act_q_clipped_T_38 = gt(activated_data_e_act_q_abs_5, _activated_data_e_act_q_clipped_T_37) node _activated_data_e_act_q_clipped_T_39 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_40 = tail(_activated_data_e_act_q_clipped_T_39, 1) node _activated_data_e_act_q_clipped_T_41 = asSInt(_activated_data_e_act_q_clipped_T_40) node activated_data_e_act_q_clipped_5 = mux(_activated_data_e_act_q_clipped_T_38, _activated_data_e_act_q_clipped_T_41, activated_data_e_act_q_abs_5) node _activated_data_e_act_q_poly_T_55 = add(activated_data_e_act_q_clipped_5, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_56 = tail(_activated_data_e_act_q_poly_T_55, 1) node _activated_data_e_act_q_poly_T_57 = asSInt(_activated_data_e_act_q_poly_T_56) node _activated_data_e_act_q_poly_T_58 = add(activated_data_e_act_q_clipped_5, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_59 = tail(_activated_data_e_act_q_poly_T_58, 1) node _activated_data_e_act_q_poly_T_60 = asSInt(_activated_data_e_act_q_poly_T_59) node _activated_data_e_act_q_poly_T_61 = mul(_activated_data_e_act_q_poly_T_57, _activated_data_e_act_q_poly_T_60) node _activated_data_e_act_q_poly_T_62 = add(_activated_data_e_act_q_poly_T_61, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_63 = tail(_activated_data_e_act_q_poly_T_62, 1) node _activated_data_e_act_q_poly_T_64 = asSInt(_activated_data_e_act_q_poly_T_63) node _activated_data_e_act_q_poly_T_65 = bits(_activated_data_e_act_q_poly_T_64, 31, 0) node activated_data_e_act_q_poly_5 = asSInt(_activated_data_e_act_q_poly_T_65) node _activated_data_e_act_q_erf_T_10 = mul(activated_data_e_act_q_sign_5, activated_data_e_act_q_poly_5) node _activated_data_e_act_q_erf_T_11 = bits(_activated_data_e_act_q_erf_T_10, 31, 0) node activated_data_e_act_q_erf_5 = asSInt(_activated_data_e_act_q_erf_T_11) node _activated_data_e_act_T_173 = add(activated_data_e_act_q_erf_5, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_174 = tail(_activated_data_e_act_T_173, 1) node _activated_data_e_act_T_175 = asSInt(_activated_data_e_act_T_174) node _activated_data_e_act_T_176 = mul(io.in.bits.acc_read_resp.data[5][0], _activated_data_e_act_T_175) node _activated_data_e_act_T_177 = bits(_activated_data_e_act_T_176, 31, 0) node _activated_data_e_act_T_178 = asSInt(_activated_data_e_act_T_177) node _activated_data_e_act_T_179 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_180 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_181 = and(_activated_data_e_act_T_179, _activated_data_e_act_T_180) node _activated_data_e_act_T_182 = sub(io.in.bits.acc_read_resp.data[5][0], io.in.bits.max) node _activated_data_e_act_T_183 = tail(_activated_data_e_act_T_182, 1) node _activated_data_e_act_T_184 = asSInt(_activated_data_e_act_T_183) node _activated_data_e_act_neg_q_iexp_T_10 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_184) node _activated_data_e_act_neg_q_iexp_T_11 = tail(_activated_data_e_act_neg_q_iexp_T_10, 1) node activated_data_e_act_neg_q_iexp_5 = asSInt(_activated_data_e_act_neg_q_iexp_T_11) node _activated_data_e_act_z_iexp_T_20 = mul(activated_data_e_act_neg_q_iexp_5, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_21 = asUInt(_activated_data_e_act_z_iexp_T_20) node _activated_data_e_act_z_iexp_T_22 = shr(_activated_data_e_act_z_iexp_T_21, 16) wire activated_data_e_act_z_iexp_5 : SInt<32> node _activated_data_e_act_z_iexp_T_23 = asSInt(_activated_data_e_act_z_iexp_T_22) connect activated_data_e_act_z_iexp_5, _activated_data_e_act_z_iexp_T_23 wire activated_data_e_act_z_iexp_saturated_5 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_165 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_166 = bits(_activated_data_e_act_z_iexp_saturated_T_165, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_167 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_168 = bits(_activated_data_e_act_z_iexp_saturated_T_167, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_169 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_170 = bits(_activated_data_e_act_z_iexp_saturated_T_169, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_171 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_172 = bits(_activated_data_e_act_z_iexp_saturated_T_171, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_173 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_174 = bits(_activated_data_e_act_z_iexp_saturated_T_173, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_175 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_176 = bits(_activated_data_e_act_z_iexp_saturated_T_175, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_177 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_178 = bits(_activated_data_e_act_z_iexp_saturated_T_177, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_179 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_180 = bits(_activated_data_e_act_z_iexp_saturated_T_179, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_181 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_182 = bits(_activated_data_e_act_z_iexp_saturated_T_181, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_183 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_184 = bits(_activated_data_e_act_z_iexp_saturated_T_183, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_185 = asUInt(activated_data_e_act_z_iexp_5) node _activated_data_e_act_z_iexp_saturated_T_186 = bits(_activated_data_e_act_z_iexp_saturated_T_185, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_187 = or(_activated_data_e_act_z_iexp_saturated_T_166, _activated_data_e_act_z_iexp_saturated_T_168) node _activated_data_e_act_z_iexp_saturated_T_188 = or(_activated_data_e_act_z_iexp_saturated_T_187, _activated_data_e_act_z_iexp_saturated_T_170) node _activated_data_e_act_z_iexp_saturated_T_189 = or(_activated_data_e_act_z_iexp_saturated_T_188, _activated_data_e_act_z_iexp_saturated_T_172) node _activated_data_e_act_z_iexp_saturated_T_190 = or(_activated_data_e_act_z_iexp_saturated_T_189, _activated_data_e_act_z_iexp_saturated_T_174) node _activated_data_e_act_z_iexp_saturated_T_191 = or(_activated_data_e_act_z_iexp_saturated_T_190, _activated_data_e_act_z_iexp_saturated_T_176) node _activated_data_e_act_z_iexp_saturated_T_192 = or(_activated_data_e_act_z_iexp_saturated_T_191, _activated_data_e_act_z_iexp_saturated_T_178) node _activated_data_e_act_z_iexp_saturated_T_193 = or(_activated_data_e_act_z_iexp_saturated_T_192, _activated_data_e_act_z_iexp_saturated_T_180) node _activated_data_e_act_z_iexp_saturated_T_194 = or(_activated_data_e_act_z_iexp_saturated_T_193, _activated_data_e_act_z_iexp_saturated_T_182) node _activated_data_e_act_z_iexp_saturated_T_195 = or(_activated_data_e_act_z_iexp_saturated_T_194, _activated_data_e_act_z_iexp_saturated_T_184) node _activated_data_e_act_z_iexp_saturated_T_196 = or(_activated_data_e_act_z_iexp_saturated_T_195, _activated_data_e_act_z_iexp_saturated_T_186) wire _activated_data_e_act_z_iexp_saturated_WIRE_5 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_5, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_197 = mux(_activated_data_e_act_z_iexp_saturated_T_196, _activated_data_e_act_z_iexp_saturated_WIRE_5, activated_data_e_act_z_iexp_5) connect activated_data_e_act_z_iexp_saturated_5, _activated_data_e_act_z_iexp_saturated_T_197 node _activated_data_e_act_qp_iexp_T_25 = mul(activated_data_e_act_z_iexp_5, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_26 = add(_activated_data_e_act_qp_iexp_T_25, _activated_data_e_act_T_184) node _activated_data_e_act_qp_iexp_T_27 = tail(_activated_data_e_act_qp_iexp_T_26, 1) node _activated_data_e_act_qp_iexp_T_28 = asSInt(_activated_data_e_act_qp_iexp_T_27) node _activated_data_e_act_qp_iexp_T_29 = bits(_activated_data_e_act_qp_iexp_T_28, 31, 0) node activated_data_e_act_qp_iexp_5 = asSInt(_activated_data_e_act_qp_iexp_T_29) node _activated_data_e_act_q_poly_iexp_T_55 = add(activated_data_e_act_qp_iexp_5, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_56 = tail(_activated_data_e_act_q_poly_iexp_T_55, 1) node _activated_data_e_act_q_poly_iexp_T_57 = asSInt(_activated_data_e_act_q_poly_iexp_T_56) node _activated_data_e_act_q_poly_iexp_T_58 = add(activated_data_e_act_qp_iexp_5, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_59 = tail(_activated_data_e_act_q_poly_iexp_T_58, 1) node _activated_data_e_act_q_poly_iexp_T_60 = asSInt(_activated_data_e_act_q_poly_iexp_T_59) node _activated_data_e_act_q_poly_iexp_T_61 = mul(_activated_data_e_act_q_poly_iexp_T_57, _activated_data_e_act_q_poly_iexp_T_60) node _activated_data_e_act_q_poly_iexp_T_62 = add(_activated_data_e_act_q_poly_iexp_T_61, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_63 = tail(_activated_data_e_act_q_poly_iexp_T_62, 1) node _activated_data_e_act_q_poly_iexp_T_64 = asSInt(_activated_data_e_act_q_poly_iexp_T_63) node _activated_data_e_act_q_poly_iexp_T_65 = bits(_activated_data_e_act_q_poly_iexp_T_64, 31, 0) node activated_data_e_act_q_poly_iexp_5 = asSInt(_activated_data_e_act_q_poly_iexp_T_65) node _activated_data_e_act_T_185 = asUInt(activated_data_e_act_q_poly_iexp_5) node _activated_data_e_act_T_186 = asUInt(activated_data_e_act_z_iexp_saturated_5) node _activated_data_e_act_T_187 = dshr(_activated_data_e_act_T_185, _activated_data_e_act_T_186) wire _activated_data_e_act_WIRE_5 : SInt<32> node _activated_data_e_act_T_188 = asSInt(_activated_data_e_act_T_187) connect _activated_data_e_act_WIRE_5, _activated_data_e_act_T_188 node _activated_data_e_act_T_189 = mux(_activated_data_e_act_T_181, _activated_data_e_act_WIRE_5, io.in.bits.acc_read_resp.data[5][0]) node _activated_data_e_act_T_190 = mux(_activated_data_e_act_T_172, _activated_data_e_act_T_178, _activated_data_e_act_T_189) node _activated_data_e_act_T_191 = mux(_activated_data_e_act_T_166, _activated_data_e_act_T_169, _activated_data_e_act_T_190) node activated_data_e_act_5 = mux(_activated_data_e_act_T_161, _activated_data_e_act_T_163, _activated_data_e_act_T_191) node _activated_data_e_scaled_T_55 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_56 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_57 = and(_activated_data_e_scaled_T_55, _activated_data_e_scaled_T_56) node _activated_data_e_scaled_T_58 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_59 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_60 = and(_activated_data_e_scaled_T_58, _activated_data_e_scaled_T_59) wire _activated_data_e_scaled_WIRE_25 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_26 : UInt<32> connect _activated_data_e_scaled_WIRE_26, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_61 = bits(_activated_data_e_scaled_WIRE_26, 31, 0) connect _activated_data_e_scaled_WIRE_25.bits, _activated_data_e_scaled_T_61 node _activated_data_e_scaled_T_62 = mux(_activated_data_e_scaled_T_60, _activated_data_e_scaled_WIRE_25, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_63 = mux(_activated_data_e_scaled_T_57, io.in.bits.inv_stddev, _activated_data_e_scaled_T_62) wire _activated_data_e_scaled_WIRE_27 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_28 : UInt<32> connect _activated_data_e_scaled_WIRE_28, _activated_data_e_scaled_T_63.bits node _activated_data_e_scaled_T_64 = bits(_activated_data_e_scaled_WIRE_28, 31, 0) connect _activated_data_e_scaled_WIRE_27.bits, _activated_data_e_scaled_T_64 node activated_data_e_scaled_f_rec_rawIn_sign_5 = bits(_activated_data_e_scaled_WIRE_27.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_5 = bits(_activated_data_e_scaled_WIRE_27.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_5 = bits(_activated_data_e_scaled_WIRE_27.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_5, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_5, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_220 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_221 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_222 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_223 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_224 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_225 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_226 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_227 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_228 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_229 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_230 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_231 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_232 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_233 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_234 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_235 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_236 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_237 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_238 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_239 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_240 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_241 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_242 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_5, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_243 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_221, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_244 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_222, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_243) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_245 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_223, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_244) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_246 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_224, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_245) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_247 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_225, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_246) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_248 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_226, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_247) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_249 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_227, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_248) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_250 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_228, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_249) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_251 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_229, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_250) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_252 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_230, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_251) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_253 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_231, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_252) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_254 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_232, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_253) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_255 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_233, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_254) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_256 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_234, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_255) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_257 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_235, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_256) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_258 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_236, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_257) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_259 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_237, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_258) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_260 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_238, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_259) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_261 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_239, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_260) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_262 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_240, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_261) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_263 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_241, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_262) node activated_data_e_scaled_f_rec_rawIn_normDist_5 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_242, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_263) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_10 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_5, activated_data_e_scaled_f_rec_rawIn_normDist_5) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_11 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_10, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_5 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_11, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_25 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_5, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_26 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_25, activated_data_e_scaled_f_rec_rawIn_expIn_5) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_27 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_28 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_27) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_29 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_26, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_28) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_5 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_29, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_5 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_5 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_5, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_5 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_5, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_5 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_10 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_11 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_5, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_10) connect activated_data_e_scaled_f_rec_rawIn_5.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_11 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_5 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_5, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5) connect activated_data_e_scaled_f_rec_rawIn_5.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_5 connect activated_data_e_scaled_f_rec_rawIn_5.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_5 connect activated_data_e_scaled_f_rec_rawIn_5.sign, activated_data_e_scaled_f_rec_rawIn_sign_5 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_10 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_5, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_11 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_10) connect activated_data_e_scaled_f_rec_rawIn_5.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_11 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_20 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_5, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_21 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_20) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_22 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5, activated_data_e_scaled_f_rec_rawIn_subnormFract_5, activated_data_e_scaled_f_rec_rawIn_fractIn_5) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_23 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_21, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_22) connect activated_data_e_scaled_f_rec_rawIn_5.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_23 node _activated_data_e_scaled_f_rec_T_40 = bits(activated_data_e_scaled_f_rec_rawIn_5.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_41 = mux(activated_data_e_scaled_f_rec_rawIn_5.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_40) node _activated_data_e_scaled_f_rec_T_42 = mux(activated_data_e_scaled_f_rec_rawIn_5.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_43 = or(_activated_data_e_scaled_f_rec_T_41, _activated_data_e_scaled_f_rec_T_42) node _activated_data_e_scaled_f_rec_T_44 = cat(activated_data_e_scaled_f_rec_rawIn_5.sign, _activated_data_e_scaled_f_rec_T_43) node _activated_data_e_scaled_f_rec_T_45 = bits(activated_data_e_scaled_f_rec_rawIn_5.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_46 = cat(_activated_data_e_scaled_f_rec_T_44, _activated_data_e_scaled_f_rec_T_45) node _activated_data_e_scaled_f_rec_T_47 = bits(activated_data_e_scaled_f_rec_rawIn_5.sig, 22, 0) node activated_data_e_scaled_f_rec_5 = cat(_activated_data_e_scaled_f_rec_T_46, _activated_data_e_scaled_f_rec_T_47) inst activated_data_e_scaled_in_to_rec_fn_5 of INToRecFN_i32_e8_s24_5 connect activated_data_e_scaled_in_to_rec_fn_5.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_5 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_5 = asUInt(activated_data_e_act_5) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_5, _activated_data_e_scaled_in_to_rec_fn_io_in_T_5 connect activated_data_e_scaled_in_to_rec_fn_5.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_5 connect activated_data_e_scaled_in_to_rec_fn_5.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_5.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_5 of MulAddRecFN_e8_s24_9 connect activated_data_e_scaled_muladder_5.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_5.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_5.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_5.io.a, activated_data_e_scaled_in_to_rec_fn_5.io.out connect activated_data_e_scaled_muladder_5.io.b, activated_data_e_scaled_f_rec_5 connect activated_data_e_scaled_muladder_5.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_5 of RecFNToIN_e8_s24_i32_5 connect activated_data_e_scaled_rec_fn_to_in_5.clock, clock connect activated_data_e_scaled_rec_fn_to_in_5.reset, reset connect activated_data_e_scaled_rec_fn_to_in_5.io.in, activated_data_e_scaled_muladder_5.io.out connect activated_data_e_scaled_rec_fn_to_in_5.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_5.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_5 = bits(activated_data_e_scaled_rec_fn_to_in_5.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_5 = bits(activated_data_e_scaled_rec_fn_to_in_5.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_5 = bits(activated_data_e_scaled_sign_exp_5, 8, 6) node activated_data_e_scaled_sign_isZero_5 = eq(_activated_data_e_scaled_sign_isZero_T_5, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_5 = bits(activated_data_e_scaled_sign_exp_5, 8, 7) node activated_data_e_scaled_sign_isSpecial_5 = eq(_activated_data_e_scaled_sign_isSpecial_T_5, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_5 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_10 = bits(activated_data_e_scaled_sign_exp_5, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_11 = and(activated_data_e_scaled_sign_isSpecial_5, _activated_data_e_scaled_sign_out_isNaN_T_10) connect activated_data_e_scaled_sign_out_5.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_11 node _activated_data_e_scaled_sign_out_isInf_T_15 = bits(activated_data_e_scaled_sign_exp_5, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_16 = eq(_activated_data_e_scaled_sign_out_isInf_T_15, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_17 = and(activated_data_e_scaled_sign_isSpecial_5, _activated_data_e_scaled_sign_out_isInf_T_16) connect activated_data_e_scaled_sign_out_5.isInf, _activated_data_e_scaled_sign_out_isInf_T_17 connect activated_data_e_scaled_sign_out_5.isZero, activated_data_e_scaled_sign_isZero_5 node _activated_data_e_scaled_sign_out_sign_T_5 = bits(activated_data_e_scaled_rec_fn_to_in_5.io.in, 32, 32) connect activated_data_e_scaled_sign_out_5.sign, _activated_data_e_scaled_sign_out_sign_T_5 node _activated_data_e_scaled_sign_out_sExp_T_5 = cvt(activated_data_e_scaled_sign_exp_5) connect activated_data_e_scaled_sign_out_5.sExp, _activated_data_e_scaled_sign_out_sExp_T_5 node _activated_data_e_scaled_sign_out_sig_T_20 = eq(activated_data_e_scaled_sign_isZero_5, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_21 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_20) node _activated_data_e_scaled_sign_out_sig_T_22 = bits(activated_data_e_scaled_rec_fn_to_in_5.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_23 = cat(_activated_data_e_scaled_sign_out_sig_T_21, _activated_data_e_scaled_sign_out_sig_T_22) connect activated_data_e_scaled_sign_out_5.sig, _activated_data_e_scaled_sign_out_sig_T_23 node activated_data_e_scaled_sat_5 = mux(activated_data_e_scaled_sign_out_5.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_29 : SInt<32> node _activated_data_e_scaled_T_65 = asSInt(activated_data_e_scaled_rec_fn_to_in_5.io.out) connect _activated_data_e_scaled_WIRE_29, _activated_data_e_scaled_T_65 node activated_data_e_scaled_5 = mux(activated_data_e_scaled_overflow_5, activated_data_e_scaled_sat_5, _activated_data_e_scaled_WIRE_29) node _activated_data_e_clipped_T_25 = gt(activated_data_e_scaled_5, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_26 = lt(activated_data_e_scaled_5, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_27 = mux(_activated_data_e_clipped_T_26, asSInt(UInt<8>(0h80)), activated_data_e_scaled_5) node _activated_data_e_clipped_T_28 = mux(_activated_data_e_clipped_T_25, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_27) node _activated_data_e_clipped_T_29 = bits(_activated_data_e_clipped_T_28, 7, 0) node activated_data_e_clipped_5 = asSInt(_activated_data_e_clipped_T_29) wire _activated_data_WIRE_5 : SInt<8>[1] connect _activated_data_WIRE_5[0], activated_data_e_clipped_5 node _activated_data_e_act_T_192 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_193 = and(UInt<1>(0h1), _activated_data_e_act_T_192) node _activated_data_e_act_T_194 = geq(io.in.bits.acc_read_resp.data[6][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_195 = mux(_activated_data_e_act_T_194, io.in.bits.acc_read_resp.data[6][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_196 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_197 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_198 = and(_activated_data_e_act_T_196, _activated_data_e_act_T_197) node _activated_data_e_act_T_199 = sub(io.in.bits.acc_read_resp.data[6][0], io.in.bits.mean) node _activated_data_e_act_T_200 = tail(_activated_data_e_act_T_199, 1) node _activated_data_e_act_T_201 = asSInt(_activated_data_e_act_T_200) node _activated_data_e_act_T_202 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_203 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_204 = and(_activated_data_e_act_T_202, _activated_data_e_act_T_203) node _activated_data_e_act_q_sign_T_24 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[6][0]) node _activated_data_e_act_q_sign_T_25 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_26 = tail(_activated_data_e_act_q_sign_T_25, 1) node _activated_data_e_act_q_sign_T_27 = asSInt(_activated_data_e_act_q_sign_T_26) node activated_data_e_act_q_sign_6 = mux(_activated_data_e_act_q_sign_T_24, _activated_data_e_act_q_sign_T_27, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_24 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[6][0]) node _activated_data_e_act_q_abs_T_25 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[6][0]) node _activated_data_e_act_q_abs_T_26 = tail(_activated_data_e_act_q_abs_T_25, 1) node _activated_data_e_act_q_abs_T_27 = asSInt(_activated_data_e_act_q_abs_T_26) node activated_data_e_act_q_abs_6 = mux(_activated_data_e_act_q_abs_T_24, _activated_data_e_act_q_abs_T_27, io.in.bits.acc_read_resp.data[6][0]) node _activated_data_e_act_q_clipped_T_42 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_43 = tail(_activated_data_e_act_q_clipped_T_42, 1) node _activated_data_e_act_q_clipped_T_44 = asSInt(_activated_data_e_act_q_clipped_T_43) node _activated_data_e_act_q_clipped_T_45 = gt(activated_data_e_act_q_abs_6, _activated_data_e_act_q_clipped_T_44) node _activated_data_e_act_q_clipped_T_46 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_47 = tail(_activated_data_e_act_q_clipped_T_46, 1) node _activated_data_e_act_q_clipped_T_48 = asSInt(_activated_data_e_act_q_clipped_T_47) node activated_data_e_act_q_clipped_6 = mux(_activated_data_e_act_q_clipped_T_45, _activated_data_e_act_q_clipped_T_48, activated_data_e_act_q_abs_6) node _activated_data_e_act_q_poly_T_66 = add(activated_data_e_act_q_clipped_6, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_67 = tail(_activated_data_e_act_q_poly_T_66, 1) node _activated_data_e_act_q_poly_T_68 = asSInt(_activated_data_e_act_q_poly_T_67) node _activated_data_e_act_q_poly_T_69 = add(activated_data_e_act_q_clipped_6, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_70 = tail(_activated_data_e_act_q_poly_T_69, 1) node _activated_data_e_act_q_poly_T_71 = asSInt(_activated_data_e_act_q_poly_T_70) node _activated_data_e_act_q_poly_T_72 = mul(_activated_data_e_act_q_poly_T_68, _activated_data_e_act_q_poly_T_71) node _activated_data_e_act_q_poly_T_73 = add(_activated_data_e_act_q_poly_T_72, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_74 = tail(_activated_data_e_act_q_poly_T_73, 1) node _activated_data_e_act_q_poly_T_75 = asSInt(_activated_data_e_act_q_poly_T_74) node _activated_data_e_act_q_poly_T_76 = bits(_activated_data_e_act_q_poly_T_75, 31, 0) node activated_data_e_act_q_poly_6 = asSInt(_activated_data_e_act_q_poly_T_76) node _activated_data_e_act_q_erf_T_12 = mul(activated_data_e_act_q_sign_6, activated_data_e_act_q_poly_6) node _activated_data_e_act_q_erf_T_13 = bits(_activated_data_e_act_q_erf_T_12, 31, 0) node activated_data_e_act_q_erf_6 = asSInt(_activated_data_e_act_q_erf_T_13) node _activated_data_e_act_T_205 = add(activated_data_e_act_q_erf_6, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_206 = tail(_activated_data_e_act_T_205, 1) node _activated_data_e_act_T_207 = asSInt(_activated_data_e_act_T_206) node _activated_data_e_act_T_208 = mul(io.in.bits.acc_read_resp.data[6][0], _activated_data_e_act_T_207) node _activated_data_e_act_T_209 = bits(_activated_data_e_act_T_208, 31, 0) node _activated_data_e_act_T_210 = asSInt(_activated_data_e_act_T_209) node _activated_data_e_act_T_211 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_212 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_213 = and(_activated_data_e_act_T_211, _activated_data_e_act_T_212) node _activated_data_e_act_T_214 = sub(io.in.bits.acc_read_resp.data[6][0], io.in.bits.max) node _activated_data_e_act_T_215 = tail(_activated_data_e_act_T_214, 1) node _activated_data_e_act_T_216 = asSInt(_activated_data_e_act_T_215) node _activated_data_e_act_neg_q_iexp_T_12 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_216) node _activated_data_e_act_neg_q_iexp_T_13 = tail(_activated_data_e_act_neg_q_iexp_T_12, 1) node activated_data_e_act_neg_q_iexp_6 = asSInt(_activated_data_e_act_neg_q_iexp_T_13) node _activated_data_e_act_z_iexp_T_24 = mul(activated_data_e_act_neg_q_iexp_6, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_25 = asUInt(_activated_data_e_act_z_iexp_T_24) node _activated_data_e_act_z_iexp_T_26 = shr(_activated_data_e_act_z_iexp_T_25, 16) wire activated_data_e_act_z_iexp_6 : SInt<32> node _activated_data_e_act_z_iexp_T_27 = asSInt(_activated_data_e_act_z_iexp_T_26) connect activated_data_e_act_z_iexp_6, _activated_data_e_act_z_iexp_T_27 wire activated_data_e_act_z_iexp_saturated_6 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_198 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_199 = bits(_activated_data_e_act_z_iexp_saturated_T_198, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_200 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_201 = bits(_activated_data_e_act_z_iexp_saturated_T_200, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_202 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_203 = bits(_activated_data_e_act_z_iexp_saturated_T_202, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_204 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_205 = bits(_activated_data_e_act_z_iexp_saturated_T_204, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_206 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_207 = bits(_activated_data_e_act_z_iexp_saturated_T_206, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_208 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_209 = bits(_activated_data_e_act_z_iexp_saturated_T_208, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_210 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_211 = bits(_activated_data_e_act_z_iexp_saturated_T_210, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_212 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_213 = bits(_activated_data_e_act_z_iexp_saturated_T_212, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_214 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_215 = bits(_activated_data_e_act_z_iexp_saturated_T_214, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_216 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_217 = bits(_activated_data_e_act_z_iexp_saturated_T_216, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_218 = asUInt(activated_data_e_act_z_iexp_6) node _activated_data_e_act_z_iexp_saturated_T_219 = bits(_activated_data_e_act_z_iexp_saturated_T_218, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_220 = or(_activated_data_e_act_z_iexp_saturated_T_199, _activated_data_e_act_z_iexp_saturated_T_201) node _activated_data_e_act_z_iexp_saturated_T_221 = or(_activated_data_e_act_z_iexp_saturated_T_220, _activated_data_e_act_z_iexp_saturated_T_203) node _activated_data_e_act_z_iexp_saturated_T_222 = or(_activated_data_e_act_z_iexp_saturated_T_221, _activated_data_e_act_z_iexp_saturated_T_205) node _activated_data_e_act_z_iexp_saturated_T_223 = or(_activated_data_e_act_z_iexp_saturated_T_222, _activated_data_e_act_z_iexp_saturated_T_207) node _activated_data_e_act_z_iexp_saturated_T_224 = or(_activated_data_e_act_z_iexp_saturated_T_223, _activated_data_e_act_z_iexp_saturated_T_209) node _activated_data_e_act_z_iexp_saturated_T_225 = or(_activated_data_e_act_z_iexp_saturated_T_224, _activated_data_e_act_z_iexp_saturated_T_211) node _activated_data_e_act_z_iexp_saturated_T_226 = or(_activated_data_e_act_z_iexp_saturated_T_225, _activated_data_e_act_z_iexp_saturated_T_213) node _activated_data_e_act_z_iexp_saturated_T_227 = or(_activated_data_e_act_z_iexp_saturated_T_226, _activated_data_e_act_z_iexp_saturated_T_215) node _activated_data_e_act_z_iexp_saturated_T_228 = or(_activated_data_e_act_z_iexp_saturated_T_227, _activated_data_e_act_z_iexp_saturated_T_217) node _activated_data_e_act_z_iexp_saturated_T_229 = or(_activated_data_e_act_z_iexp_saturated_T_228, _activated_data_e_act_z_iexp_saturated_T_219) wire _activated_data_e_act_z_iexp_saturated_WIRE_6 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_6, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_230 = mux(_activated_data_e_act_z_iexp_saturated_T_229, _activated_data_e_act_z_iexp_saturated_WIRE_6, activated_data_e_act_z_iexp_6) connect activated_data_e_act_z_iexp_saturated_6, _activated_data_e_act_z_iexp_saturated_T_230 node _activated_data_e_act_qp_iexp_T_30 = mul(activated_data_e_act_z_iexp_6, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_31 = add(_activated_data_e_act_qp_iexp_T_30, _activated_data_e_act_T_216) node _activated_data_e_act_qp_iexp_T_32 = tail(_activated_data_e_act_qp_iexp_T_31, 1) node _activated_data_e_act_qp_iexp_T_33 = asSInt(_activated_data_e_act_qp_iexp_T_32) node _activated_data_e_act_qp_iexp_T_34 = bits(_activated_data_e_act_qp_iexp_T_33, 31, 0) node activated_data_e_act_qp_iexp_6 = asSInt(_activated_data_e_act_qp_iexp_T_34) node _activated_data_e_act_q_poly_iexp_T_66 = add(activated_data_e_act_qp_iexp_6, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_67 = tail(_activated_data_e_act_q_poly_iexp_T_66, 1) node _activated_data_e_act_q_poly_iexp_T_68 = asSInt(_activated_data_e_act_q_poly_iexp_T_67) node _activated_data_e_act_q_poly_iexp_T_69 = add(activated_data_e_act_qp_iexp_6, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_70 = tail(_activated_data_e_act_q_poly_iexp_T_69, 1) node _activated_data_e_act_q_poly_iexp_T_71 = asSInt(_activated_data_e_act_q_poly_iexp_T_70) node _activated_data_e_act_q_poly_iexp_T_72 = mul(_activated_data_e_act_q_poly_iexp_T_68, _activated_data_e_act_q_poly_iexp_T_71) node _activated_data_e_act_q_poly_iexp_T_73 = add(_activated_data_e_act_q_poly_iexp_T_72, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_74 = tail(_activated_data_e_act_q_poly_iexp_T_73, 1) node _activated_data_e_act_q_poly_iexp_T_75 = asSInt(_activated_data_e_act_q_poly_iexp_T_74) node _activated_data_e_act_q_poly_iexp_T_76 = bits(_activated_data_e_act_q_poly_iexp_T_75, 31, 0) node activated_data_e_act_q_poly_iexp_6 = asSInt(_activated_data_e_act_q_poly_iexp_T_76) node _activated_data_e_act_T_217 = asUInt(activated_data_e_act_q_poly_iexp_6) node _activated_data_e_act_T_218 = asUInt(activated_data_e_act_z_iexp_saturated_6) node _activated_data_e_act_T_219 = dshr(_activated_data_e_act_T_217, _activated_data_e_act_T_218) wire _activated_data_e_act_WIRE_6 : SInt<32> node _activated_data_e_act_T_220 = asSInt(_activated_data_e_act_T_219) connect _activated_data_e_act_WIRE_6, _activated_data_e_act_T_220 node _activated_data_e_act_T_221 = mux(_activated_data_e_act_T_213, _activated_data_e_act_WIRE_6, io.in.bits.acc_read_resp.data[6][0]) node _activated_data_e_act_T_222 = mux(_activated_data_e_act_T_204, _activated_data_e_act_T_210, _activated_data_e_act_T_221) node _activated_data_e_act_T_223 = mux(_activated_data_e_act_T_198, _activated_data_e_act_T_201, _activated_data_e_act_T_222) node activated_data_e_act_6 = mux(_activated_data_e_act_T_193, _activated_data_e_act_T_195, _activated_data_e_act_T_223) node _activated_data_e_scaled_T_66 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_67 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_68 = and(_activated_data_e_scaled_T_66, _activated_data_e_scaled_T_67) node _activated_data_e_scaled_T_69 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_70 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_71 = and(_activated_data_e_scaled_T_69, _activated_data_e_scaled_T_70) wire _activated_data_e_scaled_WIRE_30 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_31 : UInt<32> connect _activated_data_e_scaled_WIRE_31, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_72 = bits(_activated_data_e_scaled_WIRE_31, 31, 0) connect _activated_data_e_scaled_WIRE_30.bits, _activated_data_e_scaled_T_72 node _activated_data_e_scaled_T_73 = mux(_activated_data_e_scaled_T_71, _activated_data_e_scaled_WIRE_30, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_74 = mux(_activated_data_e_scaled_T_68, io.in.bits.inv_stddev, _activated_data_e_scaled_T_73) wire _activated_data_e_scaled_WIRE_32 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_33 : UInt<32> connect _activated_data_e_scaled_WIRE_33, _activated_data_e_scaled_T_74.bits node _activated_data_e_scaled_T_75 = bits(_activated_data_e_scaled_WIRE_33, 31, 0) connect _activated_data_e_scaled_WIRE_32.bits, _activated_data_e_scaled_T_75 node activated_data_e_scaled_f_rec_rawIn_sign_6 = bits(_activated_data_e_scaled_WIRE_32.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_6 = bits(_activated_data_e_scaled_WIRE_32.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_6 = bits(_activated_data_e_scaled_WIRE_32.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_6, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_6, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_264 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_265 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_266 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_267 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_268 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_269 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_270 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_271 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_272 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_273 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_274 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_275 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_276 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_277 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_278 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_279 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_280 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_281 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_282 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_283 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_284 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_285 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_286 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_6, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_287 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_265, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_288 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_266, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_287) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_289 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_267, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_288) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_290 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_268, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_289) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_291 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_269, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_290) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_292 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_270, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_291) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_293 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_271, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_292) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_294 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_272, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_293) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_295 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_273, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_294) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_296 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_274, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_295) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_297 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_275, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_296) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_298 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_276, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_297) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_299 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_277, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_298) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_300 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_278, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_299) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_301 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_279, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_300) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_302 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_280, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_301) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_303 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_281, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_302) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_304 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_282, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_303) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_305 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_283, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_304) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_306 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_284, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_305) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_307 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_285, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_306) node activated_data_e_scaled_f_rec_rawIn_normDist_6 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_286, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_307) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_12 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_6, activated_data_e_scaled_f_rec_rawIn_normDist_6) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_13 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_12, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_6 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_13, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_30 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_6, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_31 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_30, activated_data_e_scaled_f_rec_rawIn_expIn_6) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_32 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_33 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_32) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_34 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_31, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_33) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_6 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_34, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_6 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_6 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_6, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_6 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_6, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_6 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_12 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_13 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_6, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_12) connect activated_data_e_scaled_f_rec_rawIn_6.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_13 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_6 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_6, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6) connect activated_data_e_scaled_f_rec_rawIn_6.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_6 connect activated_data_e_scaled_f_rec_rawIn_6.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_6 connect activated_data_e_scaled_f_rec_rawIn_6.sign, activated_data_e_scaled_f_rec_rawIn_sign_6 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_12 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_6, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_13 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_12) connect activated_data_e_scaled_f_rec_rawIn_6.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_13 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_24 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_6, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_25 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_24) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_26 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6, activated_data_e_scaled_f_rec_rawIn_subnormFract_6, activated_data_e_scaled_f_rec_rawIn_fractIn_6) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_27 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_25, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_26) connect activated_data_e_scaled_f_rec_rawIn_6.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_27 node _activated_data_e_scaled_f_rec_T_48 = bits(activated_data_e_scaled_f_rec_rawIn_6.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_49 = mux(activated_data_e_scaled_f_rec_rawIn_6.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_48) node _activated_data_e_scaled_f_rec_T_50 = mux(activated_data_e_scaled_f_rec_rawIn_6.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_51 = or(_activated_data_e_scaled_f_rec_T_49, _activated_data_e_scaled_f_rec_T_50) node _activated_data_e_scaled_f_rec_T_52 = cat(activated_data_e_scaled_f_rec_rawIn_6.sign, _activated_data_e_scaled_f_rec_T_51) node _activated_data_e_scaled_f_rec_T_53 = bits(activated_data_e_scaled_f_rec_rawIn_6.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_54 = cat(_activated_data_e_scaled_f_rec_T_52, _activated_data_e_scaled_f_rec_T_53) node _activated_data_e_scaled_f_rec_T_55 = bits(activated_data_e_scaled_f_rec_rawIn_6.sig, 22, 0) node activated_data_e_scaled_f_rec_6 = cat(_activated_data_e_scaled_f_rec_T_54, _activated_data_e_scaled_f_rec_T_55) inst activated_data_e_scaled_in_to_rec_fn_6 of INToRecFN_i32_e8_s24_6 connect activated_data_e_scaled_in_to_rec_fn_6.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_6 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_6 = asUInt(activated_data_e_act_6) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_6, _activated_data_e_scaled_in_to_rec_fn_io_in_T_6 connect activated_data_e_scaled_in_to_rec_fn_6.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_6 connect activated_data_e_scaled_in_to_rec_fn_6.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_6.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_6 of MulAddRecFN_e8_s24_10 connect activated_data_e_scaled_muladder_6.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_6.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_6.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_6.io.a, activated_data_e_scaled_in_to_rec_fn_6.io.out connect activated_data_e_scaled_muladder_6.io.b, activated_data_e_scaled_f_rec_6 connect activated_data_e_scaled_muladder_6.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_6 of RecFNToIN_e8_s24_i32_6 connect activated_data_e_scaled_rec_fn_to_in_6.clock, clock connect activated_data_e_scaled_rec_fn_to_in_6.reset, reset connect activated_data_e_scaled_rec_fn_to_in_6.io.in, activated_data_e_scaled_muladder_6.io.out connect activated_data_e_scaled_rec_fn_to_in_6.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_6.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_6 = bits(activated_data_e_scaled_rec_fn_to_in_6.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_6 = bits(activated_data_e_scaled_rec_fn_to_in_6.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_6 = bits(activated_data_e_scaled_sign_exp_6, 8, 6) node activated_data_e_scaled_sign_isZero_6 = eq(_activated_data_e_scaled_sign_isZero_T_6, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_6 = bits(activated_data_e_scaled_sign_exp_6, 8, 7) node activated_data_e_scaled_sign_isSpecial_6 = eq(_activated_data_e_scaled_sign_isSpecial_T_6, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_6 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_12 = bits(activated_data_e_scaled_sign_exp_6, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_13 = and(activated_data_e_scaled_sign_isSpecial_6, _activated_data_e_scaled_sign_out_isNaN_T_12) connect activated_data_e_scaled_sign_out_6.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_13 node _activated_data_e_scaled_sign_out_isInf_T_18 = bits(activated_data_e_scaled_sign_exp_6, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_19 = eq(_activated_data_e_scaled_sign_out_isInf_T_18, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_20 = and(activated_data_e_scaled_sign_isSpecial_6, _activated_data_e_scaled_sign_out_isInf_T_19) connect activated_data_e_scaled_sign_out_6.isInf, _activated_data_e_scaled_sign_out_isInf_T_20 connect activated_data_e_scaled_sign_out_6.isZero, activated_data_e_scaled_sign_isZero_6 node _activated_data_e_scaled_sign_out_sign_T_6 = bits(activated_data_e_scaled_rec_fn_to_in_6.io.in, 32, 32) connect activated_data_e_scaled_sign_out_6.sign, _activated_data_e_scaled_sign_out_sign_T_6 node _activated_data_e_scaled_sign_out_sExp_T_6 = cvt(activated_data_e_scaled_sign_exp_6) connect activated_data_e_scaled_sign_out_6.sExp, _activated_data_e_scaled_sign_out_sExp_T_6 node _activated_data_e_scaled_sign_out_sig_T_24 = eq(activated_data_e_scaled_sign_isZero_6, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_25 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_24) node _activated_data_e_scaled_sign_out_sig_T_26 = bits(activated_data_e_scaled_rec_fn_to_in_6.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_27 = cat(_activated_data_e_scaled_sign_out_sig_T_25, _activated_data_e_scaled_sign_out_sig_T_26) connect activated_data_e_scaled_sign_out_6.sig, _activated_data_e_scaled_sign_out_sig_T_27 node activated_data_e_scaled_sat_6 = mux(activated_data_e_scaled_sign_out_6.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_34 : SInt<32> node _activated_data_e_scaled_T_76 = asSInt(activated_data_e_scaled_rec_fn_to_in_6.io.out) connect _activated_data_e_scaled_WIRE_34, _activated_data_e_scaled_T_76 node activated_data_e_scaled_6 = mux(activated_data_e_scaled_overflow_6, activated_data_e_scaled_sat_6, _activated_data_e_scaled_WIRE_34) node _activated_data_e_clipped_T_30 = gt(activated_data_e_scaled_6, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_31 = lt(activated_data_e_scaled_6, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_32 = mux(_activated_data_e_clipped_T_31, asSInt(UInt<8>(0h80)), activated_data_e_scaled_6) node _activated_data_e_clipped_T_33 = mux(_activated_data_e_clipped_T_30, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_32) node _activated_data_e_clipped_T_34 = bits(_activated_data_e_clipped_T_33, 7, 0) node activated_data_e_clipped_6 = asSInt(_activated_data_e_clipped_T_34) wire _activated_data_WIRE_6 : SInt<8>[1] connect _activated_data_WIRE_6[0], activated_data_e_clipped_6 node _activated_data_e_act_T_224 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_225 = and(UInt<1>(0h1), _activated_data_e_act_T_224) node _activated_data_e_act_T_226 = geq(io.in.bits.acc_read_resp.data[7][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_227 = mux(_activated_data_e_act_T_226, io.in.bits.acc_read_resp.data[7][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_228 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_229 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_230 = and(_activated_data_e_act_T_228, _activated_data_e_act_T_229) node _activated_data_e_act_T_231 = sub(io.in.bits.acc_read_resp.data[7][0], io.in.bits.mean) node _activated_data_e_act_T_232 = tail(_activated_data_e_act_T_231, 1) node _activated_data_e_act_T_233 = asSInt(_activated_data_e_act_T_232) node _activated_data_e_act_T_234 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_235 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_236 = and(_activated_data_e_act_T_234, _activated_data_e_act_T_235) node _activated_data_e_act_q_sign_T_28 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[7][0]) node _activated_data_e_act_q_sign_T_29 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_30 = tail(_activated_data_e_act_q_sign_T_29, 1) node _activated_data_e_act_q_sign_T_31 = asSInt(_activated_data_e_act_q_sign_T_30) node activated_data_e_act_q_sign_7 = mux(_activated_data_e_act_q_sign_T_28, _activated_data_e_act_q_sign_T_31, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_28 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[7][0]) node _activated_data_e_act_q_abs_T_29 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[7][0]) node _activated_data_e_act_q_abs_T_30 = tail(_activated_data_e_act_q_abs_T_29, 1) node _activated_data_e_act_q_abs_T_31 = asSInt(_activated_data_e_act_q_abs_T_30) node activated_data_e_act_q_abs_7 = mux(_activated_data_e_act_q_abs_T_28, _activated_data_e_act_q_abs_T_31, io.in.bits.acc_read_resp.data[7][0]) node _activated_data_e_act_q_clipped_T_49 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_50 = tail(_activated_data_e_act_q_clipped_T_49, 1) node _activated_data_e_act_q_clipped_T_51 = asSInt(_activated_data_e_act_q_clipped_T_50) node _activated_data_e_act_q_clipped_T_52 = gt(activated_data_e_act_q_abs_7, _activated_data_e_act_q_clipped_T_51) node _activated_data_e_act_q_clipped_T_53 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_54 = tail(_activated_data_e_act_q_clipped_T_53, 1) node _activated_data_e_act_q_clipped_T_55 = asSInt(_activated_data_e_act_q_clipped_T_54) node activated_data_e_act_q_clipped_7 = mux(_activated_data_e_act_q_clipped_T_52, _activated_data_e_act_q_clipped_T_55, activated_data_e_act_q_abs_7) node _activated_data_e_act_q_poly_T_77 = add(activated_data_e_act_q_clipped_7, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_78 = tail(_activated_data_e_act_q_poly_T_77, 1) node _activated_data_e_act_q_poly_T_79 = asSInt(_activated_data_e_act_q_poly_T_78) node _activated_data_e_act_q_poly_T_80 = add(activated_data_e_act_q_clipped_7, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_81 = tail(_activated_data_e_act_q_poly_T_80, 1) node _activated_data_e_act_q_poly_T_82 = asSInt(_activated_data_e_act_q_poly_T_81) node _activated_data_e_act_q_poly_T_83 = mul(_activated_data_e_act_q_poly_T_79, _activated_data_e_act_q_poly_T_82) node _activated_data_e_act_q_poly_T_84 = add(_activated_data_e_act_q_poly_T_83, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_85 = tail(_activated_data_e_act_q_poly_T_84, 1) node _activated_data_e_act_q_poly_T_86 = asSInt(_activated_data_e_act_q_poly_T_85) node _activated_data_e_act_q_poly_T_87 = bits(_activated_data_e_act_q_poly_T_86, 31, 0) node activated_data_e_act_q_poly_7 = asSInt(_activated_data_e_act_q_poly_T_87) node _activated_data_e_act_q_erf_T_14 = mul(activated_data_e_act_q_sign_7, activated_data_e_act_q_poly_7) node _activated_data_e_act_q_erf_T_15 = bits(_activated_data_e_act_q_erf_T_14, 31, 0) node activated_data_e_act_q_erf_7 = asSInt(_activated_data_e_act_q_erf_T_15) node _activated_data_e_act_T_237 = add(activated_data_e_act_q_erf_7, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_238 = tail(_activated_data_e_act_T_237, 1) node _activated_data_e_act_T_239 = asSInt(_activated_data_e_act_T_238) node _activated_data_e_act_T_240 = mul(io.in.bits.acc_read_resp.data[7][0], _activated_data_e_act_T_239) node _activated_data_e_act_T_241 = bits(_activated_data_e_act_T_240, 31, 0) node _activated_data_e_act_T_242 = asSInt(_activated_data_e_act_T_241) node _activated_data_e_act_T_243 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_244 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_245 = and(_activated_data_e_act_T_243, _activated_data_e_act_T_244) node _activated_data_e_act_T_246 = sub(io.in.bits.acc_read_resp.data[7][0], io.in.bits.max) node _activated_data_e_act_T_247 = tail(_activated_data_e_act_T_246, 1) node _activated_data_e_act_T_248 = asSInt(_activated_data_e_act_T_247) node _activated_data_e_act_neg_q_iexp_T_14 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_248) node _activated_data_e_act_neg_q_iexp_T_15 = tail(_activated_data_e_act_neg_q_iexp_T_14, 1) node activated_data_e_act_neg_q_iexp_7 = asSInt(_activated_data_e_act_neg_q_iexp_T_15) node _activated_data_e_act_z_iexp_T_28 = mul(activated_data_e_act_neg_q_iexp_7, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_29 = asUInt(_activated_data_e_act_z_iexp_T_28) node _activated_data_e_act_z_iexp_T_30 = shr(_activated_data_e_act_z_iexp_T_29, 16) wire activated_data_e_act_z_iexp_7 : SInt<32> node _activated_data_e_act_z_iexp_T_31 = asSInt(_activated_data_e_act_z_iexp_T_30) connect activated_data_e_act_z_iexp_7, _activated_data_e_act_z_iexp_T_31 wire activated_data_e_act_z_iexp_saturated_7 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_231 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_232 = bits(_activated_data_e_act_z_iexp_saturated_T_231, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_233 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_234 = bits(_activated_data_e_act_z_iexp_saturated_T_233, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_235 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_236 = bits(_activated_data_e_act_z_iexp_saturated_T_235, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_237 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_238 = bits(_activated_data_e_act_z_iexp_saturated_T_237, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_239 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_240 = bits(_activated_data_e_act_z_iexp_saturated_T_239, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_241 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_242 = bits(_activated_data_e_act_z_iexp_saturated_T_241, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_243 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_244 = bits(_activated_data_e_act_z_iexp_saturated_T_243, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_245 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_246 = bits(_activated_data_e_act_z_iexp_saturated_T_245, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_247 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_248 = bits(_activated_data_e_act_z_iexp_saturated_T_247, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_249 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_250 = bits(_activated_data_e_act_z_iexp_saturated_T_249, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_251 = asUInt(activated_data_e_act_z_iexp_7) node _activated_data_e_act_z_iexp_saturated_T_252 = bits(_activated_data_e_act_z_iexp_saturated_T_251, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_253 = or(_activated_data_e_act_z_iexp_saturated_T_232, _activated_data_e_act_z_iexp_saturated_T_234) node _activated_data_e_act_z_iexp_saturated_T_254 = or(_activated_data_e_act_z_iexp_saturated_T_253, _activated_data_e_act_z_iexp_saturated_T_236) node _activated_data_e_act_z_iexp_saturated_T_255 = or(_activated_data_e_act_z_iexp_saturated_T_254, _activated_data_e_act_z_iexp_saturated_T_238) node _activated_data_e_act_z_iexp_saturated_T_256 = or(_activated_data_e_act_z_iexp_saturated_T_255, _activated_data_e_act_z_iexp_saturated_T_240) node _activated_data_e_act_z_iexp_saturated_T_257 = or(_activated_data_e_act_z_iexp_saturated_T_256, _activated_data_e_act_z_iexp_saturated_T_242) node _activated_data_e_act_z_iexp_saturated_T_258 = or(_activated_data_e_act_z_iexp_saturated_T_257, _activated_data_e_act_z_iexp_saturated_T_244) node _activated_data_e_act_z_iexp_saturated_T_259 = or(_activated_data_e_act_z_iexp_saturated_T_258, _activated_data_e_act_z_iexp_saturated_T_246) node _activated_data_e_act_z_iexp_saturated_T_260 = or(_activated_data_e_act_z_iexp_saturated_T_259, _activated_data_e_act_z_iexp_saturated_T_248) node _activated_data_e_act_z_iexp_saturated_T_261 = or(_activated_data_e_act_z_iexp_saturated_T_260, _activated_data_e_act_z_iexp_saturated_T_250) node _activated_data_e_act_z_iexp_saturated_T_262 = or(_activated_data_e_act_z_iexp_saturated_T_261, _activated_data_e_act_z_iexp_saturated_T_252) wire _activated_data_e_act_z_iexp_saturated_WIRE_7 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_7, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_263 = mux(_activated_data_e_act_z_iexp_saturated_T_262, _activated_data_e_act_z_iexp_saturated_WIRE_7, activated_data_e_act_z_iexp_7) connect activated_data_e_act_z_iexp_saturated_7, _activated_data_e_act_z_iexp_saturated_T_263 node _activated_data_e_act_qp_iexp_T_35 = mul(activated_data_e_act_z_iexp_7, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_36 = add(_activated_data_e_act_qp_iexp_T_35, _activated_data_e_act_T_248) node _activated_data_e_act_qp_iexp_T_37 = tail(_activated_data_e_act_qp_iexp_T_36, 1) node _activated_data_e_act_qp_iexp_T_38 = asSInt(_activated_data_e_act_qp_iexp_T_37) node _activated_data_e_act_qp_iexp_T_39 = bits(_activated_data_e_act_qp_iexp_T_38, 31, 0) node activated_data_e_act_qp_iexp_7 = asSInt(_activated_data_e_act_qp_iexp_T_39) node _activated_data_e_act_q_poly_iexp_T_77 = add(activated_data_e_act_qp_iexp_7, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_78 = tail(_activated_data_e_act_q_poly_iexp_T_77, 1) node _activated_data_e_act_q_poly_iexp_T_79 = asSInt(_activated_data_e_act_q_poly_iexp_T_78) node _activated_data_e_act_q_poly_iexp_T_80 = add(activated_data_e_act_qp_iexp_7, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_81 = tail(_activated_data_e_act_q_poly_iexp_T_80, 1) node _activated_data_e_act_q_poly_iexp_T_82 = asSInt(_activated_data_e_act_q_poly_iexp_T_81) node _activated_data_e_act_q_poly_iexp_T_83 = mul(_activated_data_e_act_q_poly_iexp_T_79, _activated_data_e_act_q_poly_iexp_T_82) node _activated_data_e_act_q_poly_iexp_T_84 = add(_activated_data_e_act_q_poly_iexp_T_83, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_85 = tail(_activated_data_e_act_q_poly_iexp_T_84, 1) node _activated_data_e_act_q_poly_iexp_T_86 = asSInt(_activated_data_e_act_q_poly_iexp_T_85) node _activated_data_e_act_q_poly_iexp_T_87 = bits(_activated_data_e_act_q_poly_iexp_T_86, 31, 0) node activated_data_e_act_q_poly_iexp_7 = asSInt(_activated_data_e_act_q_poly_iexp_T_87) node _activated_data_e_act_T_249 = asUInt(activated_data_e_act_q_poly_iexp_7) node _activated_data_e_act_T_250 = asUInt(activated_data_e_act_z_iexp_saturated_7) node _activated_data_e_act_T_251 = dshr(_activated_data_e_act_T_249, _activated_data_e_act_T_250) wire _activated_data_e_act_WIRE_7 : SInt<32> node _activated_data_e_act_T_252 = asSInt(_activated_data_e_act_T_251) connect _activated_data_e_act_WIRE_7, _activated_data_e_act_T_252 node _activated_data_e_act_T_253 = mux(_activated_data_e_act_T_245, _activated_data_e_act_WIRE_7, io.in.bits.acc_read_resp.data[7][0]) node _activated_data_e_act_T_254 = mux(_activated_data_e_act_T_236, _activated_data_e_act_T_242, _activated_data_e_act_T_253) node _activated_data_e_act_T_255 = mux(_activated_data_e_act_T_230, _activated_data_e_act_T_233, _activated_data_e_act_T_254) node activated_data_e_act_7 = mux(_activated_data_e_act_T_225, _activated_data_e_act_T_227, _activated_data_e_act_T_255) node _activated_data_e_scaled_T_77 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_78 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_79 = and(_activated_data_e_scaled_T_77, _activated_data_e_scaled_T_78) node _activated_data_e_scaled_T_80 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_81 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_82 = and(_activated_data_e_scaled_T_80, _activated_data_e_scaled_T_81) wire _activated_data_e_scaled_WIRE_35 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_36 : UInt<32> connect _activated_data_e_scaled_WIRE_36, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_83 = bits(_activated_data_e_scaled_WIRE_36, 31, 0) connect _activated_data_e_scaled_WIRE_35.bits, _activated_data_e_scaled_T_83 node _activated_data_e_scaled_T_84 = mux(_activated_data_e_scaled_T_82, _activated_data_e_scaled_WIRE_35, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_85 = mux(_activated_data_e_scaled_T_79, io.in.bits.inv_stddev, _activated_data_e_scaled_T_84) wire _activated_data_e_scaled_WIRE_37 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_38 : UInt<32> connect _activated_data_e_scaled_WIRE_38, _activated_data_e_scaled_T_85.bits node _activated_data_e_scaled_T_86 = bits(_activated_data_e_scaled_WIRE_38, 31, 0) connect _activated_data_e_scaled_WIRE_37.bits, _activated_data_e_scaled_T_86 node activated_data_e_scaled_f_rec_rawIn_sign_7 = bits(_activated_data_e_scaled_WIRE_37.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_7 = bits(_activated_data_e_scaled_WIRE_37.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_7 = bits(_activated_data_e_scaled_WIRE_37.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_7, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_7, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_308 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_309 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_310 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_311 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_312 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_313 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_314 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_315 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_316 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_317 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_318 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_319 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_320 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_321 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_322 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_323 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_324 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_325 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_326 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_327 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_328 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_329 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_330 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_7, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_331 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_309, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_332 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_310, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_331) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_333 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_311, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_332) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_334 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_312, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_333) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_335 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_313, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_334) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_336 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_314, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_335) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_337 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_315, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_336) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_338 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_316, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_337) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_339 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_317, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_338) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_340 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_318, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_339) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_341 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_319, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_340) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_342 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_320, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_341) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_343 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_321, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_342) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_344 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_322, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_343) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_345 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_323, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_344) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_346 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_324, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_345) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_347 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_325, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_346) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_348 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_326, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_347) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_349 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_327, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_348) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_350 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_328, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_349) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_351 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_329, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_350) node activated_data_e_scaled_f_rec_rawIn_normDist_7 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_330, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_351) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_14 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_7, activated_data_e_scaled_f_rec_rawIn_normDist_7) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_15 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_14, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_7 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_15, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_35 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_7, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_36 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_35, activated_data_e_scaled_f_rec_rawIn_expIn_7) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_37 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_38 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_37) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_39 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_36, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_38) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_7 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_39, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_7 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_7 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_7, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_7 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_7, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_7 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_14 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_15 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_7, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_14) connect activated_data_e_scaled_f_rec_rawIn_7.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_15 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_7 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_7, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7) connect activated_data_e_scaled_f_rec_rawIn_7.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_7 connect activated_data_e_scaled_f_rec_rawIn_7.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_7 connect activated_data_e_scaled_f_rec_rawIn_7.sign, activated_data_e_scaled_f_rec_rawIn_sign_7 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_14 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_7, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_15 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_14) connect activated_data_e_scaled_f_rec_rawIn_7.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_15 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_28 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_7, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_29 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_28) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_30 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7, activated_data_e_scaled_f_rec_rawIn_subnormFract_7, activated_data_e_scaled_f_rec_rawIn_fractIn_7) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_31 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_29, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_30) connect activated_data_e_scaled_f_rec_rawIn_7.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_31 node _activated_data_e_scaled_f_rec_T_56 = bits(activated_data_e_scaled_f_rec_rawIn_7.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_57 = mux(activated_data_e_scaled_f_rec_rawIn_7.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_56) node _activated_data_e_scaled_f_rec_T_58 = mux(activated_data_e_scaled_f_rec_rawIn_7.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_59 = or(_activated_data_e_scaled_f_rec_T_57, _activated_data_e_scaled_f_rec_T_58) node _activated_data_e_scaled_f_rec_T_60 = cat(activated_data_e_scaled_f_rec_rawIn_7.sign, _activated_data_e_scaled_f_rec_T_59) node _activated_data_e_scaled_f_rec_T_61 = bits(activated_data_e_scaled_f_rec_rawIn_7.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_62 = cat(_activated_data_e_scaled_f_rec_T_60, _activated_data_e_scaled_f_rec_T_61) node _activated_data_e_scaled_f_rec_T_63 = bits(activated_data_e_scaled_f_rec_rawIn_7.sig, 22, 0) node activated_data_e_scaled_f_rec_7 = cat(_activated_data_e_scaled_f_rec_T_62, _activated_data_e_scaled_f_rec_T_63) inst activated_data_e_scaled_in_to_rec_fn_7 of INToRecFN_i32_e8_s24_7 connect activated_data_e_scaled_in_to_rec_fn_7.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_7 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_7 = asUInt(activated_data_e_act_7) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_7, _activated_data_e_scaled_in_to_rec_fn_io_in_T_7 connect activated_data_e_scaled_in_to_rec_fn_7.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_7 connect activated_data_e_scaled_in_to_rec_fn_7.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_7.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_7 of MulAddRecFN_e8_s24_11 connect activated_data_e_scaled_muladder_7.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_7.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_7.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_7.io.a, activated_data_e_scaled_in_to_rec_fn_7.io.out connect activated_data_e_scaled_muladder_7.io.b, activated_data_e_scaled_f_rec_7 connect activated_data_e_scaled_muladder_7.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_7 of RecFNToIN_e8_s24_i32_7 connect activated_data_e_scaled_rec_fn_to_in_7.clock, clock connect activated_data_e_scaled_rec_fn_to_in_7.reset, reset connect activated_data_e_scaled_rec_fn_to_in_7.io.in, activated_data_e_scaled_muladder_7.io.out connect activated_data_e_scaled_rec_fn_to_in_7.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_7.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_7 = bits(activated_data_e_scaled_rec_fn_to_in_7.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_7 = bits(activated_data_e_scaled_rec_fn_to_in_7.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_7 = bits(activated_data_e_scaled_sign_exp_7, 8, 6) node activated_data_e_scaled_sign_isZero_7 = eq(_activated_data_e_scaled_sign_isZero_T_7, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_7 = bits(activated_data_e_scaled_sign_exp_7, 8, 7) node activated_data_e_scaled_sign_isSpecial_7 = eq(_activated_data_e_scaled_sign_isSpecial_T_7, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_7 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_14 = bits(activated_data_e_scaled_sign_exp_7, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_15 = and(activated_data_e_scaled_sign_isSpecial_7, _activated_data_e_scaled_sign_out_isNaN_T_14) connect activated_data_e_scaled_sign_out_7.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_15 node _activated_data_e_scaled_sign_out_isInf_T_21 = bits(activated_data_e_scaled_sign_exp_7, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_22 = eq(_activated_data_e_scaled_sign_out_isInf_T_21, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_23 = and(activated_data_e_scaled_sign_isSpecial_7, _activated_data_e_scaled_sign_out_isInf_T_22) connect activated_data_e_scaled_sign_out_7.isInf, _activated_data_e_scaled_sign_out_isInf_T_23 connect activated_data_e_scaled_sign_out_7.isZero, activated_data_e_scaled_sign_isZero_7 node _activated_data_e_scaled_sign_out_sign_T_7 = bits(activated_data_e_scaled_rec_fn_to_in_7.io.in, 32, 32) connect activated_data_e_scaled_sign_out_7.sign, _activated_data_e_scaled_sign_out_sign_T_7 node _activated_data_e_scaled_sign_out_sExp_T_7 = cvt(activated_data_e_scaled_sign_exp_7) connect activated_data_e_scaled_sign_out_7.sExp, _activated_data_e_scaled_sign_out_sExp_T_7 node _activated_data_e_scaled_sign_out_sig_T_28 = eq(activated_data_e_scaled_sign_isZero_7, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_29 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_28) node _activated_data_e_scaled_sign_out_sig_T_30 = bits(activated_data_e_scaled_rec_fn_to_in_7.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_31 = cat(_activated_data_e_scaled_sign_out_sig_T_29, _activated_data_e_scaled_sign_out_sig_T_30) connect activated_data_e_scaled_sign_out_7.sig, _activated_data_e_scaled_sign_out_sig_T_31 node activated_data_e_scaled_sat_7 = mux(activated_data_e_scaled_sign_out_7.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_39 : SInt<32> node _activated_data_e_scaled_T_87 = asSInt(activated_data_e_scaled_rec_fn_to_in_7.io.out) connect _activated_data_e_scaled_WIRE_39, _activated_data_e_scaled_T_87 node activated_data_e_scaled_7 = mux(activated_data_e_scaled_overflow_7, activated_data_e_scaled_sat_7, _activated_data_e_scaled_WIRE_39) node _activated_data_e_clipped_T_35 = gt(activated_data_e_scaled_7, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_36 = lt(activated_data_e_scaled_7, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_37 = mux(_activated_data_e_clipped_T_36, asSInt(UInt<8>(0h80)), activated_data_e_scaled_7) node _activated_data_e_clipped_T_38 = mux(_activated_data_e_clipped_T_35, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_37) node _activated_data_e_clipped_T_39 = bits(_activated_data_e_clipped_T_38, 7, 0) node activated_data_e_clipped_7 = asSInt(_activated_data_e_clipped_T_39) wire _activated_data_WIRE_7 : SInt<8>[1] connect _activated_data_WIRE_7[0], activated_data_e_clipped_7 node _activated_data_e_act_T_256 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_257 = and(UInt<1>(0h1), _activated_data_e_act_T_256) node _activated_data_e_act_T_258 = geq(io.in.bits.acc_read_resp.data[8][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_259 = mux(_activated_data_e_act_T_258, io.in.bits.acc_read_resp.data[8][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_260 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_261 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_262 = and(_activated_data_e_act_T_260, _activated_data_e_act_T_261) node _activated_data_e_act_T_263 = sub(io.in.bits.acc_read_resp.data[8][0], io.in.bits.mean) node _activated_data_e_act_T_264 = tail(_activated_data_e_act_T_263, 1) node _activated_data_e_act_T_265 = asSInt(_activated_data_e_act_T_264) node _activated_data_e_act_T_266 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_267 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_268 = and(_activated_data_e_act_T_266, _activated_data_e_act_T_267) node _activated_data_e_act_q_sign_T_32 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[8][0]) node _activated_data_e_act_q_sign_T_33 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_34 = tail(_activated_data_e_act_q_sign_T_33, 1) node _activated_data_e_act_q_sign_T_35 = asSInt(_activated_data_e_act_q_sign_T_34) node activated_data_e_act_q_sign_8 = mux(_activated_data_e_act_q_sign_T_32, _activated_data_e_act_q_sign_T_35, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_32 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[8][0]) node _activated_data_e_act_q_abs_T_33 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[8][0]) node _activated_data_e_act_q_abs_T_34 = tail(_activated_data_e_act_q_abs_T_33, 1) node _activated_data_e_act_q_abs_T_35 = asSInt(_activated_data_e_act_q_abs_T_34) node activated_data_e_act_q_abs_8 = mux(_activated_data_e_act_q_abs_T_32, _activated_data_e_act_q_abs_T_35, io.in.bits.acc_read_resp.data[8][0]) node _activated_data_e_act_q_clipped_T_56 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_57 = tail(_activated_data_e_act_q_clipped_T_56, 1) node _activated_data_e_act_q_clipped_T_58 = asSInt(_activated_data_e_act_q_clipped_T_57) node _activated_data_e_act_q_clipped_T_59 = gt(activated_data_e_act_q_abs_8, _activated_data_e_act_q_clipped_T_58) node _activated_data_e_act_q_clipped_T_60 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_61 = tail(_activated_data_e_act_q_clipped_T_60, 1) node _activated_data_e_act_q_clipped_T_62 = asSInt(_activated_data_e_act_q_clipped_T_61) node activated_data_e_act_q_clipped_8 = mux(_activated_data_e_act_q_clipped_T_59, _activated_data_e_act_q_clipped_T_62, activated_data_e_act_q_abs_8) node _activated_data_e_act_q_poly_T_88 = add(activated_data_e_act_q_clipped_8, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_89 = tail(_activated_data_e_act_q_poly_T_88, 1) node _activated_data_e_act_q_poly_T_90 = asSInt(_activated_data_e_act_q_poly_T_89) node _activated_data_e_act_q_poly_T_91 = add(activated_data_e_act_q_clipped_8, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_92 = tail(_activated_data_e_act_q_poly_T_91, 1) node _activated_data_e_act_q_poly_T_93 = asSInt(_activated_data_e_act_q_poly_T_92) node _activated_data_e_act_q_poly_T_94 = mul(_activated_data_e_act_q_poly_T_90, _activated_data_e_act_q_poly_T_93) node _activated_data_e_act_q_poly_T_95 = add(_activated_data_e_act_q_poly_T_94, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_96 = tail(_activated_data_e_act_q_poly_T_95, 1) node _activated_data_e_act_q_poly_T_97 = asSInt(_activated_data_e_act_q_poly_T_96) node _activated_data_e_act_q_poly_T_98 = bits(_activated_data_e_act_q_poly_T_97, 31, 0) node activated_data_e_act_q_poly_8 = asSInt(_activated_data_e_act_q_poly_T_98) node _activated_data_e_act_q_erf_T_16 = mul(activated_data_e_act_q_sign_8, activated_data_e_act_q_poly_8) node _activated_data_e_act_q_erf_T_17 = bits(_activated_data_e_act_q_erf_T_16, 31, 0) node activated_data_e_act_q_erf_8 = asSInt(_activated_data_e_act_q_erf_T_17) node _activated_data_e_act_T_269 = add(activated_data_e_act_q_erf_8, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_270 = tail(_activated_data_e_act_T_269, 1) node _activated_data_e_act_T_271 = asSInt(_activated_data_e_act_T_270) node _activated_data_e_act_T_272 = mul(io.in.bits.acc_read_resp.data[8][0], _activated_data_e_act_T_271) node _activated_data_e_act_T_273 = bits(_activated_data_e_act_T_272, 31, 0) node _activated_data_e_act_T_274 = asSInt(_activated_data_e_act_T_273) node _activated_data_e_act_T_275 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_276 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_277 = and(_activated_data_e_act_T_275, _activated_data_e_act_T_276) node _activated_data_e_act_T_278 = sub(io.in.bits.acc_read_resp.data[8][0], io.in.bits.max) node _activated_data_e_act_T_279 = tail(_activated_data_e_act_T_278, 1) node _activated_data_e_act_T_280 = asSInt(_activated_data_e_act_T_279) node _activated_data_e_act_neg_q_iexp_T_16 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_280) node _activated_data_e_act_neg_q_iexp_T_17 = tail(_activated_data_e_act_neg_q_iexp_T_16, 1) node activated_data_e_act_neg_q_iexp_8 = asSInt(_activated_data_e_act_neg_q_iexp_T_17) node _activated_data_e_act_z_iexp_T_32 = mul(activated_data_e_act_neg_q_iexp_8, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_33 = asUInt(_activated_data_e_act_z_iexp_T_32) node _activated_data_e_act_z_iexp_T_34 = shr(_activated_data_e_act_z_iexp_T_33, 16) wire activated_data_e_act_z_iexp_8 : SInt<32> node _activated_data_e_act_z_iexp_T_35 = asSInt(_activated_data_e_act_z_iexp_T_34) connect activated_data_e_act_z_iexp_8, _activated_data_e_act_z_iexp_T_35 wire activated_data_e_act_z_iexp_saturated_8 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_264 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_265 = bits(_activated_data_e_act_z_iexp_saturated_T_264, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_266 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_267 = bits(_activated_data_e_act_z_iexp_saturated_T_266, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_268 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_269 = bits(_activated_data_e_act_z_iexp_saturated_T_268, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_270 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_271 = bits(_activated_data_e_act_z_iexp_saturated_T_270, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_272 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_273 = bits(_activated_data_e_act_z_iexp_saturated_T_272, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_274 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_275 = bits(_activated_data_e_act_z_iexp_saturated_T_274, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_276 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_277 = bits(_activated_data_e_act_z_iexp_saturated_T_276, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_278 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_279 = bits(_activated_data_e_act_z_iexp_saturated_T_278, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_280 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_281 = bits(_activated_data_e_act_z_iexp_saturated_T_280, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_282 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_283 = bits(_activated_data_e_act_z_iexp_saturated_T_282, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_284 = asUInt(activated_data_e_act_z_iexp_8) node _activated_data_e_act_z_iexp_saturated_T_285 = bits(_activated_data_e_act_z_iexp_saturated_T_284, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_286 = or(_activated_data_e_act_z_iexp_saturated_T_265, _activated_data_e_act_z_iexp_saturated_T_267) node _activated_data_e_act_z_iexp_saturated_T_287 = or(_activated_data_e_act_z_iexp_saturated_T_286, _activated_data_e_act_z_iexp_saturated_T_269) node _activated_data_e_act_z_iexp_saturated_T_288 = or(_activated_data_e_act_z_iexp_saturated_T_287, _activated_data_e_act_z_iexp_saturated_T_271) node _activated_data_e_act_z_iexp_saturated_T_289 = or(_activated_data_e_act_z_iexp_saturated_T_288, _activated_data_e_act_z_iexp_saturated_T_273) node _activated_data_e_act_z_iexp_saturated_T_290 = or(_activated_data_e_act_z_iexp_saturated_T_289, _activated_data_e_act_z_iexp_saturated_T_275) node _activated_data_e_act_z_iexp_saturated_T_291 = or(_activated_data_e_act_z_iexp_saturated_T_290, _activated_data_e_act_z_iexp_saturated_T_277) node _activated_data_e_act_z_iexp_saturated_T_292 = or(_activated_data_e_act_z_iexp_saturated_T_291, _activated_data_e_act_z_iexp_saturated_T_279) node _activated_data_e_act_z_iexp_saturated_T_293 = or(_activated_data_e_act_z_iexp_saturated_T_292, _activated_data_e_act_z_iexp_saturated_T_281) node _activated_data_e_act_z_iexp_saturated_T_294 = or(_activated_data_e_act_z_iexp_saturated_T_293, _activated_data_e_act_z_iexp_saturated_T_283) node _activated_data_e_act_z_iexp_saturated_T_295 = or(_activated_data_e_act_z_iexp_saturated_T_294, _activated_data_e_act_z_iexp_saturated_T_285) wire _activated_data_e_act_z_iexp_saturated_WIRE_8 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_8, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_296 = mux(_activated_data_e_act_z_iexp_saturated_T_295, _activated_data_e_act_z_iexp_saturated_WIRE_8, activated_data_e_act_z_iexp_8) connect activated_data_e_act_z_iexp_saturated_8, _activated_data_e_act_z_iexp_saturated_T_296 node _activated_data_e_act_qp_iexp_T_40 = mul(activated_data_e_act_z_iexp_8, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_41 = add(_activated_data_e_act_qp_iexp_T_40, _activated_data_e_act_T_280) node _activated_data_e_act_qp_iexp_T_42 = tail(_activated_data_e_act_qp_iexp_T_41, 1) node _activated_data_e_act_qp_iexp_T_43 = asSInt(_activated_data_e_act_qp_iexp_T_42) node _activated_data_e_act_qp_iexp_T_44 = bits(_activated_data_e_act_qp_iexp_T_43, 31, 0) node activated_data_e_act_qp_iexp_8 = asSInt(_activated_data_e_act_qp_iexp_T_44) node _activated_data_e_act_q_poly_iexp_T_88 = add(activated_data_e_act_qp_iexp_8, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_89 = tail(_activated_data_e_act_q_poly_iexp_T_88, 1) node _activated_data_e_act_q_poly_iexp_T_90 = asSInt(_activated_data_e_act_q_poly_iexp_T_89) node _activated_data_e_act_q_poly_iexp_T_91 = add(activated_data_e_act_qp_iexp_8, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_92 = tail(_activated_data_e_act_q_poly_iexp_T_91, 1) node _activated_data_e_act_q_poly_iexp_T_93 = asSInt(_activated_data_e_act_q_poly_iexp_T_92) node _activated_data_e_act_q_poly_iexp_T_94 = mul(_activated_data_e_act_q_poly_iexp_T_90, _activated_data_e_act_q_poly_iexp_T_93) node _activated_data_e_act_q_poly_iexp_T_95 = add(_activated_data_e_act_q_poly_iexp_T_94, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_96 = tail(_activated_data_e_act_q_poly_iexp_T_95, 1) node _activated_data_e_act_q_poly_iexp_T_97 = asSInt(_activated_data_e_act_q_poly_iexp_T_96) node _activated_data_e_act_q_poly_iexp_T_98 = bits(_activated_data_e_act_q_poly_iexp_T_97, 31, 0) node activated_data_e_act_q_poly_iexp_8 = asSInt(_activated_data_e_act_q_poly_iexp_T_98) node _activated_data_e_act_T_281 = asUInt(activated_data_e_act_q_poly_iexp_8) node _activated_data_e_act_T_282 = asUInt(activated_data_e_act_z_iexp_saturated_8) node _activated_data_e_act_T_283 = dshr(_activated_data_e_act_T_281, _activated_data_e_act_T_282) wire _activated_data_e_act_WIRE_8 : SInt<32> node _activated_data_e_act_T_284 = asSInt(_activated_data_e_act_T_283) connect _activated_data_e_act_WIRE_8, _activated_data_e_act_T_284 node _activated_data_e_act_T_285 = mux(_activated_data_e_act_T_277, _activated_data_e_act_WIRE_8, io.in.bits.acc_read_resp.data[8][0]) node _activated_data_e_act_T_286 = mux(_activated_data_e_act_T_268, _activated_data_e_act_T_274, _activated_data_e_act_T_285) node _activated_data_e_act_T_287 = mux(_activated_data_e_act_T_262, _activated_data_e_act_T_265, _activated_data_e_act_T_286) node activated_data_e_act_8 = mux(_activated_data_e_act_T_257, _activated_data_e_act_T_259, _activated_data_e_act_T_287) node _activated_data_e_scaled_T_88 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_89 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_90 = and(_activated_data_e_scaled_T_88, _activated_data_e_scaled_T_89) node _activated_data_e_scaled_T_91 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_92 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_93 = and(_activated_data_e_scaled_T_91, _activated_data_e_scaled_T_92) wire _activated_data_e_scaled_WIRE_40 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_41 : UInt<32> connect _activated_data_e_scaled_WIRE_41, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_94 = bits(_activated_data_e_scaled_WIRE_41, 31, 0) connect _activated_data_e_scaled_WIRE_40.bits, _activated_data_e_scaled_T_94 node _activated_data_e_scaled_T_95 = mux(_activated_data_e_scaled_T_93, _activated_data_e_scaled_WIRE_40, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_96 = mux(_activated_data_e_scaled_T_90, io.in.bits.inv_stddev, _activated_data_e_scaled_T_95) wire _activated_data_e_scaled_WIRE_42 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_43 : UInt<32> connect _activated_data_e_scaled_WIRE_43, _activated_data_e_scaled_T_96.bits node _activated_data_e_scaled_T_97 = bits(_activated_data_e_scaled_WIRE_43, 31, 0) connect _activated_data_e_scaled_WIRE_42.bits, _activated_data_e_scaled_T_97 node activated_data_e_scaled_f_rec_rawIn_sign_8 = bits(_activated_data_e_scaled_WIRE_42.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_8 = bits(_activated_data_e_scaled_WIRE_42.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_8 = bits(_activated_data_e_scaled_WIRE_42.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_8, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_8, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_352 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_353 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_354 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_355 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_356 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_357 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_358 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_359 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_360 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_361 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_362 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_363 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_364 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_365 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_366 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_367 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_368 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_369 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_370 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_371 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_372 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_373 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_374 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_8, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_375 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_353, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_376 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_354, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_375) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_377 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_355, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_376) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_378 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_356, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_377) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_379 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_357, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_378) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_380 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_358, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_379) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_381 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_359, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_380) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_382 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_360, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_381) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_383 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_361, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_382) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_384 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_362, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_383) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_385 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_363, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_384) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_386 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_364, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_385) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_387 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_365, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_386) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_388 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_366, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_387) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_389 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_367, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_388) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_390 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_368, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_389) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_391 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_369, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_390) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_392 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_370, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_391) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_393 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_371, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_392) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_394 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_372, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_393) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_395 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_373, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_394) node activated_data_e_scaled_f_rec_rawIn_normDist_8 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_374, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_395) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_16 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_8, activated_data_e_scaled_f_rec_rawIn_normDist_8) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_17 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_16, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_8 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_17, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_40 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_8, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_41 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_40, activated_data_e_scaled_f_rec_rawIn_expIn_8) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_42 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_43 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_42) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_44 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_41, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_43) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_8 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_44, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_8 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_8 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_8, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_8 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_8, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_8 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_16 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_17 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_8, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_16) connect activated_data_e_scaled_f_rec_rawIn_8.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_17 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_8 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_8, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8) connect activated_data_e_scaled_f_rec_rawIn_8.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_8 connect activated_data_e_scaled_f_rec_rawIn_8.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_8 connect activated_data_e_scaled_f_rec_rawIn_8.sign, activated_data_e_scaled_f_rec_rawIn_sign_8 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_16 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_8, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_17 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_16) connect activated_data_e_scaled_f_rec_rawIn_8.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_17 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_32 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_8, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_33 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_32) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_34 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8, activated_data_e_scaled_f_rec_rawIn_subnormFract_8, activated_data_e_scaled_f_rec_rawIn_fractIn_8) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_35 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_33, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_34) connect activated_data_e_scaled_f_rec_rawIn_8.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_35 node _activated_data_e_scaled_f_rec_T_64 = bits(activated_data_e_scaled_f_rec_rawIn_8.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_65 = mux(activated_data_e_scaled_f_rec_rawIn_8.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_64) node _activated_data_e_scaled_f_rec_T_66 = mux(activated_data_e_scaled_f_rec_rawIn_8.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_67 = or(_activated_data_e_scaled_f_rec_T_65, _activated_data_e_scaled_f_rec_T_66) node _activated_data_e_scaled_f_rec_T_68 = cat(activated_data_e_scaled_f_rec_rawIn_8.sign, _activated_data_e_scaled_f_rec_T_67) node _activated_data_e_scaled_f_rec_T_69 = bits(activated_data_e_scaled_f_rec_rawIn_8.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_70 = cat(_activated_data_e_scaled_f_rec_T_68, _activated_data_e_scaled_f_rec_T_69) node _activated_data_e_scaled_f_rec_T_71 = bits(activated_data_e_scaled_f_rec_rawIn_8.sig, 22, 0) node activated_data_e_scaled_f_rec_8 = cat(_activated_data_e_scaled_f_rec_T_70, _activated_data_e_scaled_f_rec_T_71) inst activated_data_e_scaled_in_to_rec_fn_8 of INToRecFN_i32_e8_s24_8 connect activated_data_e_scaled_in_to_rec_fn_8.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_8 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_8 = asUInt(activated_data_e_act_8) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_8, _activated_data_e_scaled_in_to_rec_fn_io_in_T_8 connect activated_data_e_scaled_in_to_rec_fn_8.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_8 connect activated_data_e_scaled_in_to_rec_fn_8.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_8.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_8 of MulAddRecFN_e8_s24_12 connect activated_data_e_scaled_muladder_8.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_8.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_8.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_8.io.a, activated_data_e_scaled_in_to_rec_fn_8.io.out connect activated_data_e_scaled_muladder_8.io.b, activated_data_e_scaled_f_rec_8 connect activated_data_e_scaled_muladder_8.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_8 of RecFNToIN_e8_s24_i32_8 connect activated_data_e_scaled_rec_fn_to_in_8.clock, clock connect activated_data_e_scaled_rec_fn_to_in_8.reset, reset connect activated_data_e_scaled_rec_fn_to_in_8.io.in, activated_data_e_scaled_muladder_8.io.out connect activated_data_e_scaled_rec_fn_to_in_8.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_8.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_8 = bits(activated_data_e_scaled_rec_fn_to_in_8.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_8 = bits(activated_data_e_scaled_rec_fn_to_in_8.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_8 = bits(activated_data_e_scaled_sign_exp_8, 8, 6) node activated_data_e_scaled_sign_isZero_8 = eq(_activated_data_e_scaled_sign_isZero_T_8, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_8 = bits(activated_data_e_scaled_sign_exp_8, 8, 7) node activated_data_e_scaled_sign_isSpecial_8 = eq(_activated_data_e_scaled_sign_isSpecial_T_8, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_8 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_16 = bits(activated_data_e_scaled_sign_exp_8, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_17 = and(activated_data_e_scaled_sign_isSpecial_8, _activated_data_e_scaled_sign_out_isNaN_T_16) connect activated_data_e_scaled_sign_out_8.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_17 node _activated_data_e_scaled_sign_out_isInf_T_24 = bits(activated_data_e_scaled_sign_exp_8, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_25 = eq(_activated_data_e_scaled_sign_out_isInf_T_24, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_26 = and(activated_data_e_scaled_sign_isSpecial_8, _activated_data_e_scaled_sign_out_isInf_T_25) connect activated_data_e_scaled_sign_out_8.isInf, _activated_data_e_scaled_sign_out_isInf_T_26 connect activated_data_e_scaled_sign_out_8.isZero, activated_data_e_scaled_sign_isZero_8 node _activated_data_e_scaled_sign_out_sign_T_8 = bits(activated_data_e_scaled_rec_fn_to_in_8.io.in, 32, 32) connect activated_data_e_scaled_sign_out_8.sign, _activated_data_e_scaled_sign_out_sign_T_8 node _activated_data_e_scaled_sign_out_sExp_T_8 = cvt(activated_data_e_scaled_sign_exp_8) connect activated_data_e_scaled_sign_out_8.sExp, _activated_data_e_scaled_sign_out_sExp_T_8 node _activated_data_e_scaled_sign_out_sig_T_32 = eq(activated_data_e_scaled_sign_isZero_8, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_33 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_32) node _activated_data_e_scaled_sign_out_sig_T_34 = bits(activated_data_e_scaled_rec_fn_to_in_8.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_35 = cat(_activated_data_e_scaled_sign_out_sig_T_33, _activated_data_e_scaled_sign_out_sig_T_34) connect activated_data_e_scaled_sign_out_8.sig, _activated_data_e_scaled_sign_out_sig_T_35 node activated_data_e_scaled_sat_8 = mux(activated_data_e_scaled_sign_out_8.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_44 : SInt<32> node _activated_data_e_scaled_T_98 = asSInt(activated_data_e_scaled_rec_fn_to_in_8.io.out) connect _activated_data_e_scaled_WIRE_44, _activated_data_e_scaled_T_98 node activated_data_e_scaled_8 = mux(activated_data_e_scaled_overflow_8, activated_data_e_scaled_sat_8, _activated_data_e_scaled_WIRE_44) node _activated_data_e_clipped_T_40 = gt(activated_data_e_scaled_8, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_41 = lt(activated_data_e_scaled_8, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_42 = mux(_activated_data_e_clipped_T_41, asSInt(UInt<8>(0h80)), activated_data_e_scaled_8) node _activated_data_e_clipped_T_43 = mux(_activated_data_e_clipped_T_40, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_42) node _activated_data_e_clipped_T_44 = bits(_activated_data_e_clipped_T_43, 7, 0) node activated_data_e_clipped_8 = asSInt(_activated_data_e_clipped_T_44) wire _activated_data_WIRE_8 : SInt<8>[1] connect _activated_data_WIRE_8[0], activated_data_e_clipped_8 node _activated_data_e_act_T_288 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_289 = and(UInt<1>(0h1), _activated_data_e_act_T_288) node _activated_data_e_act_T_290 = geq(io.in.bits.acc_read_resp.data[9][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_291 = mux(_activated_data_e_act_T_290, io.in.bits.acc_read_resp.data[9][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_292 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_293 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_294 = and(_activated_data_e_act_T_292, _activated_data_e_act_T_293) node _activated_data_e_act_T_295 = sub(io.in.bits.acc_read_resp.data[9][0], io.in.bits.mean) node _activated_data_e_act_T_296 = tail(_activated_data_e_act_T_295, 1) node _activated_data_e_act_T_297 = asSInt(_activated_data_e_act_T_296) node _activated_data_e_act_T_298 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_299 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_300 = and(_activated_data_e_act_T_298, _activated_data_e_act_T_299) node _activated_data_e_act_q_sign_T_36 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[9][0]) node _activated_data_e_act_q_sign_T_37 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_38 = tail(_activated_data_e_act_q_sign_T_37, 1) node _activated_data_e_act_q_sign_T_39 = asSInt(_activated_data_e_act_q_sign_T_38) node activated_data_e_act_q_sign_9 = mux(_activated_data_e_act_q_sign_T_36, _activated_data_e_act_q_sign_T_39, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_36 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[9][0]) node _activated_data_e_act_q_abs_T_37 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[9][0]) node _activated_data_e_act_q_abs_T_38 = tail(_activated_data_e_act_q_abs_T_37, 1) node _activated_data_e_act_q_abs_T_39 = asSInt(_activated_data_e_act_q_abs_T_38) node activated_data_e_act_q_abs_9 = mux(_activated_data_e_act_q_abs_T_36, _activated_data_e_act_q_abs_T_39, io.in.bits.acc_read_resp.data[9][0]) node _activated_data_e_act_q_clipped_T_63 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_64 = tail(_activated_data_e_act_q_clipped_T_63, 1) node _activated_data_e_act_q_clipped_T_65 = asSInt(_activated_data_e_act_q_clipped_T_64) node _activated_data_e_act_q_clipped_T_66 = gt(activated_data_e_act_q_abs_9, _activated_data_e_act_q_clipped_T_65) node _activated_data_e_act_q_clipped_T_67 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_68 = tail(_activated_data_e_act_q_clipped_T_67, 1) node _activated_data_e_act_q_clipped_T_69 = asSInt(_activated_data_e_act_q_clipped_T_68) node activated_data_e_act_q_clipped_9 = mux(_activated_data_e_act_q_clipped_T_66, _activated_data_e_act_q_clipped_T_69, activated_data_e_act_q_abs_9) node _activated_data_e_act_q_poly_T_99 = add(activated_data_e_act_q_clipped_9, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_100 = tail(_activated_data_e_act_q_poly_T_99, 1) node _activated_data_e_act_q_poly_T_101 = asSInt(_activated_data_e_act_q_poly_T_100) node _activated_data_e_act_q_poly_T_102 = add(activated_data_e_act_q_clipped_9, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_103 = tail(_activated_data_e_act_q_poly_T_102, 1) node _activated_data_e_act_q_poly_T_104 = asSInt(_activated_data_e_act_q_poly_T_103) node _activated_data_e_act_q_poly_T_105 = mul(_activated_data_e_act_q_poly_T_101, _activated_data_e_act_q_poly_T_104) node _activated_data_e_act_q_poly_T_106 = add(_activated_data_e_act_q_poly_T_105, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_107 = tail(_activated_data_e_act_q_poly_T_106, 1) node _activated_data_e_act_q_poly_T_108 = asSInt(_activated_data_e_act_q_poly_T_107) node _activated_data_e_act_q_poly_T_109 = bits(_activated_data_e_act_q_poly_T_108, 31, 0) node activated_data_e_act_q_poly_9 = asSInt(_activated_data_e_act_q_poly_T_109) node _activated_data_e_act_q_erf_T_18 = mul(activated_data_e_act_q_sign_9, activated_data_e_act_q_poly_9) node _activated_data_e_act_q_erf_T_19 = bits(_activated_data_e_act_q_erf_T_18, 31, 0) node activated_data_e_act_q_erf_9 = asSInt(_activated_data_e_act_q_erf_T_19) node _activated_data_e_act_T_301 = add(activated_data_e_act_q_erf_9, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_302 = tail(_activated_data_e_act_T_301, 1) node _activated_data_e_act_T_303 = asSInt(_activated_data_e_act_T_302) node _activated_data_e_act_T_304 = mul(io.in.bits.acc_read_resp.data[9][0], _activated_data_e_act_T_303) node _activated_data_e_act_T_305 = bits(_activated_data_e_act_T_304, 31, 0) node _activated_data_e_act_T_306 = asSInt(_activated_data_e_act_T_305) node _activated_data_e_act_T_307 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_308 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_309 = and(_activated_data_e_act_T_307, _activated_data_e_act_T_308) node _activated_data_e_act_T_310 = sub(io.in.bits.acc_read_resp.data[9][0], io.in.bits.max) node _activated_data_e_act_T_311 = tail(_activated_data_e_act_T_310, 1) node _activated_data_e_act_T_312 = asSInt(_activated_data_e_act_T_311) node _activated_data_e_act_neg_q_iexp_T_18 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_312) node _activated_data_e_act_neg_q_iexp_T_19 = tail(_activated_data_e_act_neg_q_iexp_T_18, 1) node activated_data_e_act_neg_q_iexp_9 = asSInt(_activated_data_e_act_neg_q_iexp_T_19) node _activated_data_e_act_z_iexp_T_36 = mul(activated_data_e_act_neg_q_iexp_9, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_37 = asUInt(_activated_data_e_act_z_iexp_T_36) node _activated_data_e_act_z_iexp_T_38 = shr(_activated_data_e_act_z_iexp_T_37, 16) wire activated_data_e_act_z_iexp_9 : SInt<32> node _activated_data_e_act_z_iexp_T_39 = asSInt(_activated_data_e_act_z_iexp_T_38) connect activated_data_e_act_z_iexp_9, _activated_data_e_act_z_iexp_T_39 wire activated_data_e_act_z_iexp_saturated_9 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_297 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_298 = bits(_activated_data_e_act_z_iexp_saturated_T_297, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_299 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_300 = bits(_activated_data_e_act_z_iexp_saturated_T_299, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_301 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_302 = bits(_activated_data_e_act_z_iexp_saturated_T_301, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_303 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_304 = bits(_activated_data_e_act_z_iexp_saturated_T_303, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_305 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_306 = bits(_activated_data_e_act_z_iexp_saturated_T_305, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_307 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_308 = bits(_activated_data_e_act_z_iexp_saturated_T_307, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_309 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_310 = bits(_activated_data_e_act_z_iexp_saturated_T_309, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_311 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_312 = bits(_activated_data_e_act_z_iexp_saturated_T_311, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_313 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_314 = bits(_activated_data_e_act_z_iexp_saturated_T_313, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_315 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_316 = bits(_activated_data_e_act_z_iexp_saturated_T_315, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_317 = asUInt(activated_data_e_act_z_iexp_9) node _activated_data_e_act_z_iexp_saturated_T_318 = bits(_activated_data_e_act_z_iexp_saturated_T_317, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_319 = or(_activated_data_e_act_z_iexp_saturated_T_298, _activated_data_e_act_z_iexp_saturated_T_300) node _activated_data_e_act_z_iexp_saturated_T_320 = or(_activated_data_e_act_z_iexp_saturated_T_319, _activated_data_e_act_z_iexp_saturated_T_302) node _activated_data_e_act_z_iexp_saturated_T_321 = or(_activated_data_e_act_z_iexp_saturated_T_320, _activated_data_e_act_z_iexp_saturated_T_304) node _activated_data_e_act_z_iexp_saturated_T_322 = or(_activated_data_e_act_z_iexp_saturated_T_321, _activated_data_e_act_z_iexp_saturated_T_306) node _activated_data_e_act_z_iexp_saturated_T_323 = or(_activated_data_e_act_z_iexp_saturated_T_322, _activated_data_e_act_z_iexp_saturated_T_308) node _activated_data_e_act_z_iexp_saturated_T_324 = or(_activated_data_e_act_z_iexp_saturated_T_323, _activated_data_e_act_z_iexp_saturated_T_310) node _activated_data_e_act_z_iexp_saturated_T_325 = or(_activated_data_e_act_z_iexp_saturated_T_324, _activated_data_e_act_z_iexp_saturated_T_312) node _activated_data_e_act_z_iexp_saturated_T_326 = or(_activated_data_e_act_z_iexp_saturated_T_325, _activated_data_e_act_z_iexp_saturated_T_314) node _activated_data_e_act_z_iexp_saturated_T_327 = or(_activated_data_e_act_z_iexp_saturated_T_326, _activated_data_e_act_z_iexp_saturated_T_316) node _activated_data_e_act_z_iexp_saturated_T_328 = or(_activated_data_e_act_z_iexp_saturated_T_327, _activated_data_e_act_z_iexp_saturated_T_318) wire _activated_data_e_act_z_iexp_saturated_WIRE_9 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_9, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_329 = mux(_activated_data_e_act_z_iexp_saturated_T_328, _activated_data_e_act_z_iexp_saturated_WIRE_9, activated_data_e_act_z_iexp_9) connect activated_data_e_act_z_iexp_saturated_9, _activated_data_e_act_z_iexp_saturated_T_329 node _activated_data_e_act_qp_iexp_T_45 = mul(activated_data_e_act_z_iexp_9, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_46 = add(_activated_data_e_act_qp_iexp_T_45, _activated_data_e_act_T_312) node _activated_data_e_act_qp_iexp_T_47 = tail(_activated_data_e_act_qp_iexp_T_46, 1) node _activated_data_e_act_qp_iexp_T_48 = asSInt(_activated_data_e_act_qp_iexp_T_47) node _activated_data_e_act_qp_iexp_T_49 = bits(_activated_data_e_act_qp_iexp_T_48, 31, 0) node activated_data_e_act_qp_iexp_9 = asSInt(_activated_data_e_act_qp_iexp_T_49) node _activated_data_e_act_q_poly_iexp_T_99 = add(activated_data_e_act_qp_iexp_9, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_100 = tail(_activated_data_e_act_q_poly_iexp_T_99, 1) node _activated_data_e_act_q_poly_iexp_T_101 = asSInt(_activated_data_e_act_q_poly_iexp_T_100) node _activated_data_e_act_q_poly_iexp_T_102 = add(activated_data_e_act_qp_iexp_9, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_103 = tail(_activated_data_e_act_q_poly_iexp_T_102, 1) node _activated_data_e_act_q_poly_iexp_T_104 = asSInt(_activated_data_e_act_q_poly_iexp_T_103) node _activated_data_e_act_q_poly_iexp_T_105 = mul(_activated_data_e_act_q_poly_iexp_T_101, _activated_data_e_act_q_poly_iexp_T_104) node _activated_data_e_act_q_poly_iexp_T_106 = add(_activated_data_e_act_q_poly_iexp_T_105, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_107 = tail(_activated_data_e_act_q_poly_iexp_T_106, 1) node _activated_data_e_act_q_poly_iexp_T_108 = asSInt(_activated_data_e_act_q_poly_iexp_T_107) node _activated_data_e_act_q_poly_iexp_T_109 = bits(_activated_data_e_act_q_poly_iexp_T_108, 31, 0) node activated_data_e_act_q_poly_iexp_9 = asSInt(_activated_data_e_act_q_poly_iexp_T_109) node _activated_data_e_act_T_313 = asUInt(activated_data_e_act_q_poly_iexp_9) node _activated_data_e_act_T_314 = asUInt(activated_data_e_act_z_iexp_saturated_9) node _activated_data_e_act_T_315 = dshr(_activated_data_e_act_T_313, _activated_data_e_act_T_314) wire _activated_data_e_act_WIRE_9 : SInt<32> node _activated_data_e_act_T_316 = asSInt(_activated_data_e_act_T_315) connect _activated_data_e_act_WIRE_9, _activated_data_e_act_T_316 node _activated_data_e_act_T_317 = mux(_activated_data_e_act_T_309, _activated_data_e_act_WIRE_9, io.in.bits.acc_read_resp.data[9][0]) node _activated_data_e_act_T_318 = mux(_activated_data_e_act_T_300, _activated_data_e_act_T_306, _activated_data_e_act_T_317) node _activated_data_e_act_T_319 = mux(_activated_data_e_act_T_294, _activated_data_e_act_T_297, _activated_data_e_act_T_318) node activated_data_e_act_9 = mux(_activated_data_e_act_T_289, _activated_data_e_act_T_291, _activated_data_e_act_T_319) node _activated_data_e_scaled_T_99 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_100 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_101 = and(_activated_data_e_scaled_T_99, _activated_data_e_scaled_T_100) node _activated_data_e_scaled_T_102 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_103 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_104 = and(_activated_data_e_scaled_T_102, _activated_data_e_scaled_T_103) wire _activated_data_e_scaled_WIRE_45 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_46 : UInt<32> connect _activated_data_e_scaled_WIRE_46, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_105 = bits(_activated_data_e_scaled_WIRE_46, 31, 0) connect _activated_data_e_scaled_WIRE_45.bits, _activated_data_e_scaled_T_105 node _activated_data_e_scaled_T_106 = mux(_activated_data_e_scaled_T_104, _activated_data_e_scaled_WIRE_45, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_107 = mux(_activated_data_e_scaled_T_101, io.in.bits.inv_stddev, _activated_data_e_scaled_T_106) wire _activated_data_e_scaled_WIRE_47 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_48 : UInt<32> connect _activated_data_e_scaled_WIRE_48, _activated_data_e_scaled_T_107.bits node _activated_data_e_scaled_T_108 = bits(_activated_data_e_scaled_WIRE_48, 31, 0) connect _activated_data_e_scaled_WIRE_47.bits, _activated_data_e_scaled_T_108 node activated_data_e_scaled_f_rec_rawIn_sign_9 = bits(_activated_data_e_scaled_WIRE_47.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_9 = bits(_activated_data_e_scaled_WIRE_47.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_9 = bits(_activated_data_e_scaled_WIRE_47.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_9, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_9, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_396 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_397 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_398 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_399 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_400 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_401 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_402 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_403 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_404 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_405 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_406 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_407 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_408 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_409 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_410 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_411 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_412 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_413 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_414 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_415 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_416 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_417 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_418 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_9, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_419 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_397, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_420 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_398, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_419) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_421 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_399, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_420) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_422 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_400, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_421) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_423 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_401, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_422) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_424 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_402, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_423) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_425 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_403, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_424) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_426 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_404, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_425) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_427 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_405, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_426) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_428 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_406, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_427) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_429 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_407, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_428) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_430 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_408, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_429) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_431 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_409, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_430) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_432 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_410, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_431) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_433 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_411, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_432) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_434 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_412, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_433) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_435 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_413, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_434) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_436 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_414, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_435) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_437 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_415, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_436) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_438 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_416, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_437) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_439 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_417, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_438) node activated_data_e_scaled_f_rec_rawIn_normDist_9 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_418, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_439) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_18 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_9, activated_data_e_scaled_f_rec_rawIn_normDist_9) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_19 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_18, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_9 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_19, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_45 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_9, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_46 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_45, activated_data_e_scaled_f_rec_rawIn_expIn_9) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_47 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_48 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_47) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_49 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_46, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_48) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_9 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_49, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_9 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_9 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_9, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_9 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_9, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_9 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_18 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_19 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_9, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_18) connect activated_data_e_scaled_f_rec_rawIn_9.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_19 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_9 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_9, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9) connect activated_data_e_scaled_f_rec_rawIn_9.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_9 connect activated_data_e_scaled_f_rec_rawIn_9.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_9 connect activated_data_e_scaled_f_rec_rawIn_9.sign, activated_data_e_scaled_f_rec_rawIn_sign_9 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_18 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_9, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_19 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_18) connect activated_data_e_scaled_f_rec_rawIn_9.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_19 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_36 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_9, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_37 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_36) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_38 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9, activated_data_e_scaled_f_rec_rawIn_subnormFract_9, activated_data_e_scaled_f_rec_rawIn_fractIn_9) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_39 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_37, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_38) connect activated_data_e_scaled_f_rec_rawIn_9.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_39 node _activated_data_e_scaled_f_rec_T_72 = bits(activated_data_e_scaled_f_rec_rawIn_9.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_73 = mux(activated_data_e_scaled_f_rec_rawIn_9.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_72) node _activated_data_e_scaled_f_rec_T_74 = mux(activated_data_e_scaled_f_rec_rawIn_9.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_75 = or(_activated_data_e_scaled_f_rec_T_73, _activated_data_e_scaled_f_rec_T_74) node _activated_data_e_scaled_f_rec_T_76 = cat(activated_data_e_scaled_f_rec_rawIn_9.sign, _activated_data_e_scaled_f_rec_T_75) node _activated_data_e_scaled_f_rec_T_77 = bits(activated_data_e_scaled_f_rec_rawIn_9.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_78 = cat(_activated_data_e_scaled_f_rec_T_76, _activated_data_e_scaled_f_rec_T_77) node _activated_data_e_scaled_f_rec_T_79 = bits(activated_data_e_scaled_f_rec_rawIn_9.sig, 22, 0) node activated_data_e_scaled_f_rec_9 = cat(_activated_data_e_scaled_f_rec_T_78, _activated_data_e_scaled_f_rec_T_79) inst activated_data_e_scaled_in_to_rec_fn_9 of INToRecFN_i32_e8_s24_9 connect activated_data_e_scaled_in_to_rec_fn_9.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_9 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_9 = asUInt(activated_data_e_act_9) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_9, _activated_data_e_scaled_in_to_rec_fn_io_in_T_9 connect activated_data_e_scaled_in_to_rec_fn_9.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_9 connect activated_data_e_scaled_in_to_rec_fn_9.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_9.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_9 of MulAddRecFN_e8_s24_13 connect activated_data_e_scaled_muladder_9.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_9.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_9.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_9.io.a, activated_data_e_scaled_in_to_rec_fn_9.io.out connect activated_data_e_scaled_muladder_9.io.b, activated_data_e_scaled_f_rec_9 connect activated_data_e_scaled_muladder_9.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_9 of RecFNToIN_e8_s24_i32_9 connect activated_data_e_scaled_rec_fn_to_in_9.clock, clock connect activated_data_e_scaled_rec_fn_to_in_9.reset, reset connect activated_data_e_scaled_rec_fn_to_in_9.io.in, activated_data_e_scaled_muladder_9.io.out connect activated_data_e_scaled_rec_fn_to_in_9.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_9.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_9 = bits(activated_data_e_scaled_rec_fn_to_in_9.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_9 = bits(activated_data_e_scaled_rec_fn_to_in_9.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_9 = bits(activated_data_e_scaled_sign_exp_9, 8, 6) node activated_data_e_scaled_sign_isZero_9 = eq(_activated_data_e_scaled_sign_isZero_T_9, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_9 = bits(activated_data_e_scaled_sign_exp_9, 8, 7) node activated_data_e_scaled_sign_isSpecial_9 = eq(_activated_data_e_scaled_sign_isSpecial_T_9, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_9 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_18 = bits(activated_data_e_scaled_sign_exp_9, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_19 = and(activated_data_e_scaled_sign_isSpecial_9, _activated_data_e_scaled_sign_out_isNaN_T_18) connect activated_data_e_scaled_sign_out_9.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_19 node _activated_data_e_scaled_sign_out_isInf_T_27 = bits(activated_data_e_scaled_sign_exp_9, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_28 = eq(_activated_data_e_scaled_sign_out_isInf_T_27, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_29 = and(activated_data_e_scaled_sign_isSpecial_9, _activated_data_e_scaled_sign_out_isInf_T_28) connect activated_data_e_scaled_sign_out_9.isInf, _activated_data_e_scaled_sign_out_isInf_T_29 connect activated_data_e_scaled_sign_out_9.isZero, activated_data_e_scaled_sign_isZero_9 node _activated_data_e_scaled_sign_out_sign_T_9 = bits(activated_data_e_scaled_rec_fn_to_in_9.io.in, 32, 32) connect activated_data_e_scaled_sign_out_9.sign, _activated_data_e_scaled_sign_out_sign_T_9 node _activated_data_e_scaled_sign_out_sExp_T_9 = cvt(activated_data_e_scaled_sign_exp_9) connect activated_data_e_scaled_sign_out_9.sExp, _activated_data_e_scaled_sign_out_sExp_T_9 node _activated_data_e_scaled_sign_out_sig_T_36 = eq(activated_data_e_scaled_sign_isZero_9, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_37 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_36) node _activated_data_e_scaled_sign_out_sig_T_38 = bits(activated_data_e_scaled_rec_fn_to_in_9.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_39 = cat(_activated_data_e_scaled_sign_out_sig_T_37, _activated_data_e_scaled_sign_out_sig_T_38) connect activated_data_e_scaled_sign_out_9.sig, _activated_data_e_scaled_sign_out_sig_T_39 node activated_data_e_scaled_sat_9 = mux(activated_data_e_scaled_sign_out_9.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_49 : SInt<32> node _activated_data_e_scaled_T_109 = asSInt(activated_data_e_scaled_rec_fn_to_in_9.io.out) connect _activated_data_e_scaled_WIRE_49, _activated_data_e_scaled_T_109 node activated_data_e_scaled_9 = mux(activated_data_e_scaled_overflow_9, activated_data_e_scaled_sat_9, _activated_data_e_scaled_WIRE_49) node _activated_data_e_clipped_T_45 = gt(activated_data_e_scaled_9, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_46 = lt(activated_data_e_scaled_9, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_47 = mux(_activated_data_e_clipped_T_46, asSInt(UInt<8>(0h80)), activated_data_e_scaled_9) node _activated_data_e_clipped_T_48 = mux(_activated_data_e_clipped_T_45, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_47) node _activated_data_e_clipped_T_49 = bits(_activated_data_e_clipped_T_48, 7, 0) node activated_data_e_clipped_9 = asSInt(_activated_data_e_clipped_T_49) wire _activated_data_WIRE_9 : SInt<8>[1] connect _activated_data_WIRE_9[0], activated_data_e_clipped_9 node _activated_data_e_act_T_320 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_321 = and(UInt<1>(0h1), _activated_data_e_act_T_320) node _activated_data_e_act_T_322 = geq(io.in.bits.acc_read_resp.data[10][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_323 = mux(_activated_data_e_act_T_322, io.in.bits.acc_read_resp.data[10][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_324 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_325 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_326 = and(_activated_data_e_act_T_324, _activated_data_e_act_T_325) node _activated_data_e_act_T_327 = sub(io.in.bits.acc_read_resp.data[10][0], io.in.bits.mean) node _activated_data_e_act_T_328 = tail(_activated_data_e_act_T_327, 1) node _activated_data_e_act_T_329 = asSInt(_activated_data_e_act_T_328) node _activated_data_e_act_T_330 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_331 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_332 = and(_activated_data_e_act_T_330, _activated_data_e_act_T_331) node _activated_data_e_act_q_sign_T_40 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[10][0]) node _activated_data_e_act_q_sign_T_41 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_42 = tail(_activated_data_e_act_q_sign_T_41, 1) node _activated_data_e_act_q_sign_T_43 = asSInt(_activated_data_e_act_q_sign_T_42) node activated_data_e_act_q_sign_10 = mux(_activated_data_e_act_q_sign_T_40, _activated_data_e_act_q_sign_T_43, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_40 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[10][0]) node _activated_data_e_act_q_abs_T_41 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[10][0]) node _activated_data_e_act_q_abs_T_42 = tail(_activated_data_e_act_q_abs_T_41, 1) node _activated_data_e_act_q_abs_T_43 = asSInt(_activated_data_e_act_q_abs_T_42) node activated_data_e_act_q_abs_10 = mux(_activated_data_e_act_q_abs_T_40, _activated_data_e_act_q_abs_T_43, io.in.bits.acc_read_resp.data[10][0]) node _activated_data_e_act_q_clipped_T_70 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_71 = tail(_activated_data_e_act_q_clipped_T_70, 1) node _activated_data_e_act_q_clipped_T_72 = asSInt(_activated_data_e_act_q_clipped_T_71) node _activated_data_e_act_q_clipped_T_73 = gt(activated_data_e_act_q_abs_10, _activated_data_e_act_q_clipped_T_72) node _activated_data_e_act_q_clipped_T_74 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_75 = tail(_activated_data_e_act_q_clipped_T_74, 1) node _activated_data_e_act_q_clipped_T_76 = asSInt(_activated_data_e_act_q_clipped_T_75) node activated_data_e_act_q_clipped_10 = mux(_activated_data_e_act_q_clipped_T_73, _activated_data_e_act_q_clipped_T_76, activated_data_e_act_q_abs_10) node _activated_data_e_act_q_poly_T_110 = add(activated_data_e_act_q_clipped_10, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_111 = tail(_activated_data_e_act_q_poly_T_110, 1) node _activated_data_e_act_q_poly_T_112 = asSInt(_activated_data_e_act_q_poly_T_111) node _activated_data_e_act_q_poly_T_113 = add(activated_data_e_act_q_clipped_10, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_114 = tail(_activated_data_e_act_q_poly_T_113, 1) node _activated_data_e_act_q_poly_T_115 = asSInt(_activated_data_e_act_q_poly_T_114) node _activated_data_e_act_q_poly_T_116 = mul(_activated_data_e_act_q_poly_T_112, _activated_data_e_act_q_poly_T_115) node _activated_data_e_act_q_poly_T_117 = add(_activated_data_e_act_q_poly_T_116, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_118 = tail(_activated_data_e_act_q_poly_T_117, 1) node _activated_data_e_act_q_poly_T_119 = asSInt(_activated_data_e_act_q_poly_T_118) node _activated_data_e_act_q_poly_T_120 = bits(_activated_data_e_act_q_poly_T_119, 31, 0) node activated_data_e_act_q_poly_10 = asSInt(_activated_data_e_act_q_poly_T_120) node _activated_data_e_act_q_erf_T_20 = mul(activated_data_e_act_q_sign_10, activated_data_e_act_q_poly_10) node _activated_data_e_act_q_erf_T_21 = bits(_activated_data_e_act_q_erf_T_20, 31, 0) node activated_data_e_act_q_erf_10 = asSInt(_activated_data_e_act_q_erf_T_21) node _activated_data_e_act_T_333 = add(activated_data_e_act_q_erf_10, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_334 = tail(_activated_data_e_act_T_333, 1) node _activated_data_e_act_T_335 = asSInt(_activated_data_e_act_T_334) node _activated_data_e_act_T_336 = mul(io.in.bits.acc_read_resp.data[10][0], _activated_data_e_act_T_335) node _activated_data_e_act_T_337 = bits(_activated_data_e_act_T_336, 31, 0) node _activated_data_e_act_T_338 = asSInt(_activated_data_e_act_T_337) node _activated_data_e_act_T_339 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_340 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_341 = and(_activated_data_e_act_T_339, _activated_data_e_act_T_340) node _activated_data_e_act_T_342 = sub(io.in.bits.acc_read_resp.data[10][0], io.in.bits.max) node _activated_data_e_act_T_343 = tail(_activated_data_e_act_T_342, 1) node _activated_data_e_act_T_344 = asSInt(_activated_data_e_act_T_343) node _activated_data_e_act_neg_q_iexp_T_20 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_344) node _activated_data_e_act_neg_q_iexp_T_21 = tail(_activated_data_e_act_neg_q_iexp_T_20, 1) node activated_data_e_act_neg_q_iexp_10 = asSInt(_activated_data_e_act_neg_q_iexp_T_21) node _activated_data_e_act_z_iexp_T_40 = mul(activated_data_e_act_neg_q_iexp_10, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_41 = asUInt(_activated_data_e_act_z_iexp_T_40) node _activated_data_e_act_z_iexp_T_42 = shr(_activated_data_e_act_z_iexp_T_41, 16) wire activated_data_e_act_z_iexp_10 : SInt<32> node _activated_data_e_act_z_iexp_T_43 = asSInt(_activated_data_e_act_z_iexp_T_42) connect activated_data_e_act_z_iexp_10, _activated_data_e_act_z_iexp_T_43 wire activated_data_e_act_z_iexp_saturated_10 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_330 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_331 = bits(_activated_data_e_act_z_iexp_saturated_T_330, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_332 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_333 = bits(_activated_data_e_act_z_iexp_saturated_T_332, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_334 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_335 = bits(_activated_data_e_act_z_iexp_saturated_T_334, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_336 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_337 = bits(_activated_data_e_act_z_iexp_saturated_T_336, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_338 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_339 = bits(_activated_data_e_act_z_iexp_saturated_T_338, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_340 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_341 = bits(_activated_data_e_act_z_iexp_saturated_T_340, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_342 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_343 = bits(_activated_data_e_act_z_iexp_saturated_T_342, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_344 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_345 = bits(_activated_data_e_act_z_iexp_saturated_T_344, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_346 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_347 = bits(_activated_data_e_act_z_iexp_saturated_T_346, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_348 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_349 = bits(_activated_data_e_act_z_iexp_saturated_T_348, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_350 = asUInt(activated_data_e_act_z_iexp_10) node _activated_data_e_act_z_iexp_saturated_T_351 = bits(_activated_data_e_act_z_iexp_saturated_T_350, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_352 = or(_activated_data_e_act_z_iexp_saturated_T_331, _activated_data_e_act_z_iexp_saturated_T_333) node _activated_data_e_act_z_iexp_saturated_T_353 = or(_activated_data_e_act_z_iexp_saturated_T_352, _activated_data_e_act_z_iexp_saturated_T_335) node _activated_data_e_act_z_iexp_saturated_T_354 = or(_activated_data_e_act_z_iexp_saturated_T_353, _activated_data_e_act_z_iexp_saturated_T_337) node _activated_data_e_act_z_iexp_saturated_T_355 = or(_activated_data_e_act_z_iexp_saturated_T_354, _activated_data_e_act_z_iexp_saturated_T_339) node _activated_data_e_act_z_iexp_saturated_T_356 = or(_activated_data_e_act_z_iexp_saturated_T_355, _activated_data_e_act_z_iexp_saturated_T_341) node _activated_data_e_act_z_iexp_saturated_T_357 = or(_activated_data_e_act_z_iexp_saturated_T_356, _activated_data_e_act_z_iexp_saturated_T_343) node _activated_data_e_act_z_iexp_saturated_T_358 = or(_activated_data_e_act_z_iexp_saturated_T_357, _activated_data_e_act_z_iexp_saturated_T_345) node _activated_data_e_act_z_iexp_saturated_T_359 = or(_activated_data_e_act_z_iexp_saturated_T_358, _activated_data_e_act_z_iexp_saturated_T_347) node _activated_data_e_act_z_iexp_saturated_T_360 = or(_activated_data_e_act_z_iexp_saturated_T_359, _activated_data_e_act_z_iexp_saturated_T_349) node _activated_data_e_act_z_iexp_saturated_T_361 = or(_activated_data_e_act_z_iexp_saturated_T_360, _activated_data_e_act_z_iexp_saturated_T_351) wire _activated_data_e_act_z_iexp_saturated_WIRE_10 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_10, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_362 = mux(_activated_data_e_act_z_iexp_saturated_T_361, _activated_data_e_act_z_iexp_saturated_WIRE_10, activated_data_e_act_z_iexp_10) connect activated_data_e_act_z_iexp_saturated_10, _activated_data_e_act_z_iexp_saturated_T_362 node _activated_data_e_act_qp_iexp_T_50 = mul(activated_data_e_act_z_iexp_10, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_51 = add(_activated_data_e_act_qp_iexp_T_50, _activated_data_e_act_T_344) node _activated_data_e_act_qp_iexp_T_52 = tail(_activated_data_e_act_qp_iexp_T_51, 1) node _activated_data_e_act_qp_iexp_T_53 = asSInt(_activated_data_e_act_qp_iexp_T_52) node _activated_data_e_act_qp_iexp_T_54 = bits(_activated_data_e_act_qp_iexp_T_53, 31, 0) node activated_data_e_act_qp_iexp_10 = asSInt(_activated_data_e_act_qp_iexp_T_54) node _activated_data_e_act_q_poly_iexp_T_110 = add(activated_data_e_act_qp_iexp_10, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_111 = tail(_activated_data_e_act_q_poly_iexp_T_110, 1) node _activated_data_e_act_q_poly_iexp_T_112 = asSInt(_activated_data_e_act_q_poly_iexp_T_111) node _activated_data_e_act_q_poly_iexp_T_113 = add(activated_data_e_act_qp_iexp_10, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_114 = tail(_activated_data_e_act_q_poly_iexp_T_113, 1) node _activated_data_e_act_q_poly_iexp_T_115 = asSInt(_activated_data_e_act_q_poly_iexp_T_114) node _activated_data_e_act_q_poly_iexp_T_116 = mul(_activated_data_e_act_q_poly_iexp_T_112, _activated_data_e_act_q_poly_iexp_T_115) node _activated_data_e_act_q_poly_iexp_T_117 = add(_activated_data_e_act_q_poly_iexp_T_116, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_118 = tail(_activated_data_e_act_q_poly_iexp_T_117, 1) node _activated_data_e_act_q_poly_iexp_T_119 = asSInt(_activated_data_e_act_q_poly_iexp_T_118) node _activated_data_e_act_q_poly_iexp_T_120 = bits(_activated_data_e_act_q_poly_iexp_T_119, 31, 0) node activated_data_e_act_q_poly_iexp_10 = asSInt(_activated_data_e_act_q_poly_iexp_T_120) node _activated_data_e_act_T_345 = asUInt(activated_data_e_act_q_poly_iexp_10) node _activated_data_e_act_T_346 = asUInt(activated_data_e_act_z_iexp_saturated_10) node _activated_data_e_act_T_347 = dshr(_activated_data_e_act_T_345, _activated_data_e_act_T_346) wire _activated_data_e_act_WIRE_10 : SInt<32> node _activated_data_e_act_T_348 = asSInt(_activated_data_e_act_T_347) connect _activated_data_e_act_WIRE_10, _activated_data_e_act_T_348 node _activated_data_e_act_T_349 = mux(_activated_data_e_act_T_341, _activated_data_e_act_WIRE_10, io.in.bits.acc_read_resp.data[10][0]) node _activated_data_e_act_T_350 = mux(_activated_data_e_act_T_332, _activated_data_e_act_T_338, _activated_data_e_act_T_349) node _activated_data_e_act_T_351 = mux(_activated_data_e_act_T_326, _activated_data_e_act_T_329, _activated_data_e_act_T_350) node activated_data_e_act_10 = mux(_activated_data_e_act_T_321, _activated_data_e_act_T_323, _activated_data_e_act_T_351) node _activated_data_e_scaled_T_110 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_111 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_112 = and(_activated_data_e_scaled_T_110, _activated_data_e_scaled_T_111) node _activated_data_e_scaled_T_113 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_114 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_115 = and(_activated_data_e_scaled_T_113, _activated_data_e_scaled_T_114) wire _activated_data_e_scaled_WIRE_50 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_51 : UInt<32> connect _activated_data_e_scaled_WIRE_51, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_116 = bits(_activated_data_e_scaled_WIRE_51, 31, 0) connect _activated_data_e_scaled_WIRE_50.bits, _activated_data_e_scaled_T_116 node _activated_data_e_scaled_T_117 = mux(_activated_data_e_scaled_T_115, _activated_data_e_scaled_WIRE_50, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_118 = mux(_activated_data_e_scaled_T_112, io.in.bits.inv_stddev, _activated_data_e_scaled_T_117) wire _activated_data_e_scaled_WIRE_52 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_53 : UInt<32> connect _activated_data_e_scaled_WIRE_53, _activated_data_e_scaled_T_118.bits node _activated_data_e_scaled_T_119 = bits(_activated_data_e_scaled_WIRE_53, 31, 0) connect _activated_data_e_scaled_WIRE_52.bits, _activated_data_e_scaled_T_119 node activated_data_e_scaled_f_rec_rawIn_sign_10 = bits(_activated_data_e_scaled_WIRE_52.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_10 = bits(_activated_data_e_scaled_WIRE_52.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_10 = bits(_activated_data_e_scaled_WIRE_52.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_10, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_10, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_440 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_441 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_442 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_443 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_444 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_445 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_446 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_447 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_448 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_449 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_450 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_451 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_452 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_453 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_454 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_455 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_456 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_457 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_458 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_459 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_460 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_461 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_462 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_10, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_463 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_441, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_464 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_442, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_463) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_465 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_443, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_464) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_466 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_444, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_465) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_467 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_445, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_466) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_468 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_446, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_467) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_469 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_447, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_468) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_470 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_448, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_469) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_471 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_449, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_470) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_472 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_450, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_471) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_473 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_451, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_472) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_474 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_452, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_473) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_475 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_453, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_474) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_476 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_454, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_475) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_477 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_455, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_476) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_478 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_456, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_477) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_479 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_457, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_478) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_480 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_458, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_479) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_481 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_459, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_480) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_482 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_460, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_481) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_483 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_461, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_482) node activated_data_e_scaled_f_rec_rawIn_normDist_10 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_462, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_483) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_20 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_10, activated_data_e_scaled_f_rec_rawIn_normDist_10) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_21 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_20, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_10 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_21, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_50 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_10, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_51 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_50, activated_data_e_scaled_f_rec_rawIn_expIn_10) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_52 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_53 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_52) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_54 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_51, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_53) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_10 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_54, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_10 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_10 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_10, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_10 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_10, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_10 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_20 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_21 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_10, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_20) connect activated_data_e_scaled_f_rec_rawIn_10.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_21 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_10 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_10, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10) connect activated_data_e_scaled_f_rec_rawIn_10.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_10 connect activated_data_e_scaled_f_rec_rawIn_10.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_10 connect activated_data_e_scaled_f_rec_rawIn_10.sign, activated_data_e_scaled_f_rec_rawIn_sign_10 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_20 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_10, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_21 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_20) connect activated_data_e_scaled_f_rec_rawIn_10.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_21 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_40 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_10, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_41 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_40) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_42 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10, activated_data_e_scaled_f_rec_rawIn_subnormFract_10, activated_data_e_scaled_f_rec_rawIn_fractIn_10) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_43 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_41, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_42) connect activated_data_e_scaled_f_rec_rawIn_10.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_43 node _activated_data_e_scaled_f_rec_T_80 = bits(activated_data_e_scaled_f_rec_rawIn_10.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_81 = mux(activated_data_e_scaled_f_rec_rawIn_10.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_80) node _activated_data_e_scaled_f_rec_T_82 = mux(activated_data_e_scaled_f_rec_rawIn_10.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_83 = or(_activated_data_e_scaled_f_rec_T_81, _activated_data_e_scaled_f_rec_T_82) node _activated_data_e_scaled_f_rec_T_84 = cat(activated_data_e_scaled_f_rec_rawIn_10.sign, _activated_data_e_scaled_f_rec_T_83) node _activated_data_e_scaled_f_rec_T_85 = bits(activated_data_e_scaled_f_rec_rawIn_10.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_86 = cat(_activated_data_e_scaled_f_rec_T_84, _activated_data_e_scaled_f_rec_T_85) node _activated_data_e_scaled_f_rec_T_87 = bits(activated_data_e_scaled_f_rec_rawIn_10.sig, 22, 0) node activated_data_e_scaled_f_rec_10 = cat(_activated_data_e_scaled_f_rec_T_86, _activated_data_e_scaled_f_rec_T_87) inst activated_data_e_scaled_in_to_rec_fn_10 of INToRecFN_i32_e8_s24_10 connect activated_data_e_scaled_in_to_rec_fn_10.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_10 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_10 = asUInt(activated_data_e_act_10) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_10, _activated_data_e_scaled_in_to_rec_fn_io_in_T_10 connect activated_data_e_scaled_in_to_rec_fn_10.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_10 connect activated_data_e_scaled_in_to_rec_fn_10.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_10.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_10 of MulAddRecFN_e8_s24_14 connect activated_data_e_scaled_muladder_10.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_10.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_10.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_10.io.a, activated_data_e_scaled_in_to_rec_fn_10.io.out connect activated_data_e_scaled_muladder_10.io.b, activated_data_e_scaled_f_rec_10 connect activated_data_e_scaled_muladder_10.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_10 of RecFNToIN_e8_s24_i32_10 connect activated_data_e_scaled_rec_fn_to_in_10.clock, clock connect activated_data_e_scaled_rec_fn_to_in_10.reset, reset connect activated_data_e_scaled_rec_fn_to_in_10.io.in, activated_data_e_scaled_muladder_10.io.out connect activated_data_e_scaled_rec_fn_to_in_10.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_10.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_10 = bits(activated_data_e_scaled_rec_fn_to_in_10.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_10 = bits(activated_data_e_scaled_rec_fn_to_in_10.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_10 = bits(activated_data_e_scaled_sign_exp_10, 8, 6) node activated_data_e_scaled_sign_isZero_10 = eq(_activated_data_e_scaled_sign_isZero_T_10, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_10 = bits(activated_data_e_scaled_sign_exp_10, 8, 7) node activated_data_e_scaled_sign_isSpecial_10 = eq(_activated_data_e_scaled_sign_isSpecial_T_10, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_10 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_20 = bits(activated_data_e_scaled_sign_exp_10, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_21 = and(activated_data_e_scaled_sign_isSpecial_10, _activated_data_e_scaled_sign_out_isNaN_T_20) connect activated_data_e_scaled_sign_out_10.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_21 node _activated_data_e_scaled_sign_out_isInf_T_30 = bits(activated_data_e_scaled_sign_exp_10, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_31 = eq(_activated_data_e_scaled_sign_out_isInf_T_30, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_32 = and(activated_data_e_scaled_sign_isSpecial_10, _activated_data_e_scaled_sign_out_isInf_T_31) connect activated_data_e_scaled_sign_out_10.isInf, _activated_data_e_scaled_sign_out_isInf_T_32 connect activated_data_e_scaled_sign_out_10.isZero, activated_data_e_scaled_sign_isZero_10 node _activated_data_e_scaled_sign_out_sign_T_10 = bits(activated_data_e_scaled_rec_fn_to_in_10.io.in, 32, 32) connect activated_data_e_scaled_sign_out_10.sign, _activated_data_e_scaled_sign_out_sign_T_10 node _activated_data_e_scaled_sign_out_sExp_T_10 = cvt(activated_data_e_scaled_sign_exp_10) connect activated_data_e_scaled_sign_out_10.sExp, _activated_data_e_scaled_sign_out_sExp_T_10 node _activated_data_e_scaled_sign_out_sig_T_40 = eq(activated_data_e_scaled_sign_isZero_10, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_41 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_40) node _activated_data_e_scaled_sign_out_sig_T_42 = bits(activated_data_e_scaled_rec_fn_to_in_10.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_43 = cat(_activated_data_e_scaled_sign_out_sig_T_41, _activated_data_e_scaled_sign_out_sig_T_42) connect activated_data_e_scaled_sign_out_10.sig, _activated_data_e_scaled_sign_out_sig_T_43 node activated_data_e_scaled_sat_10 = mux(activated_data_e_scaled_sign_out_10.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_54 : SInt<32> node _activated_data_e_scaled_T_120 = asSInt(activated_data_e_scaled_rec_fn_to_in_10.io.out) connect _activated_data_e_scaled_WIRE_54, _activated_data_e_scaled_T_120 node activated_data_e_scaled_10 = mux(activated_data_e_scaled_overflow_10, activated_data_e_scaled_sat_10, _activated_data_e_scaled_WIRE_54) node _activated_data_e_clipped_T_50 = gt(activated_data_e_scaled_10, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_51 = lt(activated_data_e_scaled_10, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_52 = mux(_activated_data_e_clipped_T_51, asSInt(UInt<8>(0h80)), activated_data_e_scaled_10) node _activated_data_e_clipped_T_53 = mux(_activated_data_e_clipped_T_50, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_52) node _activated_data_e_clipped_T_54 = bits(_activated_data_e_clipped_T_53, 7, 0) node activated_data_e_clipped_10 = asSInt(_activated_data_e_clipped_T_54) wire _activated_data_WIRE_10 : SInt<8>[1] connect _activated_data_WIRE_10[0], activated_data_e_clipped_10 node _activated_data_e_act_T_352 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_353 = and(UInt<1>(0h1), _activated_data_e_act_T_352) node _activated_data_e_act_T_354 = geq(io.in.bits.acc_read_resp.data[11][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_355 = mux(_activated_data_e_act_T_354, io.in.bits.acc_read_resp.data[11][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_356 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_357 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_358 = and(_activated_data_e_act_T_356, _activated_data_e_act_T_357) node _activated_data_e_act_T_359 = sub(io.in.bits.acc_read_resp.data[11][0], io.in.bits.mean) node _activated_data_e_act_T_360 = tail(_activated_data_e_act_T_359, 1) node _activated_data_e_act_T_361 = asSInt(_activated_data_e_act_T_360) node _activated_data_e_act_T_362 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_363 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_364 = and(_activated_data_e_act_T_362, _activated_data_e_act_T_363) node _activated_data_e_act_q_sign_T_44 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[11][0]) node _activated_data_e_act_q_sign_T_45 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_46 = tail(_activated_data_e_act_q_sign_T_45, 1) node _activated_data_e_act_q_sign_T_47 = asSInt(_activated_data_e_act_q_sign_T_46) node activated_data_e_act_q_sign_11 = mux(_activated_data_e_act_q_sign_T_44, _activated_data_e_act_q_sign_T_47, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_44 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[11][0]) node _activated_data_e_act_q_abs_T_45 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[11][0]) node _activated_data_e_act_q_abs_T_46 = tail(_activated_data_e_act_q_abs_T_45, 1) node _activated_data_e_act_q_abs_T_47 = asSInt(_activated_data_e_act_q_abs_T_46) node activated_data_e_act_q_abs_11 = mux(_activated_data_e_act_q_abs_T_44, _activated_data_e_act_q_abs_T_47, io.in.bits.acc_read_resp.data[11][0]) node _activated_data_e_act_q_clipped_T_77 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_78 = tail(_activated_data_e_act_q_clipped_T_77, 1) node _activated_data_e_act_q_clipped_T_79 = asSInt(_activated_data_e_act_q_clipped_T_78) node _activated_data_e_act_q_clipped_T_80 = gt(activated_data_e_act_q_abs_11, _activated_data_e_act_q_clipped_T_79) node _activated_data_e_act_q_clipped_T_81 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_82 = tail(_activated_data_e_act_q_clipped_T_81, 1) node _activated_data_e_act_q_clipped_T_83 = asSInt(_activated_data_e_act_q_clipped_T_82) node activated_data_e_act_q_clipped_11 = mux(_activated_data_e_act_q_clipped_T_80, _activated_data_e_act_q_clipped_T_83, activated_data_e_act_q_abs_11) node _activated_data_e_act_q_poly_T_121 = add(activated_data_e_act_q_clipped_11, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_122 = tail(_activated_data_e_act_q_poly_T_121, 1) node _activated_data_e_act_q_poly_T_123 = asSInt(_activated_data_e_act_q_poly_T_122) node _activated_data_e_act_q_poly_T_124 = add(activated_data_e_act_q_clipped_11, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_125 = tail(_activated_data_e_act_q_poly_T_124, 1) node _activated_data_e_act_q_poly_T_126 = asSInt(_activated_data_e_act_q_poly_T_125) node _activated_data_e_act_q_poly_T_127 = mul(_activated_data_e_act_q_poly_T_123, _activated_data_e_act_q_poly_T_126) node _activated_data_e_act_q_poly_T_128 = add(_activated_data_e_act_q_poly_T_127, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_129 = tail(_activated_data_e_act_q_poly_T_128, 1) node _activated_data_e_act_q_poly_T_130 = asSInt(_activated_data_e_act_q_poly_T_129) node _activated_data_e_act_q_poly_T_131 = bits(_activated_data_e_act_q_poly_T_130, 31, 0) node activated_data_e_act_q_poly_11 = asSInt(_activated_data_e_act_q_poly_T_131) node _activated_data_e_act_q_erf_T_22 = mul(activated_data_e_act_q_sign_11, activated_data_e_act_q_poly_11) node _activated_data_e_act_q_erf_T_23 = bits(_activated_data_e_act_q_erf_T_22, 31, 0) node activated_data_e_act_q_erf_11 = asSInt(_activated_data_e_act_q_erf_T_23) node _activated_data_e_act_T_365 = add(activated_data_e_act_q_erf_11, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_366 = tail(_activated_data_e_act_T_365, 1) node _activated_data_e_act_T_367 = asSInt(_activated_data_e_act_T_366) node _activated_data_e_act_T_368 = mul(io.in.bits.acc_read_resp.data[11][0], _activated_data_e_act_T_367) node _activated_data_e_act_T_369 = bits(_activated_data_e_act_T_368, 31, 0) node _activated_data_e_act_T_370 = asSInt(_activated_data_e_act_T_369) node _activated_data_e_act_T_371 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_372 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_373 = and(_activated_data_e_act_T_371, _activated_data_e_act_T_372) node _activated_data_e_act_T_374 = sub(io.in.bits.acc_read_resp.data[11][0], io.in.bits.max) node _activated_data_e_act_T_375 = tail(_activated_data_e_act_T_374, 1) node _activated_data_e_act_T_376 = asSInt(_activated_data_e_act_T_375) node _activated_data_e_act_neg_q_iexp_T_22 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_376) node _activated_data_e_act_neg_q_iexp_T_23 = tail(_activated_data_e_act_neg_q_iexp_T_22, 1) node activated_data_e_act_neg_q_iexp_11 = asSInt(_activated_data_e_act_neg_q_iexp_T_23) node _activated_data_e_act_z_iexp_T_44 = mul(activated_data_e_act_neg_q_iexp_11, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_45 = asUInt(_activated_data_e_act_z_iexp_T_44) node _activated_data_e_act_z_iexp_T_46 = shr(_activated_data_e_act_z_iexp_T_45, 16) wire activated_data_e_act_z_iexp_11 : SInt<32> node _activated_data_e_act_z_iexp_T_47 = asSInt(_activated_data_e_act_z_iexp_T_46) connect activated_data_e_act_z_iexp_11, _activated_data_e_act_z_iexp_T_47 wire activated_data_e_act_z_iexp_saturated_11 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_363 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_364 = bits(_activated_data_e_act_z_iexp_saturated_T_363, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_365 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_366 = bits(_activated_data_e_act_z_iexp_saturated_T_365, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_367 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_368 = bits(_activated_data_e_act_z_iexp_saturated_T_367, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_369 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_370 = bits(_activated_data_e_act_z_iexp_saturated_T_369, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_371 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_372 = bits(_activated_data_e_act_z_iexp_saturated_T_371, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_373 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_374 = bits(_activated_data_e_act_z_iexp_saturated_T_373, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_375 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_376 = bits(_activated_data_e_act_z_iexp_saturated_T_375, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_377 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_378 = bits(_activated_data_e_act_z_iexp_saturated_T_377, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_379 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_380 = bits(_activated_data_e_act_z_iexp_saturated_T_379, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_381 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_382 = bits(_activated_data_e_act_z_iexp_saturated_T_381, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_383 = asUInt(activated_data_e_act_z_iexp_11) node _activated_data_e_act_z_iexp_saturated_T_384 = bits(_activated_data_e_act_z_iexp_saturated_T_383, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_385 = or(_activated_data_e_act_z_iexp_saturated_T_364, _activated_data_e_act_z_iexp_saturated_T_366) node _activated_data_e_act_z_iexp_saturated_T_386 = or(_activated_data_e_act_z_iexp_saturated_T_385, _activated_data_e_act_z_iexp_saturated_T_368) node _activated_data_e_act_z_iexp_saturated_T_387 = or(_activated_data_e_act_z_iexp_saturated_T_386, _activated_data_e_act_z_iexp_saturated_T_370) node _activated_data_e_act_z_iexp_saturated_T_388 = or(_activated_data_e_act_z_iexp_saturated_T_387, _activated_data_e_act_z_iexp_saturated_T_372) node _activated_data_e_act_z_iexp_saturated_T_389 = or(_activated_data_e_act_z_iexp_saturated_T_388, _activated_data_e_act_z_iexp_saturated_T_374) node _activated_data_e_act_z_iexp_saturated_T_390 = or(_activated_data_e_act_z_iexp_saturated_T_389, _activated_data_e_act_z_iexp_saturated_T_376) node _activated_data_e_act_z_iexp_saturated_T_391 = or(_activated_data_e_act_z_iexp_saturated_T_390, _activated_data_e_act_z_iexp_saturated_T_378) node _activated_data_e_act_z_iexp_saturated_T_392 = or(_activated_data_e_act_z_iexp_saturated_T_391, _activated_data_e_act_z_iexp_saturated_T_380) node _activated_data_e_act_z_iexp_saturated_T_393 = or(_activated_data_e_act_z_iexp_saturated_T_392, _activated_data_e_act_z_iexp_saturated_T_382) node _activated_data_e_act_z_iexp_saturated_T_394 = or(_activated_data_e_act_z_iexp_saturated_T_393, _activated_data_e_act_z_iexp_saturated_T_384) wire _activated_data_e_act_z_iexp_saturated_WIRE_11 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_11, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_395 = mux(_activated_data_e_act_z_iexp_saturated_T_394, _activated_data_e_act_z_iexp_saturated_WIRE_11, activated_data_e_act_z_iexp_11) connect activated_data_e_act_z_iexp_saturated_11, _activated_data_e_act_z_iexp_saturated_T_395 node _activated_data_e_act_qp_iexp_T_55 = mul(activated_data_e_act_z_iexp_11, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_56 = add(_activated_data_e_act_qp_iexp_T_55, _activated_data_e_act_T_376) node _activated_data_e_act_qp_iexp_T_57 = tail(_activated_data_e_act_qp_iexp_T_56, 1) node _activated_data_e_act_qp_iexp_T_58 = asSInt(_activated_data_e_act_qp_iexp_T_57) node _activated_data_e_act_qp_iexp_T_59 = bits(_activated_data_e_act_qp_iexp_T_58, 31, 0) node activated_data_e_act_qp_iexp_11 = asSInt(_activated_data_e_act_qp_iexp_T_59) node _activated_data_e_act_q_poly_iexp_T_121 = add(activated_data_e_act_qp_iexp_11, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_122 = tail(_activated_data_e_act_q_poly_iexp_T_121, 1) node _activated_data_e_act_q_poly_iexp_T_123 = asSInt(_activated_data_e_act_q_poly_iexp_T_122) node _activated_data_e_act_q_poly_iexp_T_124 = add(activated_data_e_act_qp_iexp_11, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_125 = tail(_activated_data_e_act_q_poly_iexp_T_124, 1) node _activated_data_e_act_q_poly_iexp_T_126 = asSInt(_activated_data_e_act_q_poly_iexp_T_125) node _activated_data_e_act_q_poly_iexp_T_127 = mul(_activated_data_e_act_q_poly_iexp_T_123, _activated_data_e_act_q_poly_iexp_T_126) node _activated_data_e_act_q_poly_iexp_T_128 = add(_activated_data_e_act_q_poly_iexp_T_127, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_129 = tail(_activated_data_e_act_q_poly_iexp_T_128, 1) node _activated_data_e_act_q_poly_iexp_T_130 = asSInt(_activated_data_e_act_q_poly_iexp_T_129) node _activated_data_e_act_q_poly_iexp_T_131 = bits(_activated_data_e_act_q_poly_iexp_T_130, 31, 0) node activated_data_e_act_q_poly_iexp_11 = asSInt(_activated_data_e_act_q_poly_iexp_T_131) node _activated_data_e_act_T_377 = asUInt(activated_data_e_act_q_poly_iexp_11) node _activated_data_e_act_T_378 = asUInt(activated_data_e_act_z_iexp_saturated_11) node _activated_data_e_act_T_379 = dshr(_activated_data_e_act_T_377, _activated_data_e_act_T_378) wire _activated_data_e_act_WIRE_11 : SInt<32> node _activated_data_e_act_T_380 = asSInt(_activated_data_e_act_T_379) connect _activated_data_e_act_WIRE_11, _activated_data_e_act_T_380 node _activated_data_e_act_T_381 = mux(_activated_data_e_act_T_373, _activated_data_e_act_WIRE_11, io.in.bits.acc_read_resp.data[11][0]) node _activated_data_e_act_T_382 = mux(_activated_data_e_act_T_364, _activated_data_e_act_T_370, _activated_data_e_act_T_381) node _activated_data_e_act_T_383 = mux(_activated_data_e_act_T_358, _activated_data_e_act_T_361, _activated_data_e_act_T_382) node activated_data_e_act_11 = mux(_activated_data_e_act_T_353, _activated_data_e_act_T_355, _activated_data_e_act_T_383) node _activated_data_e_scaled_T_121 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_122 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_123 = and(_activated_data_e_scaled_T_121, _activated_data_e_scaled_T_122) node _activated_data_e_scaled_T_124 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_125 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_126 = and(_activated_data_e_scaled_T_124, _activated_data_e_scaled_T_125) wire _activated_data_e_scaled_WIRE_55 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_56 : UInt<32> connect _activated_data_e_scaled_WIRE_56, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_127 = bits(_activated_data_e_scaled_WIRE_56, 31, 0) connect _activated_data_e_scaled_WIRE_55.bits, _activated_data_e_scaled_T_127 node _activated_data_e_scaled_T_128 = mux(_activated_data_e_scaled_T_126, _activated_data_e_scaled_WIRE_55, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_129 = mux(_activated_data_e_scaled_T_123, io.in.bits.inv_stddev, _activated_data_e_scaled_T_128) wire _activated_data_e_scaled_WIRE_57 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_58 : UInt<32> connect _activated_data_e_scaled_WIRE_58, _activated_data_e_scaled_T_129.bits node _activated_data_e_scaled_T_130 = bits(_activated_data_e_scaled_WIRE_58, 31, 0) connect _activated_data_e_scaled_WIRE_57.bits, _activated_data_e_scaled_T_130 node activated_data_e_scaled_f_rec_rawIn_sign_11 = bits(_activated_data_e_scaled_WIRE_57.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_11 = bits(_activated_data_e_scaled_WIRE_57.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_11 = bits(_activated_data_e_scaled_WIRE_57.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_11, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_11, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_484 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_485 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_486 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_487 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_488 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_489 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_490 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_491 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_492 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_493 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_494 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_495 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_496 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_497 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_498 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_499 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_500 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_501 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_502 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_503 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_504 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_505 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_506 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_11, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_507 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_485, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_508 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_486, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_507) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_509 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_487, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_508) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_510 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_488, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_509) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_511 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_489, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_510) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_512 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_490, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_511) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_513 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_491, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_512) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_514 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_492, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_513) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_515 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_493, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_514) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_516 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_494, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_515) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_517 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_495, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_516) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_518 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_496, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_517) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_519 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_497, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_518) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_520 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_498, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_519) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_521 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_499, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_520) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_522 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_500, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_521) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_523 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_501, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_522) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_524 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_502, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_523) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_525 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_503, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_524) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_526 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_504, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_525) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_527 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_505, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_526) node activated_data_e_scaled_f_rec_rawIn_normDist_11 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_506, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_527) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_22 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_11, activated_data_e_scaled_f_rec_rawIn_normDist_11) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_23 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_22, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_11 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_23, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_55 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_11, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_56 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_55, activated_data_e_scaled_f_rec_rawIn_expIn_11) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_57 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_58 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_57) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_59 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_56, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_58) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_11 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_59, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_11 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_11 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_11, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_11 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_11, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_11 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_22 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_23 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_11, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_22) connect activated_data_e_scaled_f_rec_rawIn_11.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_23 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_11 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_11, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11) connect activated_data_e_scaled_f_rec_rawIn_11.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_11 connect activated_data_e_scaled_f_rec_rawIn_11.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_11 connect activated_data_e_scaled_f_rec_rawIn_11.sign, activated_data_e_scaled_f_rec_rawIn_sign_11 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_22 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_11, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_23 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_22) connect activated_data_e_scaled_f_rec_rawIn_11.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_23 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_44 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_11, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_45 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_44) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_46 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11, activated_data_e_scaled_f_rec_rawIn_subnormFract_11, activated_data_e_scaled_f_rec_rawIn_fractIn_11) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_47 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_45, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_46) connect activated_data_e_scaled_f_rec_rawIn_11.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_47 node _activated_data_e_scaled_f_rec_T_88 = bits(activated_data_e_scaled_f_rec_rawIn_11.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_89 = mux(activated_data_e_scaled_f_rec_rawIn_11.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_88) node _activated_data_e_scaled_f_rec_T_90 = mux(activated_data_e_scaled_f_rec_rawIn_11.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_91 = or(_activated_data_e_scaled_f_rec_T_89, _activated_data_e_scaled_f_rec_T_90) node _activated_data_e_scaled_f_rec_T_92 = cat(activated_data_e_scaled_f_rec_rawIn_11.sign, _activated_data_e_scaled_f_rec_T_91) node _activated_data_e_scaled_f_rec_T_93 = bits(activated_data_e_scaled_f_rec_rawIn_11.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_94 = cat(_activated_data_e_scaled_f_rec_T_92, _activated_data_e_scaled_f_rec_T_93) node _activated_data_e_scaled_f_rec_T_95 = bits(activated_data_e_scaled_f_rec_rawIn_11.sig, 22, 0) node activated_data_e_scaled_f_rec_11 = cat(_activated_data_e_scaled_f_rec_T_94, _activated_data_e_scaled_f_rec_T_95) inst activated_data_e_scaled_in_to_rec_fn_11 of INToRecFN_i32_e8_s24_11 connect activated_data_e_scaled_in_to_rec_fn_11.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_11 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_11 = asUInt(activated_data_e_act_11) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_11, _activated_data_e_scaled_in_to_rec_fn_io_in_T_11 connect activated_data_e_scaled_in_to_rec_fn_11.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_11 connect activated_data_e_scaled_in_to_rec_fn_11.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_11.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_11 of MulAddRecFN_e8_s24_15 connect activated_data_e_scaled_muladder_11.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_11.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_11.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_11.io.a, activated_data_e_scaled_in_to_rec_fn_11.io.out connect activated_data_e_scaled_muladder_11.io.b, activated_data_e_scaled_f_rec_11 connect activated_data_e_scaled_muladder_11.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_11 of RecFNToIN_e8_s24_i32_11 connect activated_data_e_scaled_rec_fn_to_in_11.clock, clock connect activated_data_e_scaled_rec_fn_to_in_11.reset, reset connect activated_data_e_scaled_rec_fn_to_in_11.io.in, activated_data_e_scaled_muladder_11.io.out connect activated_data_e_scaled_rec_fn_to_in_11.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_11.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_11 = bits(activated_data_e_scaled_rec_fn_to_in_11.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_11 = bits(activated_data_e_scaled_rec_fn_to_in_11.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_11 = bits(activated_data_e_scaled_sign_exp_11, 8, 6) node activated_data_e_scaled_sign_isZero_11 = eq(_activated_data_e_scaled_sign_isZero_T_11, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_11 = bits(activated_data_e_scaled_sign_exp_11, 8, 7) node activated_data_e_scaled_sign_isSpecial_11 = eq(_activated_data_e_scaled_sign_isSpecial_T_11, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_11 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_22 = bits(activated_data_e_scaled_sign_exp_11, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_23 = and(activated_data_e_scaled_sign_isSpecial_11, _activated_data_e_scaled_sign_out_isNaN_T_22) connect activated_data_e_scaled_sign_out_11.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_23 node _activated_data_e_scaled_sign_out_isInf_T_33 = bits(activated_data_e_scaled_sign_exp_11, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_34 = eq(_activated_data_e_scaled_sign_out_isInf_T_33, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_35 = and(activated_data_e_scaled_sign_isSpecial_11, _activated_data_e_scaled_sign_out_isInf_T_34) connect activated_data_e_scaled_sign_out_11.isInf, _activated_data_e_scaled_sign_out_isInf_T_35 connect activated_data_e_scaled_sign_out_11.isZero, activated_data_e_scaled_sign_isZero_11 node _activated_data_e_scaled_sign_out_sign_T_11 = bits(activated_data_e_scaled_rec_fn_to_in_11.io.in, 32, 32) connect activated_data_e_scaled_sign_out_11.sign, _activated_data_e_scaled_sign_out_sign_T_11 node _activated_data_e_scaled_sign_out_sExp_T_11 = cvt(activated_data_e_scaled_sign_exp_11) connect activated_data_e_scaled_sign_out_11.sExp, _activated_data_e_scaled_sign_out_sExp_T_11 node _activated_data_e_scaled_sign_out_sig_T_44 = eq(activated_data_e_scaled_sign_isZero_11, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_45 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_44) node _activated_data_e_scaled_sign_out_sig_T_46 = bits(activated_data_e_scaled_rec_fn_to_in_11.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_47 = cat(_activated_data_e_scaled_sign_out_sig_T_45, _activated_data_e_scaled_sign_out_sig_T_46) connect activated_data_e_scaled_sign_out_11.sig, _activated_data_e_scaled_sign_out_sig_T_47 node activated_data_e_scaled_sat_11 = mux(activated_data_e_scaled_sign_out_11.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_59 : SInt<32> node _activated_data_e_scaled_T_131 = asSInt(activated_data_e_scaled_rec_fn_to_in_11.io.out) connect _activated_data_e_scaled_WIRE_59, _activated_data_e_scaled_T_131 node activated_data_e_scaled_11 = mux(activated_data_e_scaled_overflow_11, activated_data_e_scaled_sat_11, _activated_data_e_scaled_WIRE_59) node _activated_data_e_clipped_T_55 = gt(activated_data_e_scaled_11, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_56 = lt(activated_data_e_scaled_11, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_57 = mux(_activated_data_e_clipped_T_56, asSInt(UInt<8>(0h80)), activated_data_e_scaled_11) node _activated_data_e_clipped_T_58 = mux(_activated_data_e_clipped_T_55, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_57) node _activated_data_e_clipped_T_59 = bits(_activated_data_e_clipped_T_58, 7, 0) node activated_data_e_clipped_11 = asSInt(_activated_data_e_clipped_T_59) wire _activated_data_WIRE_11 : SInt<8>[1] connect _activated_data_WIRE_11[0], activated_data_e_clipped_11 node _activated_data_e_act_T_384 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_385 = and(UInt<1>(0h1), _activated_data_e_act_T_384) node _activated_data_e_act_T_386 = geq(io.in.bits.acc_read_resp.data[12][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_387 = mux(_activated_data_e_act_T_386, io.in.bits.acc_read_resp.data[12][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_388 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_389 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_390 = and(_activated_data_e_act_T_388, _activated_data_e_act_T_389) node _activated_data_e_act_T_391 = sub(io.in.bits.acc_read_resp.data[12][0], io.in.bits.mean) node _activated_data_e_act_T_392 = tail(_activated_data_e_act_T_391, 1) node _activated_data_e_act_T_393 = asSInt(_activated_data_e_act_T_392) node _activated_data_e_act_T_394 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_395 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_396 = and(_activated_data_e_act_T_394, _activated_data_e_act_T_395) node _activated_data_e_act_q_sign_T_48 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[12][0]) node _activated_data_e_act_q_sign_T_49 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_50 = tail(_activated_data_e_act_q_sign_T_49, 1) node _activated_data_e_act_q_sign_T_51 = asSInt(_activated_data_e_act_q_sign_T_50) node activated_data_e_act_q_sign_12 = mux(_activated_data_e_act_q_sign_T_48, _activated_data_e_act_q_sign_T_51, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_48 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[12][0]) node _activated_data_e_act_q_abs_T_49 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[12][0]) node _activated_data_e_act_q_abs_T_50 = tail(_activated_data_e_act_q_abs_T_49, 1) node _activated_data_e_act_q_abs_T_51 = asSInt(_activated_data_e_act_q_abs_T_50) node activated_data_e_act_q_abs_12 = mux(_activated_data_e_act_q_abs_T_48, _activated_data_e_act_q_abs_T_51, io.in.bits.acc_read_resp.data[12][0]) node _activated_data_e_act_q_clipped_T_84 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_85 = tail(_activated_data_e_act_q_clipped_T_84, 1) node _activated_data_e_act_q_clipped_T_86 = asSInt(_activated_data_e_act_q_clipped_T_85) node _activated_data_e_act_q_clipped_T_87 = gt(activated_data_e_act_q_abs_12, _activated_data_e_act_q_clipped_T_86) node _activated_data_e_act_q_clipped_T_88 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_89 = tail(_activated_data_e_act_q_clipped_T_88, 1) node _activated_data_e_act_q_clipped_T_90 = asSInt(_activated_data_e_act_q_clipped_T_89) node activated_data_e_act_q_clipped_12 = mux(_activated_data_e_act_q_clipped_T_87, _activated_data_e_act_q_clipped_T_90, activated_data_e_act_q_abs_12) node _activated_data_e_act_q_poly_T_132 = add(activated_data_e_act_q_clipped_12, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_133 = tail(_activated_data_e_act_q_poly_T_132, 1) node _activated_data_e_act_q_poly_T_134 = asSInt(_activated_data_e_act_q_poly_T_133) node _activated_data_e_act_q_poly_T_135 = add(activated_data_e_act_q_clipped_12, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_136 = tail(_activated_data_e_act_q_poly_T_135, 1) node _activated_data_e_act_q_poly_T_137 = asSInt(_activated_data_e_act_q_poly_T_136) node _activated_data_e_act_q_poly_T_138 = mul(_activated_data_e_act_q_poly_T_134, _activated_data_e_act_q_poly_T_137) node _activated_data_e_act_q_poly_T_139 = add(_activated_data_e_act_q_poly_T_138, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_140 = tail(_activated_data_e_act_q_poly_T_139, 1) node _activated_data_e_act_q_poly_T_141 = asSInt(_activated_data_e_act_q_poly_T_140) node _activated_data_e_act_q_poly_T_142 = bits(_activated_data_e_act_q_poly_T_141, 31, 0) node activated_data_e_act_q_poly_12 = asSInt(_activated_data_e_act_q_poly_T_142) node _activated_data_e_act_q_erf_T_24 = mul(activated_data_e_act_q_sign_12, activated_data_e_act_q_poly_12) node _activated_data_e_act_q_erf_T_25 = bits(_activated_data_e_act_q_erf_T_24, 31, 0) node activated_data_e_act_q_erf_12 = asSInt(_activated_data_e_act_q_erf_T_25) node _activated_data_e_act_T_397 = add(activated_data_e_act_q_erf_12, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_398 = tail(_activated_data_e_act_T_397, 1) node _activated_data_e_act_T_399 = asSInt(_activated_data_e_act_T_398) node _activated_data_e_act_T_400 = mul(io.in.bits.acc_read_resp.data[12][0], _activated_data_e_act_T_399) node _activated_data_e_act_T_401 = bits(_activated_data_e_act_T_400, 31, 0) node _activated_data_e_act_T_402 = asSInt(_activated_data_e_act_T_401) node _activated_data_e_act_T_403 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_404 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_405 = and(_activated_data_e_act_T_403, _activated_data_e_act_T_404) node _activated_data_e_act_T_406 = sub(io.in.bits.acc_read_resp.data[12][0], io.in.bits.max) node _activated_data_e_act_T_407 = tail(_activated_data_e_act_T_406, 1) node _activated_data_e_act_T_408 = asSInt(_activated_data_e_act_T_407) node _activated_data_e_act_neg_q_iexp_T_24 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_408) node _activated_data_e_act_neg_q_iexp_T_25 = tail(_activated_data_e_act_neg_q_iexp_T_24, 1) node activated_data_e_act_neg_q_iexp_12 = asSInt(_activated_data_e_act_neg_q_iexp_T_25) node _activated_data_e_act_z_iexp_T_48 = mul(activated_data_e_act_neg_q_iexp_12, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_49 = asUInt(_activated_data_e_act_z_iexp_T_48) node _activated_data_e_act_z_iexp_T_50 = shr(_activated_data_e_act_z_iexp_T_49, 16) wire activated_data_e_act_z_iexp_12 : SInt<32> node _activated_data_e_act_z_iexp_T_51 = asSInt(_activated_data_e_act_z_iexp_T_50) connect activated_data_e_act_z_iexp_12, _activated_data_e_act_z_iexp_T_51 wire activated_data_e_act_z_iexp_saturated_12 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_396 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_397 = bits(_activated_data_e_act_z_iexp_saturated_T_396, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_398 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_399 = bits(_activated_data_e_act_z_iexp_saturated_T_398, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_400 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_401 = bits(_activated_data_e_act_z_iexp_saturated_T_400, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_402 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_403 = bits(_activated_data_e_act_z_iexp_saturated_T_402, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_404 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_405 = bits(_activated_data_e_act_z_iexp_saturated_T_404, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_406 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_407 = bits(_activated_data_e_act_z_iexp_saturated_T_406, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_408 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_409 = bits(_activated_data_e_act_z_iexp_saturated_T_408, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_410 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_411 = bits(_activated_data_e_act_z_iexp_saturated_T_410, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_412 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_413 = bits(_activated_data_e_act_z_iexp_saturated_T_412, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_414 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_415 = bits(_activated_data_e_act_z_iexp_saturated_T_414, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_416 = asUInt(activated_data_e_act_z_iexp_12) node _activated_data_e_act_z_iexp_saturated_T_417 = bits(_activated_data_e_act_z_iexp_saturated_T_416, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_418 = or(_activated_data_e_act_z_iexp_saturated_T_397, _activated_data_e_act_z_iexp_saturated_T_399) node _activated_data_e_act_z_iexp_saturated_T_419 = or(_activated_data_e_act_z_iexp_saturated_T_418, _activated_data_e_act_z_iexp_saturated_T_401) node _activated_data_e_act_z_iexp_saturated_T_420 = or(_activated_data_e_act_z_iexp_saturated_T_419, _activated_data_e_act_z_iexp_saturated_T_403) node _activated_data_e_act_z_iexp_saturated_T_421 = or(_activated_data_e_act_z_iexp_saturated_T_420, _activated_data_e_act_z_iexp_saturated_T_405) node _activated_data_e_act_z_iexp_saturated_T_422 = or(_activated_data_e_act_z_iexp_saturated_T_421, _activated_data_e_act_z_iexp_saturated_T_407) node _activated_data_e_act_z_iexp_saturated_T_423 = or(_activated_data_e_act_z_iexp_saturated_T_422, _activated_data_e_act_z_iexp_saturated_T_409) node _activated_data_e_act_z_iexp_saturated_T_424 = or(_activated_data_e_act_z_iexp_saturated_T_423, _activated_data_e_act_z_iexp_saturated_T_411) node _activated_data_e_act_z_iexp_saturated_T_425 = or(_activated_data_e_act_z_iexp_saturated_T_424, _activated_data_e_act_z_iexp_saturated_T_413) node _activated_data_e_act_z_iexp_saturated_T_426 = or(_activated_data_e_act_z_iexp_saturated_T_425, _activated_data_e_act_z_iexp_saturated_T_415) node _activated_data_e_act_z_iexp_saturated_T_427 = or(_activated_data_e_act_z_iexp_saturated_T_426, _activated_data_e_act_z_iexp_saturated_T_417) wire _activated_data_e_act_z_iexp_saturated_WIRE_12 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_12, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_428 = mux(_activated_data_e_act_z_iexp_saturated_T_427, _activated_data_e_act_z_iexp_saturated_WIRE_12, activated_data_e_act_z_iexp_12) connect activated_data_e_act_z_iexp_saturated_12, _activated_data_e_act_z_iexp_saturated_T_428 node _activated_data_e_act_qp_iexp_T_60 = mul(activated_data_e_act_z_iexp_12, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_61 = add(_activated_data_e_act_qp_iexp_T_60, _activated_data_e_act_T_408) node _activated_data_e_act_qp_iexp_T_62 = tail(_activated_data_e_act_qp_iexp_T_61, 1) node _activated_data_e_act_qp_iexp_T_63 = asSInt(_activated_data_e_act_qp_iexp_T_62) node _activated_data_e_act_qp_iexp_T_64 = bits(_activated_data_e_act_qp_iexp_T_63, 31, 0) node activated_data_e_act_qp_iexp_12 = asSInt(_activated_data_e_act_qp_iexp_T_64) node _activated_data_e_act_q_poly_iexp_T_132 = add(activated_data_e_act_qp_iexp_12, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_133 = tail(_activated_data_e_act_q_poly_iexp_T_132, 1) node _activated_data_e_act_q_poly_iexp_T_134 = asSInt(_activated_data_e_act_q_poly_iexp_T_133) node _activated_data_e_act_q_poly_iexp_T_135 = add(activated_data_e_act_qp_iexp_12, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_136 = tail(_activated_data_e_act_q_poly_iexp_T_135, 1) node _activated_data_e_act_q_poly_iexp_T_137 = asSInt(_activated_data_e_act_q_poly_iexp_T_136) node _activated_data_e_act_q_poly_iexp_T_138 = mul(_activated_data_e_act_q_poly_iexp_T_134, _activated_data_e_act_q_poly_iexp_T_137) node _activated_data_e_act_q_poly_iexp_T_139 = add(_activated_data_e_act_q_poly_iexp_T_138, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_140 = tail(_activated_data_e_act_q_poly_iexp_T_139, 1) node _activated_data_e_act_q_poly_iexp_T_141 = asSInt(_activated_data_e_act_q_poly_iexp_T_140) node _activated_data_e_act_q_poly_iexp_T_142 = bits(_activated_data_e_act_q_poly_iexp_T_141, 31, 0) node activated_data_e_act_q_poly_iexp_12 = asSInt(_activated_data_e_act_q_poly_iexp_T_142) node _activated_data_e_act_T_409 = asUInt(activated_data_e_act_q_poly_iexp_12) node _activated_data_e_act_T_410 = asUInt(activated_data_e_act_z_iexp_saturated_12) node _activated_data_e_act_T_411 = dshr(_activated_data_e_act_T_409, _activated_data_e_act_T_410) wire _activated_data_e_act_WIRE_12 : SInt<32> node _activated_data_e_act_T_412 = asSInt(_activated_data_e_act_T_411) connect _activated_data_e_act_WIRE_12, _activated_data_e_act_T_412 node _activated_data_e_act_T_413 = mux(_activated_data_e_act_T_405, _activated_data_e_act_WIRE_12, io.in.bits.acc_read_resp.data[12][0]) node _activated_data_e_act_T_414 = mux(_activated_data_e_act_T_396, _activated_data_e_act_T_402, _activated_data_e_act_T_413) node _activated_data_e_act_T_415 = mux(_activated_data_e_act_T_390, _activated_data_e_act_T_393, _activated_data_e_act_T_414) node activated_data_e_act_12 = mux(_activated_data_e_act_T_385, _activated_data_e_act_T_387, _activated_data_e_act_T_415) node _activated_data_e_scaled_T_132 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_133 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_134 = and(_activated_data_e_scaled_T_132, _activated_data_e_scaled_T_133) node _activated_data_e_scaled_T_135 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_136 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_137 = and(_activated_data_e_scaled_T_135, _activated_data_e_scaled_T_136) wire _activated_data_e_scaled_WIRE_60 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_61 : UInt<32> connect _activated_data_e_scaled_WIRE_61, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_138 = bits(_activated_data_e_scaled_WIRE_61, 31, 0) connect _activated_data_e_scaled_WIRE_60.bits, _activated_data_e_scaled_T_138 node _activated_data_e_scaled_T_139 = mux(_activated_data_e_scaled_T_137, _activated_data_e_scaled_WIRE_60, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_140 = mux(_activated_data_e_scaled_T_134, io.in.bits.inv_stddev, _activated_data_e_scaled_T_139) wire _activated_data_e_scaled_WIRE_62 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_63 : UInt<32> connect _activated_data_e_scaled_WIRE_63, _activated_data_e_scaled_T_140.bits node _activated_data_e_scaled_T_141 = bits(_activated_data_e_scaled_WIRE_63, 31, 0) connect _activated_data_e_scaled_WIRE_62.bits, _activated_data_e_scaled_T_141 node activated_data_e_scaled_f_rec_rawIn_sign_12 = bits(_activated_data_e_scaled_WIRE_62.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_12 = bits(_activated_data_e_scaled_WIRE_62.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_12 = bits(_activated_data_e_scaled_WIRE_62.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_12, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_12, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_528 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_529 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_530 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_531 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_532 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_533 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_534 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_535 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_536 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_537 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_538 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_539 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_540 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_541 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_542 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_543 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_544 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_545 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_546 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_547 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_548 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_549 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_550 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_12, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_551 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_529, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_552 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_530, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_551) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_553 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_531, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_552) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_554 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_532, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_553) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_555 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_533, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_554) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_556 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_534, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_555) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_557 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_535, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_556) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_558 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_536, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_557) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_559 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_537, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_558) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_560 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_538, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_559) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_561 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_539, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_560) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_562 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_540, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_561) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_563 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_541, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_562) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_564 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_542, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_563) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_565 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_543, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_564) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_566 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_544, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_565) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_567 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_545, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_566) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_568 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_546, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_567) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_569 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_547, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_568) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_570 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_548, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_569) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_571 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_549, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_570) node activated_data_e_scaled_f_rec_rawIn_normDist_12 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_550, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_571) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_24 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_12, activated_data_e_scaled_f_rec_rawIn_normDist_12) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_25 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_24, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_12 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_25, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_60 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_12, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_61 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_60, activated_data_e_scaled_f_rec_rawIn_expIn_12) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_62 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_63 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_62) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_64 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_61, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_63) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_12 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_64, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_12 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_12 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_12, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_12 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_12, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_12 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_24 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_25 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_12, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_24) connect activated_data_e_scaled_f_rec_rawIn_12.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_25 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_12 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_12, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12) connect activated_data_e_scaled_f_rec_rawIn_12.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_12 connect activated_data_e_scaled_f_rec_rawIn_12.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_12 connect activated_data_e_scaled_f_rec_rawIn_12.sign, activated_data_e_scaled_f_rec_rawIn_sign_12 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_24 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_12, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_25 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_24) connect activated_data_e_scaled_f_rec_rawIn_12.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_25 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_48 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_12, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_49 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_48) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_50 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12, activated_data_e_scaled_f_rec_rawIn_subnormFract_12, activated_data_e_scaled_f_rec_rawIn_fractIn_12) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_51 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_49, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_50) connect activated_data_e_scaled_f_rec_rawIn_12.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_51 node _activated_data_e_scaled_f_rec_T_96 = bits(activated_data_e_scaled_f_rec_rawIn_12.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_97 = mux(activated_data_e_scaled_f_rec_rawIn_12.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_96) node _activated_data_e_scaled_f_rec_T_98 = mux(activated_data_e_scaled_f_rec_rawIn_12.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_99 = or(_activated_data_e_scaled_f_rec_T_97, _activated_data_e_scaled_f_rec_T_98) node _activated_data_e_scaled_f_rec_T_100 = cat(activated_data_e_scaled_f_rec_rawIn_12.sign, _activated_data_e_scaled_f_rec_T_99) node _activated_data_e_scaled_f_rec_T_101 = bits(activated_data_e_scaled_f_rec_rawIn_12.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_102 = cat(_activated_data_e_scaled_f_rec_T_100, _activated_data_e_scaled_f_rec_T_101) node _activated_data_e_scaled_f_rec_T_103 = bits(activated_data_e_scaled_f_rec_rawIn_12.sig, 22, 0) node activated_data_e_scaled_f_rec_12 = cat(_activated_data_e_scaled_f_rec_T_102, _activated_data_e_scaled_f_rec_T_103) inst activated_data_e_scaled_in_to_rec_fn_12 of INToRecFN_i32_e8_s24_12 connect activated_data_e_scaled_in_to_rec_fn_12.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_12 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_12 = asUInt(activated_data_e_act_12) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_12, _activated_data_e_scaled_in_to_rec_fn_io_in_T_12 connect activated_data_e_scaled_in_to_rec_fn_12.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_12 connect activated_data_e_scaled_in_to_rec_fn_12.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_12.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_12 of MulAddRecFN_e8_s24_16 connect activated_data_e_scaled_muladder_12.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_12.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_12.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_12.io.a, activated_data_e_scaled_in_to_rec_fn_12.io.out connect activated_data_e_scaled_muladder_12.io.b, activated_data_e_scaled_f_rec_12 connect activated_data_e_scaled_muladder_12.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_12 of RecFNToIN_e8_s24_i32_12 connect activated_data_e_scaled_rec_fn_to_in_12.clock, clock connect activated_data_e_scaled_rec_fn_to_in_12.reset, reset connect activated_data_e_scaled_rec_fn_to_in_12.io.in, activated_data_e_scaled_muladder_12.io.out connect activated_data_e_scaled_rec_fn_to_in_12.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_12.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_12 = bits(activated_data_e_scaled_rec_fn_to_in_12.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_12 = bits(activated_data_e_scaled_rec_fn_to_in_12.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_12 = bits(activated_data_e_scaled_sign_exp_12, 8, 6) node activated_data_e_scaled_sign_isZero_12 = eq(_activated_data_e_scaled_sign_isZero_T_12, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_12 = bits(activated_data_e_scaled_sign_exp_12, 8, 7) node activated_data_e_scaled_sign_isSpecial_12 = eq(_activated_data_e_scaled_sign_isSpecial_T_12, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_12 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_24 = bits(activated_data_e_scaled_sign_exp_12, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_25 = and(activated_data_e_scaled_sign_isSpecial_12, _activated_data_e_scaled_sign_out_isNaN_T_24) connect activated_data_e_scaled_sign_out_12.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_25 node _activated_data_e_scaled_sign_out_isInf_T_36 = bits(activated_data_e_scaled_sign_exp_12, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_37 = eq(_activated_data_e_scaled_sign_out_isInf_T_36, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_38 = and(activated_data_e_scaled_sign_isSpecial_12, _activated_data_e_scaled_sign_out_isInf_T_37) connect activated_data_e_scaled_sign_out_12.isInf, _activated_data_e_scaled_sign_out_isInf_T_38 connect activated_data_e_scaled_sign_out_12.isZero, activated_data_e_scaled_sign_isZero_12 node _activated_data_e_scaled_sign_out_sign_T_12 = bits(activated_data_e_scaled_rec_fn_to_in_12.io.in, 32, 32) connect activated_data_e_scaled_sign_out_12.sign, _activated_data_e_scaled_sign_out_sign_T_12 node _activated_data_e_scaled_sign_out_sExp_T_12 = cvt(activated_data_e_scaled_sign_exp_12) connect activated_data_e_scaled_sign_out_12.sExp, _activated_data_e_scaled_sign_out_sExp_T_12 node _activated_data_e_scaled_sign_out_sig_T_48 = eq(activated_data_e_scaled_sign_isZero_12, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_49 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_48) node _activated_data_e_scaled_sign_out_sig_T_50 = bits(activated_data_e_scaled_rec_fn_to_in_12.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_51 = cat(_activated_data_e_scaled_sign_out_sig_T_49, _activated_data_e_scaled_sign_out_sig_T_50) connect activated_data_e_scaled_sign_out_12.sig, _activated_data_e_scaled_sign_out_sig_T_51 node activated_data_e_scaled_sat_12 = mux(activated_data_e_scaled_sign_out_12.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_64 : SInt<32> node _activated_data_e_scaled_T_142 = asSInt(activated_data_e_scaled_rec_fn_to_in_12.io.out) connect _activated_data_e_scaled_WIRE_64, _activated_data_e_scaled_T_142 node activated_data_e_scaled_12 = mux(activated_data_e_scaled_overflow_12, activated_data_e_scaled_sat_12, _activated_data_e_scaled_WIRE_64) node _activated_data_e_clipped_T_60 = gt(activated_data_e_scaled_12, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_61 = lt(activated_data_e_scaled_12, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_62 = mux(_activated_data_e_clipped_T_61, asSInt(UInt<8>(0h80)), activated_data_e_scaled_12) node _activated_data_e_clipped_T_63 = mux(_activated_data_e_clipped_T_60, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_62) node _activated_data_e_clipped_T_64 = bits(_activated_data_e_clipped_T_63, 7, 0) node activated_data_e_clipped_12 = asSInt(_activated_data_e_clipped_T_64) wire _activated_data_WIRE_12 : SInt<8>[1] connect _activated_data_WIRE_12[0], activated_data_e_clipped_12 node _activated_data_e_act_T_416 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_417 = and(UInt<1>(0h1), _activated_data_e_act_T_416) node _activated_data_e_act_T_418 = geq(io.in.bits.acc_read_resp.data[13][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_419 = mux(_activated_data_e_act_T_418, io.in.bits.acc_read_resp.data[13][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_420 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_421 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_422 = and(_activated_data_e_act_T_420, _activated_data_e_act_T_421) node _activated_data_e_act_T_423 = sub(io.in.bits.acc_read_resp.data[13][0], io.in.bits.mean) node _activated_data_e_act_T_424 = tail(_activated_data_e_act_T_423, 1) node _activated_data_e_act_T_425 = asSInt(_activated_data_e_act_T_424) node _activated_data_e_act_T_426 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_427 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_428 = and(_activated_data_e_act_T_426, _activated_data_e_act_T_427) node _activated_data_e_act_q_sign_T_52 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[13][0]) node _activated_data_e_act_q_sign_T_53 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_54 = tail(_activated_data_e_act_q_sign_T_53, 1) node _activated_data_e_act_q_sign_T_55 = asSInt(_activated_data_e_act_q_sign_T_54) node activated_data_e_act_q_sign_13 = mux(_activated_data_e_act_q_sign_T_52, _activated_data_e_act_q_sign_T_55, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_52 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[13][0]) node _activated_data_e_act_q_abs_T_53 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[13][0]) node _activated_data_e_act_q_abs_T_54 = tail(_activated_data_e_act_q_abs_T_53, 1) node _activated_data_e_act_q_abs_T_55 = asSInt(_activated_data_e_act_q_abs_T_54) node activated_data_e_act_q_abs_13 = mux(_activated_data_e_act_q_abs_T_52, _activated_data_e_act_q_abs_T_55, io.in.bits.acc_read_resp.data[13][0]) node _activated_data_e_act_q_clipped_T_91 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_92 = tail(_activated_data_e_act_q_clipped_T_91, 1) node _activated_data_e_act_q_clipped_T_93 = asSInt(_activated_data_e_act_q_clipped_T_92) node _activated_data_e_act_q_clipped_T_94 = gt(activated_data_e_act_q_abs_13, _activated_data_e_act_q_clipped_T_93) node _activated_data_e_act_q_clipped_T_95 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_96 = tail(_activated_data_e_act_q_clipped_T_95, 1) node _activated_data_e_act_q_clipped_T_97 = asSInt(_activated_data_e_act_q_clipped_T_96) node activated_data_e_act_q_clipped_13 = mux(_activated_data_e_act_q_clipped_T_94, _activated_data_e_act_q_clipped_T_97, activated_data_e_act_q_abs_13) node _activated_data_e_act_q_poly_T_143 = add(activated_data_e_act_q_clipped_13, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_144 = tail(_activated_data_e_act_q_poly_T_143, 1) node _activated_data_e_act_q_poly_T_145 = asSInt(_activated_data_e_act_q_poly_T_144) node _activated_data_e_act_q_poly_T_146 = add(activated_data_e_act_q_clipped_13, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_147 = tail(_activated_data_e_act_q_poly_T_146, 1) node _activated_data_e_act_q_poly_T_148 = asSInt(_activated_data_e_act_q_poly_T_147) node _activated_data_e_act_q_poly_T_149 = mul(_activated_data_e_act_q_poly_T_145, _activated_data_e_act_q_poly_T_148) node _activated_data_e_act_q_poly_T_150 = add(_activated_data_e_act_q_poly_T_149, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_151 = tail(_activated_data_e_act_q_poly_T_150, 1) node _activated_data_e_act_q_poly_T_152 = asSInt(_activated_data_e_act_q_poly_T_151) node _activated_data_e_act_q_poly_T_153 = bits(_activated_data_e_act_q_poly_T_152, 31, 0) node activated_data_e_act_q_poly_13 = asSInt(_activated_data_e_act_q_poly_T_153) node _activated_data_e_act_q_erf_T_26 = mul(activated_data_e_act_q_sign_13, activated_data_e_act_q_poly_13) node _activated_data_e_act_q_erf_T_27 = bits(_activated_data_e_act_q_erf_T_26, 31, 0) node activated_data_e_act_q_erf_13 = asSInt(_activated_data_e_act_q_erf_T_27) node _activated_data_e_act_T_429 = add(activated_data_e_act_q_erf_13, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_430 = tail(_activated_data_e_act_T_429, 1) node _activated_data_e_act_T_431 = asSInt(_activated_data_e_act_T_430) node _activated_data_e_act_T_432 = mul(io.in.bits.acc_read_resp.data[13][0], _activated_data_e_act_T_431) node _activated_data_e_act_T_433 = bits(_activated_data_e_act_T_432, 31, 0) node _activated_data_e_act_T_434 = asSInt(_activated_data_e_act_T_433) node _activated_data_e_act_T_435 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_436 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_437 = and(_activated_data_e_act_T_435, _activated_data_e_act_T_436) node _activated_data_e_act_T_438 = sub(io.in.bits.acc_read_resp.data[13][0], io.in.bits.max) node _activated_data_e_act_T_439 = tail(_activated_data_e_act_T_438, 1) node _activated_data_e_act_T_440 = asSInt(_activated_data_e_act_T_439) node _activated_data_e_act_neg_q_iexp_T_26 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_440) node _activated_data_e_act_neg_q_iexp_T_27 = tail(_activated_data_e_act_neg_q_iexp_T_26, 1) node activated_data_e_act_neg_q_iexp_13 = asSInt(_activated_data_e_act_neg_q_iexp_T_27) node _activated_data_e_act_z_iexp_T_52 = mul(activated_data_e_act_neg_q_iexp_13, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_53 = asUInt(_activated_data_e_act_z_iexp_T_52) node _activated_data_e_act_z_iexp_T_54 = shr(_activated_data_e_act_z_iexp_T_53, 16) wire activated_data_e_act_z_iexp_13 : SInt<32> node _activated_data_e_act_z_iexp_T_55 = asSInt(_activated_data_e_act_z_iexp_T_54) connect activated_data_e_act_z_iexp_13, _activated_data_e_act_z_iexp_T_55 wire activated_data_e_act_z_iexp_saturated_13 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_429 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_430 = bits(_activated_data_e_act_z_iexp_saturated_T_429, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_431 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_432 = bits(_activated_data_e_act_z_iexp_saturated_T_431, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_433 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_434 = bits(_activated_data_e_act_z_iexp_saturated_T_433, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_435 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_436 = bits(_activated_data_e_act_z_iexp_saturated_T_435, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_437 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_438 = bits(_activated_data_e_act_z_iexp_saturated_T_437, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_439 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_440 = bits(_activated_data_e_act_z_iexp_saturated_T_439, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_441 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_442 = bits(_activated_data_e_act_z_iexp_saturated_T_441, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_443 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_444 = bits(_activated_data_e_act_z_iexp_saturated_T_443, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_445 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_446 = bits(_activated_data_e_act_z_iexp_saturated_T_445, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_447 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_448 = bits(_activated_data_e_act_z_iexp_saturated_T_447, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_449 = asUInt(activated_data_e_act_z_iexp_13) node _activated_data_e_act_z_iexp_saturated_T_450 = bits(_activated_data_e_act_z_iexp_saturated_T_449, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_451 = or(_activated_data_e_act_z_iexp_saturated_T_430, _activated_data_e_act_z_iexp_saturated_T_432) node _activated_data_e_act_z_iexp_saturated_T_452 = or(_activated_data_e_act_z_iexp_saturated_T_451, _activated_data_e_act_z_iexp_saturated_T_434) node _activated_data_e_act_z_iexp_saturated_T_453 = or(_activated_data_e_act_z_iexp_saturated_T_452, _activated_data_e_act_z_iexp_saturated_T_436) node _activated_data_e_act_z_iexp_saturated_T_454 = or(_activated_data_e_act_z_iexp_saturated_T_453, _activated_data_e_act_z_iexp_saturated_T_438) node _activated_data_e_act_z_iexp_saturated_T_455 = or(_activated_data_e_act_z_iexp_saturated_T_454, _activated_data_e_act_z_iexp_saturated_T_440) node _activated_data_e_act_z_iexp_saturated_T_456 = or(_activated_data_e_act_z_iexp_saturated_T_455, _activated_data_e_act_z_iexp_saturated_T_442) node _activated_data_e_act_z_iexp_saturated_T_457 = or(_activated_data_e_act_z_iexp_saturated_T_456, _activated_data_e_act_z_iexp_saturated_T_444) node _activated_data_e_act_z_iexp_saturated_T_458 = or(_activated_data_e_act_z_iexp_saturated_T_457, _activated_data_e_act_z_iexp_saturated_T_446) node _activated_data_e_act_z_iexp_saturated_T_459 = or(_activated_data_e_act_z_iexp_saturated_T_458, _activated_data_e_act_z_iexp_saturated_T_448) node _activated_data_e_act_z_iexp_saturated_T_460 = or(_activated_data_e_act_z_iexp_saturated_T_459, _activated_data_e_act_z_iexp_saturated_T_450) wire _activated_data_e_act_z_iexp_saturated_WIRE_13 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_13, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_461 = mux(_activated_data_e_act_z_iexp_saturated_T_460, _activated_data_e_act_z_iexp_saturated_WIRE_13, activated_data_e_act_z_iexp_13) connect activated_data_e_act_z_iexp_saturated_13, _activated_data_e_act_z_iexp_saturated_T_461 node _activated_data_e_act_qp_iexp_T_65 = mul(activated_data_e_act_z_iexp_13, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_66 = add(_activated_data_e_act_qp_iexp_T_65, _activated_data_e_act_T_440) node _activated_data_e_act_qp_iexp_T_67 = tail(_activated_data_e_act_qp_iexp_T_66, 1) node _activated_data_e_act_qp_iexp_T_68 = asSInt(_activated_data_e_act_qp_iexp_T_67) node _activated_data_e_act_qp_iexp_T_69 = bits(_activated_data_e_act_qp_iexp_T_68, 31, 0) node activated_data_e_act_qp_iexp_13 = asSInt(_activated_data_e_act_qp_iexp_T_69) node _activated_data_e_act_q_poly_iexp_T_143 = add(activated_data_e_act_qp_iexp_13, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_144 = tail(_activated_data_e_act_q_poly_iexp_T_143, 1) node _activated_data_e_act_q_poly_iexp_T_145 = asSInt(_activated_data_e_act_q_poly_iexp_T_144) node _activated_data_e_act_q_poly_iexp_T_146 = add(activated_data_e_act_qp_iexp_13, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_147 = tail(_activated_data_e_act_q_poly_iexp_T_146, 1) node _activated_data_e_act_q_poly_iexp_T_148 = asSInt(_activated_data_e_act_q_poly_iexp_T_147) node _activated_data_e_act_q_poly_iexp_T_149 = mul(_activated_data_e_act_q_poly_iexp_T_145, _activated_data_e_act_q_poly_iexp_T_148) node _activated_data_e_act_q_poly_iexp_T_150 = add(_activated_data_e_act_q_poly_iexp_T_149, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_151 = tail(_activated_data_e_act_q_poly_iexp_T_150, 1) node _activated_data_e_act_q_poly_iexp_T_152 = asSInt(_activated_data_e_act_q_poly_iexp_T_151) node _activated_data_e_act_q_poly_iexp_T_153 = bits(_activated_data_e_act_q_poly_iexp_T_152, 31, 0) node activated_data_e_act_q_poly_iexp_13 = asSInt(_activated_data_e_act_q_poly_iexp_T_153) node _activated_data_e_act_T_441 = asUInt(activated_data_e_act_q_poly_iexp_13) node _activated_data_e_act_T_442 = asUInt(activated_data_e_act_z_iexp_saturated_13) node _activated_data_e_act_T_443 = dshr(_activated_data_e_act_T_441, _activated_data_e_act_T_442) wire _activated_data_e_act_WIRE_13 : SInt<32> node _activated_data_e_act_T_444 = asSInt(_activated_data_e_act_T_443) connect _activated_data_e_act_WIRE_13, _activated_data_e_act_T_444 node _activated_data_e_act_T_445 = mux(_activated_data_e_act_T_437, _activated_data_e_act_WIRE_13, io.in.bits.acc_read_resp.data[13][0]) node _activated_data_e_act_T_446 = mux(_activated_data_e_act_T_428, _activated_data_e_act_T_434, _activated_data_e_act_T_445) node _activated_data_e_act_T_447 = mux(_activated_data_e_act_T_422, _activated_data_e_act_T_425, _activated_data_e_act_T_446) node activated_data_e_act_13 = mux(_activated_data_e_act_T_417, _activated_data_e_act_T_419, _activated_data_e_act_T_447) node _activated_data_e_scaled_T_143 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_144 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_145 = and(_activated_data_e_scaled_T_143, _activated_data_e_scaled_T_144) node _activated_data_e_scaled_T_146 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_147 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_148 = and(_activated_data_e_scaled_T_146, _activated_data_e_scaled_T_147) wire _activated_data_e_scaled_WIRE_65 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_66 : UInt<32> connect _activated_data_e_scaled_WIRE_66, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_149 = bits(_activated_data_e_scaled_WIRE_66, 31, 0) connect _activated_data_e_scaled_WIRE_65.bits, _activated_data_e_scaled_T_149 node _activated_data_e_scaled_T_150 = mux(_activated_data_e_scaled_T_148, _activated_data_e_scaled_WIRE_65, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_151 = mux(_activated_data_e_scaled_T_145, io.in.bits.inv_stddev, _activated_data_e_scaled_T_150) wire _activated_data_e_scaled_WIRE_67 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_68 : UInt<32> connect _activated_data_e_scaled_WIRE_68, _activated_data_e_scaled_T_151.bits node _activated_data_e_scaled_T_152 = bits(_activated_data_e_scaled_WIRE_68, 31, 0) connect _activated_data_e_scaled_WIRE_67.bits, _activated_data_e_scaled_T_152 node activated_data_e_scaled_f_rec_rawIn_sign_13 = bits(_activated_data_e_scaled_WIRE_67.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_13 = bits(_activated_data_e_scaled_WIRE_67.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_13 = bits(_activated_data_e_scaled_WIRE_67.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_13, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_13, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_572 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_573 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_574 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_575 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_576 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_577 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_578 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_579 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_580 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_581 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_582 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_583 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_584 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_585 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_586 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_587 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_588 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_589 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_590 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_591 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_592 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_593 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_594 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_13, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_595 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_573, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_596 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_574, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_595) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_597 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_575, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_596) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_598 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_576, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_597) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_599 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_577, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_598) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_600 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_578, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_599) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_601 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_579, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_600) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_602 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_580, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_601) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_603 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_581, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_602) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_604 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_582, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_603) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_605 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_583, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_604) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_606 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_584, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_605) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_607 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_585, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_606) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_608 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_586, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_607) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_609 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_587, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_608) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_610 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_588, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_609) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_611 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_589, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_610) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_612 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_590, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_611) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_613 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_591, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_612) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_614 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_592, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_613) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_615 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_593, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_614) node activated_data_e_scaled_f_rec_rawIn_normDist_13 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_594, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_615) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_26 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_13, activated_data_e_scaled_f_rec_rawIn_normDist_13) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_27 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_26, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_13 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_27, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_65 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_13, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_66 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_65, activated_data_e_scaled_f_rec_rawIn_expIn_13) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_67 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_68 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_67) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_69 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_66, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_68) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_13 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_69, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_13 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_13 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_13, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_13 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_13, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_13 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_26 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_27 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_13, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_26) connect activated_data_e_scaled_f_rec_rawIn_13.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_27 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_13 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_13, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13) connect activated_data_e_scaled_f_rec_rawIn_13.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_13 connect activated_data_e_scaled_f_rec_rawIn_13.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_13 connect activated_data_e_scaled_f_rec_rawIn_13.sign, activated_data_e_scaled_f_rec_rawIn_sign_13 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_26 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_13, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_27 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_26) connect activated_data_e_scaled_f_rec_rawIn_13.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_27 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_52 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_13, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_53 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_52) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_54 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13, activated_data_e_scaled_f_rec_rawIn_subnormFract_13, activated_data_e_scaled_f_rec_rawIn_fractIn_13) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_55 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_53, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_54) connect activated_data_e_scaled_f_rec_rawIn_13.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_55 node _activated_data_e_scaled_f_rec_T_104 = bits(activated_data_e_scaled_f_rec_rawIn_13.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_105 = mux(activated_data_e_scaled_f_rec_rawIn_13.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_104) node _activated_data_e_scaled_f_rec_T_106 = mux(activated_data_e_scaled_f_rec_rawIn_13.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_107 = or(_activated_data_e_scaled_f_rec_T_105, _activated_data_e_scaled_f_rec_T_106) node _activated_data_e_scaled_f_rec_T_108 = cat(activated_data_e_scaled_f_rec_rawIn_13.sign, _activated_data_e_scaled_f_rec_T_107) node _activated_data_e_scaled_f_rec_T_109 = bits(activated_data_e_scaled_f_rec_rawIn_13.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_110 = cat(_activated_data_e_scaled_f_rec_T_108, _activated_data_e_scaled_f_rec_T_109) node _activated_data_e_scaled_f_rec_T_111 = bits(activated_data_e_scaled_f_rec_rawIn_13.sig, 22, 0) node activated_data_e_scaled_f_rec_13 = cat(_activated_data_e_scaled_f_rec_T_110, _activated_data_e_scaled_f_rec_T_111) inst activated_data_e_scaled_in_to_rec_fn_13 of INToRecFN_i32_e8_s24_13 connect activated_data_e_scaled_in_to_rec_fn_13.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_13 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_13 = asUInt(activated_data_e_act_13) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_13, _activated_data_e_scaled_in_to_rec_fn_io_in_T_13 connect activated_data_e_scaled_in_to_rec_fn_13.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_13 connect activated_data_e_scaled_in_to_rec_fn_13.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_13.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_13 of MulAddRecFN_e8_s24_17 connect activated_data_e_scaled_muladder_13.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_13.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_13.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_13.io.a, activated_data_e_scaled_in_to_rec_fn_13.io.out connect activated_data_e_scaled_muladder_13.io.b, activated_data_e_scaled_f_rec_13 connect activated_data_e_scaled_muladder_13.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_13 of RecFNToIN_e8_s24_i32_13 connect activated_data_e_scaled_rec_fn_to_in_13.clock, clock connect activated_data_e_scaled_rec_fn_to_in_13.reset, reset connect activated_data_e_scaled_rec_fn_to_in_13.io.in, activated_data_e_scaled_muladder_13.io.out connect activated_data_e_scaled_rec_fn_to_in_13.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_13.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_13 = bits(activated_data_e_scaled_rec_fn_to_in_13.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_13 = bits(activated_data_e_scaled_rec_fn_to_in_13.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_13 = bits(activated_data_e_scaled_sign_exp_13, 8, 6) node activated_data_e_scaled_sign_isZero_13 = eq(_activated_data_e_scaled_sign_isZero_T_13, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_13 = bits(activated_data_e_scaled_sign_exp_13, 8, 7) node activated_data_e_scaled_sign_isSpecial_13 = eq(_activated_data_e_scaled_sign_isSpecial_T_13, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_13 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_26 = bits(activated_data_e_scaled_sign_exp_13, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_27 = and(activated_data_e_scaled_sign_isSpecial_13, _activated_data_e_scaled_sign_out_isNaN_T_26) connect activated_data_e_scaled_sign_out_13.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_27 node _activated_data_e_scaled_sign_out_isInf_T_39 = bits(activated_data_e_scaled_sign_exp_13, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_40 = eq(_activated_data_e_scaled_sign_out_isInf_T_39, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_41 = and(activated_data_e_scaled_sign_isSpecial_13, _activated_data_e_scaled_sign_out_isInf_T_40) connect activated_data_e_scaled_sign_out_13.isInf, _activated_data_e_scaled_sign_out_isInf_T_41 connect activated_data_e_scaled_sign_out_13.isZero, activated_data_e_scaled_sign_isZero_13 node _activated_data_e_scaled_sign_out_sign_T_13 = bits(activated_data_e_scaled_rec_fn_to_in_13.io.in, 32, 32) connect activated_data_e_scaled_sign_out_13.sign, _activated_data_e_scaled_sign_out_sign_T_13 node _activated_data_e_scaled_sign_out_sExp_T_13 = cvt(activated_data_e_scaled_sign_exp_13) connect activated_data_e_scaled_sign_out_13.sExp, _activated_data_e_scaled_sign_out_sExp_T_13 node _activated_data_e_scaled_sign_out_sig_T_52 = eq(activated_data_e_scaled_sign_isZero_13, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_53 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_52) node _activated_data_e_scaled_sign_out_sig_T_54 = bits(activated_data_e_scaled_rec_fn_to_in_13.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_55 = cat(_activated_data_e_scaled_sign_out_sig_T_53, _activated_data_e_scaled_sign_out_sig_T_54) connect activated_data_e_scaled_sign_out_13.sig, _activated_data_e_scaled_sign_out_sig_T_55 node activated_data_e_scaled_sat_13 = mux(activated_data_e_scaled_sign_out_13.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_69 : SInt<32> node _activated_data_e_scaled_T_153 = asSInt(activated_data_e_scaled_rec_fn_to_in_13.io.out) connect _activated_data_e_scaled_WIRE_69, _activated_data_e_scaled_T_153 node activated_data_e_scaled_13 = mux(activated_data_e_scaled_overflow_13, activated_data_e_scaled_sat_13, _activated_data_e_scaled_WIRE_69) node _activated_data_e_clipped_T_65 = gt(activated_data_e_scaled_13, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_66 = lt(activated_data_e_scaled_13, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_67 = mux(_activated_data_e_clipped_T_66, asSInt(UInt<8>(0h80)), activated_data_e_scaled_13) node _activated_data_e_clipped_T_68 = mux(_activated_data_e_clipped_T_65, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_67) node _activated_data_e_clipped_T_69 = bits(_activated_data_e_clipped_T_68, 7, 0) node activated_data_e_clipped_13 = asSInt(_activated_data_e_clipped_T_69) wire _activated_data_WIRE_13 : SInt<8>[1] connect _activated_data_WIRE_13[0], activated_data_e_clipped_13 node _activated_data_e_act_T_448 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_449 = and(UInt<1>(0h1), _activated_data_e_act_T_448) node _activated_data_e_act_T_450 = geq(io.in.bits.acc_read_resp.data[14][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_451 = mux(_activated_data_e_act_T_450, io.in.bits.acc_read_resp.data[14][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_452 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_453 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_454 = and(_activated_data_e_act_T_452, _activated_data_e_act_T_453) node _activated_data_e_act_T_455 = sub(io.in.bits.acc_read_resp.data[14][0], io.in.bits.mean) node _activated_data_e_act_T_456 = tail(_activated_data_e_act_T_455, 1) node _activated_data_e_act_T_457 = asSInt(_activated_data_e_act_T_456) node _activated_data_e_act_T_458 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_459 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_460 = and(_activated_data_e_act_T_458, _activated_data_e_act_T_459) node _activated_data_e_act_q_sign_T_56 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[14][0]) node _activated_data_e_act_q_sign_T_57 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_58 = tail(_activated_data_e_act_q_sign_T_57, 1) node _activated_data_e_act_q_sign_T_59 = asSInt(_activated_data_e_act_q_sign_T_58) node activated_data_e_act_q_sign_14 = mux(_activated_data_e_act_q_sign_T_56, _activated_data_e_act_q_sign_T_59, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_56 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[14][0]) node _activated_data_e_act_q_abs_T_57 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[14][0]) node _activated_data_e_act_q_abs_T_58 = tail(_activated_data_e_act_q_abs_T_57, 1) node _activated_data_e_act_q_abs_T_59 = asSInt(_activated_data_e_act_q_abs_T_58) node activated_data_e_act_q_abs_14 = mux(_activated_data_e_act_q_abs_T_56, _activated_data_e_act_q_abs_T_59, io.in.bits.acc_read_resp.data[14][0]) node _activated_data_e_act_q_clipped_T_98 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_99 = tail(_activated_data_e_act_q_clipped_T_98, 1) node _activated_data_e_act_q_clipped_T_100 = asSInt(_activated_data_e_act_q_clipped_T_99) node _activated_data_e_act_q_clipped_T_101 = gt(activated_data_e_act_q_abs_14, _activated_data_e_act_q_clipped_T_100) node _activated_data_e_act_q_clipped_T_102 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_103 = tail(_activated_data_e_act_q_clipped_T_102, 1) node _activated_data_e_act_q_clipped_T_104 = asSInt(_activated_data_e_act_q_clipped_T_103) node activated_data_e_act_q_clipped_14 = mux(_activated_data_e_act_q_clipped_T_101, _activated_data_e_act_q_clipped_T_104, activated_data_e_act_q_abs_14) node _activated_data_e_act_q_poly_T_154 = add(activated_data_e_act_q_clipped_14, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_155 = tail(_activated_data_e_act_q_poly_T_154, 1) node _activated_data_e_act_q_poly_T_156 = asSInt(_activated_data_e_act_q_poly_T_155) node _activated_data_e_act_q_poly_T_157 = add(activated_data_e_act_q_clipped_14, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_158 = tail(_activated_data_e_act_q_poly_T_157, 1) node _activated_data_e_act_q_poly_T_159 = asSInt(_activated_data_e_act_q_poly_T_158) node _activated_data_e_act_q_poly_T_160 = mul(_activated_data_e_act_q_poly_T_156, _activated_data_e_act_q_poly_T_159) node _activated_data_e_act_q_poly_T_161 = add(_activated_data_e_act_q_poly_T_160, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_162 = tail(_activated_data_e_act_q_poly_T_161, 1) node _activated_data_e_act_q_poly_T_163 = asSInt(_activated_data_e_act_q_poly_T_162) node _activated_data_e_act_q_poly_T_164 = bits(_activated_data_e_act_q_poly_T_163, 31, 0) node activated_data_e_act_q_poly_14 = asSInt(_activated_data_e_act_q_poly_T_164) node _activated_data_e_act_q_erf_T_28 = mul(activated_data_e_act_q_sign_14, activated_data_e_act_q_poly_14) node _activated_data_e_act_q_erf_T_29 = bits(_activated_data_e_act_q_erf_T_28, 31, 0) node activated_data_e_act_q_erf_14 = asSInt(_activated_data_e_act_q_erf_T_29) node _activated_data_e_act_T_461 = add(activated_data_e_act_q_erf_14, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_462 = tail(_activated_data_e_act_T_461, 1) node _activated_data_e_act_T_463 = asSInt(_activated_data_e_act_T_462) node _activated_data_e_act_T_464 = mul(io.in.bits.acc_read_resp.data[14][0], _activated_data_e_act_T_463) node _activated_data_e_act_T_465 = bits(_activated_data_e_act_T_464, 31, 0) node _activated_data_e_act_T_466 = asSInt(_activated_data_e_act_T_465) node _activated_data_e_act_T_467 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_468 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_469 = and(_activated_data_e_act_T_467, _activated_data_e_act_T_468) node _activated_data_e_act_T_470 = sub(io.in.bits.acc_read_resp.data[14][0], io.in.bits.max) node _activated_data_e_act_T_471 = tail(_activated_data_e_act_T_470, 1) node _activated_data_e_act_T_472 = asSInt(_activated_data_e_act_T_471) node _activated_data_e_act_neg_q_iexp_T_28 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_472) node _activated_data_e_act_neg_q_iexp_T_29 = tail(_activated_data_e_act_neg_q_iexp_T_28, 1) node activated_data_e_act_neg_q_iexp_14 = asSInt(_activated_data_e_act_neg_q_iexp_T_29) node _activated_data_e_act_z_iexp_T_56 = mul(activated_data_e_act_neg_q_iexp_14, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_57 = asUInt(_activated_data_e_act_z_iexp_T_56) node _activated_data_e_act_z_iexp_T_58 = shr(_activated_data_e_act_z_iexp_T_57, 16) wire activated_data_e_act_z_iexp_14 : SInt<32> node _activated_data_e_act_z_iexp_T_59 = asSInt(_activated_data_e_act_z_iexp_T_58) connect activated_data_e_act_z_iexp_14, _activated_data_e_act_z_iexp_T_59 wire activated_data_e_act_z_iexp_saturated_14 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_462 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_463 = bits(_activated_data_e_act_z_iexp_saturated_T_462, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_464 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_465 = bits(_activated_data_e_act_z_iexp_saturated_T_464, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_466 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_467 = bits(_activated_data_e_act_z_iexp_saturated_T_466, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_468 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_469 = bits(_activated_data_e_act_z_iexp_saturated_T_468, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_470 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_471 = bits(_activated_data_e_act_z_iexp_saturated_T_470, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_472 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_473 = bits(_activated_data_e_act_z_iexp_saturated_T_472, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_474 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_475 = bits(_activated_data_e_act_z_iexp_saturated_T_474, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_476 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_477 = bits(_activated_data_e_act_z_iexp_saturated_T_476, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_478 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_479 = bits(_activated_data_e_act_z_iexp_saturated_T_478, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_480 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_481 = bits(_activated_data_e_act_z_iexp_saturated_T_480, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_482 = asUInt(activated_data_e_act_z_iexp_14) node _activated_data_e_act_z_iexp_saturated_T_483 = bits(_activated_data_e_act_z_iexp_saturated_T_482, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_484 = or(_activated_data_e_act_z_iexp_saturated_T_463, _activated_data_e_act_z_iexp_saturated_T_465) node _activated_data_e_act_z_iexp_saturated_T_485 = or(_activated_data_e_act_z_iexp_saturated_T_484, _activated_data_e_act_z_iexp_saturated_T_467) node _activated_data_e_act_z_iexp_saturated_T_486 = or(_activated_data_e_act_z_iexp_saturated_T_485, _activated_data_e_act_z_iexp_saturated_T_469) node _activated_data_e_act_z_iexp_saturated_T_487 = or(_activated_data_e_act_z_iexp_saturated_T_486, _activated_data_e_act_z_iexp_saturated_T_471) node _activated_data_e_act_z_iexp_saturated_T_488 = or(_activated_data_e_act_z_iexp_saturated_T_487, _activated_data_e_act_z_iexp_saturated_T_473) node _activated_data_e_act_z_iexp_saturated_T_489 = or(_activated_data_e_act_z_iexp_saturated_T_488, _activated_data_e_act_z_iexp_saturated_T_475) node _activated_data_e_act_z_iexp_saturated_T_490 = or(_activated_data_e_act_z_iexp_saturated_T_489, _activated_data_e_act_z_iexp_saturated_T_477) node _activated_data_e_act_z_iexp_saturated_T_491 = or(_activated_data_e_act_z_iexp_saturated_T_490, _activated_data_e_act_z_iexp_saturated_T_479) node _activated_data_e_act_z_iexp_saturated_T_492 = or(_activated_data_e_act_z_iexp_saturated_T_491, _activated_data_e_act_z_iexp_saturated_T_481) node _activated_data_e_act_z_iexp_saturated_T_493 = or(_activated_data_e_act_z_iexp_saturated_T_492, _activated_data_e_act_z_iexp_saturated_T_483) wire _activated_data_e_act_z_iexp_saturated_WIRE_14 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_14, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_494 = mux(_activated_data_e_act_z_iexp_saturated_T_493, _activated_data_e_act_z_iexp_saturated_WIRE_14, activated_data_e_act_z_iexp_14) connect activated_data_e_act_z_iexp_saturated_14, _activated_data_e_act_z_iexp_saturated_T_494 node _activated_data_e_act_qp_iexp_T_70 = mul(activated_data_e_act_z_iexp_14, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_71 = add(_activated_data_e_act_qp_iexp_T_70, _activated_data_e_act_T_472) node _activated_data_e_act_qp_iexp_T_72 = tail(_activated_data_e_act_qp_iexp_T_71, 1) node _activated_data_e_act_qp_iexp_T_73 = asSInt(_activated_data_e_act_qp_iexp_T_72) node _activated_data_e_act_qp_iexp_T_74 = bits(_activated_data_e_act_qp_iexp_T_73, 31, 0) node activated_data_e_act_qp_iexp_14 = asSInt(_activated_data_e_act_qp_iexp_T_74) node _activated_data_e_act_q_poly_iexp_T_154 = add(activated_data_e_act_qp_iexp_14, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_155 = tail(_activated_data_e_act_q_poly_iexp_T_154, 1) node _activated_data_e_act_q_poly_iexp_T_156 = asSInt(_activated_data_e_act_q_poly_iexp_T_155) node _activated_data_e_act_q_poly_iexp_T_157 = add(activated_data_e_act_qp_iexp_14, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_158 = tail(_activated_data_e_act_q_poly_iexp_T_157, 1) node _activated_data_e_act_q_poly_iexp_T_159 = asSInt(_activated_data_e_act_q_poly_iexp_T_158) node _activated_data_e_act_q_poly_iexp_T_160 = mul(_activated_data_e_act_q_poly_iexp_T_156, _activated_data_e_act_q_poly_iexp_T_159) node _activated_data_e_act_q_poly_iexp_T_161 = add(_activated_data_e_act_q_poly_iexp_T_160, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_162 = tail(_activated_data_e_act_q_poly_iexp_T_161, 1) node _activated_data_e_act_q_poly_iexp_T_163 = asSInt(_activated_data_e_act_q_poly_iexp_T_162) node _activated_data_e_act_q_poly_iexp_T_164 = bits(_activated_data_e_act_q_poly_iexp_T_163, 31, 0) node activated_data_e_act_q_poly_iexp_14 = asSInt(_activated_data_e_act_q_poly_iexp_T_164) node _activated_data_e_act_T_473 = asUInt(activated_data_e_act_q_poly_iexp_14) node _activated_data_e_act_T_474 = asUInt(activated_data_e_act_z_iexp_saturated_14) node _activated_data_e_act_T_475 = dshr(_activated_data_e_act_T_473, _activated_data_e_act_T_474) wire _activated_data_e_act_WIRE_14 : SInt<32> node _activated_data_e_act_T_476 = asSInt(_activated_data_e_act_T_475) connect _activated_data_e_act_WIRE_14, _activated_data_e_act_T_476 node _activated_data_e_act_T_477 = mux(_activated_data_e_act_T_469, _activated_data_e_act_WIRE_14, io.in.bits.acc_read_resp.data[14][0]) node _activated_data_e_act_T_478 = mux(_activated_data_e_act_T_460, _activated_data_e_act_T_466, _activated_data_e_act_T_477) node _activated_data_e_act_T_479 = mux(_activated_data_e_act_T_454, _activated_data_e_act_T_457, _activated_data_e_act_T_478) node activated_data_e_act_14 = mux(_activated_data_e_act_T_449, _activated_data_e_act_T_451, _activated_data_e_act_T_479) node _activated_data_e_scaled_T_154 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_155 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_156 = and(_activated_data_e_scaled_T_154, _activated_data_e_scaled_T_155) node _activated_data_e_scaled_T_157 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_158 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_159 = and(_activated_data_e_scaled_T_157, _activated_data_e_scaled_T_158) wire _activated_data_e_scaled_WIRE_70 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_71 : UInt<32> connect _activated_data_e_scaled_WIRE_71, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_160 = bits(_activated_data_e_scaled_WIRE_71, 31, 0) connect _activated_data_e_scaled_WIRE_70.bits, _activated_data_e_scaled_T_160 node _activated_data_e_scaled_T_161 = mux(_activated_data_e_scaled_T_159, _activated_data_e_scaled_WIRE_70, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_162 = mux(_activated_data_e_scaled_T_156, io.in.bits.inv_stddev, _activated_data_e_scaled_T_161) wire _activated_data_e_scaled_WIRE_72 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_73 : UInt<32> connect _activated_data_e_scaled_WIRE_73, _activated_data_e_scaled_T_162.bits node _activated_data_e_scaled_T_163 = bits(_activated_data_e_scaled_WIRE_73, 31, 0) connect _activated_data_e_scaled_WIRE_72.bits, _activated_data_e_scaled_T_163 node activated_data_e_scaled_f_rec_rawIn_sign_14 = bits(_activated_data_e_scaled_WIRE_72.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_14 = bits(_activated_data_e_scaled_WIRE_72.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_14 = bits(_activated_data_e_scaled_WIRE_72.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_14, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_14, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_616 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_617 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_618 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_619 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_620 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_621 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_622 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_623 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_624 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_625 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_626 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_627 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_628 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_629 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_630 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_631 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_632 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_633 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_634 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_635 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_636 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_637 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_638 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_14, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_639 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_617, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_640 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_618, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_639) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_641 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_619, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_640) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_642 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_620, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_641) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_643 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_621, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_642) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_644 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_622, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_643) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_645 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_623, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_644) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_646 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_624, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_645) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_647 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_625, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_646) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_648 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_626, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_647) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_649 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_627, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_648) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_650 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_628, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_649) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_651 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_629, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_650) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_652 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_630, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_651) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_653 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_631, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_652) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_654 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_632, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_653) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_655 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_633, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_654) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_656 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_634, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_655) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_657 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_635, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_656) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_658 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_636, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_657) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_659 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_637, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_658) node activated_data_e_scaled_f_rec_rawIn_normDist_14 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_638, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_659) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_28 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_14, activated_data_e_scaled_f_rec_rawIn_normDist_14) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_29 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_28, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_14 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_29, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_70 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_14, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_71 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_70, activated_data_e_scaled_f_rec_rawIn_expIn_14) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_72 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_73 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_72) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_74 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_71, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_73) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_14 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_74, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_14 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_14 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_14, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_14 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_14, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_14 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_28 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_29 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_14, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_28) connect activated_data_e_scaled_f_rec_rawIn_14.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_29 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_14 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_14, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14) connect activated_data_e_scaled_f_rec_rawIn_14.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_14 connect activated_data_e_scaled_f_rec_rawIn_14.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_14 connect activated_data_e_scaled_f_rec_rawIn_14.sign, activated_data_e_scaled_f_rec_rawIn_sign_14 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_28 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_14, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_29 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_28) connect activated_data_e_scaled_f_rec_rawIn_14.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_29 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_56 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_14, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_57 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_56) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_58 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14, activated_data_e_scaled_f_rec_rawIn_subnormFract_14, activated_data_e_scaled_f_rec_rawIn_fractIn_14) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_59 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_57, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_58) connect activated_data_e_scaled_f_rec_rawIn_14.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_59 node _activated_data_e_scaled_f_rec_T_112 = bits(activated_data_e_scaled_f_rec_rawIn_14.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_113 = mux(activated_data_e_scaled_f_rec_rawIn_14.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_112) node _activated_data_e_scaled_f_rec_T_114 = mux(activated_data_e_scaled_f_rec_rawIn_14.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_115 = or(_activated_data_e_scaled_f_rec_T_113, _activated_data_e_scaled_f_rec_T_114) node _activated_data_e_scaled_f_rec_T_116 = cat(activated_data_e_scaled_f_rec_rawIn_14.sign, _activated_data_e_scaled_f_rec_T_115) node _activated_data_e_scaled_f_rec_T_117 = bits(activated_data_e_scaled_f_rec_rawIn_14.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_118 = cat(_activated_data_e_scaled_f_rec_T_116, _activated_data_e_scaled_f_rec_T_117) node _activated_data_e_scaled_f_rec_T_119 = bits(activated_data_e_scaled_f_rec_rawIn_14.sig, 22, 0) node activated_data_e_scaled_f_rec_14 = cat(_activated_data_e_scaled_f_rec_T_118, _activated_data_e_scaled_f_rec_T_119) inst activated_data_e_scaled_in_to_rec_fn_14 of INToRecFN_i32_e8_s24_14 connect activated_data_e_scaled_in_to_rec_fn_14.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_14 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_14 = asUInt(activated_data_e_act_14) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_14, _activated_data_e_scaled_in_to_rec_fn_io_in_T_14 connect activated_data_e_scaled_in_to_rec_fn_14.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_14 connect activated_data_e_scaled_in_to_rec_fn_14.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_14.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_14 of MulAddRecFN_e8_s24_18 connect activated_data_e_scaled_muladder_14.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_14.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_14.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_14.io.a, activated_data_e_scaled_in_to_rec_fn_14.io.out connect activated_data_e_scaled_muladder_14.io.b, activated_data_e_scaled_f_rec_14 connect activated_data_e_scaled_muladder_14.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_14 of RecFNToIN_e8_s24_i32_14 connect activated_data_e_scaled_rec_fn_to_in_14.clock, clock connect activated_data_e_scaled_rec_fn_to_in_14.reset, reset connect activated_data_e_scaled_rec_fn_to_in_14.io.in, activated_data_e_scaled_muladder_14.io.out connect activated_data_e_scaled_rec_fn_to_in_14.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_14.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_14 = bits(activated_data_e_scaled_rec_fn_to_in_14.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_14 = bits(activated_data_e_scaled_rec_fn_to_in_14.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_14 = bits(activated_data_e_scaled_sign_exp_14, 8, 6) node activated_data_e_scaled_sign_isZero_14 = eq(_activated_data_e_scaled_sign_isZero_T_14, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_14 = bits(activated_data_e_scaled_sign_exp_14, 8, 7) node activated_data_e_scaled_sign_isSpecial_14 = eq(_activated_data_e_scaled_sign_isSpecial_T_14, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_14 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_28 = bits(activated_data_e_scaled_sign_exp_14, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_29 = and(activated_data_e_scaled_sign_isSpecial_14, _activated_data_e_scaled_sign_out_isNaN_T_28) connect activated_data_e_scaled_sign_out_14.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_29 node _activated_data_e_scaled_sign_out_isInf_T_42 = bits(activated_data_e_scaled_sign_exp_14, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_43 = eq(_activated_data_e_scaled_sign_out_isInf_T_42, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_44 = and(activated_data_e_scaled_sign_isSpecial_14, _activated_data_e_scaled_sign_out_isInf_T_43) connect activated_data_e_scaled_sign_out_14.isInf, _activated_data_e_scaled_sign_out_isInf_T_44 connect activated_data_e_scaled_sign_out_14.isZero, activated_data_e_scaled_sign_isZero_14 node _activated_data_e_scaled_sign_out_sign_T_14 = bits(activated_data_e_scaled_rec_fn_to_in_14.io.in, 32, 32) connect activated_data_e_scaled_sign_out_14.sign, _activated_data_e_scaled_sign_out_sign_T_14 node _activated_data_e_scaled_sign_out_sExp_T_14 = cvt(activated_data_e_scaled_sign_exp_14) connect activated_data_e_scaled_sign_out_14.sExp, _activated_data_e_scaled_sign_out_sExp_T_14 node _activated_data_e_scaled_sign_out_sig_T_56 = eq(activated_data_e_scaled_sign_isZero_14, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_57 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_56) node _activated_data_e_scaled_sign_out_sig_T_58 = bits(activated_data_e_scaled_rec_fn_to_in_14.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_59 = cat(_activated_data_e_scaled_sign_out_sig_T_57, _activated_data_e_scaled_sign_out_sig_T_58) connect activated_data_e_scaled_sign_out_14.sig, _activated_data_e_scaled_sign_out_sig_T_59 node activated_data_e_scaled_sat_14 = mux(activated_data_e_scaled_sign_out_14.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_74 : SInt<32> node _activated_data_e_scaled_T_164 = asSInt(activated_data_e_scaled_rec_fn_to_in_14.io.out) connect _activated_data_e_scaled_WIRE_74, _activated_data_e_scaled_T_164 node activated_data_e_scaled_14 = mux(activated_data_e_scaled_overflow_14, activated_data_e_scaled_sat_14, _activated_data_e_scaled_WIRE_74) node _activated_data_e_clipped_T_70 = gt(activated_data_e_scaled_14, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_71 = lt(activated_data_e_scaled_14, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_72 = mux(_activated_data_e_clipped_T_71, asSInt(UInt<8>(0h80)), activated_data_e_scaled_14) node _activated_data_e_clipped_T_73 = mux(_activated_data_e_clipped_T_70, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_72) node _activated_data_e_clipped_T_74 = bits(_activated_data_e_clipped_T_73, 7, 0) node activated_data_e_clipped_14 = asSInt(_activated_data_e_clipped_T_74) wire _activated_data_WIRE_14 : SInt<8>[1] connect _activated_data_WIRE_14[0], activated_data_e_clipped_14 node _activated_data_e_act_T_480 = eq(io.in.bits.acc_read_resp.act, UInt<1>(0h1)) node _activated_data_e_act_T_481 = and(UInt<1>(0h1), _activated_data_e_act_T_480) node _activated_data_e_act_T_482 = geq(io.in.bits.acc_read_resp.data[15][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_483 = mux(_activated_data_e_act_T_482, io.in.bits.acc_read_resp.data[15][0], asSInt(UInt<1>(0h0))) node _activated_data_e_act_T_484 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_485 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_act_T_486 = and(_activated_data_e_act_T_484, _activated_data_e_act_T_485) node _activated_data_e_act_T_487 = sub(io.in.bits.acc_read_resp.data[15][0], io.in.bits.mean) node _activated_data_e_act_T_488 = tail(_activated_data_e_act_T_487, 1) node _activated_data_e_act_T_489 = asSInt(_activated_data_e_act_T_488) node _activated_data_e_act_T_490 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_491 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h3)) node _activated_data_e_act_T_492 = and(_activated_data_e_act_T_490, _activated_data_e_act_T_491) node _activated_data_e_act_q_sign_T_60 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[15][0]) node _activated_data_e_act_q_sign_T_61 = sub(asSInt(UInt<1>(0h0)), asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_sign_T_62 = tail(_activated_data_e_act_q_sign_T_61, 1) node _activated_data_e_act_q_sign_T_63 = asSInt(_activated_data_e_act_q_sign_T_62) node activated_data_e_act_q_sign_15 = mux(_activated_data_e_act_q_sign_T_60, _activated_data_e_act_q_sign_T_63, asSInt(UInt<2>(0h1))) node _activated_data_e_act_q_abs_T_60 = gt(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[15][0]) node _activated_data_e_act_q_abs_T_61 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.data[15][0]) node _activated_data_e_act_q_abs_T_62 = tail(_activated_data_e_act_q_abs_T_61, 1) node _activated_data_e_act_q_abs_T_63 = asSInt(_activated_data_e_act_q_abs_T_62) node activated_data_e_act_q_abs_15 = mux(_activated_data_e_act_q_abs_T_60, _activated_data_e_act_q_abs_T_63, io.in.bits.acc_read_resp.data[15][0]) node _activated_data_e_act_q_clipped_T_105 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_106 = tail(_activated_data_e_act_q_clipped_T_105, 1) node _activated_data_e_act_q_clipped_T_107 = asSInt(_activated_data_e_act_q_clipped_T_106) node _activated_data_e_act_q_clipped_T_108 = gt(activated_data_e_act_q_abs_15, _activated_data_e_act_q_clipped_T_107) node _activated_data_e_act_q_clipped_T_109 = sub(asSInt(UInt<1>(0h0)), io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_clipped_T_110 = tail(_activated_data_e_act_q_clipped_T_109, 1) node _activated_data_e_act_q_clipped_T_111 = asSInt(_activated_data_e_act_q_clipped_T_110) node activated_data_e_act_q_clipped_15 = mux(_activated_data_e_act_q_clipped_T_108, _activated_data_e_act_q_clipped_T_111, activated_data_e_act_q_abs_15) node _activated_data_e_act_q_poly_T_165 = add(activated_data_e_act_q_clipped_15, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_166 = tail(_activated_data_e_act_q_poly_T_165, 1) node _activated_data_e_act_q_poly_T_167 = asSInt(_activated_data_e_act_q_poly_T_166) node _activated_data_e_act_q_poly_T_168 = add(activated_data_e_act_q_clipped_15, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_T_169 = tail(_activated_data_e_act_q_poly_T_168, 1) node _activated_data_e_act_q_poly_T_170 = asSInt(_activated_data_e_act_q_poly_T_169) node _activated_data_e_act_q_poly_T_171 = mul(_activated_data_e_act_q_poly_T_167, _activated_data_e_act_q_poly_T_170) node _activated_data_e_act_q_poly_T_172 = add(_activated_data_e_act_q_poly_T_171, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_T_173 = tail(_activated_data_e_act_q_poly_T_172, 1) node _activated_data_e_act_q_poly_T_174 = asSInt(_activated_data_e_act_q_poly_T_173) node _activated_data_e_act_q_poly_T_175 = bits(_activated_data_e_act_q_poly_T_174, 31, 0) node activated_data_e_act_q_poly_15 = asSInt(_activated_data_e_act_q_poly_T_175) node _activated_data_e_act_q_erf_T_30 = mul(activated_data_e_act_q_sign_15, activated_data_e_act_q_poly_15) node _activated_data_e_act_q_erf_T_31 = bits(_activated_data_e_act_q_erf_T_30, 31, 0) node activated_data_e_act_q_erf_15 = asSInt(_activated_data_e_act_q_erf_T_31) node _activated_data_e_act_T_493 = add(activated_data_e_act_q_erf_15, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_T_494 = tail(_activated_data_e_act_T_493, 1) node _activated_data_e_act_T_495 = asSInt(_activated_data_e_act_T_494) node _activated_data_e_act_T_496 = mul(io.in.bits.acc_read_resp.data[15][0], _activated_data_e_act_T_495) node _activated_data_e_act_T_497 = bits(_activated_data_e_act_T_496, 31, 0) node _activated_data_e_act_T_498 = asSInt(_activated_data_e_act_T_497) node _activated_data_e_act_T_499 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_act_T_500 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_act_T_501 = and(_activated_data_e_act_T_499, _activated_data_e_act_T_500) node _activated_data_e_act_T_502 = sub(io.in.bits.acc_read_resp.data[15][0], io.in.bits.max) node _activated_data_e_act_T_503 = tail(_activated_data_e_act_T_502, 1) node _activated_data_e_act_T_504 = asSInt(_activated_data_e_act_T_503) node _activated_data_e_act_neg_q_iexp_T_30 = sub(asSInt(UInt<1>(0h0)), _activated_data_e_act_T_504) node _activated_data_e_act_neg_q_iexp_T_31 = tail(_activated_data_e_act_neg_q_iexp_T_30, 1) node activated_data_e_act_neg_q_iexp_15 = asSInt(_activated_data_e_act_neg_q_iexp_T_31) node _activated_data_e_act_z_iexp_T_60 = mul(activated_data_e_act_neg_q_iexp_15, io.in.bits.acc_read_resp.iexp_qln2_inv) node _activated_data_e_act_z_iexp_T_61 = asUInt(_activated_data_e_act_z_iexp_T_60) node _activated_data_e_act_z_iexp_T_62 = shr(_activated_data_e_act_z_iexp_T_61, 16) wire activated_data_e_act_z_iexp_15 : SInt<32> node _activated_data_e_act_z_iexp_T_63 = asSInt(_activated_data_e_act_z_iexp_T_62) connect activated_data_e_act_z_iexp_15, _activated_data_e_act_z_iexp_T_63 wire activated_data_e_act_z_iexp_saturated_15 : SInt<32> node _activated_data_e_act_z_iexp_saturated_T_495 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_496 = bits(_activated_data_e_act_z_iexp_saturated_T_495, 5, 5) node _activated_data_e_act_z_iexp_saturated_T_497 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_498 = bits(_activated_data_e_act_z_iexp_saturated_T_497, 6, 6) node _activated_data_e_act_z_iexp_saturated_T_499 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_500 = bits(_activated_data_e_act_z_iexp_saturated_T_499, 7, 7) node _activated_data_e_act_z_iexp_saturated_T_501 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_502 = bits(_activated_data_e_act_z_iexp_saturated_T_501, 8, 8) node _activated_data_e_act_z_iexp_saturated_T_503 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_504 = bits(_activated_data_e_act_z_iexp_saturated_T_503, 9, 9) node _activated_data_e_act_z_iexp_saturated_T_505 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_506 = bits(_activated_data_e_act_z_iexp_saturated_T_505, 10, 10) node _activated_data_e_act_z_iexp_saturated_T_507 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_508 = bits(_activated_data_e_act_z_iexp_saturated_T_507, 11, 11) node _activated_data_e_act_z_iexp_saturated_T_509 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_510 = bits(_activated_data_e_act_z_iexp_saturated_T_509, 12, 12) node _activated_data_e_act_z_iexp_saturated_T_511 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_512 = bits(_activated_data_e_act_z_iexp_saturated_T_511, 13, 13) node _activated_data_e_act_z_iexp_saturated_T_513 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_514 = bits(_activated_data_e_act_z_iexp_saturated_T_513, 14, 14) node _activated_data_e_act_z_iexp_saturated_T_515 = asUInt(activated_data_e_act_z_iexp_15) node _activated_data_e_act_z_iexp_saturated_T_516 = bits(_activated_data_e_act_z_iexp_saturated_T_515, 15, 15) node _activated_data_e_act_z_iexp_saturated_T_517 = or(_activated_data_e_act_z_iexp_saturated_T_496, _activated_data_e_act_z_iexp_saturated_T_498) node _activated_data_e_act_z_iexp_saturated_T_518 = or(_activated_data_e_act_z_iexp_saturated_T_517, _activated_data_e_act_z_iexp_saturated_T_500) node _activated_data_e_act_z_iexp_saturated_T_519 = or(_activated_data_e_act_z_iexp_saturated_T_518, _activated_data_e_act_z_iexp_saturated_T_502) node _activated_data_e_act_z_iexp_saturated_T_520 = or(_activated_data_e_act_z_iexp_saturated_T_519, _activated_data_e_act_z_iexp_saturated_T_504) node _activated_data_e_act_z_iexp_saturated_T_521 = or(_activated_data_e_act_z_iexp_saturated_T_520, _activated_data_e_act_z_iexp_saturated_T_506) node _activated_data_e_act_z_iexp_saturated_T_522 = or(_activated_data_e_act_z_iexp_saturated_T_521, _activated_data_e_act_z_iexp_saturated_T_508) node _activated_data_e_act_z_iexp_saturated_T_523 = or(_activated_data_e_act_z_iexp_saturated_T_522, _activated_data_e_act_z_iexp_saturated_T_510) node _activated_data_e_act_z_iexp_saturated_T_524 = or(_activated_data_e_act_z_iexp_saturated_T_523, _activated_data_e_act_z_iexp_saturated_T_512) node _activated_data_e_act_z_iexp_saturated_T_525 = or(_activated_data_e_act_z_iexp_saturated_T_524, _activated_data_e_act_z_iexp_saturated_T_514) node _activated_data_e_act_z_iexp_saturated_T_526 = or(_activated_data_e_act_z_iexp_saturated_T_525, _activated_data_e_act_z_iexp_saturated_T_516) wire _activated_data_e_act_z_iexp_saturated_WIRE_15 : SInt<32> connect _activated_data_e_act_z_iexp_saturated_WIRE_15, asSInt(UInt<7>(0h20)) node _activated_data_e_act_z_iexp_saturated_T_527 = mux(_activated_data_e_act_z_iexp_saturated_T_526, _activated_data_e_act_z_iexp_saturated_WIRE_15, activated_data_e_act_z_iexp_15) connect activated_data_e_act_z_iexp_saturated_15, _activated_data_e_act_z_iexp_saturated_T_527 node _activated_data_e_act_qp_iexp_T_75 = mul(activated_data_e_act_z_iexp_15, io.in.bits.acc_read_resp.iexp_qln2) node _activated_data_e_act_qp_iexp_T_76 = add(_activated_data_e_act_qp_iexp_T_75, _activated_data_e_act_T_504) node _activated_data_e_act_qp_iexp_T_77 = tail(_activated_data_e_act_qp_iexp_T_76, 1) node _activated_data_e_act_qp_iexp_T_78 = asSInt(_activated_data_e_act_qp_iexp_T_77) node _activated_data_e_act_qp_iexp_T_79 = bits(_activated_data_e_act_qp_iexp_T_78, 31, 0) node activated_data_e_act_qp_iexp_15 = asSInt(_activated_data_e_act_qp_iexp_T_79) node _activated_data_e_act_q_poly_iexp_T_165 = add(activated_data_e_act_qp_iexp_15, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_166 = tail(_activated_data_e_act_q_poly_iexp_T_165, 1) node _activated_data_e_act_q_poly_iexp_T_167 = asSInt(_activated_data_e_act_q_poly_iexp_T_166) node _activated_data_e_act_q_poly_iexp_T_168 = add(activated_data_e_act_qp_iexp_15, io.in.bits.acc_read_resp.igelu_qb) node _activated_data_e_act_q_poly_iexp_T_169 = tail(_activated_data_e_act_q_poly_iexp_T_168, 1) node _activated_data_e_act_q_poly_iexp_T_170 = asSInt(_activated_data_e_act_q_poly_iexp_T_169) node _activated_data_e_act_q_poly_iexp_T_171 = mul(_activated_data_e_act_q_poly_iexp_T_167, _activated_data_e_act_q_poly_iexp_T_170) node _activated_data_e_act_q_poly_iexp_T_172 = add(_activated_data_e_act_q_poly_iexp_T_171, io.in.bits.acc_read_resp.igelu_qc) node _activated_data_e_act_q_poly_iexp_T_173 = tail(_activated_data_e_act_q_poly_iexp_T_172, 1) node _activated_data_e_act_q_poly_iexp_T_174 = asSInt(_activated_data_e_act_q_poly_iexp_T_173) node _activated_data_e_act_q_poly_iexp_T_175 = bits(_activated_data_e_act_q_poly_iexp_T_174, 31, 0) node activated_data_e_act_q_poly_iexp_15 = asSInt(_activated_data_e_act_q_poly_iexp_T_175) node _activated_data_e_act_T_505 = asUInt(activated_data_e_act_q_poly_iexp_15) node _activated_data_e_act_T_506 = asUInt(activated_data_e_act_z_iexp_saturated_15) node _activated_data_e_act_T_507 = dshr(_activated_data_e_act_T_505, _activated_data_e_act_T_506) wire _activated_data_e_act_WIRE_15 : SInt<32> node _activated_data_e_act_T_508 = asSInt(_activated_data_e_act_T_507) connect _activated_data_e_act_WIRE_15, _activated_data_e_act_T_508 node _activated_data_e_act_T_509 = mux(_activated_data_e_act_T_501, _activated_data_e_act_WIRE_15, io.in.bits.acc_read_resp.data[15][0]) node _activated_data_e_act_T_510 = mux(_activated_data_e_act_T_492, _activated_data_e_act_T_498, _activated_data_e_act_T_509) node _activated_data_e_act_T_511 = mux(_activated_data_e_act_T_486, _activated_data_e_act_T_489, _activated_data_e_act_T_510) node activated_data_e_act_15 = mux(_activated_data_e_act_T_481, _activated_data_e_act_T_483, _activated_data_e_act_T_511) node _activated_data_e_scaled_T_165 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_166 = eq(io.in.bits.acc_read_resp.act, UInt<2>(0h2)) node _activated_data_e_scaled_T_167 = and(_activated_data_e_scaled_T_165, _activated_data_e_scaled_T_166) node _activated_data_e_scaled_T_168 = and(UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_T_169 = eq(io.in.bits.acc_read_resp.act, UInt<3>(0h4)) node _activated_data_e_scaled_T_170 = and(_activated_data_e_scaled_T_168, _activated_data_e_scaled_T_169) wire _activated_data_e_scaled_WIRE_75 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_76 : UInt<32> connect _activated_data_e_scaled_WIRE_76, io.in.bits.inv_sum_exp.bits node _activated_data_e_scaled_T_171 = bits(_activated_data_e_scaled_WIRE_76, 31, 0) connect _activated_data_e_scaled_WIRE_75.bits, _activated_data_e_scaled_T_171 node _activated_data_e_scaled_T_172 = mux(_activated_data_e_scaled_T_170, _activated_data_e_scaled_WIRE_75, io.in.bits.acc_read_resp.scale) node _activated_data_e_scaled_T_173 = mux(_activated_data_e_scaled_T_167, io.in.bits.inv_stddev, _activated_data_e_scaled_T_172) wire _activated_data_e_scaled_WIRE_77 : { bits : UInt<32>} wire _activated_data_e_scaled_WIRE_78 : UInt<32> connect _activated_data_e_scaled_WIRE_78, _activated_data_e_scaled_T_173.bits node _activated_data_e_scaled_T_174 = bits(_activated_data_e_scaled_WIRE_78, 31, 0) connect _activated_data_e_scaled_WIRE_77.bits, _activated_data_e_scaled_T_174 node activated_data_e_scaled_f_rec_rawIn_sign_15 = bits(_activated_data_e_scaled_WIRE_77.bits, 31, 31) node activated_data_e_scaled_f_rec_rawIn_expIn_15 = bits(_activated_data_e_scaled_WIRE_77.bits, 30, 23) node activated_data_e_scaled_f_rec_rawIn_fractIn_15 = bits(_activated_data_e_scaled_WIRE_77.bits, 22, 0) node activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 = eq(activated_data_e_scaled_f_rec_rawIn_expIn_15, UInt<1>(0h0)) node activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15 = eq(activated_data_e_scaled_f_rec_rawIn_fractIn_15, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_660 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 0, 0) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_661 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 1, 1) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_662 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 2, 2) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_663 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 3, 3) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_664 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 4, 4) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_665 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 5, 5) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_666 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 6, 6) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_667 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 7, 7) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_668 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 8, 8) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_669 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 9, 9) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_670 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 10, 10) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_671 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 11, 11) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_672 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 12, 12) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_673 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 13, 13) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_674 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 14, 14) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_675 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 15, 15) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_676 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 16, 16) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_677 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 17, 17) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_678 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 18, 18) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_679 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 19, 19) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_680 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 20, 20) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_681 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 21, 21) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_682 = bits(activated_data_e_scaled_f_rec_rawIn_fractIn_15, 22, 22) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_683 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_661, UInt<5>(0h15), UInt<5>(0h16)) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_684 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_662, UInt<5>(0h14), _activated_data_e_scaled_f_rec_rawIn_normDist_T_683) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_685 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_663, UInt<5>(0h13), _activated_data_e_scaled_f_rec_rawIn_normDist_T_684) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_686 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_664, UInt<5>(0h12), _activated_data_e_scaled_f_rec_rawIn_normDist_T_685) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_687 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_665, UInt<5>(0h11), _activated_data_e_scaled_f_rec_rawIn_normDist_T_686) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_688 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_666, UInt<5>(0h10), _activated_data_e_scaled_f_rec_rawIn_normDist_T_687) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_689 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_667, UInt<4>(0hf), _activated_data_e_scaled_f_rec_rawIn_normDist_T_688) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_690 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_668, UInt<4>(0he), _activated_data_e_scaled_f_rec_rawIn_normDist_T_689) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_691 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_669, UInt<4>(0hd), _activated_data_e_scaled_f_rec_rawIn_normDist_T_690) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_692 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_670, UInt<4>(0hc), _activated_data_e_scaled_f_rec_rawIn_normDist_T_691) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_693 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_671, UInt<4>(0hb), _activated_data_e_scaled_f_rec_rawIn_normDist_T_692) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_694 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_672, UInt<4>(0ha), _activated_data_e_scaled_f_rec_rawIn_normDist_T_693) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_695 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_673, UInt<4>(0h9), _activated_data_e_scaled_f_rec_rawIn_normDist_T_694) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_696 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_674, UInt<4>(0h8), _activated_data_e_scaled_f_rec_rawIn_normDist_T_695) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_697 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_675, UInt<3>(0h7), _activated_data_e_scaled_f_rec_rawIn_normDist_T_696) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_698 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_676, UInt<3>(0h6), _activated_data_e_scaled_f_rec_rawIn_normDist_T_697) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_699 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_677, UInt<3>(0h5), _activated_data_e_scaled_f_rec_rawIn_normDist_T_698) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_700 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_678, UInt<3>(0h4), _activated_data_e_scaled_f_rec_rawIn_normDist_T_699) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_701 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_679, UInt<2>(0h3), _activated_data_e_scaled_f_rec_rawIn_normDist_T_700) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_702 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_680, UInt<2>(0h2), _activated_data_e_scaled_f_rec_rawIn_normDist_T_701) node _activated_data_e_scaled_f_rec_rawIn_normDist_T_703 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_681, UInt<1>(0h1), _activated_data_e_scaled_f_rec_rawIn_normDist_T_702) node activated_data_e_scaled_f_rec_rawIn_normDist_15 = mux(_activated_data_e_scaled_f_rec_rawIn_normDist_T_682, UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_normDist_T_703) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_30 = dshl(activated_data_e_scaled_f_rec_rawIn_fractIn_15, activated_data_e_scaled_f_rec_rawIn_normDist_15) node _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_31 = bits(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_30, 21, 0) node activated_data_e_scaled_f_rec_rawIn_subnormFract_15 = shl(_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_31, 1) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_75 = xor(activated_data_e_scaled_f_rec_rawIn_normDist_15, UInt<9>(0h1ff)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_76 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_75, activated_data_e_scaled_f_rec_rawIn_expIn_15) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_77 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15, UInt<2>(0h2), UInt<1>(0h1)) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_78 = or(UInt<8>(0h80), _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_77) node _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_79 = add(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_76, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_78) node activated_data_e_scaled_f_rec_rawIn_adjustedExp_15 = tail(_activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_79, 1) node activated_data_e_scaled_f_rec_rawIn_isZero_15 = and(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15) node _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_15 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_15, 8, 7) node activated_data_e_scaled_f_rec_rawIn_isSpecial_15 = eq(_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_15, UInt<2>(0h3)) wire activated_data_e_scaled_f_rec_rawIn_15 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_30 = eq(activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_31 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_15, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_30) connect activated_data_e_scaled_f_rec_rawIn_15.isNaN, _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_31 node _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_15 = and(activated_data_e_scaled_f_rec_rawIn_isSpecial_15, activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15) connect activated_data_e_scaled_f_rec_rawIn_15.isInf, _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_15 connect activated_data_e_scaled_f_rec_rawIn_15.isZero, activated_data_e_scaled_f_rec_rawIn_isZero_15 connect activated_data_e_scaled_f_rec_rawIn_15.sign, activated_data_e_scaled_f_rec_rawIn_sign_15 node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_30 = bits(activated_data_e_scaled_f_rec_rawIn_adjustedExp_15, 8, 0) node _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_31 = cvt(_activated_data_e_scaled_f_rec_rawIn_out_sExp_T_30) connect activated_data_e_scaled_f_rec_rawIn_15.sExp, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_31 node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_60 = eq(activated_data_e_scaled_f_rec_rawIn_isZero_15, UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_61 = cat(UInt<1>(0h0), _activated_data_e_scaled_f_rec_rawIn_out_sig_T_60) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_62 = mux(activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15, activated_data_e_scaled_f_rec_rawIn_subnormFract_15, activated_data_e_scaled_f_rec_rawIn_fractIn_15) node _activated_data_e_scaled_f_rec_rawIn_out_sig_T_63 = cat(_activated_data_e_scaled_f_rec_rawIn_out_sig_T_61, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_62) connect activated_data_e_scaled_f_rec_rawIn_15.sig, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_63 node _activated_data_e_scaled_f_rec_T_120 = bits(activated_data_e_scaled_f_rec_rawIn_15.sExp, 8, 6) node _activated_data_e_scaled_f_rec_T_121 = mux(activated_data_e_scaled_f_rec_rawIn_15.isZero, UInt<3>(0h0), _activated_data_e_scaled_f_rec_T_120) node _activated_data_e_scaled_f_rec_T_122 = mux(activated_data_e_scaled_f_rec_rawIn_15.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _activated_data_e_scaled_f_rec_T_123 = or(_activated_data_e_scaled_f_rec_T_121, _activated_data_e_scaled_f_rec_T_122) node _activated_data_e_scaled_f_rec_T_124 = cat(activated_data_e_scaled_f_rec_rawIn_15.sign, _activated_data_e_scaled_f_rec_T_123) node _activated_data_e_scaled_f_rec_T_125 = bits(activated_data_e_scaled_f_rec_rawIn_15.sExp, 5, 0) node _activated_data_e_scaled_f_rec_T_126 = cat(_activated_data_e_scaled_f_rec_T_124, _activated_data_e_scaled_f_rec_T_125) node _activated_data_e_scaled_f_rec_T_127 = bits(activated_data_e_scaled_f_rec_rawIn_15.sig, 22, 0) node activated_data_e_scaled_f_rec_15 = cat(_activated_data_e_scaled_f_rec_T_126, _activated_data_e_scaled_f_rec_T_127) inst activated_data_e_scaled_in_to_rec_fn_15 of INToRecFN_i32_e8_s24_15 connect activated_data_e_scaled_in_to_rec_fn_15.io.signedIn, UInt<1>(0h1) wire _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_15 : UInt<32> node _activated_data_e_scaled_in_to_rec_fn_io_in_T_15 = asUInt(activated_data_e_act_15) connect _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_15, _activated_data_e_scaled_in_to_rec_fn_io_in_T_15 connect activated_data_e_scaled_in_to_rec_fn_15.io.in, _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_15 connect activated_data_e_scaled_in_to_rec_fn_15.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_in_to_rec_fn_15.io.detectTininess, UInt<1>(0h1) inst activated_data_e_scaled_muladder_15 of MulAddRecFN_e8_s24_19 connect activated_data_e_scaled_muladder_15.io.op, UInt<1>(0h0) connect activated_data_e_scaled_muladder_15.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_muladder_15.io.detectTininess, UInt<1>(0h1) connect activated_data_e_scaled_muladder_15.io.a, activated_data_e_scaled_in_to_rec_fn_15.io.out connect activated_data_e_scaled_muladder_15.io.b, activated_data_e_scaled_f_rec_15 connect activated_data_e_scaled_muladder_15.io.c, UInt<1>(0h0) inst activated_data_e_scaled_rec_fn_to_in_15 of RecFNToIN_e8_s24_i32_15 connect activated_data_e_scaled_rec_fn_to_in_15.clock, clock connect activated_data_e_scaled_rec_fn_to_in_15.reset, reset connect activated_data_e_scaled_rec_fn_to_in_15.io.in, activated_data_e_scaled_muladder_15.io.out connect activated_data_e_scaled_rec_fn_to_in_15.io.roundingMode, UInt<3>(0h0) connect activated_data_e_scaled_rec_fn_to_in_15.io.signedOut, UInt<1>(0h1) node activated_data_e_scaled_overflow_15 = bits(activated_data_e_scaled_rec_fn_to_in_15.io.intExceptionFlags, 1, 1) node activated_data_e_scaled_sign_exp_15 = bits(activated_data_e_scaled_rec_fn_to_in_15.io.in, 31, 23) node _activated_data_e_scaled_sign_isZero_T_15 = bits(activated_data_e_scaled_sign_exp_15, 8, 6) node activated_data_e_scaled_sign_isZero_15 = eq(_activated_data_e_scaled_sign_isZero_T_15, UInt<1>(0h0)) node _activated_data_e_scaled_sign_isSpecial_T_15 = bits(activated_data_e_scaled_sign_exp_15, 8, 7) node activated_data_e_scaled_sign_isSpecial_15 = eq(_activated_data_e_scaled_sign_isSpecial_T_15, UInt<2>(0h3)) wire activated_data_e_scaled_sign_out_15 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _activated_data_e_scaled_sign_out_isNaN_T_30 = bits(activated_data_e_scaled_sign_exp_15, 6, 6) node _activated_data_e_scaled_sign_out_isNaN_T_31 = and(activated_data_e_scaled_sign_isSpecial_15, _activated_data_e_scaled_sign_out_isNaN_T_30) connect activated_data_e_scaled_sign_out_15.isNaN, _activated_data_e_scaled_sign_out_isNaN_T_31 node _activated_data_e_scaled_sign_out_isInf_T_45 = bits(activated_data_e_scaled_sign_exp_15, 6, 6) node _activated_data_e_scaled_sign_out_isInf_T_46 = eq(_activated_data_e_scaled_sign_out_isInf_T_45, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_isInf_T_47 = and(activated_data_e_scaled_sign_isSpecial_15, _activated_data_e_scaled_sign_out_isInf_T_46) connect activated_data_e_scaled_sign_out_15.isInf, _activated_data_e_scaled_sign_out_isInf_T_47 connect activated_data_e_scaled_sign_out_15.isZero, activated_data_e_scaled_sign_isZero_15 node _activated_data_e_scaled_sign_out_sign_T_15 = bits(activated_data_e_scaled_rec_fn_to_in_15.io.in, 32, 32) connect activated_data_e_scaled_sign_out_15.sign, _activated_data_e_scaled_sign_out_sign_T_15 node _activated_data_e_scaled_sign_out_sExp_T_15 = cvt(activated_data_e_scaled_sign_exp_15) connect activated_data_e_scaled_sign_out_15.sExp, _activated_data_e_scaled_sign_out_sExp_T_15 node _activated_data_e_scaled_sign_out_sig_T_60 = eq(activated_data_e_scaled_sign_isZero_15, UInt<1>(0h0)) node _activated_data_e_scaled_sign_out_sig_T_61 = cat(UInt<1>(0h0), _activated_data_e_scaled_sign_out_sig_T_60) node _activated_data_e_scaled_sign_out_sig_T_62 = bits(activated_data_e_scaled_rec_fn_to_in_15.io.in, 22, 0) node _activated_data_e_scaled_sign_out_sig_T_63 = cat(_activated_data_e_scaled_sign_out_sig_T_61, _activated_data_e_scaled_sign_out_sig_T_62) connect activated_data_e_scaled_sign_out_15.sig, _activated_data_e_scaled_sign_out_sig_T_63 node activated_data_e_scaled_sat_15 = mux(activated_data_e_scaled_sign_out_15.sign, asSInt(UInt<32>(0h80000000)), asSInt(UInt<32>(0h7fffffff))) wire _activated_data_e_scaled_WIRE_79 : SInt<32> node _activated_data_e_scaled_T_175 = asSInt(activated_data_e_scaled_rec_fn_to_in_15.io.out) connect _activated_data_e_scaled_WIRE_79, _activated_data_e_scaled_T_175 node activated_data_e_scaled_15 = mux(activated_data_e_scaled_overflow_15, activated_data_e_scaled_sat_15, _activated_data_e_scaled_WIRE_79) node _activated_data_e_clipped_T_75 = gt(activated_data_e_scaled_15, asSInt(UInt<8>(0h7f))) node _activated_data_e_clipped_T_76 = lt(activated_data_e_scaled_15, asSInt(UInt<8>(0h80))) node _activated_data_e_clipped_T_77 = mux(_activated_data_e_clipped_T_76, asSInt(UInt<8>(0h80)), activated_data_e_scaled_15) node _activated_data_e_clipped_T_78 = mux(_activated_data_e_clipped_T_75, asSInt(UInt<8>(0h7f)), _activated_data_e_clipped_T_77) node _activated_data_e_clipped_T_79 = bits(_activated_data_e_clipped_T_78, 7, 0) node activated_data_e_clipped_15 = asSInt(_activated_data_e_clipped_T_79) wire _activated_data_WIRE_15 : SInt<8>[1] connect _activated_data_WIRE_15[0], activated_data_e_clipped_15 wire activated_data : SInt<8>[1][16] connect activated_data[0], _activated_data_WIRE connect activated_data[1], _activated_data_WIRE_1 connect activated_data[2], _activated_data_WIRE_2 connect activated_data[3], _activated_data_WIRE_3 connect activated_data[4], _activated_data_WIRE_4 connect activated_data[5], _activated_data_WIRE_5 connect activated_data[6], _activated_data_WIRE_6 connect activated_data[7], _activated_data_WIRE_7 connect activated_data[8], _activated_data_WIRE_8 connect activated_data[9], _activated_data_WIRE_9 connect activated_data[10], _activated_data_WIRE_10 connect activated_data[11], _activated_data_WIRE_11 connect activated_data[12], _activated_data_WIRE_12 connect activated_data[13], _activated_data_WIRE_13 connect activated_data[14], _activated_data_WIRE_14 connect activated_data[15], _activated_data_WIRE_15 wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { resp : { data : SInt<32>[1][16], fromDMA : UInt<1>, scale : { bits : UInt<32>}, igelu_qb : SInt<32>, igelu_qc : SInt<32>, iexp_qln2 : SInt<32>, iexp_qln2_inv : SInt<32>, act : UInt<3>, acc_bank_id : UInt<2>}, full_data : SInt<32>[1][16]}} connect in.valid, io.in.valid connect io.in.ready, in.ready connect in.bits.resp, io.in.bits.acc_read_resp connect in.bits.full_data, io.in.bits.acc_read_resp.data connect in.bits.resp.data, activated_data inst pipe_out_p of Pipeline_9 connect pipe_out_p.clock, clock connect pipe_out_p.reset, reset connect pipe_out_p.io.in, in connect out.valid, pipe_out_p.io.out.valid connect pipe_out_p.io.out.ready, out.ready connect out.bits.full_data, pipe_out_p.io.out.bits.full_data connect out.bits.data, pipe_out_p.io.out.bits.resp.data connect out.bits.fromDMA, pipe_out_p.io.out.bits.resp.fromDMA connect out.bits.acc_bank_id, pipe_out_p.io.out.bits.resp.acc_bank_id connect io.out, out connect io.out.bits.data, out.bits.data connect io.out.bits.full_data, out.bits.full_data	module AccumulatorScale( // @[AccumulatorScale.scala:88:7] input clock, // @[AccumulatorScale.scala:88:7] input reset, // @[AccumulatorScale.scala:88:7] output io_in_ready, // @[AccumulatorScale.scala:99:14] input io_in_valid, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_0_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_1_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_2_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_3_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_4_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_5_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_6_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_7_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_8_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_9_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_10_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_11_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_12_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_13_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_14_0, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_data_15_0, // @[AccumulatorScale.scala:99:14] input io_in_bits_acc_read_resp_fromDMA, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_scale_bits, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_igelu_qb, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_igelu_qc, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_iexp_qln2, // @[AccumulatorScale.scala:99:14] input [31:0] io_in_bits_acc_read_resp_iexp_qln2_inv, // @[AccumulatorScale.scala:99:14] input [2:0] io_in_bits_acc_read_resp_act, // @[AccumulatorScale.scala:99:14] input [1:0] io_in_bits_acc_read_resp_acc_bank_id, // @[AccumulatorScale.scala:99:14] input io_out_ready, // @[AccumulatorScale.scala:99:14] output io_out_valid, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_0_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_1_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_2_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_3_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_4_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_5_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_6_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_7_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_8_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_9_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_10_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_11_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_12_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_13_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_14_0, // @[AccumulatorScale.scala:99:14] output [31:0] io_out_bits_full_data_15_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_0_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_1_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_2_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_3_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_4_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_5_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_6_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_7_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_8_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_9_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_10_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_11_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_12_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_13_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_14_0, // @[AccumulatorScale.scala:99:14] output [7:0] io_out_bits_data_15_0, // @[AccumulatorScale.scala:99:14] output [1:0] io_out_bits_acc_bank_id, // @[AccumulatorScale.scala:99:14] output io_out_bits_fromDMA // @[AccumulatorScale.scala:99:14] ); wire activated_data_e_scaled_f_rec_rawIn_15_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_14_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_13_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_12_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_11_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_10_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_9_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_8_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire activated_data_e_scaled_f_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_0_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_1_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_2_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_3_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_4_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_5_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_6_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_7_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_8_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_9_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_10_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_11_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_12_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_13_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_14_0; // @[Pipeline.scala:75:19] wire [31:0] _pipe_out_p_io_out_bits_resp_data_15_0; // @[Pipeline.scala:75:19] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_15_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_15_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_15_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_14_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_14_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_14_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_13_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_13_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_13_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_12_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_12_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_12_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_11_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_11_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_11_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_10_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_10_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_10_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_9_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_9_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_9_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_8_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_8_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_8_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_7_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_7_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_7_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_6_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_6_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_6_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_5_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_5_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_5_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_4_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_4_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_4_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_3_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_3_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_3_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_2_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_2_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_2_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_1_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_1_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_1_io_out; // @[Configs.scala:118:34] wire [2:0] _activated_data_e_scaled_rec_fn_to_in_io_intExceptionFlags; // @[Configs.scala:135:34] wire [32:0] _activated_data_e_scaled_muladder_io_out; // @[Configs.scala:126:30] wire [32:0] _activated_data_e_scaled_in_to_rec_fn_io_out; // @[Configs.scala:118:34] wire io_in_valid_0 = io_in_valid; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_0_0_0 = io_in_bits_acc_read_resp_data_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_1_0_0 = io_in_bits_acc_read_resp_data_1_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_2_0_0 = io_in_bits_acc_read_resp_data_2_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_3_0_0 = io_in_bits_acc_read_resp_data_3_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_4_0_0 = io_in_bits_acc_read_resp_data_4_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_5_0_0 = io_in_bits_acc_read_resp_data_5_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_6_0_0 = io_in_bits_acc_read_resp_data_6_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_7_0_0 = io_in_bits_acc_read_resp_data_7_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_8_0_0 = io_in_bits_acc_read_resp_data_8_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_9_0_0 = io_in_bits_acc_read_resp_data_9_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_10_0_0 = io_in_bits_acc_read_resp_data_10_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_11_0_0 = io_in_bits_acc_read_resp_data_11_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_12_0_0 = io_in_bits_acc_read_resp_data_12_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_13_0_0 = io_in_bits_acc_read_resp_data_13_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_14_0_0 = io_in_bits_acc_read_resp_data_14_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_data_15_0_0 = io_in_bits_acc_read_resp_data_15_0; // @[AccumulatorScale.scala:88:7] wire io_in_bits_acc_read_resp_fromDMA_0 = io_in_bits_acc_read_resp_fromDMA; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_scale_bits_0 = io_in_bits_acc_read_resp_scale_bits; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_igelu_qb_0 = io_in_bits_acc_read_resp_igelu_qb; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_igelu_qc_0 = io_in_bits_acc_read_resp_igelu_qc; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_iexp_qln2_0 = io_in_bits_acc_read_resp_iexp_qln2; // @[AccumulatorScale.scala:88:7] wire [31:0] io_in_bits_acc_read_resp_iexp_qln2_inv_0 = io_in_bits_acc_read_resp_iexp_qln2_inv; // @[AccumulatorScale.scala:88:7] wire [2:0] io_in_bits_acc_read_resp_act_0 = io_in_bits_acc_read_resp_act; // @[AccumulatorScale.scala:88:7] wire [1:0] io_in_bits_acc_read_resp_acc_bank_id_0 = io_in_bits_acc_read_resp_acc_bank_id; // @[AccumulatorScale.scala:88:7] wire io_out_ready_0 = io_out_ready; // @[AccumulatorScale.scala:88:7] wire [2:0] _activated_data_e_act_q_sign_T_1 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_5 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_9 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_13 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_17 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_21 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_25 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_29 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_33 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_37 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_41 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_45 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_49 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_53 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_57 = 3'h7; // @[Arithmetic.scala:95:38] wire [2:0] _activated_data_e_act_q_sign_T_61 = 3'h7; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_2 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_3 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_6 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_7 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_10 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_11 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_14 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_15 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_18 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_19 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_22 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_23 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_26 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_27 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_30 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_31 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_34 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_35 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_38 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_39 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_42 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_43 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_46 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_47 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_50 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_51 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_54 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_55 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_58 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_59 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_62 = 2'h3; // @[Arithmetic.scala:95:38] wire [1:0] _activated_data_e_act_q_sign_T_63 = 2'h3; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_1 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_2 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_3 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_4 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_5 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_6 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_7 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_8 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_9 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_10 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_11 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_12 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_13 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_14 = 32'h20; // @[AccumulatorScale.scala:400:92] wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_15 = 32'h20; // @[AccumulatorScale.scala:400:92] wire _activated_data_e_act_T_4 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_6 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_10 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_12 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_19 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_21 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_2 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_3 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_5 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_36 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_38 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_42 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_44 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_51 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_53 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_11 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_13 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_14 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_16 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_68 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_70 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_74 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_76 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_83 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_85 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_22 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_24 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_25 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_27 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_100 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_102 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_106 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_108 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_115 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_117 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_33 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_35 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_36 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_38 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_132 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_134 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_138 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_140 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_147 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_149 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_44 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_46 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_47 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_49 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_164 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_166 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_170 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_172 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_179 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_181 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_55 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_57 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_58 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_60 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_196 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_198 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_202 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_204 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_211 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_213 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_66 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_68 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_69 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_71 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_228 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_230 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_234 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_236 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_243 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_245 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_77 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_79 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_80 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_82 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_260 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_262 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_266 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_268 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_275 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_277 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_88 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_90 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_91 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_93 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_292 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_294 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_298 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_300 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_307 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_309 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_99 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_101 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_102 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_104 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_324 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_326 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_330 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_332 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_339 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_341 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_110 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_112 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_113 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_115 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_356 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_358 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_362 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_364 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_371 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_373 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_121 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_123 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_124 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_126 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_388 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_390 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_394 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_396 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_403 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_405 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_132 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_134 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_135 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_137 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_420 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_422 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_426 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_428 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_435 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_437 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_143 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_145 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_146 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_148 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_452 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_454 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_458 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_460 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_467 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_469 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_154 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_156 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_157 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_159 = 1'h0; // @[AccumulatorScale.scala:130:62] wire _activated_data_e_act_T_484 = 1'h0; // @[AccumulatorScale.scala:119:38] wire _activated_data_e_act_T_486 = 1'h0; // @[AccumulatorScale.scala:119:62] wire _activated_data_e_act_T_490 = 1'h0; // @[AccumulatorScale.scala:121:38] wire _activated_data_e_act_T_492 = 1'h0; // @[AccumulatorScale.scala:121:62] wire _activated_data_e_act_T_499 = 1'h0; // @[AccumulatorScale.scala:123:38] wire _activated_data_e_act_T_501 = 1'h0; // @[AccumulatorScale.scala:123:62] wire _activated_data_e_scaled_T_165 = 1'h0; // @[AccumulatorScale.scala:128:38] wire _activated_data_e_scaled_T_167 = 1'h0; // @[AccumulatorScale.scala:128:62] wire _activated_data_e_scaled_T_168 = 1'h0; // @[AccumulatorScale.scala:130:38] wire _activated_data_e_scaled_T_170 = 1'h0; // @[AccumulatorScale.scala:130:62] wire [31:0] io_in_bits_mean = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] io_in_bits_max = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] io_in_bits_inv_stddev_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] io_in_bits_inv_sum_exp_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_1 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_6 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_5_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_6 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_17 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_10_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_11 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_28 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_15_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_16 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_39 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_20_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_21 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_50 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_25_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_26 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_61 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_30_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_31 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_72 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_35_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_36 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_83 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_40_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_41 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_94 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_45_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_46 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_105 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_50_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_51 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_116 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_55_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_56 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_127 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_60_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_61 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_138 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_65_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_66 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_149 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_70_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_71 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_160 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_75_bits = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_WIRE_76 = 32'h0; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_scaled_T_171 = 32'h0; // @[Arithmetic.scala:128:42] wire in_ready; // @[AccumulatorScale.scala:139:18] wire in_valid = io_in_valid_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_29 = io_in_bits_acc_read_resp_data_0_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_0_0 = io_in_bits_acc_read_resp_data_0_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_61 = io_in_bits_acc_read_resp_data_1_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_1_0 = io_in_bits_acc_read_resp_data_1_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_93 = io_in_bits_acc_read_resp_data_2_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_2_0 = io_in_bits_acc_read_resp_data_2_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_125 = io_in_bits_acc_read_resp_data_3_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_3_0 = io_in_bits_acc_read_resp_data_3_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_157 = io_in_bits_acc_read_resp_data_4_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_4_0 = io_in_bits_acc_read_resp_data_4_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_189 = io_in_bits_acc_read_resp_data_5_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_5_0 = io_in_bits_acc_read_resp_data_5_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_221 = io_in_bits_acc_read_resp_data_6_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_6_0 = io_in_bits_acc_read_resp_data_6_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_253 = io_in_bits_acc_read_resp_data_7_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_7_0 = io_in_bits_acc_read_resp_data_7_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_285 = io_in_bits_acc_read_resp_data_8_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_8_0 = io_in_bits_acc_read_resp_data_8_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_317 = io_in_bits_acc_read_resp_data_9_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_9_0 = io_in_bits_acc_read_resp_data_9_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_349 = io_in_bits_acc_read_resp_data_10_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_10_0 = io_in_bits_acc_read_resp_data_10_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_381 = io_in_bits_acc_read_resp_data_11_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_11_0 = io_in_bits_acc_read_resp_data_11_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_413 = io_in_bits_acc_read_resp_data_12_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_12_0 = io_in_bits_acc_read_resp_data_12_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_445 = io_in_bits_acc_read_resp_data_13_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_13_0 = io_in_bits_acc_read_resp_data_13_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_477 = io_in_bits_acc_read_resp_data_14_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_14_0 = io_in_bits_acc_read_resp_data_14_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_act_T_509 = io_in_bits_acc_read_resp_data_15_0_0; // @[Mux.scala:126:16] wire [31:0] in_bits_full_data_15_0 = io_in_bits_acc_read_resp_data_15_0_0; // @[AccumulatorScale.scala:88:7, :139:18] wire in_bits_resp_fromDMA = io_in_bits_acc_read_resp_fromDMA_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] _activated_data_e_scaled_T_7_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_18_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_29_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_40_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_51_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_62_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_73_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_84_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_95_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_106_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_117_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_128_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_139_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_150_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_161_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_172_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16] wire [31:0] in_bits_resp_scale_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] in_bits_resp_igelu_qb = io_in_bits_acc_read_resp_igelu_qb_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] in_bits_resp_igelu_qc = io_in_bits_acc_read_resp_igelu_qc_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] in_bits_resp_iexp_qln2 = io_in_bits_acc_read_resp_iexp_qln2_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] in_bits_resp_iexp_qln2_inv = io_in_bits_acc_read_resp_iexp_qln2_inv_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [2:0] in_bits_resp_act = io_in_bits_acc_read_resp_act_0; // @[AccumulatorScale.scala:88:7, :139:18] wire [1:0] in_bits_resp_acc_bank_id = io_in_bits_acc_read_resp_acc_bank_id_0; // @[AccumulatorScale.scala:88:7, :139:18] wire out_ready = io_out_ready_0; // @[AccumulatorScale.scala:88:7, :104:17] wire out_valid; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_0_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_1_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_2_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_3_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_4_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_5_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_6_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_7_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_8_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_9_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_10_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_11_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_12_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_13_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_14_0; // @[AccumulatorScale.scala:104:17] wire [31:0] out_bits_full_data_15_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_0_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_1_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_2_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_3_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_4_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_5_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_6_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_7_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_8_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_9_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_10_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_11_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_12_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_13_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_14_0; // @[AccumulatorScale.scala:104:17] wire [7:0] out_bits_data_15_0; // @[AccumulatorScale.scala:104:17] wire [1:0] out_bits_acc_bank_id; // @[AccumulatorScale.scala:104:17] wire out_bits_fromDMA; // @[AccumulatorScale.scala:104:17] wire io_in_ready_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_0_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_1_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_2_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_3_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_4_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_5_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_6_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_7_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_8_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_9_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_10_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_11_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_12_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_13_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_14_0_0; // @[AccumulatorScale.scala:88:7] wire [31:0] io_out_bits_full_data_15_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_0_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_1_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_2_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_3_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_4_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_5_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_6_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_7_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_8_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_9_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_10_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_11_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_12_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_13_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_14_0_0; // @[AccumulatorScale.scala:88:7] wire [7:0] io_out_bits_data_15_0_0; // @[AccumulatorScale.scala:88:7] wire [1:0] io_out_bits_acc_bank_id_0; // @[AccumulatorScale.scala:88:7] wire io_out_bits_fromDMA_0; // @[AccumulatorScale.scala:88:7] wire io_out_valid_0; // @[AccumulatorScale.scala:88:7] assign io_out_valid_0 = out_valid; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_0_0_0 = out_bits_full_data_0_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_1_0_0 = out_bits_full_data_1_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_2_0_0 = out_bits_full_data_2_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_3_0_0 = out_bits_full_data_3_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_4_0_0 = out_bits_full_data_4_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_5_0_0 = out_bits_full_data_5_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_6_0_0 = out_bits_full_data_6_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_7_0_0 = out_bits_full_data_7_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_8_0_0 = out_bits_full_data_8_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_9_0_0 = out_bits_full_data_9_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_10_0_0 = out_bits_full_data_10_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_11_0_0 = out_bits_full_data_11_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_12_0_0 = out_bits_full_data_12_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_13_0_0 = out_bits_full_data_13_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_14_0_0 = out_bits_full_data_14_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_full_data_15_0_0 = out_bits_full_data_15_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_0_0_0 = out_bits_data_0_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_1_0_0 = out_bits_data_1_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_2_0_0 = out_bits_data_2_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_3_0_0 = out_bits_data_3_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_4_0_0 = out_bits_data_4_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_5_0_0 = out_bits_data_5_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_6_0_0 = out_bits_data_6_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_7_0_0 = out_bits_data_7_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_8_0_0 = out_bits_data_8_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_9_0_0 = out_bits_data_9_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_10_0_0 = out_bits_data_10_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_11_0_0 = out_bits_data_11_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_12_0_0 = out_bits_data_12_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_13_0_0 = out_bits_data_13_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_14_0_0 = out_bits_data_14_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_data_15_0_0 = out_bits_data_15_0; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_acc_bank_id_0 = out_bits_acc_bank_id; // @[AccumulatorScale.scala:88:7, :104:17] assign io_out_bits_fromDMA_0 = out_bits_fromDMA; // @[AccumulatorScale.scala:88:7, :104:17] wire _GEN = io_in_bits_acc_read_resp_act_0 == 3'h1; // @[AccumulatorScale.scala:88:7, :118:45] wire _activated_data_e_act_T; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_32; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_32 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_64; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_64 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_96; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_96 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_128; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_128 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_160; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_160 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_192; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_192 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_224; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_224 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_256; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_256 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_288; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_288 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_320; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_320 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_352; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_352 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_384; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_384 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_416; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_416 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_448; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_448 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_480; // @[AccumulatorScale.scala:118:45] assign _activated_data_e_act_T_480 = _GEN; // @[AccumulatorScale.scala:118:45] wire _activated_data_e_act_T_1 = _activated_data_e_act_T; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_2 = $signed(io_in_bits_acc_read_resp_data_0_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_3 = _activated_data_e_act_T_2 ? io_in_bits_acc_read_resp_data_0_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire _GEN_0 = io_in_bits_acc_read_resp_act_0 == 3'h2; // @[AccumulatorScale.scala:88:7, :119:69] wire _activated_data_e_act_T_5; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_5 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_1; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_1 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_37; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_37 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_12; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_12 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_69; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_69 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_23; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_23 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_101; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_101 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_34; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_34 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_133; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_133 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_45; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_45 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_165; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_165 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_56; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_56 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_197; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_197 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_67; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_67 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_229; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_229 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_78; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_78 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_261; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_261 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_89; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_89 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_293; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_293 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_100; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_100 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_325; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_325 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_111; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_111 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_357; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_357 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_122; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_122 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_389; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_389 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_133; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_133 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_421; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_421 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_144; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_144 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_453; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_453 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_155; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_155 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire _activated_data_e_act_T_485; // @[AccumulatorScale.scala:119:69] assign _activated_data_e_act_T_485 = _GEN_0; // @[AccumulatorScale.scala:119:69] wire _activated_data_e_scaled_T_166; // @[AccumulatorScale.scala:128:69] assign _activated_data_e_scaled_T_166 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69] wire [32:0] _GEN_1 = {io_in_bits_acc_read_resp_data_0_0_0[31], io_in_bits_acc_read_resp_data_0_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_7; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_7 = _GEN_1; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_22; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_22 = _GEN_1; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_8 = _activated_data_e_act_T_7[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_9 = _activated_data_e_act_T_8; // @[Arithmetic.scala:95:38] wire _GEN_2 = io_in_bits_acc_read_resp_act_0 == 3'h3; // @[AccumulatorScale.scala:88:7, :121:69] wire _activated_data_e_act_T_11; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_11 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_43; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_43 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_75; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_75 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_107; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_107 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_139; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_139 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_171; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_171 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_203; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_203 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_235; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_235 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_267; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_267 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_299; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_299 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_331; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_331 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_363; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_363 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_395; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_395 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_427; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_427 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_459; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_459 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _activated_data_e_act_T_491; // @[AccumulatorScale.scala:121:69] assign _activated_data_e_act_T_491 = _GEN_2; // @[AccumulatorScale.scala:121:69] wire _GEN_3 = $signed(io_in_bits_acc_read_resp_data_0_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T = _GEN_3; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T = _GEN_3; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign = {_activated_data_e_act_q_sign_T, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_1 = 33'h0 - _GEN_1; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_2 = _activated_data_e_act_q_abs_T_1[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_3 = _activated_data_e_act_q_abs_T_2; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs = _activated_data_e_act_q_abs_T ? _activated_data_e_act_q_abs_T_3 : io_in_bits_acc_read_resp_data_0_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_4 = {io_in_bits_acc_read_resp_igelu_qb_0[31], io_in_bits_acc_read_resp_igelu_qb_0}; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _GEN_5 = 33'h0 - _GEN_4; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_4; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_4 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_7; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_7 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_11; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_11 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_14; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_14 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_18; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_18 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_21; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_21 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_25; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_25 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_28; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_28 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_32; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_32 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_35; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_35 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_39; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_39 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_42; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_42 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_46; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_46 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_49; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_49 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_53; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_53 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_56; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_56 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_60; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_60 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_63; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_63 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_67; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_67 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_70; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_70 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_74; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_74 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_77; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_77 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_81; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_81 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_84; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_84 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_88; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_88 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_91; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_91 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_95; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_95 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_98; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_98 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_102; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_102 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_105; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_105 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [32:0] _activated_data_e_act_q_clipped_T_109; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_q_clipped_T_109 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_clipped_T_1 = _activated_data_e_act_q_clipped_T[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_2 = _activated_data_e_act_q_clipped_T_1; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_3 = $signed(activated_data_e_act_q_abs) > $signed(_activated_data_e_act_q_clipped_T_2); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_5 = _activated_data_e_act_q_clipped_T_4[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_6 = _activated_data_e_act_q_clipped_T_5; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped = _activated_data_e_act_q_clipped_T_3 ? _activated_data_e_act_q_clipped_T_6 : activated_data_e_act_q_abs; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_6 = {activated_data_e_act_q_clipped[31], activated_data_e_act_q_clipped} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T = _GEN_6; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_3; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_3 = _GEN_6; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_1 = _activated_data_e_act_q_poly_T[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_2 = _activated_data_e_act_q_poly_T_1; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_4 = _activated_data_e_act_q_poly_T_3[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_5 = _activated_data_e_act_q_poly_T_4; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_6 = {{32{_activated_data_e_act_q_poly_T_2[31]}}, _activated_data_e_act_q_poly_T_2} * {{32{_activated_data_e_act_q_poly_T_5[31]}}, _activated_data_e_act_q_poly_T_5}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _GEN_7 = {{33{io_in_bits_acc_read_resp_igelu_qc_0[31]}}, io_in_bits_acc_read_resp_igelu_qc_0}; // @[Arithmetic.scala:93:54] wire [64:0] _activated_data_e_act_q_poly_T_7 = {_activated_data_e_act_q_poly_T_6[63], _activated_data_e_act_q_poly_T_6} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_8 = _activated_data_e_act_q_poly_T_7[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_9 = _activated_data_e_act_q_poly_T_8; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_10 = _activated_data_e_act_q_poly_T_9[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly = _activated_data_e_act_q_poly_T_10; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T = {{32{activated_data_e_act_q_sign[1]}}, activated_data_e_act_q_sign} * {{2{activated_data_e_act_q_poly[31]}}, activated_data_e_act_q_poly}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_1 = _activated_data_e_act_q_erf_T[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf = _activated_data_e_act_q_erf_T_1; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_8 = {io_in_bits_acc_read_resp_igelu_qc_0[31], io_in_bits_acc_read_resp_igelu_qc_0}; // @[Arithmetic.scala:93:54, :94:38] wire [32:0] _activated_data_e_act_T_13 = {activated_data_e_act_q_erf[31], activated_data_e_act_q_erf} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_14 = _activated_data_e_act_T_13[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_15 = _activated_data_e_act_T_14; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_16 = {{32{io_in_bits_acc_read_resp_data_0_0_0[31]}}, io_in_bits_acc_read_resp_data_0_0_0} * {{32{_activated_data_e_act_T_15[31]}}, _activated_data_e_act_T_15}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_17 = _activated_data_e_act_T_16[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_18 = _activated_data_e_act_T_17; // @[Arithmetic.scala:114:{15,33}] wire _GEN_9 = io_in_bits_acc_read_resp_act_0 == 3'h4; // @[AccumulatorScale.scala:88:7, :123:69] wire _activated_data_e_act_T_20; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_20 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_4; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_4 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_52; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_52 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_15; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_15 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_84; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_84 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_26; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_26 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_116; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_116 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_37; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_37 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_148; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_148 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_48; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_48 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_180; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_180 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_59; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_59 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_212; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_212 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_70; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_70 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_244; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_244 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_81; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_81 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_276; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_276 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_92; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_92 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_308; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_308 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_103; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_103 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_340; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_340 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_114; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_114 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_372; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_372 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_125; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_125 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_404; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_404 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_136; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_136 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_436; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_436 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_147; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_147 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_468; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_468 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_158; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_158 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire _activated_data_e_act_T_500; // @[AccumulatorScale.scala:123:69] assign _activated_data_e_act_T_500 = _GEN_9; // @[AccumulatorScale.scala:123:69] wire _activated_data_e_scaled_T_169; // @[AccumulatorScale.scala:130:69] assign _activated_data_e_scaled_T_169 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69] wire [31:0] _activated_data_e_act_T_23 = _activated_data_e_act_T_22[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_24 = _activated_data_e_act_T_23; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T = 33'h0 - {_activated_data_e_act_T_24[31], _activated_data_e_act_T_24}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_1 = _activated_data_e_act_neg_q_iexp_T[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp = _activated_data_e_act_neg_q_iexp_T_1; // @[Arithmetic.scala:95:38] wire [63:0] _GEN_10 = {{32{io_in_bits_acc_read_resp_iexp_qln2_inv_0[31]}}, io_in_bits_acc_read_resp_iexp_qln2_inv_0}; // @[Arithmetic.scala:92:38] wire [63:0] _activated_data_e_act_z_iexp_T = {{32{activated_data_e_act_neg_q_iexp[31]}}, activated_data_e_act_neg_q_iexp} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_1 = _activated_data_e_act_z_iexp_T; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_2 = _activated_data_e_act_z_iexp_T_1[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_3 = _activated_data_e_act_z_iexp_T_2; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_2 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_4 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_6 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_8 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_10 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_12 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_14 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_16 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_18 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_20 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp = _activated_data_e_act_z_iexp_T_3[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_32; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_26 = activated_data_e_act_z_iexp_saturated; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_1 = _activated_data_e_act_z_iexp_saturated_T[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_3 = _activated_data_e_act_z_iexp_saturated_T_2[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_5 = _activated_data_e_act_z_iexp_saturated_T_4[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_7 = _activated_data_e_act_z_iexp_saturated_T_6[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_9 = _activated_data_e_act_z_iexp_saturated_T_8[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_11 = _activated_data_e_act_z_iexp_saturated_T_10[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_13 = _activated_data_e_act_z_iexp_saturated_T_12[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_15 = _activated_data_e_act_z_iexp_saturated_T_14[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_17 = _activated_data_e_act_z_iexp_saturated_T_16[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_19 = _activated_data_e_act_z_iexp_saturated_T_18[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_21 = _activated_data_e_act_z_iexp_saturated_T_20[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_22 = _activated_data_e_act_z_iexp_saturated_T_1 \| _activated_data_e_act_z_iexp_saturated_T_3; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_23 = _activated_data_e_act_z_iexp_saturated_T_22 \| _activated_data_e_act_z_iexp_saturated_T_5; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_24 = _activated_data_e_act_z_iexp_saturated_T_23 \| _activated_data_e_act_z_iexp_saturated_T_7; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_25 = _activated_data_e_act_z_iexp_saturated_T_24 \| _activated_data_e_act_z_iexp_saturated_T_9; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_26 = _activated_data_e_act_z_iexp_saturated_T_25 \| _activated_data_e_act_z_iexp_saturated_T_11; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_27 = _activated_data_e_act_z_iexp_saturated_T_26 \| _activated_data_e_act_z_iexp_saturated_T_13; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_28 = _activated_data_e_act_z_iexp_saturated_T_27 \| _activated_data_e_act_z_iexp_saturated_T_15; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_29 = _activated_data_e_act_z_iexp_saturated_T_28 \| _activated_data_e_act_z_iexp_saturated_T_17; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_30 = _activated_data_e_act_z_iexp_saturated_T_29 \| _activated_data_e_act_z_iexp_saturated_T_19; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_31 = _activated_data_e_act_z_iexp_saturated_T_30 \| _activated_data_e_act_z_iexp_saturated_T_21; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_32 = _activated_data_e_act_z_iexp_saturated_T_31 ? 32'h20 : activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated = _activated_data_e_act_z_iexp_saturated_T_32; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _GEN_11 = {{32{io_in_bits_acc_read_resp_iexp_qln2_0[31]}}, io_in_bits_acc_read_resp_iexp_qln2_0}; // @[Arithmetic.scala:93:49] wire [63:0] _activated_data_e_act_qp_iexp_T = {{32{activated_data_e_act_z_iexp[31]}}, activated_data_e_act_z_iexp} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_1 = {_activated_data_e_act_qp_iexp_T[63], _activated_data_e_act_qp_iexp_T} + {{33{_activated_data_e_act_T_24[31]}}, _activated_data_e_act_T_24}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_2 = _activated_data_e_act_qp_iexp_T_1[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_3 = _activated_data_e_act_qp_iexp_T_2; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_4 = _activated_data_e_act_qp_iexp_T_3[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp = _activated_data_e_act_qp_iexp_T_4; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_12 = {activated_data_e_act_qp_iexp[31], activated_data_e_act_qp_iexp} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T = _GEN_12; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_3; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_3 = _GEN_12; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_1 = _activated_data_e_act_q_poly_iexp_T[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_2 = _activated_data_e_act_q_poly_iexp_T_1; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_4 = _activated_data_e_act_q_poly_iexp_T_3[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_5 = _activated_data_e_act_q_poly_iexp_T_4; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_6 = {{32{_activated_data_e_act_q_poly_iexp_T_2[31]}}, _activated_data_e_act_q_poly_iexp_T_2} * {{32{_activated_data_e_act_q_poly_iexp_T_5[31]}}, _activated_data_e_act_q_poly_iexp_T_5}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_7 = {_activated_data_e_act_q_poly_iexp_T_6[63], _activated_data_e_act_q_poly_iexp_T_6} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_8 = _activated_data_e_act_q_poly_iexp_T_7[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_9 = _activated_data_e_act_q_poly_iexp_T_8; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_10 = _activated_data_e_act_q_poly_iexp_T_9[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp = _activated_data_e_act_q_poly_iexp_T_10; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_25 = activated_data_e_act_q_poly_iexp; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_27 = _activated_data_e_act_T_25 >> _activated_data_e_act_T_26; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_28 = _activated_data_e_act_T_27; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE = _activated_data_e_act_T_28; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_30 = _activated_data_e_act_T_29; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_31 = _activated_data_e_act_T_30; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act = _activated_data_e_act_T_1 ? _activated_data_e_act_T_3 : _activated_data_e_act_T_31; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T = activated_data_e_act; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_8_bits = _activated_data_e_scaled_T_7_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_3 = _activated_data_e_scaled_T_8_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_9; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_9 = _activated_data_e_scaled_WIRE_3; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_2_bits = _activated_data_e_scaled_T_9; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign = _activated_data_e_scaled_WIRE_2_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_sign_0 = activated_data_e_scaled_f_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn = _activated_data_e_scaled_WIRE_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn = _activated_data_e_scaled_WIRE_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn = activated_data_e_scaled_f_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn = activated_data_e_scaled_f_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T = activated_data_e_scaled_f_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_1 = activated_data_e_scaled_f_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_2 = activated_data_e_scaled_f_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_3 = activated_data_e_scaled_f_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_4 = activated_data_e_scaled_f_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_5 = activated_data_e_scaled_f_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_6 = activated_data_e_scaled_f_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_7 = activated_data_e_scaled_f_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_8 = activated_data_e_scaled_f_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_9 = activated_data_e_scaled_f_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_10 = activated_data_e_scaled_f_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_11 = activated_data_e_scaled_f_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_12 = activated_data_e_scaled_f_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_13 = activated_data_e_scaled_f_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_14 = activated_data_e_scaled_f_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_15 = activated_data_e_scaled_f_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_16 = activated_data_e_scaled_f_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_17 = activated_data_e_scaled_f_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_18 = activated_data_e_scaled_f_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_19 = activated_data_e_scaled_f_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_20 = activated_data_e_scaled_f_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_21 = activated_data_e_scaled_f_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_22 = activated_data_e_scaled_f_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_23 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_24 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_25 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_26 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_27 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_28 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_29 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_30 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_31 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_32 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_33 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_34 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_35 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_36 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_37 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_38 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_39 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_40 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_41 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_42 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_43 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist = _activated_data_e_scaled_f_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn} << activated_data_e_scaled_f_rec_rawIn_normDist; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_1 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_1 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_2 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T = activated_data_e_scaled_f_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_isZero_0 = activated_data_e_scaled_f_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T = activated_data_e_scaled_f_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_2 = activated_data_e_scaled_f_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_1 = activated_data_e_scaled_f_rec_rawIn_isSpecial & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T = activated_data_e_scaled_f_rec_rawIn_isSpecial & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T = ~activated_data_e_scaled_f_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_2 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn ? activated_data_e_scaled_f_rec_rawIn_subnormFract : activated_data_e_scaled_f_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_3 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_1, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T = activated_data_e_scaled_f_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_1 = activated_data_e_scaled_f_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_scaled_f_rec_T; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_3 = {_activated_data_e_scaled_f_rec_T_1[2:1], _activated_data_e_scaled_f_rec_T_1[0] \| _activated_data_e_scaled_f_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_4 = {activated_data_e_scaled_f_rec_rawIn_sign_0, _activated_data_e_scaled_f_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_5 = activated_data_e_scaled_f_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_6 = {_activated_data_e_scaled_f_rec_T_4, _activated_data_e_scaled_f_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_7 = activated_data_e_scaled_f_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec = {_activated_data_e_scaled_f_rec_T_6, _activated_data_e_scaled_f_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE = _activated_data_e_scaled_in_to_rec_fn_io_in_T; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow = _activated_data_e_scaled_rec_fn_to_in_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp = _activated_data_e_scaled_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T = activated_data_e_scaled_sign_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero = _activated_data_e_scaled_sign_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_isZero = activated_data_e_scaled_sign_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T = activated_data_e_scaled_sign_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial = &_activated_data_e_scaled_sign_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T = activated_data_e_scaled_sign_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T = activated_data_e_scaled_sign_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_1 = activated_data_e_scaled_sign_isSpecial & _activated_data_e_scaled_sign_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_1 = ~_activated_data_e_scaled_sign_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_2 = activated_data_e_scaled_sign_isSpecial & _activated_data_e_scaled_sign_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_isInf = _activated_data_e_scaled_sign_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T = _activated_data_e_scaled_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_sign = _activated_data_e_scaled_sign_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T = {1'h0, activated_data_e_scaled_sign_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_sExp = _activated_data_e_scaled_sign_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T = ~activated_data_e_scaled_sign_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_1 = {1'h0, _activated_data_e_scaled_sign_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_2 = _activated_data_e_scaled_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_3 = {_activated_data_e_scaled_sign_out_sig_T_1, _activated_data_e_scaled_sign_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_sig = _activated_data_e_scaled_sign_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat = activated_data_e_scaled_sign_out_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_10; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_4 = _activated_data_e_scaled_T_10; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled = activated_data_e_scaled_overflow ? activated_data_e_scaled_sat : _activated_data_e_scaled_WIRE_4; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T = $signed(activated_data_e_scaled) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_1 = $signed(activated_data_e_scaled) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_2 = _activated_data_e_clipped_T_1 ? 32'hFFFFFF80 : activated_data_e_scaled; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_3 = _activated_data_e_clipped_T ? 32'h7F : _activated_data_e_clipped_T_2; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_4 = _activated_data_e_clipped_T_3[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped = _activated_data_e_clipped_T_4; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_0 = activated_data_e_clipped; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_0_0 = _activated_data_WIRE_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_33 = _activated_data_e_act_T_32; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_34 = $signed(io_in_bits_acc_read_resp_data_1_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_35 = _activated_data_e_act_T_34 ? io_in_bits_acc_read_resp_data_1_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_13 = {io_in_bits_acc_read_resp_data_1_0_0[31], io_in_bits_acc_read_resp_data_1_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_39; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_39 = _GEN_13; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_54; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_54 = _GEN_13; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_40 = _activated_data_e_act_T_39[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_41 = _activated_data_e_act_T_40; // @[Arithmetic.scala:95:38] wire _GEN_14 = $signed(io_in_bits_acc_read_resp_data_1_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_4; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_4 = _GEN_14; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_4; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_4 = _GEN_14; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_1 = {_activated_data_e_act_q_sign_T_4, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_5 = 33'h0 - _GEN_13; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_6 = _activated_data_e_act_q_abs_T_5[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_7 = _activated_data_e_act_q_abs_T_6; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_1 = _activated_data_e_act_q_abs_T_4 ? _activated_data_e_act_q_abs_T_7 : io_in_bits_acc_read_resp_data_1_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_8 = _activated_data_e_act_q_clipped_T_7[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_9 = _activated_data_e_act_q_clipped_T_8; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_10 = $signed(activated_data_e_act_q_abs_1) > $signed(_activated_data_e_act_q_clipped_T_9); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_12 = _activated_data_e_act_q_clipped_T_11[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_13 = _activated_data_e_act_q_clipped_T_12; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_1 = _activated_data_e_act_q_clipped_T_10 ? _activated_data_e_act_q_clipped_T_13 : activated_data_e_act_q_abs_1; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_15 = {activated_data_e_act_q_clipped_1[31], activated_data_e_act_q_clipped_1} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_11; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_11 = _GEN_15; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_14; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_14 = _GEN_15; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_12 = _activated_data_e_act_q_poly_T_11[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_13 = _activated_data_e_act_q_poly_T_12; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_15 = _activated_data_e_act_q_poly_T_14[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_16 = _activated_data_e_act_q_poly_T_15; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_17 = {{32{_activated_data_e_act_q_poly_T_13[31]}}, _activated_data_e_act_q_poly_T_13} * {{32{_activated_data_e_act_q_poly_T_16[31]}}, _activated_data_e_act_q_poly_T_16}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_18 = {_activated_data_e_act_q_poly_T_17[63], _activated_data_e_act_q_poly_T_17} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_19 = _activated_data_e_act_q_poly_T_18[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_20 = _activated_data_e_act_q_poly_T_19; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_21 = _activated_data_e_act_q_poly_T_20[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_1 = _activated_data_e_act_q_poly_T_21; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_2 = {{32{activated_data_e_act_q_sign_1[1]}}, activated_data_e_act_q_sign_1} * {{2{activated_data_e_act_q_poly_1[31]}}, activated_data_e_act_q_poly_1}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_3 = _activated_data_e_act_q_erf_T_2[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_1 = _activated_data_e_act_q_erf_T_3; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_45 = {activated_data_e_act_q_erf_1[31], activated_data_e_act_q_erf_1} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_46 = _activated_data_e_act_T_45[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_47 = _activated_data_e_act_T_46; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_48 = {{32{io_in_bits_acc_read_resp_data_1_0_0[31]}}, io_in_bits_acc_read_resp_data_1_0_0} * {{32{_activated_data_e_act_T_47[31]}}, _activated_data_e_act_T_47}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_49 = _activated_data_e_act_T_48[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_50 = _activated_data_e_act_T_49; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_55 = _activated_data_e_act_T_54[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_56 = _activated_data_e_act_T_55; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_2 = 33'h0 - {_activated_data_e_act_T_56[31], _activated_data_e_act_T_56}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_3 = _activated_data_e_act_neg_q_iexp_T_2[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_1 = _activated_data_e_act_neg_q_iexp_T_3; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_4 = {{32{activated_data_e_act_neg_q_iexp_1[31]}}, activated_data_e_act_neg_q_iexp_1} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_5 = _activated_data_e_act_z_iexp_T_4; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_6 = _activated_data_e_act_z_iexp_T_5[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_7 = _activated_data_e_act_z_iexp_T_6; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_33 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_35 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_37 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_39 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_41 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_43 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_45 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_47 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_49 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_51 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_53 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_1 = _activated_data_e_act_z_iexp_T_7[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_65; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_1; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_58 = activated_data_e_act_z_iexp_saturated_1; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_34 = _activated_data_e_act_z_iexp_saturated_T_33[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_36 = _activated_data_e_act_z_iexp_saturated_T_35[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_38 = _activated_data_e_act_z_iexp_saturated_T_37[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_40 = _activated_data_e_act_z_iexp_saturated_T_39[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_42 = _activated_data_e_act_z_iexp_saturated_T_41[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_44 = _activated_data_e_act_z_iexp_saturated_T_43[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_46 = _activated_data_e_act_z_iexp_saturated_T_45[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_48 = _activated_data_e_act_z_iexp_saturated_T_47[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_50 = _activated_data_e_act_z_iexp_saturated_T_49[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_52 = _activated_data_e_act_z_iexp_saturated_T_51[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_54 = _activated_data_e_act_z_iexp_saturated_T_53[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_55 = _activated_data_e_act_z_iexp_saturated_T_34 \| _activated_data_e_act_z_iexp_saturated_T_36; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_56 = _activated_data_e_act_z_iexp_saturated_T_55 \| _activated_data_e_act_z_iexp_saturated_T_38; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_57 = _activated_data_e_act_z_iexp_saturated_T_56 \| _activated_data_e_act_z_iexp_saturated_T_40; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_58 = _activated_data_e_act_z_iexp_saturated_T_57 \| _activated_data_e_act_z_iexp_saturated_T_42; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_59 = _activated_data_e_act_z_iexp_saturated_T_58 \| _activated_data_e_act_z_iexp_saturated_T_44; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_60 = _activated_data_e_act_z_iexp_saturated_T_59 \| _activated_data_e_act_z_iexp_saturated_T_46; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_61 = _activated_data_e_act_z_iexp_saturated_T_60 \| _activated_data_e_act_z_iexp_saturated_T_48; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_62 = _activated_data_e_act_z_iexp_saturated_T_61 \| _activated_data_e_act_z_iexp_saturated_T_50; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_63 = _activated_data_e_act_z_iexp_saturated_T_62 \| _activated_data_e_act_z_iexp_saturated_T_52; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_64 = _activated_data_e_act_z_iexp_saturated_T_63 \| _activated_data_e_act_z_iexp_saturated_T_54; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_65 = _activated_data_e_act_z_iexp_saturated_T_64 ? 32'h20 : activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_1 = _activated_data_e_act_z_iexp_saturated_T_65; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_5 = {{32{activated_data_e_act_z_iexp_1[31]}}, activated_data_e_act_z_iexp_1} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_6 = {_activated_data_e_act_qp_iexp_T_5[63], _activated_data_e_act_qp_iexp_T_5} + {{33{_activated_data_e_act_T_56[31]}}, _activated_data_e_act_T_56}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_7 = _activated_data_e_act_qp_iexp_T_6[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_8 = _activated_data_e_act_qp_iexp_T_7; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_9 = _activated_data_e_act_qp_iexp_T_8[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_1 = _activated_data_e_act_qp_iexp_T_9; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_16 = {activated_data_e_act_qp_iexp_1[31], activated_data_e_act_qp_iexp_1} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_11; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_11 = _GEN_16; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_14; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_14 = _GEN_16; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_12 = _activated_data_e_act_q_poly_iexp_T_11[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_13 = _activated_data_e_act_q_poly_iexp_T_12; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_15 = _activated_data_e_act_q_poly_iexp_T_14[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_16 = _activated_data_e_act_q_poly_iexp_T_15; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_17 = {{32{_activated_data_e_act_q_poly_iexp_T_13[31]}}, _activated_data_e_act_q_poly_iexp_T_13} * {{32{_activated_data_e_act_q_poly_iexp_T_16[31]}}, _activated_data_e_act_q_poly_iexp_T_16}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_18 = {_activated_data_e_act_q_poly_iexp_T_17[63], _activated_data_e_act_q_poly_iexp_T_17} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_19 = _activated_data_e_act_q_poly_iexp_T_18[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_20 = _activated_data_e_act_q_poly_iexp_T_19; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_21 = _activated_data_e_act_q_poly_iexp_T_20[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_1 = _activated_data_e_act_q_poly_iexp_T_21; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_57 = activated_data_e_act_q_poly_iexp_1; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_59 = _activated_data_e_act_T_57 >> _activated_data_e_act_T_58; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_60 = _activated_data_e_act_T_59; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_1 = _activated_data_e_act_T_60; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_62 = _activated_data_e_act_T_61; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_63 = _activated_data_e_act_T_62; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_1 = _activated_data_e_act_T_33 ? _activated_data_e_act_T_35 : _activated_data_e_act_T_63; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_1 = activated_data_e_act_1; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_19_bits = _activated_data_e_scaled_T_18_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_8 = _activated_data_e_scaled_T_19_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_20; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_20 = _activated_data_e_scaled_WIRE_8; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_7_bits = _activated_data_e_scaled_T_20; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_1 = _activated_data_e_scaled_WIRE_7_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_1_sign = activated_data_e_scaled_f_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_1 = _activated_data_e_scaled_WIRE_7_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_1 = _activated_data_e_scaled_WIRE_7_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 = activated_data_e_scaled_f_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1 = activated_data_e_scaled_f_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_44 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_45 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_46 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_47 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_48 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_49 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_50 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_51 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_52 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_53 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_54 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_55 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_56 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_57 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_58 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_59 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_60 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_61 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_62 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_63 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_64 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_65 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_66 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_67 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_68 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_69 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_70 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_71 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_72 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_73 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_74 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_75 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_76 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_77 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_78 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_79 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_80 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_81 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_82 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_83 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_84 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_85 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_86 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_87 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_1 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_1} << activated_data_e_scaled_f_rec_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_3 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_1 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_6 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_7 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_1 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_2 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_1 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_1_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_1 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_1 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_10 = activated_data_e_scaled_f_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_3 = activated_data_e_scaled_f_rec_rawIn_isSpecial_1 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_1_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_1 = activated_data_e_scaled_f_rec_rawIn_isSpecial_1 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_1_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_1_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_4 = ~activated_data_e_scaled_f_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_6 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_1 : activated_data_e_scaled_f_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_7 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_5, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_1_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_8 = activated_data_e_scaled_f_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_9 = activated_data_e_scaled_f_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_8; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_11 = {_activated_data_e_scaled_f_rec_T_9[2:1], _activated_data_e_scaled_f_rec_T_9[0] \| _activated_data_e_scaled_f_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_12 = {activated_data_e_scaled_f_rec_rawIn_1_sign, _activated_data_e_scaled_f_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_13 = activated_data_e_scaled_f_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_14 = {_activated_data_e_scaled_f_rec_T_12, _activated_data_e_scaled_f_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_15 = activated_data_e_scaled_f_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_1 = {_activated_data_e_scaled_f_rec_T_14, _activated_data_e_scaled_f_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_1 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_1; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_1 = _activated_data_e_scaled_rec_fn_to_in_1_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_1 = _activated_data_e_scaled_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_1 = activated_data_e_scaled_sign_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_1 = _activated_data_e_scaled_sign_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_1_isZero = activated_data_e_scaled_sign_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_1 = activated_data_e_scaled_sign_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_1 = &_activated_data_e_scaled_sign_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_2 = activated_data_e_scaled_sign_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_3 = activated_data_e_scaled_sign_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_3 = activated_data_e_scaled_sign_isSpecial_1 & _activated_data_e_scaled_sign_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_1_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_4 = ~_activated_data_e_scaled_sign_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_5 = activated_data_e_scaled_sign_isSpecial_1 & _activated_data_e_scaled_sign_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_1_isInf = _activated_data_e_scaled_sign_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_1 = _activated_data_e_scaled_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_1_sign = _activated_data_e_scaled_sign_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_1 = {1'h0, activated_data_e_scaled_sign_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_1_sExp = _activated_data_e_scaled_sign_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_4 = ~activated_data_e_scaled_sign_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_5 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_6 = _activated_data_e_scaled_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_7 = {_activated_data_e_scaled_sign_out_sig_T_5, _activated_data_e_scaled_sign_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_1_sig = _activated_data_e_scaled_sign_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_1 = activated_data_e_scaled_sign_out_1_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_21; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_9 = _activated_data_e_scaled_T_21; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_1 = activated_data_e_scaled_overflow_1 ? activated_data_e_scaled_sat_1 : _activated_data_e_scaled_WIRE_9; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_5 = $signed(activated_data_e_scaled_1) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_6 = $signed(activated_data_e_scaled_1) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_7 = _activated_data_e_clipped_T_6 ? 32'hFFFFFF80 : activated_data_e_scaled_1; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_8 = _activated_data_e_clipped_T_5 ? 32'h7F : _activated_data_e_clipped_T_7; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_9 = _activated_data_e_clipped_T_8[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_1 = _activated_data_e_clipped_T_9; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_1_0 = activated_data_e_clipped_1; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_1_0 = _activated_data_WIRE_1_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_65 = _activated_data_e_act_T_64; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_66 = $signed(io_in_bits_acc_read_resp_data_2_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_67 = _activated_data_e_act_T_66 ? io_in_bits_acc_read_resp_data_2_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_17 = {io_in_bits_acc_read_resp_data_2_0_0[31], io_in_bits_acc_read_resp_data_2_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_71; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_71 = _GEN_17; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_86; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_86 = _GEN_17; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_72 = _activated_data_e_act_T_71[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_73 = _activated_data_e_act_T_72; // @[Arithmetic.scala:95:38] wire _GEN_18 = $signed(io_in_bits_acc_read_resp_data_2_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_8; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_8 = _GEN_18; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_8; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_8 = _GEN_18; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_2 = {_activated_data_e_act_q_sign_T_8, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_9 = 33'h0 - _GEN_17; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_10 = _activated_data_e_act_q_abs_T_9[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_11 = _activated_data_e_act_q_abs_T_10; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_2 = _activated_data_e_act_q_abs_T_8 ? _activated_data_e_act_q_abs_T_11 : io_in_bits_acc_read_resp_data_2_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_15 = _activated_data_e_act_q_clipped_T_14[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_16 = _activated_data_e_act_q_clipped_T_15; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_17 = $signed(activated_data_e_act_q_abs_2) > $signed(_activated_data_e_act_q_clipped_T_16); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_19 = _activated_data_e_act_q_clipped_T_18[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_20 = _activated_data_e_act_q_clipped_T_19; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_2 = _activated_data_e_act_q_clipped_T_17 ? _activated_data_e_act_q_clipped_T_20 : activated_data_e_act_q_abs_2; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_19 = {activated_data_e_act_q_clipped_2[31], activated_data_e_act_q_clipped_2} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_22; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_22 = _GEN_19; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_25; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_25 = _GEN_19; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_23 = _activated_data_e_act_q_poly_T_22[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_24 = _activated_data_e_act_q_poly_T_23; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_26 = _activated_data_e_act_q_poly_T_25[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_27 = _activated_data_e_act_q_poly_T_26; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_28 = {{32{_activated_data_e_act_q_poly_T_24[31]}}, _activated_data_e_act_q_poly_T_24} * {{32{_activated_data_e_act_q_poly_T_27[31]}}, _activated_data_e_act_q_poly_T_27}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_29 = {_activated_data_e_act_q_poly_T_28[63], _activated_data_e_act_q_poly_T_28} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_30 = _activated_data_e_act_q_poly_T_29[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_31 = _activated_data_e_act_q_poly_T_30; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_32 = _activated_data_e_act_q_poly_T_31[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_2 = _activated_data_e_act_q_poly_T_32; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_4 = {{32{activated_data_e_act_q_sign_2[1]}}, activated_data_e_act_q_sign_2} * {{2{activated_data_e_act_q_poly_2[31]}}, activated_data_e_act_q_poly_2}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_5 = _activated_data_e_act_q_erf_T_4[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_2 = _activated_data_e_act_q_erf_T_5; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_77 = {activated_data_e_act_q_erf_2[31], activated_data_e_act_q_erf_2} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_78 = _activated_data_e_act_T_77[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_79 = _activated_data_e_act_T_78; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_80 = {{32{io_in_bits_acc_read_resp_data_2_0_0[31]}}, io_in_bits_acc_read_resp_data_2_0_0} * {{32{_activated_data_e_act_T_79[31]}}, _activated_data_e_act_T_79}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_81 = _activated_data_e_act_T_80[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_82 = _activated_data_e_act_T_81; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_87 = _activated_data_e_act_T_86[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_88 = _activated_data_e_act_T_87; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_4 = 33'h0 - {_activated_data_e_act_T_88[31], _activated_data_e_act_T_88}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_5 = _activated_data_e_act_neg_q_iexp_T_4[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_2 = _activated_data_e_act_neg_q_iexp_T_5; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_8 = {{32{activated_data_e_act_neg_q_iexp_2[31]}}, activated_data_e_act_neg_q_iexp_2} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_9 = _activated_data_e_act_z_iexp_T_8; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_10 = _activated_data_e_act_z_iexp_T_9[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_11 = _activated_data_e_act_z_iexp_T_10; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_66 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_68 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_70 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_72 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_74 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_76 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_78 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_80 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_82 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_84 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_86 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_2 = _activated_data_e_act_z_iexp_T_11[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_98; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_2; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_90 = activated_data_e_act_z_iexp_saturated_2; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_67 = _activated_data_e_act_z_iexp_saturated_T_66[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_69 = _activated_data_e_act_z_iexp_saturated_T_68[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_71 = _activated_data_e_act_z_iexp_saturated_T_70[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_73 = _activated_data_e_act_z_iexp_saturated_T_72[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_75 = _activated_data_e_act_z_iexp_saturated_T_74[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_77 = _activated_data_e_act_z_iexp_saturated_T_76[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_79 = _activated_data_e_act_z_iexp_saturated_T_78[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_81 = _activated_data_e_act_z_iexp_saturated_T_80[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_83 = _activated_data_e_act_z_iexp_saturated_T_82[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_85 = _activated_data_e_act_z_iexp_saturated_T_84[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_87 = _activated_data_e_act_z_iexp_saturated_T_86[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_88 = _activated_data_e_act_z_iexp_saturated_T_67 \| _activated_data_e_act_z_iexp_saturated_T_69; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_89 = _activated_data_e_act_z_iexp_saturated_T_88 \| _activated_data_e_act_z_iexp_saturated_T_71; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_90 = _activated_data_e_act_z_iexp_saturated_T_89 \| _activated_data_e_act_z_iexp_saturated_T_73; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_91 = _activated_data_e_act_z_iexp_saturated_T_90 \| _activated_data_e_act_z_iexp_saturated_T_75; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_92 = _activated_data_e_act_z_iexp_saturated_T_91 \| _activated_data_e_act_z_iexp_saturated_T_77; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_93 = _activated_data_e_act_z_iexp_saturated_T_92 \| _activated_data_e_act_z_iexp_saturated_T_79; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_94 = _activated_data_e_act_z_iexp_saturated_T_93 \| _activated_data_e_act_z_iexp_saturated_T_81; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_95 = _activated_data_e_act_z_iexp_saturated_T_94 \| _activated_data_e_act_z_iexp_saturated_T_83; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_96 = _activated_data_e_act_z_iexp_saturated_T_95 \| _activated_data_e_act_z_iexp_saturated_T_85; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_97 = _activated_data_e_act_z_iexp_saturated_T_96 \| _activated_data_e_act_z_iexp_saturated_T_87; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_98 = _activated_data_e_act_z_iexp_saturated_T_97 ? 32'h20 : activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_2 = _activated_data_e_act_z_iexp_saturated_T_98; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_10 = {{32{activated_data_e_act_z_iexp_2[31]}}, activated_data_e_act_z_iexp_2} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_11 = {_activated_data_e_act_qp_iexp_T_10[63], _activated_data_e_act_qp_iexp_T_10} + {{33{_activated_data_e_act_T_88[31]}}, _activated_data_e_act_T_88}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_12 = _activated_data_e_act_qp_iexp_T_11[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_13 = _activated_data_e_act_qp_iexp_T_12; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_14 = _activated_data_e_act_qp_iexp_T_13[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_2 = _activated_data_e_act_qp_iexp_T_14; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_20 = {activated_data_e_act_qp_iexp_2[31], activated_data_e_act_qp_iexp_2} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_22; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_22 = _GEN_20; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_25; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_25 = _GEN_20; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_23 = _activated_data_e_act_q_poly_iexp_T_22[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_24 = _activated_data_e_act_q_poly_iexp_T_23; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_26 = _activated_data_e_act_q_poly_iexp_T_25[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_27 = _activated_data_e_act_q_poly_iexp_T_26; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_28 = {{32{_activated_data_e_act_q_poly_iexp_T_24[31]}}, _activated_data_e_act_q_poly_iexp_T_24} * {{32{_activated_data_e_act_q_poly_iexp_T_27[31]}}, _activated_data_e_act_q_poly_iexp_T_27}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_29 = {_activated_data_e_act_q_poly_iexp_T_28[63], _activated_data_e_act_q_poly_iexp_T_28} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_30 = _activated_data_e_act_q_poly_iexp_T_29[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_31 = _activated_data_e_act_q_poly_iexp_T_30; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_32 = _activated_data_e_act_q_poly_iexp_T_31[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_2 = _activated_data_e_act_q_poly_iexp_T_32; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_89 = activated_data_e_act_q_poly_iexp_2; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_91 = _activated_data_e_act_T_89 >> _activated_data_e_act_T_90; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_92 = _activated_data_e_act_T_91; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_2 = _activated_data_e_act_T_92; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_94 = _activated_data_e_act_T_93; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_95 = _activated_data_e_act_T_94; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_2 = _activated_data_e_act_T_65 ? _activated_data_e_act_T_67 : _activated_data_e_act_T_95; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_2 = activated_data_e_act_2; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_30_bits = _activated_data_e_scaled_T_29_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_13 = _activated_data_e_scaled_T_30_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_31; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_31 = _activated_data_e_scaled_WIRE_13; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_12_bits = _activated_data_e_scaled_T_31; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_2 = _activated_data_e_scaled_WIRE_12_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_2_sign = activated_data_e_scaled_f_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_2 = _activated_data_e_scaled_WIRE_12_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_2 = _activated_data_e_scaled_WIRE_12_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 = activated_data_e_scaled_f_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2 = activated_data_e_scaled_f_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_88 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_89 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_90 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_91 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_92 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_93 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_94 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_95 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_96 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_97 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_98 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_99 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_100 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_101 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_102 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_103 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_104 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_105 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_106 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_107 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_108 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_109 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_110 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_111 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_112 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_113 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_114 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_115 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_116 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_117 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_118 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_119 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_120 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_121 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_122 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_123 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_124 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_125 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_126 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_127 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_128 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_129 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_130 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_131 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_2 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_2} << activated_data_e_scaled_f_rec_rawIn_normDist_2; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_5 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_2 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_11 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_12 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_2 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_4 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_2 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_2_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_2 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_2 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_18 = activated_data_e_scaled_f_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_5 = activated_data_e_scaled_f_rec_rawIn_isSpecial_2 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_2_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_2 = activated_data_e_scaled_f_rec_rawIn_isSpecial_2 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_2_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_2_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_8 = ~activated_data_e_scaled_f_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_10 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_2 : activated_data_e_scaled_f_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_11 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_9, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_2_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_16 = activated_data_e_scaled_f_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_17 = activated_data_e_scaled_f_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_19 = {_activated_data_e_scaled_f_rec_T_17[2:1], _activated_data_e_scaled_f_rec_T_17[0] \| _activated_data_e_scaled_f_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_20 = {activated_data_e_scaled_f_rec_rawIn_2_sign, _activated_data_e_scaled_f_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_21 = activated_data_e_scaled_f_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_22 = {_activated_data_e_scaled_f_rec_T_20, _activated_data_e_scaled_f_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_23 = activated_data_e_scaled_f_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_2 = {_activated_data_e_scaled_f_rec_T_22, _activated_data_e_scaled_f_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_2 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_2; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_2 = _activated_data_e_scaled_rec_fn_to_in_2_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_2 = _activated_data_e_scaled_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_2 = activated_data_e_scaled_sign_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_2 = _activated_data_e_scaled_sign_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_2_isZero = activated_data_e_scaled_sign_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_2 = activated_data_e_scaled_sign_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_2 = &_activated_data_e_scaled_sign_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_4 = activated_data_e_scaled_sign_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_6 = activated_data_e_scaled_sign_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_5 = activated_data_e_scaled_sign_isSpecial_2 & _activated_data_e_scaled_sign_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_2_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_7 = ~_activated_data_e_scaled_sign_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_8 = activated_data_e_scaled_sign_isSpecial_2 & _activated_data_e_scaled_sign_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_2_isInf = _activated_data_e_scaled_sign_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_2 = _activated_data_e_scaled_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_2_sign = _activated_data_e_scaled_sign_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_2 = {1'h0, activated_data_e_scaled_sign_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_2_sExp = _activated_data_e_scaled_sign_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_8 = ~activated_data_e_scaled_sign_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_9 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_10 = _activated_data_e_scaled_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_11 = {_activated_data_e_scaled_sign_out_sig_T_9, _activated_data_e_scaled_sign_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_2_sig = _activated_data_e_scaled_sign_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_2 = activated_data_e_scaled_sign_out_2_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_32; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_14 = _activated_data_e_scaled_T_32; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_2 = activated_data_e_scaled_overflow_2 ? activated_data_e_scaled_sat_2 : _activated_data_e_scaled_WIRE_14; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_10 = $signed(activated_data_e_scaled_2) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_11 = $signed(activated_data_e_scaled_2) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_12 = _activated_data_e_clipped_T_11 ? 32'hFFFFFF80 : activated_data_e_scaled_2; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_13 = _activated_data_e_clipped_T_10 ? 32'h7F : _activated_data_e_clipped_T_12; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_14 = _activated_data_e_clipped_T_13[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_2 = _activated_data_e_clipped_T_14; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_2_0 = activated_data_e_clipped_2; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_2_0 = _activated_data_WIRE_2_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_97 = _activated_data_e_act_T_96; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_98 = $signed(io_in_bits_acc_read_resp_data_3_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_99 = _activated_data_e_act_T_98 ? io_in_bits_acc_read_resp_data_3_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_21 = {io_in_bits_acc_read_resp_data_3_0_0[31], io_in_bits_acc_read_resp_data_3_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_103; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_103 = _GEN_21; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_118; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_118 = _GEN_21; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_104 = _activated_data_e_act_T_103[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_105 = _activated_data_e_act_T_104; // @[Arithmetic.scala:95:38] wire _GEN_22 = $signed(io_in_bits_acc_read_resp_data_3_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_12; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_12 = _GEN_22; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_12; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_12 = _GEN_22; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_3 = {_activated_data_e_act_q_sign_T_12, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_13 = 33'h0 - _GEN_21; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_14 = _activated_data_e_act_q_abs_T_13[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_15 = _activated_data_e_act_q_abs_T_14; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_3 = _activated_data_e_act_q_abs_T_12 ? _activated_data_e_act_q_abs_T_15 : io_in_bits_acc_read_resp_data_3_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_22 = _activated_data_e_act_q_clipped_T_21[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_23 = _activated_data_e_act_q_clipped_T_22; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_24 = $signed(activated_data_e_act_q_abs_3) > $signed(_activated_data_e_act_q_clipped_T_23); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_26 = _activated_data_e_act_q_clipped_T_25[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_27 = _activated_data_e_act_q_clipped_T_26; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_3 = _activated_data_e_act_q_clipped_T_24 ? _activated_data_e_act_q_clipped_T_27 : activated_data_e_act_q_abs_3; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_23 = {activated_data_e_act_q_clipped_3[31], activated_data_e_act_q_clipped_3} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_33; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_33 = _GEN_23; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_36; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_36 = _GEN_23; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_34 = _activated_data_e_act_q_poly_T_33[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_35 = _activated_data_e_act_q_poly_T_34; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_37 = _activated_data_e_act_q_poly_T_36[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_38 = _activated_data_e_act_q_poly_T_37; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_39 = {{32{_activated_data_e_act_q_poly_T_35[31]}}, _activated_data_e_act_q_poly_T_35} * {{32{_activated_data_e_act_q_poly_T_38[31]}}, _activated_data_e_act_q_poly_T_38}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_40 = {_activated_data_e_act_q_poly_T_39[63], _activated_data_e_act_q_poly_T_39} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_41 = _activated_data_e_act_q_poly_T_40[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_42 = _activated_data_e_act_q_poly_T_41; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_43 = _activated_data_e_act_q_poly_T_42[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_3 = _activated_data_e_act_q_poly_T_43; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_6 = {{32{activated_data_e_act_q_sign_3[1]}}, activated_data_e_act_q_sign_3} * {{2{activated_data_e_act_q_poly_3[31]}}, activated_data_e_act_q_poly_3}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_7 = _activated_data_e_act_q_erf_T_6[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_3 = _activated_data_e_act_q_erf_T_7; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_109 = {activated_data_e_act_q_erf_3[31], activated_data_e_act_q_erf_3} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_110 = _activated_data_e_act_T_109[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_111 = _activated_data_e_act_T_110; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_112 = {{32{io_in_bits_acc_read_resp_data_3_0_0[31]}}, io_in_bits_acc_read_resp_data_3_0_0} * {{32{_activated_data_e_act_T_111[31]}}, _activated_data_e_act_T_111}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_113 = _activated_data_e_act_T_112[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_114 = _activated_data_e_act_T_113; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_119 = _activated_data_e_act_T_118[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_120 = _activated_data_e_act_T_119; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_6 = 33'h0 - {_activated_data_e_act_T_120[31], _activated_data_e_act_T_120}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_7 = _activated_data_e_act_neg_q_iexp_T_6[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_3 = _activated_data_e_act_neg_q_iexp_T_7; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_12 = {{32{activated_data_e_act_neg_q_iexp_3[31]}}, activated_data_e_act_neg_q_iexp_3} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_13 = _activated_data_e_act_z_iexp_T_12; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_14 = _activated_data_e_act_z_iexp_T_13[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_15 = _activated_data_e_act_z_iexp_T_14; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_99 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_101 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_103 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_105 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_107 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_109 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_111 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_113 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_115 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_117 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_119 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_3 = _activated_data_e_act_z_iexp_T_15[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_131; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_3; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_122 = activated_data_e_act_z_iexp_saturated_3; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_100 = _activated_data_e_act_z_iexp_saturated_T_99[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_102 = _activated_data_e_act_z_iexp_saturated_T_101[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_104 = _activated_data_e_act_z_iexp_saturated_T_103[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_106 = _activated_data_e_act_z_iexp_saturated_T_105[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_108 = _activated_data_e_act_z_iexp_saturated_T_107[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_110 = _activated_data_e_act_z_iexp_saturated_T_109[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_112 = _activated_data_e_act_z_iexp_saturated_T_111[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_114 = _activated_data_e_act_z_iexp_saturated_T_113[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_116 = _activated_data_e_act_z_iexp_saturated_T_115[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_118 = _activated_data_e_act_z_iexp_saturated_T_117[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_120 = _activated_data_e_act_z_iexp_saturated_T_119[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_121 = _activated_data_e_act_z_iexp_saturated_T_100 \| _activated_data_e_act_z_iexp_saturated_T_102; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_122 = _activated_data_e_act_z_iexp_saturated_T_121 \| _activated_data_e_act_z_iexp_saturated_T_104; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_123 = _activated_data_e_act_z_iexp_saturated_T_122 \| _activated_data_e_act_z_iexp_saturated_T_106; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_124 = _activated_data_e_act_z_iexp_saturated_T_123 \| _activated_data_e_act_z_iexp_saturated_T_108; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_125 = _activated_data_e_act_z_iexp_saturated_T_124 \| _activated_data_e_act_z_iexp_saturated_T_110; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_126 = _activated_data_e_act_z_iexp_saturated_T_125 \| _activated_data_e_act_z_iexp_saturated_T_112; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_127 = _activated_data_e_act_z_iexp_saturated_T_126 \| _activated_data_e_act_z_iexp_saturated_T_114; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_128 = _activated_data_e_act_z_iexp_saturated_T_127 \| _activated_data_e_act_z_iexp_saturated_T_116; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_129 = _activated_data_e_act_z_iexp_saturated_T_128 \| _activated_data_e_act_z_iexp_saturated_T_118; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_130 = _activated_data_e_act_z_iexp_saturated_T_129 \| _activated_data_e_act_z_iexp_saturated_T_120; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_131 = _activated_data_e_act_z_iexp_saturated_T_130 ? 32'h20 : activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_3 = _activated_data_e_act_z_iexp_saturated_T_131; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_15 = {{32{activated_data_e_act_z_iexp_3[31]}}, activated_data_e_act_z_iexp_3} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_16 = {_activated_data_e_act_qp_iexp_T_15[63], _activated_data_e_act_qp_iexp_T_15} + {{33{_activated_data_e_act_T_120[31]}}, _activated_data_e_act_T_120}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_17 = _activated_data_e_act_qp_iexp_T_16[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_18 = _activated_data_e_act_qp_iexp_T_17; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_19 = _activated_data_e_act_qp_iexp_T_18[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_3 = _activated_data_e_act_qp_iexp_T_19; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_24 = {activated_data_e_act_qp_iexp_3[31], activated_data_e_act_qp_iexp_3} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_33; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_33 = _GEN_24; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_36; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_36 = _GEN_24; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_34 = _activated_data_e_act_q_poly_iexp_T_33[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_35 = _activated_data_e_act_q_poly_iexp_T_34; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_37 = _activated_data_e_act_q_poly_iexp_T_36[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_38 = _activated_data_e_act_q_poly_iexp_T_37; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_39 = {{32{_activated_data_e_act_q_poly_iexp_T_35[31]}}, _activated_data_e_act_q_poly_iexp_T_35} * {{32{_activated_data_e_act_q_poly_iexp_T_38[31]}}, _activated_data_e_act_q_poly_iexp_T_38}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_40 = {_activated_data_e_act_q_poly_iexp_T_39[63], _activated_data_e_act_q_poly_iexp_T_39} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_41 = _activated_data_e_act_q_poly_iexp_T_40[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_42 = _activated_data_e_act_q_poly_iexp_T_41; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_43 = _activated_data_e_act_q_poly_iexp_T_42[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_3 = _activated_data_e_act_q_poly_iexp_T_43; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_121 = activated_data_e_act_q_poly_iexp_3; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_123 = _activated_data_e_act_T_121 >> _activated_data_e_act_T_122; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_124 = _activated_data_e_act_T_123; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_3 = _activated_data_e_act_T_124; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_126 = _activated_data_e_act_T_125; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_127 = _activated_data_e_act_T_126; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_3 = _activated_data_e_act_T_97 ? _activated_data_e_act_T_99 : _activated_data_e_act_T_127; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_3 = activated_data_e_act_3; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_41_bits = _activated_data_e_scaled_T_40_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_18 = _activated_data_e_scaled_T_41_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_42; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_42 = _activated_data_e_scaled_WIRE_18; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_17_bits = _activated_data_e_scaled_T_42; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_3 = _activated_data_e_scaled_WIRE_17_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_3_sign = activated_data_e_scaled_f_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_3 = _activated_data_e_scaled_WIRE_17_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_3 = _activated_data_e_scaled_WIRE_17_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 = activated_data_e_scaled_f_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3 = activated_data_e_scaled_f_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_132 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_133 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_134 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_135 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_136 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_137 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_138 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_139 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_140 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_141 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_142 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_143 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_144 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_145 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_146 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_147 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_148 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_149 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_150 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_151 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_152 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_153 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_154 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_155 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_156 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_157 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_158 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_159 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_160 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_161 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_162 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_163 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_164 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_165 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_166 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_167 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_168 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_169 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_170 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_171 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_172 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_173 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_174 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_175 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_3 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_3} << activated_data_e_scaled_f_rec_rawIn_normDist_3; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_7 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_3 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_3}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_16 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_17 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_3 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_6 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_3 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_3_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_3 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_3 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_26 = activated_data_e_scaled_f_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_7 = activated_data_e_scaled_f_rec_rawIn_isSpecial_3 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_3_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_3 = activated_data_e_scaled_f_rec_rawIn_isSpecial_3 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_3_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_3_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_12 = ~activated_data_e_scaled_f_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_14 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_3 : activated_data_e_scaled_f_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_15 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_13, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_3_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_24 = activated_data_e_scaled_f_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_25 = activated_data_e_scaled_f_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_24; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_27 = {_activated_data_e_scaled_f_rec_T_25[2:1], _activated_data_e_scaled_f_rec_T_25[0] \| _activated_data_e_scaled_f_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_28 = {activated_data_e_scaled_f_rec_rawIn_3_sign, _activated_data_e_scaled_f_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_29 = activated_data_e_scaled_f_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_30 = {_activated_data_e_scaled_f_rec_T_28, _activated_data_e_scaled_f_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_31 = activated_data_e_scaled_f_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_3 = {_activated_data_e_scaled_f_rec_T_30, _activated_data_e_scaled_f_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_3 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_3; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_3 = _activated_data_e_scaled_rec_fn_to_in_3_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_3 = _activated_data_e_scaled_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_3 = activated_data_e_scaled_sign_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_3 = _activated_data_e_scaled_sign_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_3_isZero = activated_data_e_scaled_sign_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_3 = activated_data_e_scaled_sign_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_3 = &_activated_data_e_scaled_sign_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_3_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_3_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_3_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_3_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_3_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_6 = activated_data_e_scaled_sign_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_9 = activated_data_e_scaled_sign_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_7 = activated_data_e_scaled_sign_isSpecial_3 & _activated_data_e_scaled_sign_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_3_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_10 = ~_activated_data_e_scaled_sign_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_11 = activated_data_e_scaled_sign_isSpecial_3 & _activated_data_e_scaled_sign_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_3_isInf = _activated_data_e_scaled_sign_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_3 = _activated_data_e_scaled_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_3_sign = _activated_data_e_scaled_sign_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_3 = {1'h0, activated_data_e_scaled_sign_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_3_sExp = _activated_data_e_scaled_sign_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_12 = ~activated_data_e_scaled_sign_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_13 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_14 = _activated_data_e_scaled_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_15 = {_activated_data_e_scaled_sign_out_sig_T_13, _activated_data_e_scaled_sign_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_3_sig = _activated_data_e_scaled_sign_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_3 = activated_data_e_scaled_sign_out_3_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_43; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_19 = _activated_data_e_scaled_T_43; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_3 = activated_data_e_scaled_overflow_3 ? activated_data_e_scaled_sat_3 : _activated_data_e_scaled_WIRE_19; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_15 = $signed(activated_data_e_scaled_3) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_16 = $signed(activated_data_e_scaled_3) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_17 = _activated_data_e_clipped_T_16 ? 32'hFFFFFF80 : activated_data_e_scaled_3; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_18 = _activated_data_e_clipped_T_15 ? 32'h7F : _activated_data_e_clipped_T_17; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_19 = _activated_data_e_clipped_T_18[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_3 = _activated_data_e_clipped_T_19; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_3_0 = activated_data_e_clipped_3; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_3_0 = _activated_data_WIRE_3_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_129 = _activated_data_e_act_T_128; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_130 = $signed(io_in_bits_acc_read_resp_data_4_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_131 = _activated_data_e_act_T_130 ? io_in_bits_acc_read_resp_data_4_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_25 = {io_in_bits_acc_read_resp_data_4_0_0[31], io_in_bits_acc_read_resp_data_4_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_135; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_135 = _GEN_25; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_150; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_150 = _GEN_25; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_136 = _activated_data_e_act_T_135[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_137 = _activated_data_e_act_T_136; // @[Arithmetic.scala:95:38] wire _GEN_26 = $signed(io_in_bits_acc_read_resp_data_4_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_16; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_16 = _GEN_26; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_16; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_16 = _GEN_26; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_4 = {_activated_data_e_act_q_sign_T_16, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_17 = 33'h0 - _GEN_25; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_18 = _activated_data_e_act_q_abs_T_17[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_19 = _activated_data_e_act_q_abs_T_18; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_4 = _activated_data_e_act_q_abs_T_16 ? _activated_data_e_act_q_abs_T_19 : io_in_bits_acc_read_resp_data_4_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_29 = _activated_data_e_act_q_clipped_T_28[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_30 = _activated_data_e_act_q_clipped_T_29; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_31 = $signed(activated_data_e_act_q_abs_4) > $signed(_activated_data_e_act_q_clipped_T_30); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_33 = _activated_data_e_act_q_clipped_T_32[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_34 = _activated_data_e_act_q_clipped_T_33; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_4 = _activated_data_e_act_q_clipped_T_31 ? _activated_data_e_act_q_clipped_T_34 : activated_data_e_act_q_abs_4; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_27 = {activated_data_e_act_q_clipped_4[31], activated_data_e_act_q_clipped_4} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_44; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_44 = _GEN_27; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_47; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_47 = _GEN_27; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_45 = _activated_data_e_act_q_poly_T_44[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_46 = _activated_data_e_act_q_poly_T_45; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_48 = _activated_data_e_act_q_poly_T_47[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_49 = _activated_data_e_act_q_poly_T_48; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_50 = {{32{_activated_data_e_act_q_poly_T_46[31]}}, _activated_data_e_act_q_poly_T_46} * {{32{_activated_data_e_act_q_poly_T_49[31]}}, _activated_data_e_act_q_poly_T_49}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_51 = {_activated_data_e_act_q_poly_T_50[63], _activated_data_e_act_q_poly_T_50} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_52 = _activated_data_e_act_q_poly_T_51[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_53 = _activated_data_e_act_q_poly_T_52; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_54 = _activated_data_e_act_q_poly_T_53[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_4 = _activated_data_e_act_q_poly_T_54; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_8 = {{32{activated_data_e_act_q_sign_4[1]}}, activated_data_e_act_q_sign_4} * {{2{activated_data_e_act_q_poly_4[31]}}, activated_data_e_act_q_poly_4}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_9 = _activated_data_e_act_q_erf_T_8[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_4 = _activated_data_e_act_q_erf_T_9; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_141 = {activated_data_e_act_q_erf_4[31], activated_data_e_act_q_erf_4} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_142 = _activated_data_e_act_T_141[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_143 = _activated_data_e_act_T_142; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_144 = {{32{io_in_bits_acc_read_resp_data_4_0_0[31]}}, io_in_bits_acc_read_resp_data_4_0_0} * {{32{_activated_data_e_act_T_143[31]}}, _activated_data_e_act_T_143}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_145 = _activated_data_e_act_T_144[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_146 = _activated_data_e_act_T_145; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_151 = _activated_data_e_act_T_150[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_152 = _activated_data_e_act_T_151; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_8 = 33'h0 - {_activated_data_e_act_T_152[31], _activated_data_e_act_T_152}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_9 = _activated_data_e_act_neg_q_iexp_T_8[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_4 = _activated_data_e_act_neg_q_iexp_T_9; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_16 = {{32{activated_data_e_act_neg_q_iexp_4[31]}}, activated_data_e_act_neg_q_iexp_4} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_17 = _activated_data_e_act_z_iexp_T_16; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_18 = _activated_data_e_act_z_iexp_T_17[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_19 = _activated_data_e_act_z_iexp_T_18; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_132 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_134 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_136 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_138 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_140 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_142 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_144 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_146 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_148 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_150 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_152 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_4 = _activated_data_e_act_z_iexp_T_19[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_164; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_4; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_154 = activated_data_e_act_z_iexp_saturated_4; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_133 = _activated_data_e_act_z_iexp_saturated_T_132[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_135 = _activated_data_e_act_z_iexp_saturated_T_134[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_137 = _activated_data_e_act_z_iexp_saturated_T_136[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_139 = _activated_data_e_act_z_iexp_saturated_T_138[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_141 = _activated_data_e_act_z_iexp_saturated_T_140[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_143 = _activated_data_e_act_z_iexp_saturated_T_142[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_145 = _activated_data_e_act_z_iexp_saturated_T_144[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_147 = _activated_data_e_act_z_iexp_saturated_T_146[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_149 = _activated_data_e_act_z_iexp_saturated_T_148[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_151 = _activated_data_e_act_z_iexp_saturated_T_150[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_153 = _activated_data_e_act_z_iexp_saturated_T_152[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_154 = _activated_data_e_act_z_iexp_saturated_T_133 \| _activated_data_e_act_z_iexp_saturated_T_135; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_155 = _activated_data_e_act_z_iexp_saturated_T_154 \| _activated_data_e_act_z_iexp_saturated_T_137; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_156 = _activated_data_e_act_z_iexp_saturated_T_155 \| _activated_data_e_act_z_iexp_saturated_T_139; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_157 = _activated_data_e_act_z_iexp_saturated_T_156 \| _activated_data_e_act_z_iexp_saturated_T_141; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_158 = _activated_data_e_act_z_iexp_saturated_T_157 \| _activated_data_e_act_z_iexp_saturated_T_143; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_159 = _activated_data_e_act_z_iexp_saturated_T_158 \| _activated_data_e_act_z_iexp_saturated_T_145; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_160 = _activated_data_e_act_z_iexp_saturated_T_159 \| _activated_data_e_act_z_iexp_saturated_T_147; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_161 = _activated_data_e_act_z_iexp_saturated_T_160 \| _activated_data_e_act_z_iexp_saturated_T_149; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_162 = _activated_data_e_act_z_iexp_saturated_T_161 \| _activated_data_e_act_z_iexp_saturated_T_151; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_163 = _activated_data_e_act_z_iexp_saturated_T_162 \| _activated_data_e_act_z_iexp_saturated_T_153; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_164 = _activated_data_e_act_z_iexp_saturated_T_163 ? 32'h20 : activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_4 = _activated_data_e_act_z_iexp_saturated_T_164; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_20 = {{32{activated_data_e_act_z_iexp_4[31]}}, activated_data_e_act_z_iexp_4} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_21 = {_activated_data_e_act_qp_iexp_T_20[63], _activated_data_e_act_qp_iexp_T_20} + {{33{_activated_data_e_act_T_152[31]}}, _activated_data_e_act_T_152}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_22 = _activated_data_e_act_qp_iexp_T_21[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_23 = _activated_data_e_act_qp_iexp_T_22; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_24 = _activated_data_e_act_qp_iexp_T_23[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_4 = _activated_data_e_act_qp_iexp_T_24; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_28 = {activated_data_e_act_qp_iexp_4[31], activated_data_e_act_qp_iexp_4} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_44; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_44 = _GEN_28; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_47; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_47 = _GEN_28; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_45 = _activated_data_e_act_q_poly_iexp_T_44[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_46 = _activated_data_e_act_q_poly_iexp_T_45; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_48 = _activated_data_e_act_q_poly_iexp_T_47[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_49 = _activated_data_e_act_q_poly_iexp_T_48; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_50 = {{32{_activated_data_e_act_q_poly_iexp_T_46[31]}}, _activated_data_e_act_q_poly_iexp_T_46} * {{32{_activated_data_e_act_q_poly_iexp_T_49[31]}}, _activated_data_e_act_q_poly_iexp_T_49}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_51 = {_activated_data_e_act_q_poly_iexp_T_50[63], _activated_data_e_act_q_poly_iexp_T_50} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_52 = _activated_data_e_act_q_poly_iexp_T_51[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_53 = _activated_data_e_act_q_poly_iexp_T_52; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_54 = _activated_data_e_act_q_poly_iexp_T_53[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_4 = _activated_data_e_act_q_poly_iexp_T_54; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_153 = activated_data_e_act_q_poly_iexp_4; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_155 = _activated_data_e_act_T_153 >> _activated_data_e_act_T_154; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_156 = _activated_data_e_act_T_155; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_4 = _activated_data_e_act_T_156; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_158 = _activated_data_e_act_T_157; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_159 = _activated_data_e_act_T_158; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_4 = _activated_data_e_act_T_129 ? _activated_data_e_act_T_131 : _activated_data_e_act_T_159; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_4 = activated_data_e_act_4; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_52_bits = _activated_data_e_scaled_T_51_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_23 = _activated_data_e_scaled_T_52_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_53; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_53 = _activated_data_e_scaled_WIRE_23; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_22_bits = _activated_data_e_scaled_T_53; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_4 = _activated_data_e_scaled_WIRE_22_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_4_sign = activated_data_e_scaled_f_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_4 = _activated_data_e_scaled_WIRE_22_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_4 = _activated_data_e_scaled_WIRE_22_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 = activated_data_e_scaled_f_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4 = activated_data_e_scaled_f_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_176 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_177 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_178 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_179 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_180 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_181 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_182 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_183 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_184 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_185 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_186 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_187 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_188 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_189 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_190 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_191 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_192 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_193 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_194 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_195 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_196 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_197 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_198 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_199 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_200 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_201 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_202 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_203 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_204 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_205 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_206 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_207 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_208 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_209 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_210 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_211 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_212 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_213 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_214 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_215 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_216 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_217 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_218 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_219 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_4 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_4} << activated_data_e_scaled_f_rec_rawIn_normDist_4; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_9 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_4 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_4}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_21 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_22 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_4 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_8 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_4 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_4_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_4 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_4 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_34 = activated_data_e_scaled_f_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_9 = activated_data_e_scaled_f_rec_rawIn_isSpecial_4 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_4_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_4 = activated_data_e_scaled_f_rec_rawIn_isSpecial_4 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_4_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_4_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_16 = ~activated_data_e_scaled_f_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_18 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_4 : activated_data_e_scaled_f_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_19 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_17, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_4_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_32 = activated_data_e_scaled_f_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_33 = activated_data_e_scaled_f_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_32; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_35 = {_activated_data_e_scaled_f_rec_T_33[2:1], _activated_data_e_scaled_f_rec_T_33[0] \| _activated_data_e_scaled_f_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_36 = {activated_data_e_scaled_f_rec_rawIn_4_sign, _activated_data_e_scaled_f_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_37 = activated_data_e_scaled_f_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_38 = {_activated_data_e_scaled_f_rec_T_36, _activated_data_e_scaled_f_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_39 = activated_data_e_scaled_f_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_4 = {_activated_data_e_scaled_f_rec_T_38, _activated_data_e_scaled_f_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_4 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_4; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_4 = _activated_data_e_scaled_rec_fn_to_in_4_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_4 = _activated_data_e_scaled_muladder_4_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_4 = activated_data_e_scaled_sign_exp_4[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_4 = _activated_data_e_scaled_sign_isZero_T_4 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_4_isZero = activated_data_e_scaled_sign_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_4 = activated_data_e_scaled_sign_exp_4[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_4 = &_activated_data_e_scaled_sign_isSpecial_T_4; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_14; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_4; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_4; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_19; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_4_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_4_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_4_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_4_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_4_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_8 = activated_data_e_scaled_sign_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_12 = activated_data_e_scaled_sign_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_9 = activated_data_e_scaled_sign_isSpecial_4 & _activated_data_e_scaled_sign_out_isNaN_T_8; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_4_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_13 = ~_activated_data_e_scaled_sign_out_isInf_T_12; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_14 = activated_data_e_scaled_sign_isSpecial_4 & _activated_data_e_scaled_sign_out_isInf_T_13; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_4_isInf = _activated_data_e_scaled_sign_out_isInf_T_14; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_4 = _activated_data_e_scaled_muladder_4_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_4_sign = _activated_data_e_scaled_sign_out_sign_T_4; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_4 = {1'h0, activated_data_e_scaled_sign_exp_4}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_4_sExp = _activated_data_e_scaled_sign_out_sExp_T_4; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_16 = ~activated_data_e_scaled_sign_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_17 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_16}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_18 = _activated_data_e_scaled_muladder_4_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_19 = {_activated_data_e_scaled_sign_out_sig_T_17, _activated_data_e_scaled_sign_out_sig_T_18}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_4_sig = _activated_data_e_scaled_sign_out_sig_T_19; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_4 = activated_data_e_scaled_sign_out_4_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_54; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_24 = _activated_data_e_scaled_T_54; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_4 = activated_data_e_scaled_overflow_4 ? activated_data_e_scaled_sat_4 : _activated_data_e_scaled_WIRE_24; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_20 = $signed(activated_data_e_scaled_4) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_21 = $signed(activated_data_e_scaled_4) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_22 = _activated_data_e_clipped_T_21 ? 32'hFFFFFF80 : activated_data_e_scaled_4; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_23 = _activated_data_e_clipped_T_20 ? 32'h7F : _activated_data_e_clipped_T_22; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_24 = _activated_data_e_clipped_T_23[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_4 = _activated_data_e_clipped_T_24; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_4_0 = activated_data_e_clipped_4; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_4_0 = _activated_data_WIRE_4_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_161 = _activated_data_e_act_T_160; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_162 = $signed(io_in_bits_acc_read_resp_data_5_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_163 = _activated_data_e_act_T_162 ? io_in_bits_acc_read_resp_data_5_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_29 = {io_in_bits_acc_read_resp_data_5_0_0[31], io_in_bits_acc_read_resp_data_5_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_167; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_167 = _GEN_29; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_182; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_182 = _GEN_29; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_168 = _activated_data_e_act_T_167[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_169 = _activated_data_e_act_T_168; // @[Arithmetic.scala:95:38] wire _GEN_30 = $signed(io_in_bits_acc_read_resp_data_5_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_20; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_20 = _GEN_30; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_20; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_20 = _GEN_30; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_5 = {_activated_data_e_act_q_sign_T_20, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_21 = 33'h0 - _GEN_29; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_22 = _activated_data_e_act_q_abs_T_21[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_23 = _activated_data_e_act_q_abs_T_22; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_5 = _activated_data_e_act_q_abs_T_20 ? _activated_data_e_act_q_abs_T_23 : io_in_bits_acc_read_resp_data_5_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_36 = _activated_data_e_act_q_clipped_T_35[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_37 = _activated_data_e_act_q_clipped_T_36; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_38 = $signed(activated_data_e_act_q_abs_5) > $signed(_activated_data_e_act_q_clipped_T_37); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_40 = _activated_data_e_act_q_clipped_T_39[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_41 = _activated_data_e_act_q_clipped_T_40; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_5 = _activated_data_e_act_q_clipped_T_38 ? _activated_data_e_act_q_clipped_T_41 : activated_data_e_act_q_abs_5; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_31 = {activated_data_e_act_q_clipped_5[31], activated_data_e_act_q_clipped_5} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_55; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_55 = _GEN_31; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_58; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_58 = _GEN_31; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_56 = _activated_data_e_act_q_poly_T_55[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_57 = _activated_data_e_act_q_poly_T_56; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_59 = _activated_data_e_act_q_poly_T_58[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_60 = _activated_data_e_act_q_poly_T_59; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_61 = {{32{_activated_data_e_act_q_poly_T_57[31]}}, _activated_data_e_act_q_poly_T_57} * {{32{_activated_data_e_act_q_poly_T_60[31]}}, _activated_data_e_act_q_poly_T_60}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_62 = {_activated_data_e_act_q_poly_T_61[63], _activated_data_e_act_q_poly_T_61} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_63 = _activated_data_e_act_q_poly_T_62[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_64 = _activated_data_e_act_q_poly_T_63; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_65 = _activated_data_e_act_q_poly_T_64[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_5 = _activated_data_e_act_q_poly_T_65; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_10 = {{32{activated_data_e_act_q_sign_5[1]}}, activated_data_e_act_q_sign_5} * {{2{activated_data_e_act_q_poly_5[31]}}, activated_data_e_act_q_poly_5}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_11 = _activated_data_e_act_q_erf_T_10[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_5 = _activated_data_e_act_q_erf_T_11; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_173 = {activated_data_e_act_q_erf_5[31], activated_data_e_act_q_erf_5} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_174 = _activated_data_e_act_T_173[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_175 = _activated_data_e_act_T_174; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_176 = {{32{io_in_bits_acc_read_resp_data_5_0_0[31]}}, io_in_bits_acc_read_resp_data_5_0_0} * {{32{_activated_data_e_act_T_175[31]}}, _activated_data_e_act_T_175}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_177 = _activated_data_e_act_T_176[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_178 = _activated_data_e_act_T_177; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_183 = _activated_data_e_act_T_182[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_184 = _activated_data_e_act_T_183; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_10 = 33'h0 - {_activated_data_e_act_T_184[31], _activated_data_e_act_T_184}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_11 = _activated_data_e_act_neg_q_iexp_T_10[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_5 = _activated_data_e_act_neg_q_iexp_T_11; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_20 = {{32{activated_data_e_act_neg_q_iexp_5[31]}}, activated_data_e_act_neg_q_iexp_5} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_21 = _activated_data_e_act_z_iexp_T_20; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_22 = _activated_data_e_act_z_iexp_T_21[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_23 = _activated_data_e_act_z_iexp_T_22; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_165 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_167 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_169 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_171 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_173 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_175 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_177 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_179 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_181 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_183 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_185 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_5 = _activated_data_e_act_z_iexp_T_23[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_197; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_5; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_186 = activated_data_e_act_z_iexp_saturated_5; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_166 = _activated_data_e_act_z_iexp_saturated_T_165[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_168 = _activated_data_e_act_z_iexp_saturated_T_167[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_170 = _activated_data_e_act_z_iexp_saturated_T_169[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_172 = _activated_data_e_act_z_iexp_saturated_T_171[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_174 = _activated_data_e_act_z_iexp_saturated_T_173[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_176 = _activated_data_e_act_z_iexp_saturated_T_175[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_178 = _activated_data_e_act_z_iexp_saturated_T_177[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_180 = _activated_data_e_act_z_iexp_saturated_T_179[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_182 = _activated_data_e_act_z_iexp_saturated_T_181[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_184 = _activated_data_e_act_z_iexp_saturated_T_183[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_186 = _activated_data_e_act_z_iexp_saturated_T_185[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_187 = _activated_data_e_act_z_iexp_saturated_T_166 \| _activated_data_e_act_z_iexp_saturated_T_168; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_188 = _activated_data_e_act_z_iexp_saturated_T_187 \| _activated_data_e_act_z_iexp_saturated_T_170; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_189 = _activated_data_e_act_z_iexp_saturated_T_188 \| _activated_data_e_act_z_iexp_saturated_T_172; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_190 = _activated_data_e_act_z_iexp_saturated_T_189 \| _activated_data_e_act_z_iexp_saturated_T_174; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_191 = _activated_data_e_act_z_iexp_saturated_T_190 \| _activated_data_e_act_z_iexp_saturated_T_176; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_192 = _activated_data_e_act_z_iexp_saturated_T_191 \| _activated_data_e_act_z_iexp_saturated_T_178; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_193 = _activated_data_e_act_z_iexp_saturated_T_192 \| _activated_data_e_act_z_iexp_saturated_T_180; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_194 = _activated_data_e_act_z_iexp_saturated_T_193 \| _activated_data_e_act_z_iexp_saturated_T_182; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_195 = _activated_data_e_act_z_iexp_saturated_T_194 \| _activated_data_e_act_z_iexp_saturated_T_184; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_196 = _activated_data_e_act_z_iexp_saturated_T_195 \| _activated_data_e_act_z_iexp_saturated_T_186; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_197 = _activated_data_e_act_z_iexp_saturated_T_196 ? 32'h20 : activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_5 = _activated_data_e_act_z_iexp_saturated_T_197; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_25 = {{32{activated_data_e_act_z_iexp_5[31]}}, activated_data_e_act_z_iexp_5} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_26 = {_activated_data_e_act_qp_iexp_T_25[63], _activated_data_e_act_qp_iexp_T_25} + {{33{_activated_data_e_act_T_184[31]}}, _activated_data_e_act_T_184}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_27 = _activated_data_e_act_qp_iexp_T_26[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_28 = _activated_data_e_act_qp_iexp_T_27; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_29 = _activated_data_e_act_qp_iexp_T_28[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_5 = _activated_data_e_act_qp_iexp_T_29; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_32 = {activated_data_e_act_qp_iexp_5[31], activated_data_e_act_qp_iexp_5} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_55; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_55 = _GEN_32; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_58; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_58 = _GEN_32; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_56 = _activated_data_e_act_q_poly_iexp_T_55[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_57 = _activated_data_e_act_q_poly_iexp_T_56; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_59 = _activated_data_e_act_q_poly_iexp_T_58[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_60 = _activated_data_e_act_q_poly_iexp_T_59; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_61 = {{32{_activated_data_e_act_q_poly_iexp_T_57[31]}}, _activated_data_e_act_q_poly_iexp_T_57} * {{32{_activated_data_e_act_q_poly_iexp_T_60[31]}}, _activated_data_e_act_q_poly_iexp_T_60}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_62 = {_activated_data_e_act_q_poly_iexp_T_61[63], _activated_data_e_act_q_poly_iexp_T_61} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_63 = _activated_data_e_act_q_poly_iexp_T_62[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_64 = _activated_data_e_act_q_poly_iexp_T_63; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_65 = _activated_data_e_act_q_poly_iexp_T_64[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_5 = _activated_data_e_act_q_poly_iexp_T_65; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_185 = activated_data_e_act_q_poly_iexp_5; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_187 = _activated_data_e_act_T_185 >> _activated_data_e_act_T_186; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_188 = _activated_data_e_act_T_187; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_5 = _activated_data_e_act_T_188; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_190 = _activated_data_e_act_T_189; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_191 = _activated_data_e_act_T_190; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_5 = _activated_data_e_act_T_161 ? _activated_data_e_act_T_163 : _activated_data_e_act_T_191; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_5 = activated_data_e_act_5; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_63_bits = _activated_data_e_scaled_T_62_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_28 = _activated_data_e_scaled_T_63_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_64; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_64 = _activated_data_e_scaled_WIRE_28; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_27_bits = _activated_data_e_scaled_T_64; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_5 = _activated_data_e_scaled_WIRE_27_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_5_sign = activated_data_e_scaled_f_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_5 = _activated_data_e_scaled_WIRE_27_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_5 = _activated_data_e_scaled_WIRE_27_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 = activated_data_e_scaled_f_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5 = activated_data_e_scaled_f_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_220 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_221 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_222 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_223 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_224 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_225 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_226 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_227 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_228 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_229 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_230 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_231 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_232 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_233 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_234 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_235 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_236 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_237 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_238 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_239 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_240 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_241 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_242 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_243 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_244 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_245 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_246 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_247 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_248 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_249 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_250 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_251 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_252 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_253 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_254 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_255 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_256 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_257 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_258 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_259 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_260 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_261 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_262 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_263 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_5 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_5} << activated_data_e_scaled_f_rec_rawIn_normDist_5; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_11 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_5 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_5}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_26 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_27 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_5 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_10 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_5 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_5_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_5 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_5 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_42 = activated_data_e_scaled_f_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_11 = activated_data_e_scaled_f_rec_rawIn_isSpecial_5 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_5_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_5 = activated_data_e_scaled_f_rec_rawIn_isSpecial_5 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_5_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_5_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_20 = ~activated_data_e_scaled_f_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_22 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_5 : activated_data_e_scaled_f_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_23 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_21, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_5_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_40 = activated_data_e_scaled_f_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_41 = activated_data_e_scaled_f_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_40; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_43 = {_activated_data_e_scaled_f_rec_T_41[2:1], _activated_data_e_scaled_f_rec_T_41[0] \| _activated_data_e_scaled_f_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_44 = {activated_data_e_scaled_f_rec_rawIn_5_sign, _activated_data_e_scaled_f_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_45 = activated_data_e_scaled_f_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_46 = {_activated_data_e_scaled_f_rec_T_44, _activated_data_e_scaled_f_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_47 = activated_data_e_scaled_f_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_5 = {_activated_data_e_scaled_f_rec_T_46, _activated_data_e_scaled_f_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_5 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_5; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_5 = _activated_data_e_scaled_rec_fn_to_in_5_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_5 = _activated_data_e_scaled_muladder_5_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_5 = activated_data_e_scaled_sign_exp_5[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_5 = _activated_data_e_scaled_sign_isZero_T_5 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_5_isZero = activated_data_e_scaled_sign_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_5 = activated_data_e_scaled_sign_exp_5[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_5 = &_activated_data_e_scaled_sign_isSpecial_T_5; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_17; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_5; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_5; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_23; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_5_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_5_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_5_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_5_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_5_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_10 = activated_data_e_scaled_sign_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_15 = activated_data_e_scaled_sign_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_11 = activated_data_e_scaled_sign_isSpecial_5 & _activated_data_e_scaled_sign_out_isNaN_T_10; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_5_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_16 = ~_activated_data_e_scaled_sign_out_isInf_T_15; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_17 = activated_data_e_scaled_sign_isSpecial_5 & _activated_data_e_scaled_sign_out_isInf_T_16; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_5_isInf = _activated_data_e_scaled_sign_out_isInf_T_17; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_5 = _activated_data_e_scaled_muladder_5_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_5_sign = _activated_data_e_scaled_sign_out_sign_T_5; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_5 = {1'h0, activated_data_e_scaled_sign_exp_5}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_5_sExp = _activated_data_e_scaled_sign_out_sExp_T_5; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_20 = ~activated_data_e_scaled_sign_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_21 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_20}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_22 = _activated_data_e_scaled_muladder_5_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_23 = {_activated_data_e_scaled_sign_out_sig_T_21, _activated_data_e_scaled_sign_out_sig_T_22}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_5_sig = _activated_data_e_scaled_sign_out_sig_T_23; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_5 = activated_data_e_scaled_sign_out_5_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_65; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_29 = _activated_data_e_scaled_T_65; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_5 = activated_data_e_scaled_overflow_5 ? activated_data_e_scaled_sat_5 : _activated_data_e_scaled_WIRE_29; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_25 = $signed(activated_data_e_scaled_5) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_26 = $signed(activated_data_e_scaled_5) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_27 = _activated_data_e_clipped_T_26 ? 32'hFFFFFF80 : activated_data_e_scaled_5; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_28 = _activated_data_e_clipped_T_25 ? 32'h7F : _activated_data_e_clipped_T_27; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_29 = _activated_data_e_clipped_T_28[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_5 = _activated_data_e_clipped_T_29; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_5_0 = activated_data_e_clipped_5; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_5_0 = _activated_data_WIRE_5_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_193 = _activated_data_e_act_T_192; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_194 = $signed(io_in_bits_acc_read_resp_data_6_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_195 = _activated_data_e_act_T_194 ? io_in_bits_acc_read_resp_data_6_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_33 = {io_in_bits_acc_read_resp_data_6_0_0[31], io_in_bits_acc_read_resp_data_6_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_199; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_199 = _GEN_33; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_214; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_214 = _GEN_33; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_200 = _activated_data_e_act_T_199[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_201 = _activated_data_e_act_T_200; // @[Arithmetic.scala:95:38] wire _GEN_34 = $signed(io_in_bits_acc_read_resp_data_6_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_24; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_24 = _GEN_34; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_24; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_24 = _GEN_34; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_6 = {_activated_data_e_act_q_sign_T_24, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_25 = 33'h0 - _GEN_33; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_26 = _activated_data_e_act_q_abs_T_25[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_27 = _activated_data_e_act_q_abs_T_26; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_6 = _activated_data_e_act_q_abs_T_24 ? _activated_data_e_act_q_abs_T_27 : io_in_bits_acc_read_resp_data_6_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_43 = _activated_data_e_act_q_clipped_T_42[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_44 = _activated_data_e_act_q_clipped_T_43; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_45 = $signed(activated_data_e_act_q_abs_6) > $signed(_activated_data_e_act_q_clipped_T_44); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_47 = _activated_data_e_act_q_clipped_T_46[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_48 = _activated_data_e_act_q_clipped_T_47; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_6 = _activated_data_e_act_q_clipped_T_45 ? _activated_data_e_act_q_clipped_T_48 : activated_data_e_act_q_abs_6; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_35 = {activated_data_e_act_q_clipped_6[31], activated_data_e_act_q_clipped_6} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_66; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_66 = _GEN_35; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_69; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_69 = _GEN_35; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_67 = _activated_data_e_act_q_poly_T_66[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_68 = _activated_data_e_act_q_poly_T_67; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_70 = _activated_data_e_act_q_poly_T_69[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_71 = _activated_data_e_act_q_poly_T_70; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_72 = {{32{_activated_data_e_act_q_poly_T_68[31]}}, _activated_data_e_act_q_poly_T_68} * {{32{_activated_data_e_act_q_poly_T_71[31]}}, _activated_data_e_act_q_poly_T_71}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_73 = {_activated_data_e_act_q_poly_T_72[63], _activated_data_e_act_q_poly_T_72} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_74 = _activated_data_e_act_q_poly_T_73[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_75 = _activated_data_e_act_q_poly_T_74; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_76 = _activated_data_e_act_q_poly_T_75[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_6 = _activated_data_e_act_q_poly_T_76; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_12 = {{32{activated_data_e_act_q_sign_6[1]}}, activated_data_e_act_q_sign_6} * {{2{activated_data_e_act_q_poly_6[31]}}, activated_data_e_act_q_poly_6}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_13 = _activated_data_e_act_q_erf_T_12[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_6 = _activated_data_e_act_q_erf_T_13; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_205 = {activated_data_e_act_q_erf_6[31], activated_data_e_act_q_erf_6} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_206 = _activated_data_e_act_T_205[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_207 = _activated_data_e_act_T_206; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_208 = {{32{io_in_bits_acc_read_resp_data_6_0_0[31]}}, io_in_bits_acc_read_resp_data_6_0_0} * {{32{_activated_data_e_act_T_207[31]}}, _activated_data_e_act_T_207}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_209 = _activated_data_e_act_T_208[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_210 = _activated_data_e_act_T_209; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_215 = _activated_data_e_act_T_214[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_216 = _activated_data_e_act_T_215; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_12 = 33'h0 - {_activated_data_e_act_T_216[31], _activated_data_e_act_T_216}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_13 = _activated_data_e_act_neg_q_iexp_T_12[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_6 = _activated_data_e_act_neg_q_iexp_T_13; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_24 = {{32{activated_data_e_act_neg_q_iexp_6[31]}}, activated_data_e_act_neg_q_iexp_6} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_25 = _activated_data_e_act_z_iexp_T_24; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_26 = _activated_data_e_act_z_iexp_T_25[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_27 = _activated_data_e_act_z_iexp_T_26; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_198 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_200 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_202 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_204 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_206 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_208 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_210 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_212 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_214 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_216 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_218 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_6 = _activated_data_e_act_z_iexp_T_27[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_230; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_6; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_218 = activated_data_e_act_z_iexp_saturated_6; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_199 = _activated_data_e_act_z_iexp_saturated_T_198[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_201 = _activated_data_e_act_z_iexp_saturated_T_200[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_203 = _activated_data_e_act_z_iexp_saturated_T_202[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_205 = _activated_data_e_act_z_iexp_saturated_T_204[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_207 = _activated_data_e_act_z_iexp_saturated_T_206[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_209 = _activated_data_e_act_z_iexp_saturated_T_208[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_211 = _activated_data_e_act_z_iexp_saturated_T_210[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_213 = _activated_data_e_act_z_iexp_saturated_T_212[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_215 = _activated_data_e_act_z_iexp_saturated_T_214[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_217 = _activated_data_e_act_z_iexp_saturated_T_216[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_219 = _activated_data_e_act_z_iexp_saturated_T_218[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_220 = _activated_data_e_act_z_iexp_saturated_T_199 \| _activated_data_e_act_z_iexp_saturated_T_201; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_221 = _activated_data_e_act_z_iexp_saturated_T_220 \| _activated_data_e_act_z_iexp_saturated_T_203; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_222 = _activated_data_e_act_z_iexp_saturated_T_221 \| _activated_data_e_act_z_iexp_saturated_T_205; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_223 = _activated_data_e_act_z_iexp_saturated_T_222 \| _activated_data_e_act_z_iexp_saturated_T_207; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_224 = _activated_data_e_act_z_iexp_saturated_T_223 \| _activated_data_e_act_z_iexp_saturated_T_209; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_225 = _activated_data_e_act_z_iexp_saturated_T_224 \| _activated_data_e_act_z_iexp_saturated_T_211; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_226 = _activated_data_e_act_z_iexp_saturated_T_225 \| _activated_data_e_act_z_iexp_saturated_T_213; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_227 = _activated_data_e_act_z_iexp_saturated_T_226 \| _activated_data_e_act_z_iexp_saturated_T_215; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_228 = _activated_data_e_act_z_iexp_saturated_T_227 \| _activated_data_e_act_z_iexp_saturated_T_217; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_229 = _activated_data_e_act_z_iexp_saturated_T_228 \| _activated_data_e_act_z_iexp_saturated_T_219; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_230 = _activated_data_e_act_z_iexp_saturated_T_229 ? 32'h20 : activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_6 = _activated_data_e_act_z_iexp_saturated_T_230; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_30 = {{32{activated_data_e_act_z_iexp_6[31]}}, activated_data_e_act_z_iexp_6} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_31 = {_activated_data_e_act_qp_iexp_T_30[63], _activated_data_e_act_qp_iexp_T_30} + {{33{_activated_data_e_act_T_216[31]}}, _activated_data_e_act_T_216}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_32 = _activated_data_e_act_qp_iexp_T_31[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_33 = _activated_data_e_act_qp_iexp_T_32; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_34 = _activated_data_e_act_qp_iexp_T_33[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_6 = _activated_data_e_act_qp_iexp_T_34; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_36 = {activated_data_e_act_qp_iexp_6[31], activated_data_e_act_qp_iexp_6} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_66; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_66 = _GEN_36; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_69; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_69 = _GEN_36; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_67 = _activated_data_e_act_q_poly_iexp_T_66[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_68 = _activated_data_e_act_q_poly_iexp_T_67; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_70 = _activated_data_e_act_q_poly_iexp_T_69[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_71 = _activated_data_e_act_q_poly_iexp_T_70; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_72 = {{32{_activated_data_e_act_q_poly_iexp_T_68[31]}}, _activated_data_e_act_q_poly_iexp_T_68} * {{32{_activated_data_e_act_q_poly_iexp_T_71[31]}}, _activated_data_e_act_q_poly_iexp_T_71}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_73 = {_activated_data_e_act_q_poly_iexp_T_72[63], _activated_data_e_act_q_poly_iexp_T_72} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_74 = _activated_data_e_act_q_poly_iexp_T_73[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_75 = _activated_data_e_act_q_poly_iexp_T_74; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_76 = _activated_data_e_act_q_poly_iexp_T_75[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_6 = _activated_data_e_act_q_poly_iexp_T_76; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_217 = activated_data_e_act_q_poly_iexp_6; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_219 = _activated_data_e_act_T_217 >> _activated_data_e_act_T_218; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_220 = _activated_data_e_act_T_219; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_6 = _activated_data_e_act_T_220; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_222 = _activated_data_e_act_T_221; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_223 = _activated_data_e_act_T_222; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_6 = _activated_data_e_act_T_193 ? _activated_data_e_act_T_195 : _activated_data_e_act_T_223; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_6 = activated_data_e_act_6; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_74_bits = _activated_data_e_scaled_T_73_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_33 = _activated_data_e_scaled_T_74_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_75; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_75 = _activated_data_e_scaled_WIRE_33; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_32_bits = _activated_data_e_scaled_T_75; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_6 = _activated_data_e_scaled_WIRE_32_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_6_sign = activated_data_e_scaled_f_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_6 = _activated_data_e_scaled_WIRE_32_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_6 = _activated_data_e_scaled_WIRE_32_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 = activated_data_e_scaled_f_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6 = activated_data_e_scaled_f_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_264 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_265 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_266 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_267 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_268 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_269 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_270 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_271 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_272 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_273 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_274 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_275 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_276 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_277 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_278 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_279 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_280 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_281 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_282 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_283 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_284 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_285 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_286 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_287 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_288 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_289 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_290 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_291 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_292 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_293 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_294 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_295 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_296 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_297 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_298 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_299 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_300 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_301 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_302 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_303 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_304 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_305 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_306 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_307 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_6 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_6} << activated_data_e_scaled_f_rec_rawIn_normDist_6; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_13 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_6 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_6}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_31 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_32 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_6 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_12 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_6 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_6_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_6 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_6 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_50 = activated_data_e_scaled_f_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_13 = activated_data_e_scaled_f_rec_rawIn_isSpecial_6 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_6_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_6 = activated_data_e_scaled_f_rec_rawIn_isSpecial_6 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_6_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_6_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_24 = ~activated_data_e_scaled_f_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_26 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_6 : activated_data_e_scaled_f_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_27 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_25, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_6_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_48 = activated_data_e_scaled_f_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_49 = activated_data_e_scaled_f_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_48; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_51 = {_activated_data_e_scaled_f_rec_T_49[2:1], _activated_data_e_scaled_f_rec_T_49[0] \| _activated_data_e_scaled_f_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_52 = {activated_data_e_scaled_f_rec_rawIn_6_sign, _activated_data_e_scaled_f_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_53 = activated_data_e_scaled_f_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_54 = {_activated_data_e_scaled_f_rec_T_52, _activated_data_e_scaled_f_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_55 = activated_data_e_scaled_f_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_6 = {_activated_data_e_scaled_f_rec_T_54, _activated_data_e_scaled_f_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_6 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_6; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_6 = _activated_data_e_scaled_rec_fn_to_in_6_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_6 = _activated_data_e_scaled_muladder_6_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_6 = activated_data_e_scaled_sign_exp_6[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_6 = _activated_data_e_scaled_sign_isZero_T_6 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_6_isZero = activated_data_e_scaled_sign_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_6 = activated_data_e_scaled_sign_exp_6[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_6 = &_activated_data_e_scaled_sign_isSpecial_T_6; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_20; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_6; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_6; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_27; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_6_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_6_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_6_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_6_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_6_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_12 = activated_data_e_scaled_sign_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_18 = activated_data_e_scaled_sign_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_13 = activated_data_e_scaled_sign_isSpecial_6 & _activated_data_e_scaled_sign_out_isNaN_T_12; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_6_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_19 = ~_activated_data_e_scaled_sign_out_isInf_T_18; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_20 = activated_data_e_scaled_sign_isSpecial_6 & _activated_data_e_scaled_sign_out_isInf_T_19; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_6_isInf = _activated_data_e_scaled_sign_out_isInf_T_20; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_6 = _activated_data_e_scaled_muladder_6_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_6_sign = _activated_data_e_scaled_sign_out_sign_T_6; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_6 = {1'h0, activated_data_e_scaled_sign_exp_6}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_6_sExp = _activated_data_e_scaled_sign_out_sExp_T_6; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_24 = ~activated_data_e_scaled_sign_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_25 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_24}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_26 = _activated_data_e_scaled_muladder_6_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_27 = {_activated_data_e_scaled_sign_out_sig_T_25, _activated_data_e_scaled_sign_out_sig_T_26}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_6_sig = _activated_data_e_scaled_sign_out_sig_T_27; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_6 = activated_data_e_scaled_sign_out_6_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_76; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_34 = _activated_data_e_scaled_T_76; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_6 = activated_data_e_scaled_overflow_6 ? activated_data_e_scaled_sat_6 : _activated_data_e_scaled_WIRE_34; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_30 = $signed(activated_data_e_scaled_6) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_31 = $signed(activated_data_e_scaled_6) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_32 = _activated_data_e_clipped_T_31 ? 32'hFFFFFF80 : activated_data_e_scaled_6; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_33 = _activated_data_e_clipped_T_30 ? 32'h7F : _activated_data_e_clipped_T_32; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_34 = _activated_data_e_clipped_T_33[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_6 = _activated_data_e_clipped_T_34; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_6_0 = activated_data_e_clipped_6; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_6_0 = _activated_data_WIRE_6_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_225 = _activated_data_e_act_T_224; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_226 = $signed(io_in_bits_acc_read_resp_data_7_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_227 = _activated_data_e_act_T_226 ? io_in_bits_acc_read_resp_data_7_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_37 = {io_in_bits_acc_read_resp_data_7_0_0[31], io_in_bits_acc_read_resp_data_7_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_231; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_231 = _GEN_37; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_246; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_246 = _GEN_37; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_232 = _activated_data_e_act_T_231[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_233 = _activated_data_e_act_T_232; // @[Arithmetic.scala:95:38] wire _GEN_38 = $signed(io_in_bits_acc_read_resp_data_7_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_28; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_28 = _GEN_38; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_28; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_28 = _GEN_38; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_7 = {_activated_data_e_act_q_sign_T_28, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_29 = 33'h0 - _GEN_37; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_30 = _activated_data_e_act_q_abs_T_29[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_31 = _activated_data_e_act_q_abs_T_30; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_7 = _activated_data_e_act_q_abs_T_28 ? _activated_data_e_act_q_abs_T_31 : io_in_bits_acc_read_resp_data_7_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_50 = _activated_data_e_act_q_clipped_T_49[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_51 = _activated_data_e_act_q_clipped_T_50; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_52 = $signed(activated_data_e_act_q_abs_7) > $signed(_activated_data_e_act_q_clipped_T_51); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_54 = _activated_data_e_act_q_clipped_T_53[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_55 = _activated_data_e_act_q_clipped_T_54; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_7 = _activated_data_e_act_q_clipped_T_52 ? _activated_data_e_act_q_clipped_T_55 : activated_data_e_act_q_abs_7; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_39 = {activated_data_e_act_q_clipped_7[31], activated_data_e_act_q_clipped_7} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_77; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_77 = _GEN_39; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_80; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_80 = _GEN_39; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_78 = _activated_data_e_act_q_poly_T_77[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_79 = _activated_data_e_act_q_poly_T_78; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_81 = _activated_data_e_act_q_poly_T_80[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_82 = _activated_data_e_act_q_poly_T_81; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_83 = {{32{_activated_data_e_act_q_poly_T_79[31]}}, _activated_data_e_act_q_poly_T_79} * {{32{_activated_data_e_act_q_poly_T_82[31]}}, _activated_data_e_act_q_poly_T_82}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_84 = {_activated_data_e_act_q_poly_T_83[63], _activated_data_e_act_q_poly_T_83} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_85 = _activated_data_e_act_q_poly_T_84[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_86 = _activated_data_e_act_q_poly_T_85; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_87 = _activated_data_e_act_q_poly_T_86[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_7 = _activated_data_e_act_q_poly_T_87; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_14 = {{32{activated_data_e_act_q_sign_7[1]}}, activated_data_e_act_q_sign_7} * {{2{activated_data_e_act_q_poly_7[31]}}, activated_data_e_act_q_poly_7}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_15 = _activated_data_e_act_q_erf_T_14[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_7 = _activated_data_e_act_q_erf_T_15; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_237 = {activated_data_e_act_q_erf_7[31], activated_data_e_act_q_erf_7} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_238 = _activated_data_e_act_T_237[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_239 = _activated_data_e_act_T_238; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_240 = {{32{io_in_bits_acc_read_resp_data_7_0_0[31]}}, io_in_bits_acc_read_resp_data_7_0_0} * {{32{_activated_data_e_act_T_239[31]}}, _activated_data_e_act_T_239}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_241 = _activated_data_e_act_T_240[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_242 = _activated_data_e_act_T_241; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_247 = _activated_data_e_act_T_246[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_248 = _activated_data_e_act_T_247; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_14 = 33'h0 - {_activated_data_e_act_T_248[31], _activated_data_e_act_T_248}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_15 = _activated_data_e_act_neg_q_iexp_T_14[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_7 = _activated_data_e_act_neg_q_iexp_T_15; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_28 = {{32{activated_data_e_act_neg_q_iexp_7[31]}}, activated_data_e_act_neg_q_iexp_7} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_29 = _activated_data_e_act_z_iexp_T_28; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_30 = _activated_data_e_act_z_iexp_T_29[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_31 = _activated_data_e_act_z_iexp_T_30; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_231 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_233 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_235 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_237 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_239 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_241 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_243 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_245 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_247 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_249 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_251 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_7 = _activated_data_e_act_z_iexp_T_31[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_263; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_7; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_250 = activated_data_e_act_z_iexp_saturated_7; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_232 = _activated_data_e_act_z_iexp_saturated_T_231[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_234 = _activated_data_e_act_z_iexp_saturated_T_233[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_236 = _activated_data_e_act_z_iexp_saturated_T_235[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_238 = _activated_data_e_act_z_iexp_saturated_T_237[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_240 = _activated_data_e_act_z_iexp_saturated_T_239[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_242 = _activated_data_e_act_z_iexp_saturated_T_241[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_244 = _activated_data_e_act_z_iexp_saturated_T_243[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_246 = _activated_data_e_act_z_iexp_saturated_T_245[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_248 = _activated_data_e_act_z_iexp_saturated_T_247[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_250 = _activated_data_e_act_z_iexp_saturated_T_249[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_252 = _activated_data_e_act_z_iexp_saturated_T_251[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_253 = _activated_data_e_act_z_iexp_saturated_T_232 \| _activated_data_e_act_z_iexp_saturated_T_234; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_254 = _activated_data_e_act_z_iexp_saturated_T_253 \| _activated_data_e_act_z_iexp_saturated_T_236; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_255 = _activated_data_e_act_z_iexp_saturated_T_254 \| _activated_data_e_act_z_iexp_saturated_T_238; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_256 = _activated_data_e_act_z_iexp_saturated_T_255 \| _activated_data_e_act_z_iexp_saturated_T_240; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_257 = _activated_data_e_act_z_iexp_saturated_T_256 \| _activated_data_e_act_z_iexp_saturated_T_242; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_258 = _activated_data_e_act_z_iexp_saturated_T_257 \| _activated_data_e_act_z_iexp_saturated_T_244; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_259 = _activated_data_e_act_z_iexp_saturated_T_258 \| _activated_data_e_act_z_iexp_saturated_T_246; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_260 = _activated_data_e_act_z_iexp_saturated_T_259 \| _activated_data_e_act_z_iexp_saturated_T_248; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_261 = _activated_data_e_act_z_iexp_saturated_T_260 \| _activated_data_e_act_z_iexp_saturated_T_250; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_262 = _activated_data_e_act_z_iexp_saturated_T_261 \| _activated_data_e_act_z_iexp_saturated_T_252; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_263 = _activated_data_e_act_z_iexp_saturated_T_262 ? 32'h20 : activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_7 = _activated_data_e_act_z_iexp_saturated_T_263; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_35 = {{32{activated_data_e_act_z_iexp_7[31]}}, activated_data_e_act_z_iexp_7} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_36 = {_activated_data_e_act_qp_iexp_T_35[63], _activated_data_e_act_qp_iexp_T_35} + {{33{_activated_data_e_act_T_248[31]}}, _activated_data_e_act_T_248}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_37 = _activated_data_e_act_qp_iexp_T_36[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_38 = _activated_data_e_act_qp_iexp_T_37; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_39 = _activated_data_e_act_qp_iexp_T_38[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_7 = _activated_data_e_act_qp_iexp_T_39; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_40 = {activated_data_e_act_qp_iexp_7[31], activated_data_e_act_qp_iexp_7} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_77; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_77 = _GEN_40; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_80; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_80 = _GEN_40; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_78 = _activated_data_e_act_q_poly_iexp_T_77[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_79 = _activated_data_e_act_q_poly_iexp_T_78; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_81 = _activated_data_e_act_q_poly_iexp_T_80[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_82 = _activated_data_e_act_q_poly_iexp_T_81; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_83 = {{32{_activated_data_e_act_q_poly_iexp_T_79[31]}}, _activated_data_e_act_q_poly_iexp_T_79} * {{32{_activated_data_e_act_q_poly_iexp_T_82[31]}}, _activated_data_e_act_q_poly_iexp_T_82}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_84 = {_activated_data_e_act_q_poly_iexp_T_83[63], _activated_data_e_act_q_poly_iexp_T_83} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_85 = _activated_data_e_act_q_poly_iexp_T_84[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_86 = _activated_data_e_act_q_poly_iexp_T_85; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_87 = _activated_data_e_act_q_poly_iexp_T_86[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_7 = _activated_data_e_act_q_poly_iexp_T_87; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_249 = activated_data_e_act_q_poly_iexp_7; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_251 = _activated_data_e_act_T_249 >> _activated_data_e_act_T_250; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_252 = _activated_data_e_act_T_251; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_7 = _activated_data_e_act_T_252; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_254 = _activated_data_e_act_T_253; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_255 = _activated_data_e_act_T_254; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_7 = _activated_data_e_act_T_225 ? _activated_data_e_act_T_227 : _activated_data_e_act_T_255; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_7 = activated_data_e_act_7; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_85_bits = _activated_data_e_scaled_T_84_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_38 = _activated_data_e_scaled_T_85_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_86; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_86 = _activated_data_e_scaled_WIRE_38; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_37_bits = _activated_data_e_scaled_T_86; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_7 = _activated_data_e_scaled_WIRE_37_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_7_sign = activated_data_e_scaled_f_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_7 = _activated_data_e_scaled_WIRE_37_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_7 = _activated_data_e_scaled_WIRE_37_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 = activated_data_e_scaled_f_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7 = activated_data_e_scaled_f_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_308 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_309 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_310 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_311 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_312 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_313 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_314 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_315 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_316 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_317 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_318 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_319 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_320 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_321 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_322 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_323 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_324 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_325 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_326 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_327 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_328 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_329 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_330 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_331 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_332 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_333 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_334 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_335 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_336 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_337 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_338 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_339 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_340 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_341 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_342 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_343 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_344 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_345 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_346 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_347 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_348 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_349 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_350 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_351 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_7 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_7} << activated_data_e_scaled_f_rec_rawIn_normDist_7; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_15 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_7 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_7}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_36 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_37 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_7 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_14 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_7 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_7_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_7 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_7 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_58 = activated_data_e_scaled_f_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_15 = activated_data_e_scaled_f_rec_rawIn_isSpecial_7 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_7_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_7 = activated_data_e_scaled_f_rec_rawIn_isSpecial_7 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_7_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_7_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_28 = ~activated_data_e_scaled_f_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_30 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_7 : activated_data_e_scaled_f_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_31 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_29, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_7_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_56 = activated_data_e_scaled_f_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_57 = activated_data_e_scaled_f_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_56; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_59 = {_activated_data_e_scaled_f_rec_T_57[2:1], _activated_data_e_scaled_f_rec_T_57[0] \| _activated_data_e_scaled_f_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_60 = {activated_data_e_scaled_f_rec_rawIn_7_sign, _activated_data_e_scaled_f_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_61 = activated_data_e_scaled_f_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_62 = {_activated_data_e_scaled_f_rec_T_60, _activated_data_e_scaled_f_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_63 = activated_data_e_scaled_f_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_7 = {_activated_data_e_scaled_f_rec_T_62, _activated_data_e_scaled_f_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_7 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_7; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_7 = _activated_data_e_scaled_rec_fn_to_in_7_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_7 = _activated_data_e_scaled_muladder_7_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_7 = activated_data_e_scaled_sign_exp_7[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_7 = _activated_data_e_scaled_sign_isZero_T_7 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_7_isZero = activated_data_e_scaled_sign_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_7 = activated_data_e_scaled_sign_exp_7[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_7 = &_activated_data_e_scaled_sign_isSpecial_T_7; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_23; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_7; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_7; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_31; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_7_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_7_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_7_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_7_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_7_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_14 = activated_data_e_scaled_sign_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_21 = activated_data_e_scaled_sign_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_15 = activated_data_e_scaled_sign_isSpecial_7 & _activated_data_e_scaled_sign_out_isNaN_T_14; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_7_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_22 = ~_activated_data_e_scaled_sign_out_isInf_T_21; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_23 = activated_data_e_scaled_sign_isSpecial_7 & _activated_data_e_scaled_sign_out_isInf_T_22; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_7_isInf = _activated_data_e_scaled_sign_out_isInf_T_23; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_7 = _activated_data_e_scaled_muladder_7_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_7_sign = _activated_data_e_scaled_sign_out_sign_T_7; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_7 = {1'h0, activated_data_e_scaled_sign_exp_7}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_7_sExp = _activated_data_e_scaled_sign_out_sExp_T_7; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_28 = ~activated_data_e_scaled_sign_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_29 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_28}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_30 = _activated_data_e_scaled_muladder_7_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_31 = {_activated_data_e_scaled_sign_out_sig_T_29, _activated_data_e_scaled_sign_out_sig_T_30}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_7_sig = _activated_data_e_scaled_sign_out_sig_T_31; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_7 = activated_data_e_scaled_sign_out_7_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_87; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_39 = _activated_data_e_scaled_T_87; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_7 = activated_data_e_scaled_overflow_7 ? activated_data_e_scaled_sat_7 : _activated_data_e_scaled_WIRE_39; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_35 = $signed(activated_data_e_scaled_7) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_36 = $signed(activated_data_e_scaled_7) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_37 = _activated_data_e_clipped_T_36 ? 32'hFFFFFF80 : activated_data_e_scaled_7; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_38 = _activated_data_e_clipped_T_35 ? 32'h7F : _activated_data_e_clipped_T_37; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_39 = _activated_data_e_clipped_T_38[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_7 = _activated_data_e_clipped_T_39; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_7_0 = activated_data_e_clipped_7; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_7_0 = _activated_data_WIRE_7_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_257 = _activated_data_e_act_T_256; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_258 = $signed(io_in_bits_acc_read_resp_data_8_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_259 = _activated_data_e_act_T_258 ? io_in_bits_acc_read_resp_data_8_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_41 = {io_in_bits_acc_read_resp_data_8_0_0[31], io_in_bits_acc_read_resp_data_8_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_263; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_263 = _GEN_41; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_278; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_278 = _GEN_41; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_264 = _activated_data_e_act_T_263[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_265 = _activated_data_e_act_T_264; // @[Arithmetic.scala:95:38] wire _GEN_42 = $signed(io_in_bits_acc_read_resp_data_8_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_32; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_32 = _GEN_42; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_32; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_32 = _GEN_42; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_8 = {_activated_data_e_act_q_sign_T_32, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_33 = 33'h0 - _GEN_41; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_34 = _activated_data_e_act_q_abs_T_33[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_35 = _activated_data_e_act_q_abs_T_34; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_8 = _activated_data_e_act_q_abs_T_32 ? _activated_data_e_act_q_abs_T_35 : io_in_bits_acc_read_resp_data_8_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_57 = _activated_data_e_act_q_clipped_T_56[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_58 = _activated_data_e_act_q_clipped_T_57; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_59 = $signed(activated_data_e_act_q_abs_8) > $signed(_activated_data_e_act_q_clipped_T_58); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_61 = _activated_data_e_act_q_clipped_T_60[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_62 = _activated_data_e_act_q_clipped_T_61; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_8 = _activated_data_e_act_q_clipped_T_59 ? _activated_data_e_act_q_clipped_T_62 : activated_data_e_act_q_abs_8; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_43 = {activated_data_e_act_q_clipped_8[31], activated_data_e_act_q_clipped_8} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_88; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_88 = _GEN_43; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_91; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_91 = _GEN_43; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_89 = _activated_data_e_act_q_poly_T_88[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_90 = _activated_data_e_act_q_poly_T_89; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_92 = _activated_data_e_act_q_poly_T_91[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_93 = _activated_data_e_act_q_poly_T_92; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_94 = {{32{_activated_data_e_act_q_poly_T_90[31]}}, _activated_data_e_act_q_poly_T_90} * {{32{_activated_data_e_act_q_poly_T_93[31]}}, _activated_data_e_act_q_poly_T_93}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_95 = {_activated_data_e_act_q_poly_T_94[63], _activated_data_e_act_q_poly_T_94} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_96 = _activated_data_e_act_q_poly_T_95[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_97 = _activated_data_e_act_q_poly_T_96; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_98 = _activated_data_e_act_q_poly_T_97[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_8 = _activated_data_e_act_q_poly_T_98; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_16 = {{32{activated_data_e_act_q_sign_8[1]}}, activated_data_e_act_q_sign_8} * {{2{activated_data_e_act_q_poly_8[31]}}, activated_data_e_act_q_poly_8}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_17 = _activated_data_e_act_q_erf_T_16[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_8 = _activated_data_e_act_q_erf_T_17; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_269 = {activated_data_e_act_q_erf_8[31], activated_data_e_act_q_erf_8} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_270 = _activated_data_e_act_T_269[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_271 = _activated_data_e_act_T_270; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_272 = {{32{io_in_bits_acc_read_resp_data_8_0_0[31]}}, io_in_bits_acc_read_resp_data_8_0_0} * {{32{_activated_data_e_act_T_271[31]}}, _activated_data_e_act_T_271}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_273 = _activated_data_e_act_T_272[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_274 = _activated_data_e_act_T_273; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_279 = _activated_data_e_act_T_278[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_280 = _activated_data_e_act_T_279; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_16 = 33'h0 - {_activated_data_e_act_T_280[31], _activated_data_e_act_T_280}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_17 = _activated_data_e_act_neg_q_iexp_T_16[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_8 = _activated_data_e_act_neg_q_iexp_T_17; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_32 = {{32{activated_data_e_act_neg_q_iexp_8[31]}}, activated_data_e_act_neg_q_iexp_8} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_33 = _activated_data_e_act_z_iexp_T_32; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_34 = _activated_data_e_act_z_iexp_T_33[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_35 = _activated_data_e_act_z_iexp_T_34; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_264 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_266 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_268 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_270 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_272 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_274 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_276 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_278 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_280 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_282 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_284 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_8 = _activated_data_e_act_z_iexp_T_35[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_296; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_8; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_282 = activated_data_e_act_z_iexp_saturated_8; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_265 = _activated_data_e_act_z_iexp_saturated_T_264[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_267 = _activated_data_e_act_z_iexp_saturated_T_266[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_269 = _activated_data_e_act_z_iexp_saturated_T_268[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_271 = _activated_data_e_act_z_iexp_saturated_T_270[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_273 = _activated_data_e_act_z_iexp_saturated_T_272[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_275 = _activated_data_e_act_z_iexp_saturated_T_274[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_277 = _activated_data_e_act_z_iexp_saturated_T_276[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_279 = _activated_data_e_act_z_iexp_saturated_T_278[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_281 = _activated_data_e_act_z_iexp_saturated_T_280[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_283 = _activated_data_e_act_z_iexp_saturated_T_282[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_285 = _activated_data_e_act_z_iexp_saturated_T_284[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_286 = _activated_data_e_act_z_iexp_saturated_T_265 \| _activated_data_e_act_z_iexp_saturated_T_267; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_287 = _activated_data_e_act_z_iexp_saturated_T_286 \| _activated_data_e_act_z_iexp_saturated_T_269; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_288 = _activated_data_e_act_z_iexp_saturated_T_287 \| _activated_data_e_act_z_iexp_saturated_T_271; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_289 = _activated_data_e_act_z_iexp_saturated_T_288 \| _activated_data_e_act_z_iexp_saturated_T_273; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_290 = _activated_data_e_act_z_iexp_saturated_T_289 \| _activated_data_e_act_z_iexp_saturated_T_275; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_291 = _activated_data_e_act_z_iexp_saturated_T_290 \| _activated_data_e_act_z_iexp_saturated_T_277; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_292 = _activated_data_e_act_z_iexp_saturated_T_291 \| _activated_data_e_act_z_iexp_saturated_T_279; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_293 = _activated_data_e_act_z_iexp_saturated_T_292 \| _activated_data_e_act_z_iexp_saturated_T_281; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_294 = _activated_data_e_act_z_iexp_saturated_T_293 \| _activated_data_e_act_z_iexp_saturated_T_283; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_295 = _activated_data_e_act_z_iexp_saturated_T_294 \| _activated_data_e_act_z_iexp_saturated_T_285; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_296 = _activated_data_e_act_z_iexp_saturated_T_295 ? 32'h20 : activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_8 = _activated_data_e_act_z_iexp_saturated_T_296; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_40 = {{32{activated_data_e_act_z_iexp_8[31]}}, activated_data_e_act_z_iexp_8} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_41 = {_activated_data_e_act_qp_iexp_T_40[63], _activated_data_e_act_qp_iexp_T_40} + {{33{_activated_data_e_act_T_280[31]}}, _activated_data_e_act_T_280}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_42 = _activated_data_e_act_qp_iexp_T_41[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_43 = _activated_data_e_act_qp_iexp_T_42; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_44 = _activated_data_e_act_qp_iexp_T_43[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_8 = _activated_data_e_act_qp_iexp_T_44; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_44 = {activated_data_e_act_qp_iexp_8[31], activated_data_e_act_qp_iexp_8} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_88; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_88 = _GEN_44; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_91; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_91 = _GEN_44; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_89 = _activated_data_e_act_q_poly_iexp_T_88[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_90 = _activated_data_e_act_q_poly_iexp_T_89; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_92 = _activated_data_e_act_q_poly_iexp_T_91[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_93 = _activated_data_e_act_q_poly_iexp_T_92; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_94 = {{32{_activated_data_e_act_q_poly_iexp_T_90[31]}}, _activated_data_e_act_q_poly_iexp_T_90} * {{32{_activated_data_e_act_q_poly_iexp_T_93[31]}}, _activated_data_e_act_q_poly_iexp_T_93}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_95 = {_activated_data_e_act_q_poly_iexp_T_94[63], _activated_data_e_act_q_poly_iexp_T_94} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_96 = _activated_data_e_act_q_poly_iexp_T_95[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_97 = _activated_data_e_act_q_poly_iexp_T_96; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_98 = _activated_data_e_act_q_poly_iexp_T_97[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_8 = _activated_data_e_act_q_poly_iexp_T_98; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_281 = activated_data_e_act_q_poly_iexp_8; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_283 = _activated_data_e_act_T_281 >> _activated_data_e_act_T_282; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_284 = _activated_data_e_act_T_283; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_8 = _activated_data_e_act_T_284; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_286 = _activated_data_e_act_T_285; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_287 = _activated_data_e_act_T_286; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_8 = _activated_data_e_act_T_257 ? _activated_data_e_act_T_259 : _activated_data_e_act_T_287; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_8 = activated_data_e_act_8; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_96_bits = _activated_data_e_scaled_T_95_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_43 = _activated_data_e_scaled_T_96_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_97; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_97 = _activated_data_e_scaled_WIRE_43; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_42_bits = _activated_data_e_scaled_T_97; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_8 = _activated_data_e_scaled_WIRE_42_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_8_sign = activated_data_e_scaled_f_rec_rawIn_sign_8; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_8 = _activated_data_e_scaled_WIRE_42_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_8 = _activated_data_e_scaled_WIRE_42_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 = activated_data_e_scaled_f_rec_rawIn_expIn_8 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8 = activated_data_e_scaled_f_rec_rawIn_fractIn_8 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_352 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_353 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_354 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_355 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_356 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_357 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_358 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_359 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_360 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_361 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_362 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_363 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_364 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_365 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_366 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_367 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_368 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_369 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_370 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_371 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_372 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_373 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_374 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_375 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_353 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_376 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_354 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_375; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_377 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_355 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_376; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_378 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_356 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_377; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_379 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_357 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_378; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_380 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_358 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_379; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_381 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_359 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_380; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_382 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_360 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_381; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_383 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_361 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_382; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_384 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_362 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_383; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_385 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_363 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_384; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_386 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_364 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_385; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_387 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_365 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_386; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_388 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_366 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_387; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_389 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_367 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_388; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_390 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_368 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_389; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_391 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_369 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_390; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_392 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_370 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_391; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_393 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_371 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_392; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_394 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_372 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_393; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_395 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_373 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_394; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_8 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_374 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_395; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_16 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_8} << activated_data_e_scaled_f_rec_rawIn_normDist_8; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_17 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_16[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_8 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_17, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_40 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_8}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_41 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_40 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_8}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_42 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_43 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_42}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_44 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_41} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_43}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_8 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_44[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_16 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_8; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_8 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_8_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_8 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_8[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_8 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_8; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_66 = activated_data_e_scaled_f_rec_rawIn_8_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_8_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_8_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_8_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_16 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_17 = activated_data_e_scaled_f_rec_rawIn_isSpecial_8 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_16; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_8_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_8 = activated_data_e_scaled_f_rec_rawIn_isSpecial_8 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_8_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_17 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_16}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_8_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_32 = ~activated_data_e_scaled_f_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_33 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_32}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_34 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_8 : activated_data_e_scaled_f_rec_rawIn_fractIn_8; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_35 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_33, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_34}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_8_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_64 = activated_data_e_scaled_f_rec_rawIn_8_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_65 = activated_data_e_scaled_f_rec_rawIn_8_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_64; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_67 = {_activated_data_e_scaled_f_rec_T_65[2:1], _activated_data_e_scaled_f_rec_T_65[0] \| _activated_data_e_scaled_f_rec_T_66}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_68 = {activated_data_e_scaled_f_rec_rawIn_8_sign, _activated_data_e_scaled_f_rec_T_67}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_69 = activated_data_e_scaled_f_rec_rawIn_8_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_70 = {_activated_data_e_scaled_f_rec_T_68, _activated_data_e_scaled_f_rec_T_69}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_71 = activated_data_e_scaled_f_rec_rawIn_8_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_8 = {_activated_data_e_scaled_f_rec_T_70, _activated_data_e_scaled_f_rec_T_71}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_8 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_8; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_8 = _activated_data_e_scaled_rec_fn_to_in_8_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_8 = _activated_data_e_scaled_muladder_8_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_8 = activated_data_e_scaled_sign_exp_8[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_8 = _activated_data_e_scaled_sign_isZero_T_8 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_8_isZero = activated_data_e_scaled_sign_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_8 = activated_data_e_scaled_sign_exp_8[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_8 = &_activated_data_e_scaled_sign_isSpecial_T_8; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_26; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_8; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_8; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_35; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_8_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_8_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_8_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_8_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_8_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_16 = activated_data_e_scaled_sign_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_24 = activated_data_e_scaled_sign_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_17 = activated_data_e_scaled_sign_isSpecial_8 & _activated_data_e_scaled_sign_out_isNaN_T_16; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_8_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_25 = ~_activated_data_e_scaled_sign_out_isInf_T_24; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_26 = activated_data_e_scaled_sign_isSpecial_8 & _activated_data_e_scaled_sign_out_isInf_T_25; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_8_isInf = _activated_data_e_scaled_sign_out_isInf_T_26; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_8 = _activated_data_e_scaled_muladder_8_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_8_sign = _activated_data_e_scaled_sign_out_sign_T_8; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_8 = {1'h0, activated_data_e_scaled_sign_exp_8}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_8_sExp = _activated_data_e_scaled_sign_out_sExp_T_8; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_32 = ~activated_data_e_scaled_sign_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_33 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_32}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_34 = _activated_data_e_scaled_muladder_8_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_35 = {_activated_data_e_scaled_sign_out_sig_T_33, _activated_data_e_scaled_sign_out_sig_T_34}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_8_sig = _activated_data_e_scaled_sign_out_sig_T_35; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_8 = activated_data_e_scaled_sign_out_8_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_98; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_44 = _activated_data_e_scaled_T_98; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_8 = activated_data_e_scaled_overflow_8 ? activated_data_e_scaled_sat_8 : _activated_data_e_scaled_WIRE_44; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_40 = $signed(activated_data_e_scaled_8) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_41 = $signed(activated_data_e_scaled_8) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_42 = _activated_data_e_clipped_T_41 ? 32'hFFFFFF80 : activated_data_e_scaled_8; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_43 = _activated_data_e_clipped_T_40 ? 32'h7F : _activated_data_e_clipped_T_42; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_44 = _activated_data_e_clipped_T_43[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_8 = _activated_data_e_clipped_T_44; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_8_0 = activated_data_e_clipped_8; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_8_0 = _activated_data_WIRE_8_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_289 = _activated_data_e_act_T_288; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_290 = $signed(io_in_bits_acc_read_resp_data_9_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_291 = _activated_data_e_act_T_290 ? io_in_bits_acc_read_resp_data_9_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_45 = {io_in_bits_acc_read_resp_data_9_0_0[31], io_in_bits_acc_read_resp_data_9_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_295; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_295 = _GEN_45; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_310; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_310 = _GEN_45; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_296 = _activated_data_e_act_T_295[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_297 = _activated_data_e_act_T_296; // @[Arithmetic.scala:95:38] wire _GEN_46 = $signed(io_in_bits_acc_read_resp_data_9_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_36; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_36 = _GEN_46; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_36; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_36 = _GEN_46; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_9 = {_activated_data_e_act_q_sign_T_36, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_37 = 33'h0 - _GEN_45; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_38 = _activated_data_e_act_q_abs_T_37[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_39 = _activated_data_e_act_q_abs_T_38; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_9 = _activated_data_e_act_q_abs_T_36 ? _activated_data_e_act_q_abs_T_39 : io_in_bits_acc_read_resp_data_9_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_64 = _activated_data_e_act_q_clipped_T_63[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_65 = _activated_data_e_act_q_clipped_T_64; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_66 = $signed(activated_data_e_act_q_abs_9) > $signed(_activated_data_e_act_q_clipped_T_65); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_68 = _activated_data_e_act_q_clipped_T_67[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_69 = _activated_data_e_act_q_clipped_T_68; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_9 = _activated_data_e_act_q_clipped_T_66 ? _activated_data_e_act_q_clipped_T_69 : activated_data_e_act_q_abs_9; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_47 = {activated_data_e_act_q_clipped_9[31], activated_data_e_act_q_clipped_9} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_99; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_99 = _GEN_47; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_102; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_102 = _GEN_47; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_100 = _activated_data_e_act_q_poly_T_99[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_101 = _activated_data_e_act_q_poly_T_100; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_103 = _activated_data_e_act_q_poly_T_102[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_104 = _activated_data_e_act_q_poly_T_103; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_105 = {{32{_activated_data_e_act_q_poly_T_101[31]}}, _activated_data_e_act_q_poly_T_101} * {{32{_activated_data_e_act_q_poly_T_104[31]}}, _activated_data_e_act_q_poly_T_104}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_106 = {_activated_data_e_act_q_poly_T_105[63], _activated_data_e_act_q_poly_T_105} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_107 = _activated_data_e_act_q_poly_T_106[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_108 = _activated_data_e_act_q_poly_T_107; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_109 = _activated_data_e_act_q_poly_T_108[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_9 = _activated_data_e_act_q_poly_T_109; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_18 = {{32{activated_data_e_act_q_sign_9[1]}}, activated_data_e_act_q_sign_9} * {{2{activated_data_e_act_q_poly_9[31]}}, activated_data_e_act_q_poly_9}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_19 = _activated_data_e_act_q_erf_T_18[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_9 = _activated_data_e_act_q_erf_T_19; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_301 = {activated_data_e_act_q_erf_9[31], activated_data_e_act_q_erf_9} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_302 = _activated_data_e_act_T_301[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_303 = _activated_data_e_act_T_302; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_304 = {{32{io_in_bits_acc_read_resp_data_9_0_0[31]}}, io_in_bits_acc_read_resp_data_9_0_0} * {{32{_activated_data_e_act_T_303[31]}}, _activated_data_e_act_T_303}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_305 = _activated_data_e_act_T_304[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_306 = _activated_data_e_act_T_305; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_311 = _activated_data_e_act_T_310[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_312 = _activated_data_e_act_T_311; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_18 = 33'h0 - {_activated_data_e_act_T_312[31], _activated_data_e_act_T_312}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_19 = _activated_data_e_act_neg_q_iexp_T_18[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_9 = _activated_data_e_act_neg_q_iexp_T_19; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_36 = {{32{activated_data_e_act_neg_q_iexp_9[31]}}, activated_data_e_act_neg_q_iexp_9} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_37 = _activated_data_e_act_z_iexp_T_36; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_38 = _activated_data_e_act_z_iexp_T_37[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_39 = _activated_data_e_act_z_iexp_T_38; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_297 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_299 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_301 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_303 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_305 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_307 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_309 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_311 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_313 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_315 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_317 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_9 = _activated_data_e_act_z_iexp_T_39[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_329; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_9; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_314 = activated_data_e_act_z_iexp_saturated_9; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_298 = _activated_data_e_act_z_iexp_saturated_T_297[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_300 = _activated_data_e_act_z_iexp_saturated_T_299[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_302 = _activated_data_e_act_z_iexp_saturated_T_301[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_304 = _activated_data_e_act_z_iexp_saturated_T_303[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_306 = _activated_data_e_act_z_iexp_saturated_T_305[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_308 = _activated_data_e_act_z_iexp_saturated_T_307[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_310 = _activated_data_e_act_z_iexp_saturated_T_309[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_312 = _activated_data_e_act_z_iexp_saturated_T_311[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_314 = _activated_data_e_act_z_iexp_saturated_T_313[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_316 = _activated_data_e_act_z_iexp_saturated_T_315[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_318 = _activated_data_e_act_z_iexp_saturated_T_317[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_319 = _activated_data_e_act_z_iexp_saturated_T_298 \| _activated_data_e_act_z_iexp_saturated_T_300; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_320 = _activated_data_e_act_z_iexp_saturated_T_319 \| _activated_data_e_act_z_iexp_saturated_T_302; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_321 = _activated_data_e_act_z_iexp_saturated_T_320 \| _activated_data_e_act_z_iexp_saturated_T_304; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_322 = _activated_data_e_act_z_iexp_saturated_T_321 \| _activated_data_e_act_z_iexp_saturated_T_306; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_323 = _activated_data_e_act_z_iexp_saturated_T_322 \| _activated_data_e_act_z_iexp_saturated_T_308; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_324 = _activated_data_e_act_z_iexp_saturated_T_323 \| _activated_data_e_act_z_iexp_saturated_T_310; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_325 = _activated_data_e_act_z_iexp_saturated_T_324 \| _activated_data_e_act_z_iexp_saturated_T_312; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_326 = _activated_data_e_act_z_iexp_saturated_T_325 \| _activated_data_e_act_z_iexp_saturated_T_314; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_327 = _activated_data_e_act_z_iexp_saturated_T_326 \| _activated_data_e_act_z_iexp_saturated_T_316; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_328 = _activated_data_e_act_z_iexp_saturated_T_327 \| _activated_data_e_act_z_iexp_saturated_T_318; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_329 = _activated_data_e_act_z_iexp_saturated_T_328 ? 32'h20 : activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_9 = _activated_data_e_act_z_iexp_saturated_T_329; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_45 = {{32{activated_data_e_act_z_iexp_9[31]}}, activated_data_e_act_z_iexp_9} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_46 = {_activated_data_e_act_qp_iexp_T_45[63], _activated_data_e_act_qp_iexp_T_45} + {{33{_activated_data_e_act_T_312[31]}}, _activated_data_e_act_T_312}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_47 = _activated_data_e_act_qp_iexp_T_46[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_48 = _activated_data_e_act_qp_iexp_T_47; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_49 = _activated_data_e_act_qp_iexp_T_48[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_9 = _activated_data_e_act_qp_iexp_T_49; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_48 = {activated_data_e_act_qp_iexp_9[31], activated_data_e_act_qp_iexp_9} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_99; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_99 = _GEN_48; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_102; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_102 = _GEN_48; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_100 = _activated_data_e_act_q_poly_iexp_T_99[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_101 = _activated_data_e_act_q_poly_iexp_T_100; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_103 = _activated_data_e_act_q_poly_iexp_T_102[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_104 = _activated_data_e_act_q_poly_iexp_T_103; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_105 = {{32{_activated_data_e_act_q_poly_iexp_T_101[31]}}, _activated_data_e_act_q_poly_iexp_T_101} * {{32{_activated_data_e_act_q_poly_iexp_T_104[31]}}, _activated_data_e_act_q_poly_iexp_T_104}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_106 = {_activated_data_e_act_q_poly_iexp_T_105[63], _activated_data_e_act_q_poly_iexp_T_105} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_107 = _activated_data_e_act_q_poly_iexp_T_106[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_108 = _activated_data_e_act_q_poly_iexp_T_107; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_109 = _activated_data_e_act_q_poly_iexp_T_108[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_9 = _activated_data_e_act_q_poly_iexp_T_109; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_313 = activated_data_e_act_q_poly_iexp_9; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_315 = _activated_data_e_act_T_313 >> _activated_data_e_act_T_314; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_316 = _activated_data_e_act_T_315; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_9 = _activated_data_e_act_T_316; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_318 = _activated_data_e_act_T_317; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_319 = _activated_data_e_act_T_318; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_9 = _activated_data_e_act_T_289 ? _activated_data_e_act_T_291 : _activated_data_e_act_T_319; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_9 = activated_data_e_act_9; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_107_bits = _activated_data_e_scaled_T_106_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_48 = _activated_data_e_scaled_T_107_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_108; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_108 = _activated_data_e_scaled_WIRE_48; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_47_bits = _activated_data_e_scaled_T_108; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_9 = _activated_data_e_scaled_WIRE_47_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_9_sign = activated_data_e_scaled_f_rec_rawIn_sign_9; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_9 = _activated_data_e_scaled_WIRE_47_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_9 = _activated_data_e_scaled_WIRE_47_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 = activated_data_e_scaled_f_rec_rawIn_expIn_9 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9 = activated_data_e_scaled_f_rec_rawIn_fractIn_9 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_396 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_397 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_398 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_399 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_400 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_401 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_402 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_403 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_404 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_405 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_406 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_407 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_408 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_409 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_410 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_411 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_412 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_413 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_414 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_415 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_416 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_417 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_418 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_419 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_397 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_420 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_398 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_419; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_421 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_399 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_420; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_422 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_400 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_421; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_423 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_401 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_422; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_424 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_402 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_423; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_425 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_403 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_424; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_426 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_404 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_425; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_427 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_405 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_426; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_428 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_406 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_427; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_429 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_407 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_428; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_430 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_408 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_429; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_431 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_409 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_430; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_432 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_410 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_431; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_433 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_411 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_432; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_434 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_412 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_433; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_435 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_413 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_434; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_436 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_414 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_435; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_437 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_415 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_436; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_438 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_416 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_437; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_439 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_417 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_438; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_9 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_418 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_439; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_18 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_9} << activated_data_e_scaled_f_rec_rawIn_normDist_9; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_19 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_18[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_9 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_19, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_45 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_9}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_46 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_45 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_9}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_47 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_48 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_47}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_49 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_46} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_48}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_9 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_49[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_18 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_9; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_9 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_9_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_9 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_9[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_9 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_9; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_74 = activated_data_e_scaled_f_rec_rawIn_9_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_9_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_9_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_9_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_18 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_19 = activated_data_e_scaled_f_rec_rawIn_isSpecial_9 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_18; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_9_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_9 = activated_data_e_scaled_f_rec_rawIn_isSpecial_9 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_9_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_19 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_18}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_9_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_36 = ~activated_data_e_scaled_f_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_37 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_36}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_38 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_9 : activated_data_e_scaled_f_rec_rawIn_fractIn_9; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_39 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_37, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_38}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_9_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_72 = activated_data_e_scaled_f_rec_rawIn_9_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_73 = activated_data_e_scaled_f_rec_rawIn_9_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_72; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_75 = {_activated_data_e_scaled_f_rec_T_73[2:1], _activated_data_e_scaled_f_rec_T_73[0] \| _activated_data_e_scaled_f_rec_T_74}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_76 = {activated_data_e_scaled_f_rec_rawIn_9_sign, _activated_data_e_scaled_f_rec_T_75}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_77 = activated_data_e_scaled_f_rec_rawIn_9_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_78 = {_activated_data_e_scaled_f_rec_T_76, _activated_data_e_scaled_f_rec_T_77}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_79 = activated_data_e_scaled_f_rec_rawIn_9_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_9 = {_activated_data_e_scaled_f_rec_T_78, _activated_data_e_scaled_f_rec_T_79}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_9 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_9; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_9 = _activated_data_e_scaled_rec_fn_to_in_9_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_9 = _activated_data_e_scaled_muladder_9_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_9 = activated_data_e_scaled_sign_exp_9[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_9 = _activated_data_e_scaled_sign_isZero_T_9 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_9_isZero = activated_data_e_scaled_sign_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_9 = activated_data_e_scaled_sign_exp_9[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_9 = &_activated_data_e_scaled_sign_isSpecial_T_9; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_29; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_9; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_9; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_39; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_9_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_9_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_9_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_9_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_9_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_18 = activated_data_e_scaled_sign_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_27 = activated_data_e_scaled_sign_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_19 = activated_data_e_scaled_sign_isSpecial_9 & _activated_data_e_scaled_sign_out_isNaN_T_18; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_9_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_28 = ~_activated_data_e_scaled_sign_out_isInf_T_27; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_29 = activated_data_e_scaled_sign_isSpecial_9 & _activated_data_e_scaled_sign_out_isInf_T_28; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_9_isInf = _activated_data_e_scaled_sign_out_isInf_T_29; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_9 = _activated_data_e_scaled_muladder_9_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_9_sign = _activated_data_e_scaled_sign_out_sign_T_9; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_9 = {1'h0, activated_data_e_scaled_sign_exp_9}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_9_sExp = _activated_data_e_scaled_sign_out_sExp_T_9; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_36 = ~activated_data_e_scaled_sign_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_37 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_36}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_38 = _activated_data_e_scaled_muladder_9_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_39 = {_activated_data_e_scaled_sign_out_sig_T_37, _activated_data_e_scaled_sign_out_sig_T_38}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_9_sig = _activated_data_e_scaled_sign_out_sig_T_39; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_9 = activated_data_e_scaled_sign_out_9_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_109; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_49 = _activated_data_e_scaled_T_109; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_9 = activated_data_e_scaled_overflow_9 ? activated_data_e_scaled_sat_9 : _activated_data_e_scaled_WIRE_49; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_45 = $signed(activated_data_e_scaled_9) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_46 = $signed(activated_data_e_scaled_9) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_47 = _activated_data_e_clipped_T_46 ? 32'hFFFFFF80 : activated_data_e_scaled_9; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_48 = _activated_data_e_clipped_T_45 ? 32'h7F : _activated_data_e_clipped_T_47; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_49 = _activated_data_e_clipped_T_48[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_9 = _activated_data_e_clipped_T_49; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_9_0 = activated_data_e_clipped_9; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_9_0 = _activated_data_WIRE_9_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_321 = _activated_data_e_act_T_320; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_322 = $signed(io_in_bits_acc_read_resp_data_10_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_323 = _activated_data_e_act_T_322 ? io_in_bits_acc_read_resp_data_10_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_49 = {io_in_bits_acc_read_resp_data_10_0_0[31], io_in_bits_acc_read_resp_data_10_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_327; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_327 = _GEN_49; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_342; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_342 = _GEN_49; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_328 = _activated_data_e_act_T_327[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_329 = _activated_data_e_act_T_328; // @[Arithmetic.scala:95:38] wire _GEN_50 = $signed(io_in_bits_acc_read_resp_data_10_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_40; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_40 = _GEN_50; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_40; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_40 = _GEN_50; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_10 = {_activated_data_e_act_q_sign_T_40, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_41 = 33'h0 - _GEN_49; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_42 = _activated_data_e_act_q_abs_T_41[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_43 = _activated_data_e_act_q_abs_T_42; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_10 = _activated_data_e_act_q_abs_T_40 ? _activated_data_e_act_q_abs_T_43 : io_in_bits_acc_read_resp_data_10_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_71 = _activated_data_e_act_q_clipped_T_70[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_72 = _activated_data_e_act_q_clipped_T_71; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_73 = $signed(activated_data_e_act_q_abs_10) > $signed(_activated_data_e_act_q_clipped_T_72); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_75 = _activated_data_e_act_q_clipped_T_74[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_76 = _activated_data_e_act_q_clipped_T_75; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_10 = _activated_data_e_act_q_clipped_T_73 ? _activated_data_e_act_q_clipped_T_76 : activated_data_e_act_q_abs_10; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_51 = {activated_data_e_act_q_clipped_10[31], activated_data_e_act_q_clipped_10} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_110; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_110 = _GEN_51; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_113; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_113 = _GEN_51; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_111 = _activated_data_e_act_q_poly_T_110[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_112 = _activated_data_e_act_q_poly_T_111; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_114 = _activated_data_e_act_q_poly_T_113[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_115 = _activated_data_e_act_q_poly_T_114; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_116 = {{32{_activated_data_e_act_q_poly_T_112[31]}}, _activated_data_e_act_q_poly_T_112} * {{32{_activated_data_e_act_q_poly_T_115[31]}}, _activated_data_e_act_q_poly_T_115}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_117 = {_activated_data_e_act_q_poly_T_116[63], _activated_data_e_act_q_poly_T_116} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_118 = _activated_data_e_act_q_poly_T_117[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_119 = _activated_data_e_act_q_poly_T_118; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_120 = _activated_data_e_act_q_poly_T_119[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_10 = _activated_data_e_act_q_poly_T_120; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_20 = {{32{activated_data_e_act_q_sign_10[1]}}, activated_data_e_act_q_sign_10} * {{2{activated_data_e_act_q_poly_10[31]}}, activated_data_e_act_q_poly_10}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_21 = _activated_data_e_act_q_erf_T_20[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_10 = _activated_data_e_act_q_erf_T_21; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_333 = {activated_data_e_act_q_erf_10[31], activated_data_e_act_q_erf_10} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_334 = _activated_data_e_act_T_333[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_335 = _activated_data_e_act_T_334; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_336 = {{32{io_in_bits_acc_read_resp_data_10_0_0[31]}}, io_in_bits_acc_read_resp_data_10_0_0} * {{32{_activated_data_e_act_T_335[31]}}, _activated_data_e_act_T_335}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_337 = _activated_data_e_act_T_336[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_338 = _activated_data_e_act_T_337; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_343 = _activated_data_e_act_T_342[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_344 = _activated_data_e_act_T_343; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_20 = 33'h0 - {_activated_data_e_act_T_344[31], _activated_data_e_act_T_344}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_21 = _activated_data_e_act_neg_q_iexp_T_20[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_10 = _activated_data_e_act_neg_q_iexp_T_21; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_40 = {{32{activated_data_e_act_neg_q_iexp_10[31]}}, activated_data_e_act_neg_q_iexp_10} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_41 = _activated_data_e_act_z_iexp_T_40; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_42 = _activated_data_e_act_z_iexp_T_41[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_43 = _activated_data_e_act_z_iexp_T_42; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_330 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_332 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_334 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_336 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_338 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_340 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_342 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_344 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_346 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_348 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_350 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_10 = _activated_data_e_act_z_iexp_T_43[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_362; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_10; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_346 = activated_data_e_act_z_iexp_saturated_10; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_331 = _activated_data_e_act_z_iexp_saturated_T_330[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_333 = _activated_data_e_act_z_iexp_saturated_T_332[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_335 = _activated_data_e_act_z_iexp_saturated_T_334[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_337 = _activated_data_e_act_z_iexp_saturated_T_336[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_339 = _activated_data_e_act_z_iexp_saturated_T_338[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_341 = _activated_data_e_act_z_iexp_saturated_T_340[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_343 = _activated_data_e_act_z_iexp_saturated_T_342[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_345 = _activated_data_e_act_z_iexp_saturated_T_344[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_347 = _activated_data_e_act_z_iexp_saturated_T_346[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_349 = _activated_data_e_act_z_iexp_saturated_T_348[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_351 = _activated_data_e_act_z_iexp_saturated_T_350[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_352 = _activated_data_e_act_z_iexp_saturated_T_331 \| _activated_data_e_act_z_iexp_saturated_T_333; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_353 = _activated_data_e_act_z_iexp_saturated_T_352 \| _activated_data_e_act_z_iexp_saturated_T_335; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_354 = _activated_data_e_act_z_iexp_saturated_T_353 \| _activated_data_e_act_z_iexp_saturated_T_337; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_355 = _activated_data_e_act_z_iexp_saturated_T_354 \| _activated_data_e_act_z_iexp_saturated_T_339; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_356 = _activated_data_e_act_z_iexp_saturated_T_355 \| _activated_data_e_act_z_iexp_saturated_T_341; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_357 = _activated_data_e_act_z_iexp_saturated_T_356 \| _activated_data_e_act_z_iexp_saturated_T_343; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_358 = _activated_data_e_act_z_iexp_saturated_T_357 \| _activated_data_e_act_z_iexp_saturated_T_345; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_359 = _activated_data_e_act_z_iexp_saturated_T_358 \| _activated_data_e_act_z_iexp_saturated_T_347; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_360 = _activated_data_e_act_z_iexp_saturated_T_359 \| _activated_data_e_act_z_iexp_saturated_T_349; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_361 = _activated_data_e_act_z_iexp_saturated_T_360 \| _activated_data_e_act_z_iexp_saturated_T_351; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_362 = _activated_data_e_act_z_iexp_saturated_T_361 ? 32'h20 : activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_10 = _activated_data_e_act_z_iexp_saturated_T_362; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_50 = {{32{activated_data_e_act_z_iexp_10[31]}}, activated_data_e_act_z_iexp_10} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_51 = {_activated_data_e_act_qp_iexp_T_50[63], _activated_data_e_act_qp_iexp_T_50} + {{33{_activated_data_e_act_T_344[31]}}, _activated_data_e_act_T_344}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_52 = _activated_data_e_act_qp_iexp_T_51[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_53 = _activated_data_e_act_qp_iexp_T_52; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_54 = _activated_data_e_act_qp_iexp_T_53[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_10 = _activated_data_e_act_qp_iexp_T_54; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_52 = {activated_data_e_act_qp_iexp_10[31], activated_data_e_act_qp_iexp_10} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_110; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_110 = _GEN_52; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_113; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_113 = _GEN_52; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_111 = _activated_data_e_act_q_poly_iexp_T_110[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_112 = _activated_data_e_act_q_poly_iexp_T_111; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_114 = _activated_data_e_act_q_poly_iexp_T_113[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_115 = _activated_data_e_act_q_poly_iexp_T_114; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_116 = {{32{_activated_data_e_act_q_poly_iexp_T_112[31]}}, _activated_data_e_act_q_poly_iexp_T_112} * {{32{_activated_data_e_act_q_poly_iexp_T_115[31]}}, _activated_data_e_act_q_poly_iexp_T_115}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_117 = {_activated_data_e_act_q_poly_iexp_T_116[63], _activated_data_e_act_q_poly_iexp_T_116} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_118 = _activated_data_e_act_q_poly_iexp_T_117[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_119 = _activated_data_e_act_q_poly_iexp_T_118; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_120 = _activated_data_e_act_q_poly_iexp_T_119[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_10 = _activated_data_e_act_q_poly_iexp_T_120; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_345 = activated_data_e_act_q_poly_iexp_10; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_347 = _activated_data_e_act_T_345 >> _activated_data_e_act_T_346; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_348 = _activated_data_e_act_T_347; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_10 = _activated_data_e_act_T_348; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_350 = _activated_data_e_act_T_349; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_351 = _activated_data_e_act_T_350; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_10 = _activated_data_e_act_T_321 ? _activated_data_e_act_T_323 : _activated_data_e_act_T_351; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_10 = activated_data_e_act_10; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_118_bits = _activated_data_e_scaled_T_117_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_53 = _activated_data_e_scaled_T_118_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_119; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_119 = _activated_data_e_scaled_WIRE_53; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_52_bits = _activated_data_e_scaled_T_119; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_10 = _activated_data_e_scaled_WIRE_52_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_10_sign = activated_data_e_scaled_f_rec_rawIn_sign_10; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_10 = _activated_data_e_scaled_WIRE_52_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_10 = _activated_data_e_scaled_WIRE_52_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 = activated_data_e_scaled_f_rec_rawIn_expIn_10 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10 = activated_data_e_scaled_f_rec_rawIn_fractIn_10 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_440 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_441 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_442 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_443 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_444 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_445 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_446 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_447 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_448 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_449 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_450 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_451 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_452 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_453 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_454 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_455 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_456 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_457 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_458 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_459 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_460 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_461 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_462 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_463 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_441 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_464 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_442 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_463; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_465 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_443 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_464; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_466 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_444 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_465; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_467 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_445 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_466; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_468 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_446 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_467; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_469 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_447 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_468; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_470 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_448 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_469; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_471 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_449 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_470; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_472 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_450 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_471; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_473 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_451 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_472; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_474 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_452 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_473; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_475 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_453 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_474; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_476 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_454 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_475; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_477 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_455 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_476; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_478 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_456 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_477; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_479 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_457 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_478; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_480 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_458 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_479; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_481 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_459 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_480; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_482 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_460 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_481; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_483 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_461 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_482; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_10 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_462 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_483; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_20 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_10} << activated_data_e_scaled_f_rec_rawIn_normDist_10; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_21 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_20[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_10 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_21, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_50 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_10}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_51 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_50 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_10}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_52 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_53 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_52}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_54 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_51} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_53}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_10 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_54[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_20 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_10; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_10 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_10_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_10 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_10[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_10 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_10; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_82 = activated_data_e_scaled_f_rec_rawIn_10_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_10_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_10_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_10_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_20 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_21 = activated_data_e_scaled_f_rec_rawIn_isSpecial_10 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_20; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_10_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_10 = activated_data_e_scaled_f_rec_rawIn_isSpecial_10 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_10_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_21 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_20}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_10_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_40 = ~activated_data_e_scaled_f_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_40}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_42 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_10 : activated_data_e_scaled_f_rec_rawIn_fractIn_10; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_43 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_41, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_42}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_10_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_80 = activated_data_e_scaled_f_rec_rawIn_10_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_81 = activated_data_e_scaled_f_rec_rawIn_10_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_80; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_83 = {_activated_data_e_scaled_f_rec_T_81[2:1], _activated_data_e_scaled_f_rec_T_81[0] \| _activated_data_e_scaled_f_rec_T_82}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_84 = {activated_data_e_scaled_f_rec_rawIn_10_sign, _activated_data_e_scaled_f_rec_T_83}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_85 = activated_data_e_scaled_f_rec_rawIn_10_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_86 = {_activated_data_e_scaled_f_rec_T_84, _activated_data_e_scaled_f_rec_T_85}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_87 = activated_data_e_scaled_f_rec_rawIn_10_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_10 = {_activated_data_e_scaled_f_rec_T_86, _activated_data_e_scaled_f_rec_T_87}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_10 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_10; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_10 = _activated_data_e_scaled_rec_fn_to_in_10_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_10 = _activated_data_e_scaled_muladder_10_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_10 = activated_data_e_scaled_sign_exp_10[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_10 = _activated_data_e_scaled_sign_isZero_T_10 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_10_isZero = activated_data_e_scaled_sign_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_10 = activated_data_e_scaled_sign_exp_10[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_10 = &_activated_data_e_scaled_sign_isSpecial_T_10; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_32; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_10; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_10; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_43; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_10_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_10_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_10_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_10_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_10_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_20 = activated_data_e_scaled_sign_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_30 = activated_data_e_scaled_sign_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_21 = activated_data_e_scaled_sign_isSpecial_10 & _activated_data_e_scaled_sign_out_isNaN_T_20; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_10_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_31 = ~_activated_data_e_scaled_sign_out_isInf_T_30; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_32 = activated_data_e_scaled_sign_isSpecial_10 & _activated_data_e_scaled_sign_out_isInf_T_31; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_10_isInf = _activated_data_e_scaled_sign_out_isInf_T_32; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_10 = _activated_data_e_scaled_muladder_10_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_10_sign = _activated_data_e_scaled_sign_out_sign_T_10; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_10 = {1'h0, activated_data_e_scaled_sign_exp_10}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_10_sExp = _activated_data_e_scaled_sign_out_sExp_T_10; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_40 = ~activated_data_e_scaled_sign_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_41 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_40}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_42 = _activated_data_e_scaled_muladder_10_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_43 = {_activated_data_e_scaled_sign_out_sig_T_41, _activated_data_e_scaled_sign_out_sig_T_42}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_10_sig = _activated_data_e_scaled_sign_out_sig_T_43; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_10 = activated_data_e_scaled_sign_out_10_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_120; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_54 = _activated_data_e_scaled_T_120; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_10 = activated_data_e_scaled_overflow_10 ? activated_data_e_scaled_sat_10 : _activated_data_e_scaled_WIRE_54; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_50 = $signed(activated_data_e_scaled_10) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_51 = $signed(activated_data_e_scaled_10) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_52 = _activated_data_e_clipped_T_51 ? 32'hFFFFFF80 : activated_data_e_scaled_10; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_53 = _activated_data_e_clipped_T_50 ? 32'h7F : _activated_data_e_clipped_T_52; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_54 = _activated_data_e_clipped_T_53[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_10 = _activated_data_e_clipped_T_54; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_10_0 = activated_data_e_clipped_10; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_10_0 = _activated_data_WIRE_10_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_353 = _activated_data_e_act_T_352; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_354 = $signed(io_in_bits_acc_read_resp_data_11_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_355 = _activated_data_e_act_T_354 ? io_in_bits_acc_read_resp_data_11_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_53 = {io_in_bits_acc_read_resp_data_11_0_0[31], io_in_bits_acc_read_resp_data_11_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_359; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_359 = _GEN_53; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_374; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_374 = _GEN_53; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_360 = _activated_data_e_act_T_359[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_361 = _activated_data_e_act_T_360; // @[Arithmetic.scala:95:38] wire _GEN_54 = $signed(io_in_bits_acc_read_resp_data_11_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_44; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_44 = _GEN_54; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_44; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_44 = _GEN_54; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_11 = {_activated_data_e_act_q_sign_T_44, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_45 = 33'h0 - _GEN_53; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_46 = _activated_data_e_act_q_abs_T_45[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_47 = _activated_data_e_act_q_abs_T_46; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_11 = _activated_data_e_act_q_abs_T_44 ? _activated_data_e_act_q_abs_T_47 : io_in_bits_acc_read_resp_data_11_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_78 = _activated_data_e_act_q_clipped_T_77[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_79 = _activated_data_e_act_q_clipped_T_78; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_80 = $signed(activated_data_e_act_q_abs_11) > $signed(_activated_data_e_act_q_clipped_T_79); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_82 = _activated_data_e_act_q_clipped_T_81[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_83 = _activated_data_e_act_q_clipped_T_82; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_11 = _activated_data_e_act_q_clipped_T_80 ? _activated_data_e_act_q_clipped_T_83 : activated_data_e_act_q_abs_11; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_55 = {activated_data_e_act_q_clipped_11[31], activated_data_e_act_q_clipped_11} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_121; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_121 = _GEN_55; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_124; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_124 = _GEN_55; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_122 = _activated_data_e_act_q_poly_T_121[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_123 = _activated_data_e_act_q_poly_T_122; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_125 = _activated_data_e_act_q_poly_T_124[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_126 = _activated_data_e_act_q_poly_T_125; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_127 = {{32{_activated_data_e_act_q_poly_T_123[31]}}, _activated_data_e_act_q_poly_T_123} * {{32{_activated_data_e_act_q_poly_T_126[31]}}, _activated_data_e_act_q_poly_T_126}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_128 = {_activated_data_e_act_q_poly_T_127[63], _activated_data_e_act_q_poly_T_127} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_129 = _activated_data_e_act_q_poly_T_128[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_130 = _activated_data_e_act_q_poly_T_129; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_131 = _activated_data_e_act_q_poly_T_130[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_11 = _activated_data_e_act_q_poly_T_131; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_22 = {{32{activated_data_e_act_q_sign_11[1]}}, activated_data_e_act_q_sign_11} * {{2{activated_data_e_act_q_poly_11[31]}}, activated_data_e_act_q_poly_11}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_23 = _activated_data_e_act_q_erf_T_22[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_11 = _activated_data_e_act_q_erf_T_23; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_365 = {activated_data_e_act_q_erf_11[31], activated_data_e_act_q_erf_11} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_366 = _activated_data_e_act_T_365[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_367 = _activated_data_e_act_T_366; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_368 = {{32{io_in_bits_acc_read_resp_data_11_0_0[31]}}, io_in_bits_acc_read_resp_data_11_0_0} * {{32{_activated_data_e_act_T_367[31]}}, _activated_data_e_act_T_367}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_369 = _activated_data_e_act_T_368[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_370 = _activated_data_e_act_T_369; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_375 = _activated_data_e_act_T_374[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_376 = _activated_data_e_act_T_375; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_22 = 33'h0 - {_activated_data_e_act_T_376[31], _activated_data_e_act_T_376}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_23 = _activated_data_e_act_neg_q_iexp_T_22[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_11 = _activated_data_e_act_neg_q_iexp_T_23; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_44 = {{32{activated_data_e_act_neg_q_iexp_11[31]}}, activated_data_e_act_neg_q_iexp_11} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_45 = _activated_data_e_act_z_iexp_T_44; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_46 = _activated_data_e_act_z_iexp_T_45[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_47 = _activated_data_e_act_z_iexp_T_46; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_363 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_365 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_367 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_369 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_371 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_373 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_375 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_377 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_379 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_381 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_383 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_11 = _activated_data_e_act_z_iexp_T_47[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_395; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_11; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_378 = activated_data_e_act_z_iexp_saturated_11; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_364 = _activated_data_e_act_z_iexp_saturated_T_363[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_366 = _activated_data_e_act_z_iexp_saturated_T_365[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_368 = _activated_data_e_act_z_iexp_saturated_T_367[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_370 = _activated_data_e_act_z_iexp_saturated_T_369[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_372 = _activated_data_e_act_z_iexp_saturated_T_371[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_374 = _activated_data_e_act_z_iexp_saturated_T_373[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_376 = _activated_data_e_act_z_iexp_saturated_T_375[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_378 = _activated_data_e_act_z_iexp_saturated_T_377[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_380 = _activated_data_e_act_z_iexp_saturated_T_379[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_382 = _activated_data_e_act_z_iexp_saturated_T_381[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_384 = _activated_data_e_act_z_iexp_saturated_T_383[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_385 = _activated_data_e_act_z_iexp_saturated_T_364 \| _activated_data_e_act_z_iexp_saturated_T_366; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_386 = _activated_data_e_act_z_iexp_saturated_T_385 \| _activated_data_e_act_z_iexp_saturated_T_368; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_387 = _activated_data_e_act_z_iexp_saturated_T_386 \| _activated_data_e_act_z_iexp_saturated_T_370; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_388 = _activated_data_e_act_z_iexp_saturated_T_387 \| _activated_data_e_act_z_iexp_saturated_T_372; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_389 = _activated_data_e_act_z_iexp_saturated_T_388 \| _activated_data_e_act_z_iexp_saturated_T_374; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_390 = _activated_data_e_act_z_iexp_saturated_T_389 \| _activated_data_e_act_z_iexp_saturated_T_376; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_391 = _activated_data_e_act_z_iexp_saturated_T_390 \| _activated_data_e_act_z_iexp_saturated_T_378; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_392 = _activated_data_e_act_z_iexp_saturated_T_391 \| _activated_data_e_act_z_iexp_saturated_T_380; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_393 = _activated_data_e_act_z_iexp_saturated_T_392 \| _activated_data_e_act_z_iexp_saturated_T_382; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_394 = _activated_data_e_act_z_iexp_saturated_T_393 \| _activated_data_e_act_z_iexp_saturated_T_384; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_395 = _activated_data_e_act_z_iexp_saturated_T_394 ? 32'h20 : activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_11 = _activated_data_e_act_z_iexp_saturated_T_395; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_55 = {{32{activated_data_e_act_z_iexp_11[31]}}, activated_data_e_act_z_iexp_11} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_56 = {_activated_data_e_act_qp_iexp_T_55[63], _activated_data_e_act_qp_iexp_T_55} + {{33{_activated_data_e_act_T_376[31]}}, _activated_data_e_act_T_376}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_57 = _activated_data_e_act_qp_iexp_T_56[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_58 = _activated_data_e_act_qp_iexp_T_57; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_59 = _activated_data_e_act_qp_iexp_T_58[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_11 = _activated_data_e_act_qp_iexp_T_59; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_56 = {activated_data_e_act_qp_iexp_11[31], activated_data_e_act_qp_iexp_11} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_121; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_121 = _GEN_56; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_124; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_124 = _GEN_56; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_122 = _activated_data_e_act_q_poly_iexp_T_121[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_123 = _activated_data_e_act_q_poly_iexp_T_122; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_125 = _activated_data_e_act_q_poly_iexp_T_124[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_126 = _activated_data_e_act_q_poly_iexp_T_125; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_127 = {{32{_activated_data_e_act_q_poly_iexp_T_123[31]}}, _activated_data_e_act_q_poly_iexp_T_123} * {{32{_activated_data_e_act_q_poly_iexp_T_126[31]}}, _activated_data_e_act_q_poly_iexp_T_126}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_128 = {_activated_data_e_act_q_poly_iexp_T_127[63], _activated_data_e_act_q_poly_iexp_T_127} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_129 = _activated_data_e_act_q_poly_iexp_T_128[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_130 = _activated_data_e_act_q_poly_iexp_T_129; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_131 = _activated_data_e_act_q_poly_iexp_T_130[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_11 = _activated_data_e_act_q_poly_iexp_T_131; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_377 = activated_data_e_act_q_poly_iexp_11; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_379 = _activated_data_e_act_T_377 >> _activated_data_e_act_T_378; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_380 = _activated_data_e_act_T_379; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_11 = _activated_data_e_act_T_380; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_382 = _activated_data_e_act_T_381; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_383 = _activated_data_e_act_T_382; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_11 = _activated_data_e_act_T_353 ? _activated_data_e_act_T_355 : _activated_data_e_act_T_383; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_11 = activated_data_e_act_11; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_129_bits = _activated_data_e_scaled_T_128_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_58 = _activated_data_e_scaled_T_129_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_130; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_130 = _activated_data_e_scaled_WIRE_58; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_57_bits = _activated_data_e_scaled_T_130; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_11 = _activated_data_e_scaled_WIRE_57_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_11_sign = activated_data_e_scaled_f_rec_rawIn_sign_11; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_11 = _activated_data_e_scaled_WIRE_57_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_11 = _activated_data_e_scaled_WIRE_57_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 = activated_data_e_scaled_f_rec_rawIn_expIn_11 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11 = activated_data_e_scaled_f_rec_rawIn_fractIn_11 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_484 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_485 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_486 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_487 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_488 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_489 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_490 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_491 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_492 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_493 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_494 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_495 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_496 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_497 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_498 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_499 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_500 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_501 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_502 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_503 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_504 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_505 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_506 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_507 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_485 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_508 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_486 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_507; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_509 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_487 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_508; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_510 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_488 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_509; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_511 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_489 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_510; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_512 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_490 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_511; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_513 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_491 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_512; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_514 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_492 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_513; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_515 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_493 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_514; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_516 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_494 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_515; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_517 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_495 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_516; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_518 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_496 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_517; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_519 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_497 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_518; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_520 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_498 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_519; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_521 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_499 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_520; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_522 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_500 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_521; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_523 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_501 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_522; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_524 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_502 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_523; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_525 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_503 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_524; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_526 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_504 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_525; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_527 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_505 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_526; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_11 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_506 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_527; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_22 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_11} << activated_data_e_scaled_f_rec_rawIn_normDist_11; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_23 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_22[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_11 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_23, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_55 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_11}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_56 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_55 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_11}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_57 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_58 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_57}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_59 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_56} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_58}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_11 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_59[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_22 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_11; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_11 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_11_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_11 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_11[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_11 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_11; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_90 = activated_data_e_scaled_f_rec_rawIn_11_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_11_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_11_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_11_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_22 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_23 = activated_data_e_scaled_f_rec_rawIn_isSpecial_11 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_22; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_11_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_11 = activated_data_e_scaled_f_rec_rawIn_isSpecial_11 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_11_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_23 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_22}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_11_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_44 = ~activated_data_e_scaled_f_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_45 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_44}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_46 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_11 : activated_data_e_scaled_f_rec_rawIn_fractIn_11; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_47 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_45, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_46}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_11_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_88 = activated_data_e_scaled_f_rec_rawIn_11_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_89 = activated_data_e_scaled_f_rec_rawIn_11_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_88; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_91 = {_activated_data_e_scaled_f_rec_T_89[2:1], _activated_data_e_scaled_f_rec_T_89[0] \| _activated_data_e_scaled_f_rec_T_90}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_92 = {activated_data_e_scaled_f_rec_rawIn_11_sign, _activated_data_e_scaled_f_rec_T_91}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_93 = activated_data_e_scaled_f_rec_rawIn_11_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_94 = {_activated_data_e_scaled_f_rec_T_92, _activated_data_e_scaled_f_rec_T_93}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_95 = activated_data_e_scaled_f_rec_rawIn_11_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_11 = {_activated_data_e_scaled_f_rec_T_94, _activated_data_e_scaled_f_rec_T_95}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_11 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_11; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_11 = _activated_data_e_scaled_rec_fn_to_in_11_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_11 = _activated_data_e_scaled_muladder_11_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_11 = activated_data_e_scaled_sign_exp_11[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_11 = _activated_data_e_scaled_sign_isZero_T_11 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_11_isZero = activated_data_e_scaled_sign_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_11 = activated_data_e_scaled_sign_exp_11[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_11 = &_activated_data_e_scaled_sign_isSpecial_T_11; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_35; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_11; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_11; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_47; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_11_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_11_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_11_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_11_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_11_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_22 = activated_data_e_scaled_sign_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_33 = activated_data_e_scaled_sign_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_23 = activated_data_e_scaled_sign_isSpecial_11 & _activated_data_e_scaled_sign_out_isNaN_T_22; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_11_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_34 = ~_activated_data_e_scaled_sign_out_isInf_T_33; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_35 = activated_data_e_scaled_sign_isSpecial_11 & _activated_data_e_scaled_sign_out_isInf_T_34; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_11_isInf = _activated_data_e_scaled_sign_out_isInf_T_35; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_11 = _activated_data_e_scaled_muladder_11_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_11_sign = _activated_data_e_scaled_sign_out_sign_T_11; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_11 = {1'h0, activated_data_e_scaled_sign_exp_11}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_11_sExp = _activated_data_e_scaled_sign_out_sExp_T_11; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_44 = ~activated_data_e_scaled_sign_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_45 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_44}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_46 = _activated_data_e_scaled_muladder_11_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_47 = {_activated_data_e_scaled_sign_out_sig_T_45, _activated_data_e_scaled_sign_out_sig_T_46}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_11_sig = _activated_data_e_scaled_sign_out_sig_T_47; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_11 = activated_data_e_scaled_sign_out_11_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_131; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_59 = _activated_data_e_scaled_T_131; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_11 = activated_data_e_scaled_overflow_11 ? activated_data_e_scaled_sat_11 : _activated_data_e_scaled_WIRE_59; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_55 = $signed(activated_data_e_scaled_11) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_56 = $signed(activated_data_e_scaled_11) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_57 = _activated_data_e_clipped_T_56 ? 32'hFFFFFF80 : activated_data_e_scaled_11; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_58 = _activated_data_e_clipped_T_55 ? 32'h7F : _activated_data_e_clipped_T_57; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_59 = _activated_data_e_clipped_T_58[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_11 = _activated_data_e_clipped_T_59; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_11_0 = activated_data_e_clipped_11; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_11_0 = _activated_data_WIRE_11_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_385 = _activated_data_e_act_T_384; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_386 = $signed(io_in_bits_acc_read_resp_data_12_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_387 = _activated_data_e_act_T_386 ? io_in_bits_acc_read_resp_data_12_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_57 = {io_in_bits_acc_read_resp_data_12_0_0[31], io_in_bits_acc_read_resp_data_12_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_391; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_391 = _GEN_57; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_406; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_406 = _GEN_57; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_392 = _activated_data_e_act_T_391[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_393 = _activated_data_e_act_T_392; // @[Arithmetic.scala:95:38] wire _GEN_58 = $signed(io_in_bits_acc_read_resp_data_12_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_48; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_48 = _GEN_58; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_48; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_48 = _GEN_58; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_12 = {_activated_data_e_act_q_sign_T_48, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_49 = 33'h0 - _GEN_57; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_50 = _activated_data_e_act_q_abs_T_49[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_51 = _activated_data_e_act_q_abs_T_50; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_12 = _activated_data_e_act_q_abs_T_48 ? _activated_data_e_act_q_abs_T_51 : io_in_bits_acc_read_resp_data_12_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_85 = _activated_data_e_act_q_clipped_T_84[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_86 = _activated_data_e_act_q_clipped_T_85; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_87 = $signed(activated_data_e_act_q_abs_12) > $signed(_activated_data_e_act_q_clipped_T_86); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_89 = _activated_data_e_act_q_clipped_T_88[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_90 = _activated_data_e_act_q_clipped_T_89; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_12 = _activated_data_e_act_q_clipped_T_87 ? _activated_data_e_act_q_clipped_T_90 : activated_data_e_act_q_abs_12; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_59 = {activated_data_e_act_q_clipped_12[31], activated_data_e_act_q_clipped_12} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_132; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_132 = _GEN_59; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_135; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_135 = _GEN_59; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_133 = _activated_data_e_act_q_poly_T_132[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_134 = _activated_data_e_act_q_poly_T_133; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_136 = _activated_data_e_act_q_poly_T_135[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_137 = _activated_data_e_act_q_poly_T_136; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_138 = {{32{_activated_data_e_act_q_poly_T_134[31]}}, _activated_data_e_act_q_poly_T_134} * {{32{_activated_data_e_act_q_poly_T_137[31]}}, _activated_data_e_act_q_poly_T_137}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_139 = {_activated_data_e_act_q_poly_T_138[63], _activated_data_e_act_q_poly_T_138} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_140 = _activated_data_e_act_q_poly_T_139[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_141 = _activated_data_e_act_q_poly_T_140; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_142 = _activated_data_e_act_q_poly_T_141[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_12 = _activated_data_e_act_q_poly_T_142; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_24 = {{32{activated_data_e_act_q_sign_12[1]}}, activated_data_e_act_q_sign_12} * {{2{activated_data_e_act_q_poly_12[31]}}, activated_data_e_act_q_poly_12}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_25 = _activated_data_e_act_q_erf_T_24[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_12 = _activated_data_e_act_q_erf_T_25; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_397 = {activated_data_e_act_q_erf_12[31], activated_data_e_act_q_erf_12} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_398 = _activated_data_e_act_T_397[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_399 = _activated_data_e_act_T_398; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_400 = {{32{io_in_bits_acc_read_resp_data_12_0_0[31]}}, io_in_bits_acc_read_resp_data_12_0_0} * {{32{_activated_data_e_act_T_399[31]}}, _activated_data_e_act_T_399}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_401 = _activated_data_e_act_T_400[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_402 = _activated_data_e_act_T_401; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_407 = _activated_data_e_act_T_406[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_408 = _activated_data_e_act_T_407; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_24 = 33'h0 - {_activated_data_e_act_T_408[31], _activated_data_e_act_T_408}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_25 = _activated_data_e_act_neg_q_iexp_T_24[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_12 = _activated_data_e_act_neg_q_iexp_T_25; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_48 = {{32{activated_data_e_act_neg_q_iexp_12[31]}}, activated_data_e_act_neg_q_iexp_12} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_49 = _activated_data_e_act_z_iexp_T_48; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_50 = _activated_data_e_act_z_iexp_T_49[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_51 = _activated_data_e_act_z_iexp_T_50; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_396 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_398 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_400 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_402 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_404 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_406 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_408 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_410 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_412 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_414 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_416 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_12 = _activated_data_e_act_z_iexp_T_51[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_428; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_12; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_410 = activated_data_e_act_z_iexp_saturated_12; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_397 = _activated_data_e_act_z_iexp_saturated_T_396[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_399 = _activated_data_e_act_z_iexp_saturated_T_398[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_401 = _activated_data_e_act_z_iexp_saturated_T_400[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_403 = _activated_data_e_act_z_iexp_saturated_T_402[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_405 = _activated_data_e_act_z_iexp_saturated_T_404[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_407 = _activated_data_e_act_z_iexp_saturated_T_406[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_409 = _activated_data_e_act_z_iexp_saturated_T_408[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_411 = _activated_data_e_act_z_iexp_saturated_T_410[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_413 = _activated_data_e_act_z_iexp_saturated_T_412[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_415 = _activated_data_e_act_z_iexp_saturated_T_414[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_417 = _activated_data_e_act_z_iexp_saturated_T_416[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_418 = _activated_data_e_act_z_iexp_saturated_T_397 \| _activated_data_e_act_z_iexp_saturated_T_399; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_419 = _activated_data_e_act_z_iexp_saturated_T_418 \| _activated_data_e_act_z_iexp_saturated_T_401; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_420 = _activated_data_e_act_z_iexp_saturated_T_419 \| _activated_data_e_act_z_iexp_saturated_T_403; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_421 = _activated_data_e_act_z_iexp_saturated_T_420 \| _activated_data_e_act_z_iexp_saturated_T_405; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_422 = _activated_data_e_act_z_iexp_saturated_T_421 \| _activated_data_e_act_z_iexp_saturated_T_407; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_423 = _activated_data_e_act_z_iexp_saturated_T_422 \| _activated_data_e_act_z_iexp_saturated_T_409; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_424 = _activated_data_e_act_z_iexp_saturated_T_423 \| _activated_data_e_act_z_iexp_saturated_T_411; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_425 = _activated_data_e_act_z_iexp_saturated_T_424 \| _activated_data_e_act_z_iexp_saturated_T_413; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_426 = _activated_data_e_act_z_iexp_saturated_T_425 \| _activated_data_e_act_z_iexp_saturated_T_415; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_427 = _activated_data_e_act_z_iexp_saturated_T_426 \| _activated_data_e_act_z_iexp_saturated_T_417; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_428 = _activated_data_e_act_z_iexp_saturated_T_427 ? 32'h20 : activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_12 = _activated_data_e_act_z_iexp_saturated_T_428; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_60 = {{32{activated_data_e_act_z_iexp_12[31]}}, activated_data_e_act_z_iexp_12} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_61 = {_activated_data_e_act_qp_iexp_T_60[63], _activated_data_e_act_qp_iexp_T_60} + {{33{_activated_data_e_act_T_408[31]}}, _activated_data_e_act_T_408}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_62 = _activated_data_e_act_qp_iexp_T_61[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_63 = _activated_data_e_act_qp_iexp_T_62; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_64 = _activated_data_e_act_qp_iexp_T_63[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_12 = _activated_data_e_act_qp_iexp_T_64; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_60 = {activated_data_e_act_qp_iexp_12[31], activated_data_e_act_qp_iexp_12} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_132; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_132 = _GEN_60; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_135; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_135 = _GEN_60; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_133 = _activated_data_e_act_q_poly_iexp_T_132[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_134 = _activated_data_e_act_q_poly_iexp_T_133; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_136 = _activated_data_e_act_q_poly_iexp_T_135[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_137 = _activated_data_e_act_q_poly_iexp_T_136; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_138 = {{32{_activated_data_e_act_q_poly_iexp_T_134[31]}}, _activated_data_e_act_q_poly_iexp_T_134} * {{32{_activated_data_e_act_q_poly_iexp_T_137[31]}}, _activated_data_e_act_q_poly_iexp_T_137}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_139 = {_activated_data_e_act_q_poly_iexp_T_138[63], _activated_data_e_act_q_poly_iexp_T_138} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_140 = _activated_data_e_act_q_poly_iexp_T_139[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_141 = _activated_data_e_act_q_poly_iexp_T_140; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_142 = _activated_data_e_act_q_poly_iexp_T_141[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_12 = _activated_data_e_act_q_poly_iexp_T_142; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_409 = activated_data_e_act_q_poly_iexp_12; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_411 = _activated_data_e_act_T_409 >> _activated_data_e_act_T_410; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_412 = _activated_data_e_act_T_411; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_12 = _activated_data_e_act_T_412; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_414 = _activated_data_e_act_T_413; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_415 = _activated_data_e_act_T_414; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_12 = _activated_data_e_act_T_385 ? _activated_data_e_act_T_387 : _activated_data_e_act_T_415; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_12 = activated_data_e_act_12; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_140_bits = _activated_data_e_scaled_T_139_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_63 = _activated_data_e_scaled_T_140_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_141; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_141 = _activated_data_e_scaled_WIRE_63; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_62_bits = _activated_data_e_scaled_T_141; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_12 = _activated_data_e_scaled_WIRE_62_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_12_sign = activated_data_e_scaled_f_rec_rawIn_sign_12; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_12 = _activated_data_e_scaled_WIRE_62_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_12 = _activated_data_e_scaled_WIRE_62_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 = activated_data_e_scaled_f_rec_rawIn_expIn_12 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12 = activated_data_e_scaled_f_rec_rawIn_fractIn_12 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_528 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_529 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_530 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_531 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_532 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_533 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_534 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_535 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_536 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_537 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_538 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_539 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_540 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_541 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_542 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_543 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_544 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_545 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_546 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_547 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_548 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_549 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_550 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_551 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_529 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_552 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_530 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_551; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_553 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_531 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_552; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_554 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_532 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_553; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_555 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_533 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_554; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_556 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_534 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_555; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_557 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_535 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_556; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_558 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_536 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_557; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_559 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_537 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_558; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_560 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_538 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_559; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_561 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_539 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_560; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_562 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_540 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_561; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_563 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_541 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_562; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_564 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_542 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_563; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_565 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_543 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_564; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_566 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_544 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_565; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_567 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_545 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_566; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_568 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_546 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_567; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_569 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_547 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_568; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_570 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_548 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_569; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_571 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_549 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_570; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_12 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_550 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_571; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_24 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_12} << activated_data_e_scaled_f_rec_rawIn_normDist_12; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_25 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_24[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_12 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_25, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_60 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_12}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_61 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_60 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_12}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_62 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_63 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_62}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_64 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_61} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_63}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_12 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_64[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_24 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_12; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_12 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_12_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_12 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_12[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_12 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_12; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_98 = activated_data_e_scaled_f_rec_rawIn_12_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_12_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_12_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_12_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_24 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_25 = activated_data_e_scaled_f_rec_rawIn_isSpecial_12 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_24; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_12_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_12 = activated_data_e_scaled_f_rec_rawIn_isSpecial_12 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_12_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_25 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_24}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_12_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_48 = ~activated_data_e_scaled_f_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_49 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_48}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_50 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_12 : activated_data_e_scaled_f_rec_rawIn_fractIn_12; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_51 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_49, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_50}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_12_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_96 = activated_data_e_scaled_f_rec_rawIn_12_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_97 = activated_data_e_scaled_f_rec_rawIn_12_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_96; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_99 = {_activated_data_e_scaled_f_rec_T_97[2:1], _activated_data_e_scaled_f_rec_T_97[0] \| _activated_data_e_scaled_f_rec_T_98}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_100 = {activated_data_e_scaled_f_rec_rawIn_12_sign, _activated_data_e_scaled_f_rec_T_99}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_101 = activated_data_e_scaled_f_rec_rawIn_12_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_102 = {_activated_data_e_scaled_f_rec_T_100, _activated_data_e_scaled_f_rec_T_101}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_103 = activated_data_e_scaled_f_rec_rawIn_12_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_12 = {_activated_data_e_scaled_f_rec_T_102, _activated_data_e_scaled_f_rec_T_103}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_12 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_12; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_12 = _activated_data_e_scaled_rec_fn_to_in_12_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_12 = _activated_data_e_scaled_muladder_12_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_12 = activated_data_e_scaled_sign_exp_12[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_12 = _activated_data_e_scaled_sign_isZero_T_12 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_12_isZero = activated_data_e_scaled_sign_isZero_12; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_12 = activated_data_e_scaled_sign_exp_12[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_12 = &_activated_data_e_scaled_sign_isSpecial_T_12; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_25; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_38; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_12; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_12; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_51; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_12_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_12_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_12_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_12_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_12_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_24 = activated_data_e_scaled_sign_exp_12[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_36 = activated_data_e_scaled_sign_exp_12[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_25 = activated_data_e_scaled_sign_isSpecial_12 & _activated_data_e_scaled_sign_out_isNaN_T_24; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_12_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_25; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_37 = ~_activated_data_e_scaled_sign_out_isInf_T_36; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_38 = activated_data_e_scaled_sign_isSpecial_12 & _activated_data_e_scaled_sign_out_isInf_T_37; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_12_isInf = _activated_data_e_scaled_sign_out_isInf_T_38; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_12 = _activated_data_e_scaled_muladder_12_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_12_sign = _activated_data_e_scaled_sign_out_sign_T_12; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_12 = {1'h0, activated_data_e_scaled_sign_exp_12}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_12_sExp = _activated_data_e_scaled_sign_out_sExp_T_12; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_48 = ~activated_data_e_scaled_sign_isZero_12; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_49 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_48}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_50 = _activated_data_e_scaled_muladder_12_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_51 = {_activated_data_e_scaled_sign_out_sig_T_49, _activated_data_e_scaled_sign_out_sig_T_50}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_12_sig = _activated_data_e_scaled_sign_out_sig_T_51; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_12 = activated_data_e_scaled_sign_out_12_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_142; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_64 = _activated_data_e_scaled_T_142; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_12 = activated_data_e_scaled_overflow_12 ? activated_data_e_scaled_sat_12 : _activated_data_e_scaled_WIRE_64; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_60 = $signed(activated_data_e_scaled_12) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_61 = $signed(activated_data_e_scaled_12) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_62 = _activated_data_e_clipped_T_61 ? 32'hFFFFFF80 : activated_data_e_scaled_12; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_63 = _activated_data_e_clipped_T_60 ? 32'h7F : _activated_data_e_clipped_T_62; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_64 = _activated_data_e_clipped_T_63[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_12 = _activated_data_e_clipped_T_64; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_12_0 = activated_data_e_clipped_12; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_12_0 = _activated_data_WIRE_12_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_417 = _activated_data_e_act_T_416; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_418 = $signed(io_in_bits_acc_read_resp_data_13_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_419 = _activated_data_e_act_T_418 ? io_in_bits_acc_read_resp_data_13_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_61 = {io_in_bits_acc_read_resp_data_13_0_0[31], io_in_bits_acc_read_resp_data_13_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_423; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_423 = _GEN_61; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_438; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_438 = _GEN_61; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_424 = _activated_data_e_act_T_423[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_425 = _activated_data_e_act_T_424; // @[Arithmetic.scala:95:38] wire _GEN_62 = $signed(io_in_bits_acc_read_resp_data_13_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_52; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_52 = _GEN_62; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_52; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_52 = _GEN_62; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_13 = {_activated_data_e_act_q_sign_T_52, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_53 = 33'h0 - _GEN_61; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_54 = _activated_data_e_act_q_abs_T_53[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_55 = _activated_data_e_act_q_abs_T_54; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_13 = _activated_data_e_act_q_abs_T_52 ? _activated_data_e_act_q_abs_T_55 : io_in_bits_acc_read_resp_data_13_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_92 = _activated_data_e_act_q_clipped_T_91[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_93 = _activated_data_e_act_q_clipped_T_92; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_94 = $signed(activated_data_e_act_q_abs_13) > $signed(_activated_data_e_act_q_clipped_T_93); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_96 = _activated_data_e_act_q_clipped_T_95[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_97 = _activated_data_e_act_q_clipped_T_96; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_13 = _activated_data_e_act_q_clipped_T_94 ? _activated_data_e_act_q_clipped_T_97 : activated_data_e_act_q_abs_13; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_63 = {activated_data_e_act_q_clipped_13[31], activated_data_e_act_q_clipped_13} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_143; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_143 = _GEN_63; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_146; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_146 = _GEN_63; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_144 = _activated_data_e_act_q_poly_T_143[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_145 = _activated_data_e_act_q_poly_T_144; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_147 = _activated_data_e_act_q_poly_T_146[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_148 = _activated_data_e_act_q_poly_T_147; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_149 = {{32{_activated_data_e_act_q_poly_T_145[31]}}, _activated_data_e_act_q_poly_T_145} * {{32{_activated_data_e_act_q_poly_T_148[31]}}, _activated_data_e_act_q_poly_T_148}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_150 = {_activated_data_e_act_q_poly_T_149[63], _activated_data_e_act_q_poly_T_149} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_151 = _activated_data_e_act_q_poly_T_150[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_152 = _activated_data_e_act_q_poly_T_151; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_153 = _activated_data_e_act_q_poly_T_152[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_13 = _activated_data_e_act_q_poly_T_153; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_26 = {{32{activated_data_e_act_q_sign_13[1]}}, activated_data_e_act_q_sign_13} * {{2{activated_data_e_act_q_poly_13[31]}}, activated_data_e_act_q_poly_13}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_27 = _activated_data_e_act_q_erf_T_26[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_13 = _activated_data_e_act_q_erf_T_27; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_429 = {activated_data_e_act_q_erf_13[31], activated_data_e_act_q_erf_13} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_430 = _activated_data_e_act_T_429[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_431 = _activated_data_e_act_T_430; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_432 = {{32{io_in_bits_acc_read_resp_data_13_0_0[31]}}, io_in_bits_acc_read_resp_data_13_0_0} * {{32{_activated_data_e_act_T_431[31]}}, _activated_data_e_act_T_431}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_433 = _activated_data_e_act_T_432[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_434 = _activated_data_e_act_T_433; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_439 = _activated_data_e_act_T_438[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_440 = _activated_data_e_act_T_439; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_26 = 33'h0 - {_activated_data_e_act_T_440[31], _activated_data_e_act_T_440}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_27 = _activated_data_e_act_neg_q_iexp_T_26[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_13 = _activated_data_e_act_neg_q_iexp_T_27; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_52 = {{32{activated_data_e_act_neg_q_iexp_13[31]}}, activated_data_e_act_neg_q_iexp_13} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_53 = _activated_data_e_act_z_iexp_T_52; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_54 = _activated_data_e_act_z_iexp_T_53[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_55 = _activated_data_e_act_z_iexp_T_54; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_429 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_431 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_433 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_435 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_437 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_439 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_441 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_443 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_445 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_447 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_449 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_13 = _activated_data_e_act_z_iexp_T_55[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_461; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_13; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_442 = activated_data_e_act_z_iexp_saturated_13; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_430 = _activated_data_e_act_z_iexp_saturated_T_429[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_432 = _activated_data_e_act_z_iexp_saturated_T_431[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_434 = _activated_data_e_act_z_iexp_saturated_T_433[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_436 = _activated_data_e_act_z_iexp_saturated_T_435[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_438 = _activated_data_e_act_z_iexp_saturated_T_437[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_440 = _activated_data_e_act_z_iexp_saturated_T_439[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_442 = _activated_data_e_act_z_iexp_saturated_T_441[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_444 = _activated_data_e_act_z_iexp_saturated_T_443[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_446 = _activated_data_e_act_z_iexp_saturated_T_445[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_448 = _activated_data_e_act_z_iexp_saturated_T_447[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_450 = _activated_data_e_act_z_iexp_saturated_T_449[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_451 = _activated_data_e_act_z_iexp_saturated_T_430 \| _activated_data_e_act_z_iexp_saturated_T_432; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_452 = _activated_data_e_act_z_iexp_saturated_T_451 \| _activated_data_e_act_z_iexp_saturated_T_434; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_453 = _activated_data_e_act_z_iexp_saturated_T_452 \| _activated_data_e_act_z_iexp_saturated_T_436; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_454 = _activated_data_e_act_z_iexp_saturated_T_453 \| _activated_data_e_act_z_iexp_saturated_T_438; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_455 = _activated_data_e_act_z_iexp_saturated_T_454 \| _activated_data_e_act_z_iexp_saturated_T_440; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_456 = _activated_data_e_act_z_iexp_saturated_T_455 \| _activated_data_e_act_z_iexp_saturated_T_442; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_457 = _activated_data_e_act_z_iexp_saturated_T_456 \| _activated_data_e_act_z_iexp_saturated_T_444; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_458 = _activated_data_e_act_z_iexp_saturated_T_457 \| _activated_data_e_act_z_iexp_saturated_T_446; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_459 = _activated_data_e_act_z_iexp_saturated_T_458 \| _activated_data_e_act_z_iexp_saturated_T_448; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_460 = _activated_data_e_act_z_iexp_saturated_T_459 \| _activated_data_e_act_z_iexp_saturated_T_450; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_461 = _activated_data_e_act_z_iexp_saturated_T_460 ? 32'h20 : activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_13 = _activated_data_e_act_z_iexp_saturated_T_461; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_65 = {{32{activated_data_e_act_z_iexp_13[31]}}, activated_data_e_act_z_iexp_13} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_66 = {_activated_data_e_act_qp_iexp_T_65[63], _activated_data_e_act_qp_iexp_T_65} + {{33{_activated_data_e_act_T_440[31]}}, _activated_data_e_act_T_440}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_67 = _activated_data_e_act_qp_iexp_T_66[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_68 = _activated_data_e_act_qp_iexp_T_67; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_69 = _activated_data_e_act_qp_iexp_T_68[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_13 = _activated_data_e_act_qp_iexp_T_69; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_64 = {activated_data_e_act_qp_iexp_13[31], activated_data_e_act_qp_iexp_13} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_143; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_143 = _GEN_64; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_146; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_146 = _GEN_64; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_144 = _activated_data_e_act_q_poly_iexp_T_143[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_145 = _activated_data_e_act_q_poly_iexp_T_144; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_147 = _activated_data_e_act_q_poly_iexp_T_146[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_148 = _activated_data_e_act_q_poly_iexp_T_147; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_149 = {{32{_activated_data_e_act_q_poly_iexp_T_145[31]}}, _activated_data_e_act_q_poly_iexp_T_145} * {{32{_activated_data_e_act_q_poly_iexp_T_148[31]}}, _activated_data_e_act_q_poly_iexp_T_148}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_150 = {_activated_data_e_act_q_poly_iexp_T_149[63], _activated_data_e_act_q_poly_iexp_T_149} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_151 = _activated_data_e_act_q_poly_iexp_T_150[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_152 = _activated_data_e_act_q_poly_iexp_T_151; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_153 = _activated_data_e_act_q_poly_iexp_T_152[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_13 = _activated_data_e_act_q_poly_iexp_T_153; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_441 = activated_data_e_act_q_poly_iexp_13; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_443 = _activated_data_e_act_T_441 >> _activated_data_e_act_T_442; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_444 = _activated_data_e_act_T_443; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_13 = _activated_data_e_act_T_444; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_446 = _activated_data_e_act_T_445; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_447 = _activated_data_e_act_T_446; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_13 = _activated_data_e_act_T_417 ? _activated_data_e_act_T_419 : _activated_data_e_act_T_447; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_13 = activated_data_e_act_13; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_151_bits = _activated_data_e_scaled_T_150_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_68 = _activated_data_e_scaled_T_151_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_152; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_152 = _activated_data_e_scaled_WIRE_68; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_67_bits = _activated_data_e_scaled_T_152; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_13 = _activated_data_e_scaled_WIRE_67_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_13_sign = activated_data_e_scaled_f_rec_rawIn_sign_13; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_13 = _activated_data_e_scaled_WIRE_67_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_13 = _activated_data_e_scaled_WIRE_67_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 = activated_data_e_scaled_f_rec_rawIn_expIn_13 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13 = activated_data_e_scaled_f_rec_rawIn_fractIn_13 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_572 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_573 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_574 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_575 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_576 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_577 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_578 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_579 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_580 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_581 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_582 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_583 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_584 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_585 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_586 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_587 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_588 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_589 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_590 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_591 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_592 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_593 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_594 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_595 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_573 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_596 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_574 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_595; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_597 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_575 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_596; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_598 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_576 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_597; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_599 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_577 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_598; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_600 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_578 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_599; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_601 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_579 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_600; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_602 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_580 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_601; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_603 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_581 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_602; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_604 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_582 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_603; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_605 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_583 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_604; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_606 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_584 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_605; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_607 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_585 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_606; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_608 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_586 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_607; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_609 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_587 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_608; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_610 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_588 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_609; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_611 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_589 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_610; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_612 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_590 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_611; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_613 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_591 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_612; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_614 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_592 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_613; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_615 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_593 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_614; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_13 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_594 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_615; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_26 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_13} << activated_data_e_scaled_f_rec_rawIn_normDist_13; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_27 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_26[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_13 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_27, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_65 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_13}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_66 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_65 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_13}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_67 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_68 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_67}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_69 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_66} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_68}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_13 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_69[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_26 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_13; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_13 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_13_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_13 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_13[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_13 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_13; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_106 = activated_data_e_scaled_f_rec_rawIn_13_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_13_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_13_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_13_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_26 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_27 = activated_data_e_scaled_f_rec_rawIn_isSpecial_13 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_26; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_13_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_13 = activated_data_e_scaled_f_rec_rawIn_isSpecial_13 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_13_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_27 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_26}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_13_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_52 = ~activated_data_e_scaled_f_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_53 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_52}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_54 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_13 : activated_data_e_scaled_f_rec_rawIn_fractIn_13; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_55 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_53, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_54}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_13_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_104 = activated_data_e_scaled_f_rec_rawIn_13_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_105 = activated_data_e_scaled_f_rec_rawIn_13_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_104; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_107 = {_activated_data_e_scaled_f_rec_T_105[2:1], _activated_data_e_scaled_f_rec_T_105[0] \| _activated_data_e_scaled_f_rec_T_106}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_108 = {activated_data_e_scaled_f_rec_rawIn_13_sign, _activated_data_e_scaled_f_rec_T_107}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_109 = activated_data_e_scaled_f_rec_rawIn_13_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_110 = {_activated_data_e_scaled_f_rec_T_108, _activated_data_e_scaled_f_rec_T_109}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_111 = activated_data_e_scaled_f_rec_rawIn_13_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_13 = {_activated_data_e_scaled_f_rec_T_110, _activated_data_e_scaled_f_rec_T_111}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_13 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_13; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_13 = _activated_data_e_scaled_rec_fn_to_in_13_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_13 = _activated_data_e_scaled_muladder_13_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_13 = activated_data_e_scaled_sign_exp_13[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_13 = _activated_data_e_scaled_sign_isZero_T_13 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_13_isZero = activated_data_e_scaled_sign_isZero_13; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_13 = activated_data_e_scaled_sign_exp_13[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_13 = &_activated_data_e_scaled_sign_isSpecial_T_13; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_27; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_41; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_13; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_13; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_55; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_13_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_13_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_13_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_13_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_13_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_26 = activated_data_e_scaled_sign_exp_13[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_39 = activated_data_e_scaled_sign_exp_13[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_27 = activated_data_e_scaled_sign_isSpecial_13 & _activated_data_e_scaled_sign_out_isNaN_T_26; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_13_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_27; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_40 = ~_activated_data_e_scaled_sign_out_isInf_T_39; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_41 = activated_data_e_scaled_sign_isSpecial_13 & _activated_data_e_scaled_sign_out_isInf_T_40; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_13_isInf = _activated_data_e_scaled_sign_out_isInf_T_41; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_13 = _activated_data_e_scaled_muladder_13_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_13_sign = _activated_data_e_scaled_sign_out_sign_T_13; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_13 = {1'h0, activated_data_e_scaled_sign_exp_13}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_13_sExp = _activated_data_e_scaled_sign_out_sExp_T_13; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_52 = ~activated_data_e_scaled_sign_isZero_13; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_53 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_52}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_54 = _activated_data_e_scaled_muladder_13_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_55 = {_activated_data_e_scaled_sign_out_sig_T_53, _activated_data_e_scaled_sign_out_sig_T_54}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_13_sig = _activated_data_e_scaled_sign_out_sig_T_55; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_13 = activated_data_e_scaled_sign_out_13_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_153; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_69 = _activated_data_e_scaled_T_153; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_13 = activated_data_e_scaled_overflow_13 ? activated_data_e_scaled_sat_13 : _activated_data_e_scaled_WIRE_69; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_65 = $signed(activated_data_e_scaled_13) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_66 = $signed(activated_data_e_scaled_13) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_67 = _activated_data_e_clipped_T_66 ? 32'hFFFFFF80 : activated_data_e_scaled_13; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_68 = _activated_data_e_clipped_T_65 ? 32'h7F : _activated_data_e_clipped_T_67; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_69 = _activated_data_e_clipped_T_68[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_13 = _activated_data_e_clipped_T_69; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_13_0 = activated_data_e_clipped_13; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_13_0 = _activated_data_WIRE_13_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_449 = _activated_data_e_act_T_448; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_450 = $signed(io_in_bits_acc_read_resp_data_14_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_451 = _activated_data_e_act_T_450 ? io_in_bits_acc_read_resp_data_14_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_65 = {io_in_bits_acc_read_resp_data_14_0_0[31], io_in_bits_acc_read_resp_data_14_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_455; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_455 = _GEN_65; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_470; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_470 = _GEN_65; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_456 = _activated_data_e_act_T_455[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_457 = _activated_data_e_act_T_456; // @[Arithmetic.scala:95:38] wire _GEN_66 = $signed(io_in_bits_acc_read_resp_data_14_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_56; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_56 = _GEN_66; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_56; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_56 = _GEN_66; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_14 = {_activated_data_e_act_q_sign_T_56, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_57 = 33'h0 - _GEN_65; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_58 = _activated_data_e_act_q_abs_T_57[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_59 = _activated_data_e_act_q_abs_T_58; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_14 = _activated_data_e_act_q_abs_T_56 ? _activated_data_e_act_q_abs_T_59 : io_in_bits_acc_read_resp_data_14_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_99 = _activated_data_e_act_q_clipped_T_98[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_100 = _activated_data_e_act_q_clipped_T_99; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_101 = $signed(activated_data_e_act_q_abs_14) > $signed(_activated_data_e_act_q_clipped_T_100); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_103 = _activated_data_e_act_q_clipped_T_102[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_104 = _activated_data_e_act_q_clipped_T_103; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_14 = _activated_data_e_act_q_clipped_T_101 ? _activated_data_e_act_q_clipped_T_104 : activated_data_e_act_q_abs_14; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_67 = {activated_data_e_act_q_clipped_14[31], activated_data_e_act_q_clipped_14} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_154; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_154 = _GEN_67; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_157; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_157 = _GEN_67; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_155 = _activated_data_e_act_q_poly_T_154[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_156 = _activated_data_e_act_q_poly_T_155; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_158 = _activated_data_e_act_q_poly_T_157[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_159 = _activated_data_e_act_q_poly_T_158; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_160 = {{32{_activated_data_e_act_q_poly_T_156[31]}}, _activated_data_e_act_q_poly_T_156} * {{32{_activated_data_e_act_q_poly_T_159[31]}}, _activated_data_e_act_q_poly_T_159}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_161 = {_activated_data_e_act_q_poly_T_160[63], _activated_data_e_act_q_poly_T_160} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_162 = _activated_data_e_act_q_poly_T_161[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_163 = _activated_data_e_act_q_poly_T_162; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_164 = _activated_data_e_act_q_poly_T_163[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_14 = _activated_data_e_act_q_poly_T_164; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_28 = {{32{activated_data_e_act_q_sign_14[1]}}, activated_data_e_act_q_sign_14} * {{2{activated_data_e_act_q_poly_14[31]}}, activated_data_e_act_q_poly_14}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_29 = _activated_data_e_act_q_erf_T_28[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_14 = _activated_data_e_act_q_erf_T_29; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_461 = {activated_data_e_act_q_erf_14[31], activated_data_e_act_q_erf_14} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_462 = _activated_data_e_act_T_461[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_463 = _activated_data_e_act_T_462; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_464 = {{32{io_in_bits_acc_read_resp_data_14_0_0[31]}}, io_in_bits_acc_read_resp_data_14_0_0} * {{32{_activated_data_e_act_T_463[31]}}, _activated_data_e_act_T_463}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_465 = _activated_data_e_act_T_464[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_466 = _activated_data_e_act_T_465; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_471 = _activated_data_e_act_T_470[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_472 = _activated_data_e_act_T_471; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_28 = 33'h0 - {_activated_data_e_act_T_472[31], _activated_data_e_act_T_472}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_29 = _activated_data_e_act_neg_q_iexp_T_28[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_14 = _activated_data_e_act_neg_q_iexp_T_29; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_56 = {{32{activated_data_e_act_neg_q_iexp_14[31]}}, activated_data_e_act_neg_q_iexp_14} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_57 = _activated_data_e_act_z_iexp_T_56; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_58 = _activated_data_e_act_z_iexp_T_57[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_59 = _activated_data_e_act_z_iexp_T_58; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_462 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_464 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_466 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_468 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_470 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_472 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_474 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_476 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_478 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_480 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_482 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_14 = _activated_data_e_act_z_iexp_T_59[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_494; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_14; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_474 = activated_data_e_act_z_iexp_saturated_14; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_463 = _activated_data_e_act_z_iexp_saturated_T_462[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_465 = _activated_data_e_act_z_iexp_saturated_T_464[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_467 = _activated_data_e_act_z_iexp_saturated_T_466[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_469 = _activated_data_e_act_z_iexp_saturated_T_468[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_471 = _activated_data_e_act_z_iexp_saturated_T_470[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_473 = _activated_data_e_act_z_iexp_saturated_T_472[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_475 = _activated_data_e_act_z_iexp_saturated_T_474[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_477 = _activated_data_e_act_z_iexp_saturated_T_476[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_479 = _activated_data_e_act_z_iexp_saturated_T_478[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_481 = _activated_data_e_act_z_iexp_saturated_T_480[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_483 = _activated_data_e_act_z_iexp_saturated_T_482[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_484 = _activated_data_e_act_z_iexp_saturated_T_463 \| _activated_data_e_act_z_iexp_saturated_T_465; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_485 = _activated_data_e_act_z_iexp_saturated_T_484 \| _activated_data_e_act_z_iexp_saturated_T_467; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_486 = _activated_data_e_act_z_iexp_saturated_T_485 \| _activated_data_e_act_z_iexp_saturated_T_469; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_487 = _activated_data_e_act_z_iexp_saturated_T_486 \| _activated_data_e_act_z_iexp_saturated_T_471; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_488 = _activated_data_e_act_z_iexp_saturated_T_487 \| _activated_data_e_act_z_iexp_saturated_T_473; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_489 = _activated_data_e_act_z_iexp_saturated_T_488 \| _activated_data_e_act_z_iexp_saturated_T_475; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_490 = _activated_data_e_act_z_iexp_saturated_T_489 \| _activated_data_e_act_z_iexp_saturated_T_477; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_491 = _activated_data_e_act_z_iexp_saturated_T_490 \| _activated_data_e_act_z_iexp_saturated_T_479; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_492 = _activated_data_e_act_z_iexp_saturated_T_491 \| _activated_data_e_act_z_iexp_saturated_T_481; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_493 = _activated_data_e_act_z_iexp_saturated_T_492 \| _activated_data_e_act_z_iexp_saturated_T_483; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_494 = _activated_data_e_act_z_iexp_saturated_T_493 ? 32'h20 : activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_14 = _activated_data_e_act_z_iexp_saturated_T_494; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_70 = {{32{activated_data_e_act_z_iexp_14[31]}}, activated_data_e_act_z_iexp_14} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_71 = {_activated_data_e_act_qp_iexp_T_70[63], _activated_data_e_act_qp_iexp_T_70} + {{33{_activated_data_e_act_T_472[31]}}, _activated_data_e_act_T_472}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_72 = _activated_data_e_act_qp_iexp_T_71[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_73 = _activated_data_e_act_qp_iexp_T_72; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_74 = _activated_data_e_act_qp_iexp_T_73[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_14 = _activated_data_e_act_qp_iexp_T_74; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_68 = {activated_data_e_act_qp_iexp_14[31], activated_data_e_act_qp_iexp_14} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_154; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_154 = _GEN_68; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_157; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_157 = _GEN_68; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_155 = _activated_data_e_act_q_poly_iexp_T_154[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_156 = _activated_data_e_act_q_poly_iexp_T_155; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_158 = _activated_data_e_act_q_poly_iexp_T_157[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_159 = _activated_data_e_act_q_poly_iexp_T_158; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_160 = {{32{_activated_data_e_act_q_poly_iexp_T_156[31]}}, _activated_data_e_act_q_poly_iexp_T_156} * {{32{_activated_data_e_act_q_poly_iexp_T_159[31]}}, _activated_data_e_act_q_poly_iexp_T_159}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_161 = {_activated_data_e_act_q_poly_iexp_T_160[63], _activated_data_e_act_q_poly_iexp_T_160} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_162 = _activated_data_e_act_q_poly_iexp_T_161[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_163 = _activated_data_e_act_q_poly_iexp_T_162; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_164 = _activated_data_e_act_q_poly_iexp_T_163[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_14 = _activated_data_e_act_q_poly_iexp_T_164; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_473 = activated_data_e_act_q_poly_iexp_14; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_475 = _activated_data_e_act_T_473 >> _activated_data_e_act_T_474; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_476 = _activated_data_e_act_T_475; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_14 = _activated_data_e_act_T_476; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_478 = _activated_data_e_act_T_477; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_479 = _activated_data_e_act_T_478; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_14 = _activated_data_e_act_T_449 ? _activated_data_e_act_T_451 : _activated_data_e_act_T_479; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_14 = activated_data_e_act_14; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_162_bits = _activated_data_e_scaled_T_161_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_73 = _activated_data_e_scaled_T_162_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_163; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_163 = _activated_data_e_scaled_WIRE_73; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_72_bits = _activated_data_e_scaled_T_163; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_14 = _activated_data_e_scaled_WIRE_72_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_14_sign = activated_data_e_scaled_f_rec_rawIn_sign_14; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_14 = _activated_data_e_scaled_WIRE_72_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_14 = _activated_data_e_scaled_WIRE_72_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 = activated_data_e_scaled_f_rec_rawIn_expIn_14 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14 = activated_data_e_scaled_f_rec_rawIn_fractIn_14 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_616 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_617 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_618 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_619 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_620 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_621 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_622 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_623 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_624 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_625 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_626 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_627 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_628 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_629 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_630 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_631 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_632 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_633 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_634 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_635 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_636 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_637 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_638 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_639 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_617 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_640 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_618 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_639; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_641 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_619 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_640; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_642 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_620 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_641; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_643 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_621 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_642; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_644 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_622 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_643; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_645 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_623 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_644; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_646 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_624 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_645; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_647 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_625 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_646; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_648 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_626 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_647; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_649 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_627 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_648; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_650 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_628 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_649; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_651 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_629 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_650; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_652 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_630 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_651; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_653 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_631 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_652; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_654 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_632 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_653; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_655 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_633 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_654; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_656 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_634 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_655; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_657 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_635 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_656; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_658 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_636 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_657; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_659 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_637 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_658; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_14 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_638 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_659; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_28 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_14} << activated_data_e_scaled_f_rec_rawIn_normDist_14; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_29 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_28[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_14 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_29, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_70 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_14}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_71 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_70 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_14}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_72 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_73 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_72}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_74 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_71} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_73}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_14 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_74[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_28 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_14; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_14 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_14_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_14 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_14[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_14 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_14; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_114 = activated_data_e_scaled_f_rec_rawIn_14_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_14_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_14_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_14_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_28 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_29 = activated_data_e_scaled_f_rec_rawIn_isSpecial_14 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_28; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_14_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_14 = activated_data_e_scaled_f_rec_rawIn_isSpecial_14 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_14_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_29 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_28}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_14_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_56 = ~activated_data_e_scaled_f_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_57 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_56}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_58 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_14 : activated_data_e_scaled_f_rec_rawIn_fractIn_14; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_59 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_57, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_58}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_14_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_112 = activated_data_e_scaled_f_rec_rawIn_14_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_113 = activated_data_e_scaled_f_rec_rawIn_14_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_112; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_115 = {_activated_data_e_scaled_f_rec_T_113[2:1], _activated_data_e_scaled_f_rec_T_113[0] \| _activated_data_e_scaled_f_rec_T_114}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_116 = {activated_data_e_scaled_f_rec_rawIn_14_sign, _activated_data_e_scaled_f_rec_T_115}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_117 = activated_data_e_scaled_f_rec_rawIn_14_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_118 = {_activated_data_e_scaled_f_rec_T_116, _activated_data_e_scaled_f_rec_T_117}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_119 = activated_data_e_scaled_f_rec_rawIn_14_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_14 = {_activated_data_e_scaled_f_rec_T_118, _activated_data_e_scaled_f_rec_T_119}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_14 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_14; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_14 = _activated_data_e_scaled_rec_fn_to_in_14_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_14 = _activated_data_e_scaled_muladder_14_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_14 = activated_data_e_scaled_sign_exp_14[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_14 = _activated_data_e_scaled_sign_isZero_T_14 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_14_isZero = activated_data_e_scaled_sign_isZero_14; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_14 = activated_data_e_scaled_sign_exp_14[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_14 = &_activated_data_e_scaled_sign_isSpecial_T_14; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_29; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_44; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_14; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_14; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_59; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_14_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_14_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_14_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_14_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_14_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_28 = activated_data_e_scaled_sign_exp_14[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_42 = activated_data_e_scaled_sign_exp_14[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_29 = activated_data_e_scaled_sign_isSpecial_14 & _activated_data_e_scaled_sign_out_isNaN_T_28; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_14_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_29; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_43 = ~_activated_data_e_scaled_sign_out_isInf_T_42; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_44 = activated_data_e_scaled_sign_isSpecial_14 & _activated_data_e_scaled_sign_out_isInf_T_43; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_14_isInf = _activated_data_e_scaled_sign_out_isInf_T_44; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_14 = _activated_data_e_scaled_muladder_14_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_14_sign = _activated_data_e_scaled_sign_out_sign_T_14; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_14 = {1'h0, activated_data_e_scaled_sign_exp_14}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_14_sExp = _activated_data_e_scaled_sign_out_sExp_T_14; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_56 = ~activated_data_e_scaled_sign_isZero_14; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_57 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_56}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_58 = _activated_data_e_scaled_muladder_14_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_59 = {_activated_data_e_scaled_sign_out_sig_T_57, _activated_data_e_scaled_sign_out_sig_T_58}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_14_sig = _activated_data_e_scaled_sign_out_sig_T_59; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_14 = activated_data_e_scaled_sign_out_14_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_164; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_74 = _activated_data_e_scaled_T_164; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_14 = activated_data_e_scaled_overflow_14 ? activated_data_e_scaled_sat_14 : _activated_data_e_scaled_WIRE_74; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_70 = $signed(activated_data_e_scaled_14) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_71 = $signed(activated_data_e_scaled_14) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_72 = _activated_data_e_clipped_T_71 ? 32'hFFFFFF80 : activated_data_e_scaled_14; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_73 = _activated_data_e_clipped_T_70 ? 32'h7F : _activated_data_e_clipped_T_72; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_74 = _activated_data_e_clipped_T_73[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_14 = _activated_data_e_clipped_T_74; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_14_0 = activated_data_e_clipped_14; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_14_0 = _activated_data_WIRE_14_0; // @[AccumulatorScale.scala:116:{33,55}] wire _activated_data_e_act_T_481 = _activated_data_e_act_T_480; // @[AccumulatorScale.scala:118:{38,45}] wire _activated_data_e_act_T_482 = $signed(io_in_bits_acc_read_resp_data_15_0_0) > -32'sh1; // @[Arithmetic.scala:128:42] wire [31:0] _activated_data_e_act_T_483 = _activated_data_e_act_T_482 ? io_in_bits_acc_read_resp_data_15_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}] wire [32:0] _GEN_69 = {io_in_bits_acc_read_resp_data_15_0_0[31], io_in_bits_acc_read_resp_data_15_0_0}; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_487; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_487 = _GEN_69; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_T_502; // @[Arithmetic.scala:95:38] assign _activated_data_e_act_T_502 = _GEN_69; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_488 = _activated_data_e_act_T_487[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_489 = _activated_data_e_act_T_488; // @[Arithmetic.scala:95:38] wire _GEN_70 = $signed(io_in_bits_acc_read_resp_data_15_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42] wire _activated_data_e_act_q_sign_T_60; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_sign_T_60 = _GEN_70; // @[Arithmetic.scala:110:44] wire _activated_data_e_act_q_abs_T_60; // @[Arithmetic.scala:110:44] assign _activated_data_e_act_q_abs_T_60 = _GEN_70; // @[Arithmetic.scala:110:44] wire [1:0] activated_data_e_act_q_sign_15 = {_activated_data_e_act_q_sign_T_60, 1'h1}; // @[Arithmetic.scala:110:44] wire [32:0] _activated_data_e_act_q_abs_T_61 = 33'h0 - _GEN_69; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_q_abs_T_62 = _activated_data_e_act_q_abs_T_61[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_abs_T_63 = _activated_data_e_act_q_abs_T_62; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_abs_15 = _activated_data_e_act_q_abs_T_60 ? _activated_data_e_act_q_abs_T_63 : io_in_bits_acc_read_resp_data_15_0_0; // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_106 = _activated_data_e_act_q_clipped_T_105[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_107 = _activated_data_e_act_q_clipped_T_106; // @[Arithmetic.scala:95:38] wire _activated_data_e_act_q_clipped_T_108 = $signed(activated_data_e_act_q_abs_15) > $signed(_activated_data_e_act_q_clipped_T_107); // @[Arithmetic.scala:95:38, :110:44] wire [31:0] _activated_data_e_act_q_clipped_T_110 = _activated_data_e_act_q_clipped_T_109[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_q_clipped_T_111 = _activated_data_e_act_q_clipped_T_110; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_q_clipped_15 = _activated_data_e_act_q_clipped_T_108 ? _activated_data_e_act_q_clipped_T_111 : activated_data_e_act_q_abs_15; // @[Arithmetic.scala:95:38, :110:44] wire [32:0] _GEN_71 = {activated_data_e_act_q_clipped_15[31], activated_data_e_act_q_clipped_15} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42] wire [32:0] _activated_data_e_act_q_poly_T_165; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_165 = _GEN_71; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_T_168; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_T_168 = _GEN_71; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_166 = _activated_data_e_act_q_poly_T_165[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_167 = _activated_data_e_act_q_poly_T_166; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_169 = _activated_data_e_act_q_poly_T_168[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_T_170 = _activated_data_e_act_q_poly_T_169; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_T_171 = {{32{_activated_data_e_act_q_poly_T_167[31]}}, _activated_data_e_act_q_poly_T_167} * {{32{_activated_data_e_act_q_poly_T_170[31]}}, _activated_data_e_act_q_poly_T_170}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_T_172 = {_activated_data_e_act_q_poly_T_171[63], _activated_data_e_act_q_poly_T_171} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_T_173 = _activated_data_e_act_q_poly_T_172[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_T_174 = _activated_data_e_act_q_poly_T_173; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_T_175 = _activated_data_e_act_q_poly_T_174[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_15 = _activated_data_e_act_q_poly_T_175; // @[Arithmetic.scala:114:{15,33}] wire [33:0] _activated_data_e_act_q_erf_T_30 = {{32{activated_data_e_act_q_sign_15[1]}}, activated_data_e_act_q_sign_15} * {{2{activated_data_e_act_q_poly_15[31]}}, activated_data_e_act_q_poly_15}; // @[Arithmetic.scala:92:38, :114:33] wire [31:0] _activated_data_e_act_q_erf_T_31 = _activated_data_e_act_q_erf_T_30[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] activated_data_e_act_q_erf_15 = _activated_data_e_act_q_erf_T_31; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _activated_data_e_act_T_493 = {activated_data_e_act_q_erf_15[31], activated_data_e_act_q_erf_15} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33] wire [31:0] _activated_data_e_act_T_494 = _activated_data_e_act_T_493[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_T_495 = _activated_data_e_act_T_494; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_T_496 = {{32{io_in_bits_acc_read_resp_data_15_0_0[31]}}, io_in_bits_acc_read_resp_data_15_0_0} * {{32{_activated_data_e_act_T_495[31]}}, _activated_data_e_act_T_495}; // @[Arithmetic.scala:92:38, :94:38, :95:38] wire [31:0] _activated_data_e_act_T_497 = _activated_data_e_act_T_496[31:0]; // @[Arithmetic.scala:92:38, :114:15] wire [31:0] _activated_data_e_act_T_498 = _activated_data_e_act_T_497; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_503 = _activated_data_e_act_T_502[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] _activated_data_e_act_T_504 = _activated_data_e_act_T_503; // @[Arithmetic.scala:95:38] wire [32:0] _activated_data_e_act_neg_q_iexp_T_30 = 33'h0 - {_activated_data_e_act_T_504[31], _activated_data_e_act_T_504}; // @[Arithmetic.scala:95:38, :128:42] wire [31:0] _activated_data_e_act_neg_q_iexp_T_31 = _activated_data_e_act_neg_q_iexp_T_30[31:0]; // @[Arithmetic.scala:95:38] wire [31:0] activated_data_e_act_neg_q_iexp_15 = _activated_data_e_act_neg_q_iexp_T_31; // @[Arithmetic.scala:95:38] wire [63:0] _activated_data_e_act_z_iexp_T_60 = {{32{activated_data_e_act_neg_q_iexp_15[31]}}, activated_data_e_act_neg_q_iexp_15} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38] wire [63:0] _activated_data_e_act_z_iexp_T_61 = _activated_data_e_act_z_iexp_T_60; // @[Arithmetic.scala:92:38] wire [47:0] _activated_data_e_act_z_iexp_T_62 = _activated_data_e_act_z_iexp_T_61[63:16]; // @[AccumulatorScale.scala:398:{42,54}] wire [47:0] _activated_data_e_act_z_iexp_T_63 = _activated_data_e_act_z_iexp_T_62; // @[AccumulatorScale.scala:398:{54,67}] wire [31:0] activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_495 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_497 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_499 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_501 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_503 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_505 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_507 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_509 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_511 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_513 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_515 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53] assign activated_data_e_act_z_iexp_15 = _activated_data_e_act_z_iexp_T_63[31:0]; // @[AccumulatorScale.scala:398:67] wire [31:0] _activated_data_e_act_z_iexp_saturated_T_527; // @[AccumulatorScale.scala:400:28] wire [31:0] activated_data_e_act_z_iexp_saturated_15; // @[AccumulatorScale.scala:399:32] wire [31:0] _activated_data_e_act_T_506 = activated_data_e_act_z_iexp_saturated_15; // @[AccumulatorScale.scala:399:32, :405:48] wire _activated_data_e_act_z_iexp_saturated_T_496 = _activated_data_e_act_z_iexp_saturated_T_495[5]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_498 = _activated_data_e_act_z_iexp_saturated_T_497[6]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_500 = _activated_data_e_act_z_iexp_saturated_T_499[7]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_502 = _activated_data_e_act_z_iexp_saturated_T_501[8]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_504 = _activated_data_e_act_z_iexp_saturated_T_503[9]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_506 = _activated_data_e_act_z_iexp_saturated_T_505[10]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_508 = _activated_data_e_act_z_iexp_saturated_T_507[11]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_510 = _activated_data_e_act_z_iexp_saturated_T_509[12]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_512 = _activated_data_e_act_z_iexp_saturated_T_511[13]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_514 = _activated_data_e_act_z_iexp_saturated_T_513[14]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_516 = _activated_data_e_act_z_iexp_saturated_T_515[15]; // @[AccumulatorScale.scala:400:{53,59}] wire _activated_data_e_act_z_iexp_saturated_T_517 = _activated_data_e_act_z_iexp_saturated_T_496 \| _activated_data_e_act_z_iexp_saturated_T_498; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_518 = _activated_data_e_act_z_iexp_saturated_T_517 \| _activated_data_e_act_z_iexp_saturated_T_500; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_519 = _activated_data_e_act_z_iexp_saturated_T_518 \| _activated_data_e_act_z_iexp_saturated_T_502; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_520 = _activated_data_e_act_z_iexp_saturated_T_519 \| _activated_data_e_act_z_iexp_saturated_T_504; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_521 = _activated_data_e_act_z_iexp_saturated_T_520 \| _activated_data_e_act_z_iexp_saturated_T_506; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_522 = _activated_data_e_act_z_iexp_saturated_T_521 \| _activated_data_e_act_z_iexp_saturated_T_508; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_523 = _activated_data_e_act_z_iexp_saturated_T_522 \| _activated_data_e_act_z_iexp_saturated_T_510; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_524 = _activated_data_e_act_z_iexp_saturated_T_523 \| _activated_data_e_act_z_iexp_saturated_T_512; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_525 = _activated_data_e_act_z_iexp_saturated_T_524 \| _activated_data_e_act_z_iexp_saturated_T_514; // @[AccumulatorScale.scala:400:{59,73}] wire _activated_data_e_act_z_iexp_saturated_T_526 = _activated_data_e_act_z_iexp_saturated_T_525 \| _activated_data_e_act_z_iexp_saturated_T_516; // @[AccumulatorScale.scala:400:{59,73}] assign _activated_data_e_act_z_iexp_saturated_T_527 = _activated_data_e_act_z_iexp_saturated_T_526 ? 32'h20 : activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:{28,73}] assign activated_data_e_act_z_iexp_saturated_15 = _activated_data_e_act_z_iexp_saturated_T_527; // @[AccumulatorScale.scala:399:32, :400:28] wire [63:0] _activated_data_e_act_qp_iexp_T_75 = {{32{activated_data_e_act_z_iexp_15[31]}}, activated_data_e_act_z_iexp_15} * _GEN_11; // @[Arithmetic.scala:93:49] wire [64:0] _activated_data_e_act_qp_iexp_T_76 = {_activated_data_e_act_qp_iexp_T_75[63], _activated_data_e_act_qp_iexp_T_75} + {{33{_activated_data_e_act_T_504[31]}}, _activated_data_e_act_T_504}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42] wire [63:0] _activated_data_e_act_qp_iexp_T_77 = _activated_data_e_act_qp_iexp_T_76[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_qp_iexp_T_78 = _activated_data_e_act_qp_iexp_T_77; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_qp_iexp_T_79 = _activated_data_e_act_qp_iexp_T_78[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_qp_iexp_15 = _activated_data_e_act_qp_iexp_T_79; // @[Arithmetic.scala:114:{15,33}] wire [32:0] _GEN_72 = {activated_data_e_act_qp_iexp_15[31], activated_data_e_act_qp_iexp_15} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42] wire [32:0] _activated_data_e_act_q_poly_iexp_T_165; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_165 = _GEN_72; // @[Arithmetic.scala:94:38] wire [32:0] _activated_data_e_act_q_poly_iexp_T_168; // @[Arithmetic.scala:94:38] assign _activated_data_e_act_q_poly_iexp_T_168 = _GEN_72; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_166 = _activated_data_e_act_q_poly_iexp_T_165[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_167 = _activated_data_e_act_q_poly_iexp_T_166; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_169 = _activated_data_e_act_q_poly_iexp_T_168[31:0]; // @[Arithmetic.scala:94:38] wire [31:0] _activated_data_e_act_q_poly_iexp_T_170 = _activated_data_e_act_q_poly_iexp_T_169; // @[Arithmetic.scala:94:38] wire [63:0] _activated_data_e_act_q_poly_iexp_T_171 = {{32{_activated_data_e_act_q_poly_iexp_T_167[31]}}, _activated_data_e_act_q_poly_iexp_T_167} * {{32{_activated_data_e_act_q_poly_iexp_T_170[31]}}, _activated_data_e_act_q_poly_iexp_T_170}; // @[Arithmetic.scala:93:49, :94:38] wire [64:0] _activated_data_e_act_q_poly_iexp_T_172 = {_activated_data_e_act_q_poly_iexp_T_171[63], _activated_data_e_act_q_poly_iexp_T_171} + _GEN_7; // @[Arithmetic.scala:93:{49,54}] wire [63:0] _activated_data_e_act_q_poly_iexp_T_173 = _activated_data_e_act_q_poly_iexp_T_172[63:0]; // @[Arithmetic.scala:93:54] wire [63:0] _activated_data_e_act_q_poly_iexp_T_174 = _activated_data_e_act_q_poly_iexp_T_173; // @[Arithmetic.scala:93:54] wire [31:0] _activated_data_e_act_q_poly_iexp_T_175 = _activated_data_e_act_q_poly_iexp_T_174[31:0]; // @[Arithmetic.scala:93:54, :114:15] wire [31:0] activated_data_e_act_q_poly_iexp_15 = _activated_data_e_act_q_poly_iexp_T_175; // @[Arithmetic.scala:114:{15,33}] wire [31:0] _activated_data_e_act_T_505 = activated_data_e_act_q_poly_iexp_15; // @[Arithmetic.scala:114:33] wire [31:0] _activated_data_e_act_T_507 = _activated_data_e_act_T_505 >> _activated_data_e_act_T_506; // @[AccumulatorScale.scala:405:{18,30,48}] wire [31:0] _activated_data_e_act_T_508 = _activated_data_e_act_T_507; // @[AccumulatorScale.scala:405:{30,65}] wire [31:0] _activated_data_e_act_WIRE_15 = _activated_data_e_act_T_508; // @[AccumulatorScale.scala:405:65] wire [31:0] _activated_data_e_act_T_510 = _activated_data_e_act_T_509; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_act_T_511 = _activated_data_e_act_T_510; // @[Mux.scala:126:16] wire [31:0] activated_data_e_act_15 = _activated_data_e_act_T_481 ? _activated_data_e_act_T_483 : _activated_data_e_act_T_511; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_15 = activated_data_e_act_15; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_173_bits = _activated_data_e_scaled_T_172_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_WIRE_78 = _activated_data_e_scaled_T_173_bits; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_scaled_T_174; // @[AccumulatorScale.scala:132:18] assign _activated_data_e_scaled_T_174 = _activated_data_e_scaled_WIRE_78; // @[AccumulatorScale.scala:132:18] wire [31:0] _activated_data_e_scaled_WIRE_77_bits = _activated_data_e_scaled_T_174; // @[AccumulatorScale.scala:132:18] wire activated_data_e_scaled_f_rec_rawIn_sign_15 = _activated_data_e_scaled_WIRE_77_bits[31]; // @[rawFloatFromFN.scala:44:18] wire activated_data_e_scaled_f_rec_rawIn_15_sign = activated_data_e_scaled_f_rec_rawIn_sign_15; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_15 = _activated_data_e_scaled_WIRE_77_bits[30:23]; // @[rawFloatFromFN.scala:45:19] wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_15 = _activated_data_e_scaled_WIRE_77_bits[22:0]; // @[rawFloatFromFN.scala:46:21] wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 = activated_data_e_scaled_f_rec_rawIn_expIn_15 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15 = activated_data_e_scaled_f_rec_rawIn_fractIn_15 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_660 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[0]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_661 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[1]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_662 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[2]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_663 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[3]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_664 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[4]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_665 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[5]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_666 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[6]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_667 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[7]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_668 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[8]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_669 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[9]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_670 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[10]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_671 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[11]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_672 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[12]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_673 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[13]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_674 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[14]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_675 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[15]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_676 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[16]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_677 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[17]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_678 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[18]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_679 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[19]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_680 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[20]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_681 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[21]; // @[rawFloatFromFN.scala:46:21] wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_682 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_683 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_661 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_684 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_662 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_683; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_685 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_663 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_684; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_686 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_664 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_685; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_687 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_665 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_686; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_688 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_666 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_687; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_689 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_667 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_688; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_690 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_668 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_689; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_691 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_669 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_690; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_692 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_670 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_691; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_693 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_671 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_692; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_694 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_672 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_693; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_695 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_673 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_694; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_696 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_674 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_695; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_697 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_675 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_696; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_698 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_676 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_697; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_699 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_677 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_698; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_700 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_678 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_699; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_701 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_679 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_700; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_702 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_680 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_701; // @[Mux.scala:50:70] wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_703 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_681 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_702; // @[Mux.scala:50:70] wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_15 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_682 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_703; // @[Mux.scala:50:70] wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_30 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_15} << activated_data_e_scaled_f_rec_rawIn_normDist_15; // @[Mux.scala:50:70] wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_31 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_30[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_15 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_31, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_75 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_15}; // @[Mux.scala:50:70] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_76 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_75 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_15}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_77 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_78 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_77}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_79 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_76} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_78}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_15 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_79[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_30 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_15; // @[rawFloatFromFN.scala:57:9, :68:28] wire activated_data_e_scaled_f_rec_rawIn_isZero_15 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire activated_data_e_scaled_f_rec_rawIn_15_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_15 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_15[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire activated_data_e_scaled_f_rec_rawIn_isSpecial_15 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_15; // @[rawFloatFromFN.scala:61:{32,57}] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:64:28] wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:65:28] wire _activated_data_e_scaled_f_rec_T_122 = activated_data_e_scaled_f_rec_rawIn_15_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:68:42] wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:70:27] wire activated_data_e_scaled_f_rec_rawIn_15_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] activated_data_e_scaled_f_rec_rawIn_15_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] activated_data_e_scaled_f_rec_rawIn_15_sig; // @[rawFloatFromFN.scala:63:19] wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_30 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :64:31] assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_31 = activated_data_e_scaled_f_rec_rawIn_isSpecial_15 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_30; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign activated_data_e_scaled_f_rec_rawIn_15_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:63:19, :64:28] assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_15 = activated_data_e_scaled_f_rec_rawIn_isSpecial_15 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign activated_data_e_scaled_f_rec_rawIn_15_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:63:19, :65:28] assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_31 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_30}; // @[rawFloatFromFN.scala:68:{28,42}] assign activated_data_e_scaled_f_rec_rawIn_15_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:63:19, :68:42] wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_60 = ~activated_data_e_scaled_f_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_61 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_60}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_62 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_15 : activated_data_e_scaled_f_rec_rawIn_fractIn_15; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_63 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_61, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_62}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign activated_data_e_scaled_f_rec_rawIn_15_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _activated_data_e_scaled_f_rec_T_120 = activated_data_e_scaled_f_rec_rawIn_15_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _activated_data_e_scaled_f_rec_T_121 = activated_data_e_scaled_f_rec_rawIn_15_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_120; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _activated_data_e_scaled_f_rec_T_123 = {_activated_data_e_scaled_f_rec_T_121[2:1], _activated_data_e_scaled_f_rec_T_121[0] \| _activated_data_e_scaled_f_rec_T_122}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _activated_data_e_scaled_f_rec_T_124 = {activated_data_e_scaled_f_rec_rawIn_15_sign, _activated_data_e_scaled_f_rec_T_123}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _activated_data_e_scaled_f_rec_T_125 = activated_data_e_scaled_f_rec_rawIn_15_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _activated_data_e_scaled_f_rec_T_126 = {_activated_data_e_scaled_f_rec_T_124, _activated_data_e_scaled_f_rec_T_125}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _activated_data_e_scaled_f_rec_T_127 = activated_data_e_scaled_f_rec_rawIn_15_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] activated_data_e_scaled_f_rec_15 = {_activated_data_e_scaled_f_rec_T_126, _activated_data_e_scaled_f_rec_T_127}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_15 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_15; // @[Configs.scala:120:41] wire activated_data_e_scaled_overflow_15 = _activated_data_e_scaled_rec_fn_to_in_15_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57] wire [8:0] activated_data_e_scaled_sign_exp_15 = _activated_data_e_scaled_muladder_15_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _activated_data_e_scaled_sign_isZero_T_15 = activated_data_e_scaled_sign_exp_15[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire activated_data_e_scaled_sign_isZero_15 = _activated_data_e_scaled_sign_isZero_T_15 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire activated_data_e_scaled_sign_out_15_isZero = activated_data_e_scaled_sign_isZero_15; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_15 = activated_data_e_scaled_sign_exp_15[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire activated_data_e_scaled_sign_isSpecial_15 = &_activated_data_e_scaled_sign_isSpecial_T_15; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _activated_data_e_scaled_sign_out_isNaN_T_31; // @[rawFloatFromRecFN.scala:56:33] wire _activated_data_e_scaled_sign_out_isInf_T_47; // @[rawFloatFromRecFN.scala:57:33] wire _activated_data_e_scaled_sign_out_sign_T_15; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_15; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _activated_data_e_scaled_sign_out_sig_T_63; // @[rawFloatFromRecFN.scala:61:44] wire activated_data_e_scaled_sign_out_15_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_15_isInf; // @[rawFloatFromRecFN.scala:55:23] wire activated_data_e_scaled_sign_out_15_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] activated_data_e_scaled_sign_out_15_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] activated_data_e_scaled_sign_out_15_sig; // @[rawFloatFromRecFN.scala:55:23] wire _activated_data_e_scaled_sign_out_isNaN_T_30 = activated_data_e_scaled_sign_exp_15[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _activated_data_e_scaled_sign_out_isInf_T_45 = activated_data_e_scaled_sign_exp_15[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _activated_data_e_scaled_sign_out_isNaN_T_31 = activated_data_e_scaled_sign_isSpecial_15 & _activated_data_e_scaled_sign_out_isNaN_T_30; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign activated_data_e_scaled_sign_out_15_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_31; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _activated_data_e_scaled_sign_out_isInf_T_46 = ~_activated_data_e_scaled_sign_out_isInf_T_45; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _activated_data_e_scaled_sign_out_isInf_T_47 = activated_data_e_scaled_sign_isSpecial_15 & _activated_data_e_scaled_sign_out_isInf_T_46; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign activated_data_e_scaled_sign_out_15_isInf = _activated_data_e_scaled_sign_out_isInf_T_47; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _activated_data_e_scaled_sign_out_sign_T_15 = _activated_data_e_scaled_muladder_15_io_out[32]; // @[rawFloatFromRecFN.scala:59:25] assign activated_data_e_scaled_sign_out_15_sign = _activated_data_e_scaled_sign_out_sign_T_15; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _activated_data_e_scaled_sign_out_sExp_T_15 = {1'h0, activated_data_e_scaled_sign_exp_15}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign activated_data_e_scaled_sign_out_15_sExp = _activated_data_e_scaled_sign_out_sExp_T_15; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _activated_data_e_scaled_sign_out_sig_T_60 = ~activated_data_e_scaled_sign_isZero_15; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _activated_data_e_scaled_sign_out_sig_T_61 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_60}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _activated_data_e_scaled_sign_out_sig_T_62 = _activated_data_e_scaled_muladder_15_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _activated_data_e_scaled_sign_out_sig_T_63 = {_activated_data_e_scaled_sign_out_sig_T_61, _activated_data_e_scaled_sign_out_sig_T_62}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign activated_data_e_scaled_sign_out_15_sig = _activated_data_e_scaled_sign_out_sig_T_63; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [31:0] activated_data_e_scaled_sat_15 = activated_data_e_scaled_sign_out_15_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] _activated_data_e_scaled_T_175; // @[Configs.scala:146:56] wire [31:0] _activated_data_e_scaled_WIRE_79 = _activated_data_e_scaled_T_175; // @[Configs.scala:146:56] wire [31:0] activated_data_e_scaled_15 = activated_data_e_scaled_overflow_15 ? activated_data_e_scaled_sat_15 : _activated_data_e_scaled_WIRE_79; // @[Configs.scala:140:57, :144:22, :146:{12,56}] wire _activated_data_e_clipped_T_75 = $signed(activated_data_e_scaled_15) > 32'sh7F; // @[Configs.scala:146:12] wire _activated_data_e_clipped_T_76 = $signed(activated_data_e_scaled_15) < -32'sh80; // @[Configs.scala:146:12] wire [31:0] _activated_data_e_clipped_T_77 = _activated_data_e_clipped_T_76 ? 32'hFFFFFF80 : activated_data_e_scaled_15; // @[Mux.scala:126:16] wire [31:0] _activated_data_e_clipped_T_78 = _activated_data_e_clipped_T_75 ? 32'h7F : _activated_data_e_clipped_T_77; // @[Mux.scala:126:16] wire [7:0] _activated_data_e_clipped_T_79 = _activated_data_e_clipped_T_78[7:0]; // @[Mux.scala:126:16] wire [7:0] activated_data_e_clipped_15 = _activated_data_e_clipped_T_79; // @[Arithmetic.scala:125:{81,99}] wire [7:0] _activated_data_WIRE_15_0 = activated_data_e_clipped_15; // @[Arithmetic.scala:125:99] wire [7:0] activated_data_15_0 = _activated_data_WIRE_15_0; // @[AccumulatorScale.scala:116:{33,55}] assign io_in_ready_0 = in_ready; // @[AccumulatorScale.scala:88:7, :139:18] wire [31:0] in_bits_resp_data_0_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_1_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_2_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_3_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_4_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_5_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_6_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_7_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_8_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_9_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_10_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_11_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_12_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_13_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_14_0; // @[AccumulatorScale.scala:139:18] wire [31:0] in_bits_resp_data_15_0; // @[AccumulatorScale.scala:139:18] assign in_bits_resp_data_0_0 = {{24{activated_data_0_0[7]}}, activated_data_0_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_1_0 = {{24{activated_data_1_0[7]}}, activated_data_1_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_2_0 = {{24{activated_data_2_0[7]}}, activated_data_2_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_3_0 = {{24{activated_data_3_0[7]}}, activated_data_3_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_4_0 = {{24{activated_data_4_0[7]}}, activated_data_4_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_5_0 = {{24{activated_data_5_0[7]}}, activated_data_5_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_6_0 = {{24{activated_data_6_0[7]}}, activated_data_6_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_7_0 = {{24{activated_data_7_0[7]}}, activated_data_7_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_8_0 = {{24{activated_data_8_0[7]}}, activated_data_8_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_9_0 = {{24{activated_data_9_0[7]}}, activated_data_9_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_10_0 = {{24{activated_data_10_0[7]}}, activated_data_10_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_11_0 = {{24{activated_data_11_0[7]}}, activated_data_11_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_12_0 = {{24{activated_data_12_0[7]}}, activated_data_12_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_13_0 = {{24{activated_data_13_0[7]}}, activated_data_13_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_14_0 = {{24{activated_data_14_0[7]}}, activated_data_14_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign in_bits_resp_data_15_0 = {{24{activated_data_15_0[7]}}, activated_data_15_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23] assign out_bits_data_0_0 = _pipe_out_p_io_out_bits_resp_data_0_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_1_0 = _pipe_out_p_io_out_bits_resp_data_1_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_2_0 = _pipe_out_p_io_out_bits_resp_data_2_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_3_0 = _pipe_out_p_io_out_bits_resp_data_3_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_4_0 = _pipe_out_p_io_out_bits_resp_data_4_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_5_0 = _pipe_out_p_io_out_bits_resp_data_5_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_6_0 = _pipe_out_p_io_out_bits_resp_data_6_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_7_0 = _pipe_out_p_io_out_bits_resp_data_7_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_8_0 = _pipe_out_p_io_out_bits_resp_data_8_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_9_0 = _pipe_out_p_io_out_bits_resp_data_9_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_10_0 = _pipe_out_p_io_out_bits_resp_data_10_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_11_0 = _pipe_out_p_io_out_bits_resp_data_11_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_12_0 = _pipe_out_p_io_out_bits_resp_data_12_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_13_0 = _pipe_out_p_io_out_bits_resp_data_13_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_14_0 = _pipe_out_p_io_out_bits_resp_data_14_0[7:0]; // @[Pipeline.scala:75:19] assign out_bits_data_15_0 = _pipe_out_p_io_out_bits_resp_data_15_0[7:0]; // @[Pipeline.scala:75:19] INToRecFN_i32_e8_s24 activated_data_e_scaled_in_to_rec_fn ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_4 activated_data_e_scaled_muladder ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32 activated_data_e_scaled_rec_fn_to_in ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_10), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_1 activated_data_e_scaled_in_to_rec_fn_1 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_1), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_1_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_5 activated_data_e_scaled_muladder_1 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_1_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_1), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_1_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_1 activated_data_e_scaled_rec_fn_to_in_1 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_1_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_21), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_1_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_2 activated_data_e_scaled_in_to_rec_fn_2 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_2), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_2_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_6 activated_data_e_scaled_muladder_2 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_2_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_2), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_2_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_2 activated_data_e_scaled_rec_fn_to_in_2 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_2_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_32), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_2_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_3 activated_data_e_scaled_in_to_rec_fn_3 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_3), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_3_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_7 activated_data_e_scaled_muladder_3 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_3_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_3), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_3_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_3 activated_data_e_scaled_rec_fn_to_in_3 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_3_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_43), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_3_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_4 activated_data_e_scaled_in_to_rec_fn_4 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_4), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_4_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_8 activated_data_e_scaled_muladder_4 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_4_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_4), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_4_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_4 activated_data_e_scaled_rec_fn_to_in_4 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_4_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_54), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_4_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_5 activated_data_e_scaled_in_to_rec_fn_5 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_5), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_5_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_9 activated_data_e_scaled_muladder_5 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_5_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_5), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_5_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_5 activated_data_e_scaled_rec_fn_to_in_5 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_5_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_65), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_5_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_6 activated_data_e_scaled_in_to_rec_fn_6 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_6), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_6_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_10 activated_data_e_scaled_muladder_6 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_6_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_6), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_6_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_6 activated_data_e_scaled_rec_fn_to_in_6 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_6_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_76), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_6_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_7 activated_data_e_scaled_in_to_rec_fn_7 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_7), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_7_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_11 activated_data_e_scaled_muladder_7 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_7_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_7), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_7_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_7 activated_data_e_scaled_rec_fn_to_in_7 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_7_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_87), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_7_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_8 activated_data_e_scaled_in_to_rec_fn_8 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_8), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_8_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_12 activated_data_e_scaled_muladder_8 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_8_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_8), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_8_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_8 activated_data_e_scaled_rec_fn_to_in_8 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_8_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_98), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_8_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_9 activated_data_e_scaled_in_to_rec_fn_9 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_9), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_9_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_13 activated_data_e_scaled_muladder_9 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_9_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_9), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_9_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_9 activated_data_e_scaled_rec_fn_to_in_9 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_9_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_109), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_9_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_10 activated_data_e_scaled_in_to_rec_fn_10 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_10), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_10_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_14 activated_data_e_scaled_muladder_10 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_10_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_10), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_10_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_10 activated_data_e_scaled_rec_fn_to_in_10 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_10_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_120), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_10_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_11 activated_data_e_scaled_in_to_rec_fn_11 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_11), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_11_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_15 activated_data_e_scaled_muladder_11 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_11_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_11), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_11_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_11 activated_data_e_scaled_rec_fn_to_in_11 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_11_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_131), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_11_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_12 activated_data_e_scaled_in_to_rec_fn_12 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_12), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_12_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_16 activated_data_e_scaled_muladder_12 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_12_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_12), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_12_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_12 activated_data_e_scaled_rec_fn_to_in_12 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_12_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_142), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_12_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_13 activated_data_e_scaled_in_to_rec_fn_13 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_13), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_13_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_17 activated_data_e_scaled_muladder_13 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_13_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_13), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_13_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_13 activated_data_e_scaled_rec_fn_to_in_13 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_13_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_153), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_13_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_14 activated_data_e_scaled_in_to_rec_fn_14 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_14), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_14_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_18 activated_data_e_scaled_muladder_14 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_14_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_14), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_14_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_14 activated_data_e_scaled_rec_fn_to_in_14 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_14_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_164), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_14_io_intExceptionFlags) ); // @[Configs.scala:135:34] INToRecFN_i32_e8_s24_15 activated_data_e_scaled_in_to_rec_fn_15 ( // @[Configs.scala:118:34] .io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_15), // @[Configs.scala:120:41] .io_out (_activated_data_e_scaled_in_to_rec_fn_15_io_out) ); // @[Configs.scala:118:34] MulAddRecFN_e8_s24_19 activated_data_e_scaled_muladder_15 ( // @[Configs.scala:126:30] .io_a (_activated_data_e_scaled_in_to_rec_fn_15_io_out), // @[Configs.scala:118:34] .io_b (activated_data_e_scaled_f_rec_15), // @[recFNFromFN.scala:50:41] .io_out (_activated_data_e_scaled_muladder_15_io_out) ); // @[Configs.scala:126:30] RecFNToIN_e8_s24_i32_15 activated_data_e_scaled_rec_fn_to_in_15 ( // @[Configs.scala:135:34] .clock (clock), .reset (reset), .io_in (_activated_data_e_scaled_muladder_15_io_out), // @[Configs.scala:126:30] .io_out (_activated_data_e_scaled_T_175), .io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_15_io_intExceptionFlags) ); // @[Configs.scala:135:34] Pipeline_9 pipe_out_p ( // @[Pipeline.scala:75:19] .clock (clock), .reset (reset), .io_in_ready (in_ready), .io_in_valid (in_valid), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_0_0 (in_bits_resp_data_0_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_1_0 (in_bits_resp_data_1_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_2_0 (in_bits_resp_data_2_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_3_0 (in_bits_resp_data_3_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_4_0 (in_bits_resp_data_4_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_5_0 (in_bits_resp_data_5_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_6_0 (in_bits_resp_data_6_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_7_0 (in_bits_resp_data_7_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_8_0 (in_bits_resp_data_8_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_9_0 (in_bits_resp_data_9_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_10_0 (in_bits_resp_data_10_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_11_0 (in_bits_resp_data_11_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_12_0 (in_bits_resp_data_12_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_13_0 (in_bits_resp_data_13_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_14_0 (in_bits_resp_data_14_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_data_15_0 (in_bits_resp_data_15_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_fromDMA (in_bits_resp_fromDMA), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_scale_bits (in_bits_resp_scale_bits), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_igelu_qb (in_bits_resp_igelu_qb), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_igelu_qc (in_bits_resp_igelu_qc), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_iexp_qln2 (in_bits_resp_iexp_qln2), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_iexp_qln2_inv (in_bits_resp_iexp_qln2_inv), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_act (in_bits_resp_act), // @[AccumulatorScale.scala:139:18] .io_in_bits_resp_acc_bank_id (in_bits_resp_acc_bank_id), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_0_0 (in_bits_full_data_0_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_1_0 (in_bits_full_data_1_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_2_0 (in_bits_full_data_2_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_3_0 (in_bits_full_data_3_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_4_0 (in_bits_full_data_4_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_5_0 (in_bits_full_data_5_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_6_0 (in_bits_full_data_6_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_7_0 (in_bits_full_data_7_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_8_0 (in_bits_full_data_8_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_9_0 (in_bits_full_data_9_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_10_0 (in_bits_full_data_10_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_11_0 (in_bits_full_data_11_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_12_0 (in_bits_full_data_12_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_13_0 (in_bits_full_data_13_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_14_0 (in_bits_full_data_14_0), // @[AccumulatorScale.scala:139:18] .io_in_bits_full_data_15_0 (in_bits_full_data_15_0), // @[AccumulatorScale.scala:139:18] .io_out_ready (out_ready), // @[AccumulatorScale.scala:104:17] .io_out_valid (out_valid), .io_out_bits_resp_data_0_0 (_pipe_out_p_io_out_bits_resp_data_0_0), .io_out_bits_resp_data_1_0 (_pipe_out_p_io_out_bits_resp_data_1_0), .io_out_bits_resp_data_2_0 (_pipe_out_p_io_out_bits_resp_data_2_0), .io_out_bits_resp_data_3_0 (_pipe_out_p_io_out_bits_resp_data_3_0), .io_out_bits_resp_data_4_0 (_pipe_out_p_io_out_bits_resp_data_4_0), .io_out_bits_resp_data_5_0 (_pipe_out_p_io_out_bits_resp_data_5_0), .io_out_bits_resp_data_6_0 (_pipe_out_p_io_out_bits_resp_data_6_0), .io_out_bits_resp_data_7_0 (_pipe_out_p_io_out_bits_resp_data_7_0), .io_out_bits_resp_data_8_0 (_pipe_out_p_io_out_bits_resp_data_8_0), .io_out_bits_resp_data_9_0 (_pipe_out_p_io_out_bits_resp_data_9_0), .io_out_bits_resp_data_10_0 (_pipe_out_p_io_out_bits_resp_data_10_0), .io_out_bits_resp_data_11_0 (_pipe_out_p_io_out_bits_resp_data_11_0), .io_out_bits_resp_data_12_0 (_pipe_out_p_io_out_bits_resp_data_12_0), .io_out_bits_resp_data_13_0 (_pipe_out_p_io_out_bits_resp_data_13_0), .io_out_bits_resp_data_14_0 (_pipe_out_p_io_out_bits_resp_data_14_0), .io_out_bits_resp_data_15_0 (_pipe_out_p_io_out_bits_resp_data_15_0), .io_out_bits_resp_fromDMA (out_bits_fromDMA), .io_out_bits_resp_acc_bank_id (out_bits_acc_bank_id), .io_out_bits_full_data_0_0 (out_bits_full_data_0_0), .io_out_bits_full_data_1_0 (out_bits_full_data_1_0), .io_out_bits_full_data_2_0 (out_bits_full_data_2_0), .io_out_bits_full_data_3_0 (out_bits_full_data_3_0), .io_out_bits_full_data_4_0 (out_bits_full_data_4_0), .io_out_bits_full_data_5_0 (out_bits_full_data_5_0), .io_out_bits_full_data_6_0 (out_bits_full_data_6_0), .io_out_bits_full_data_7_0 (out_bits_full_data_7_0), .io_out_bits_full_data_8_0 (out_bits_full_data_8_0), .io_out_bits_full_data_9_0 (out_bits_full_data_9_0), .io_out_bits_full_data_10_0 (out_bits_full_data_10_0), .io_out_bits_full_data_11_0 (out_bits_full_data_11_0), .io_out_bits_full_data_12_0 (out_bits_full_data_12_0), .io_out_bits_full_data_13_0 (out_bits_full_data_13_0), .io_out_bits_full_data_14_0 (out_bits_full_data_14_0), .io_out_bits_full_data_15_0 (out_bits_full_data_15_0) ); // @[Pipeline.scala:75:19] assign io_in_ready = io_in_ready_0; // @[AccumulatorScale.scala:88:7] assign io_out_valid = io_out_valid_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_0_0 = io_out_bits_full_data_0_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_1_0 = io_out_bits_full_data_1_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_2_0 = io_out_bits_full_data_2_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_3_0 = io_out_bits_full_data_3_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_4_0 = io_out_bits_full_data_4_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_5_0 = io_out_bits_full_data_5_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_6_0 = io_out_bits_full_data_6_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_7_0 = io_out_bits_full_data_7_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_8_0 = io_out_bits_full_data_8_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_9_0 = io_out_bits_full_data_9_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_10_0 = io_out_bits_full_data_10_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_11_0 = io_out_bits_full_data_11_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_12_0 = io_out_bits_full_data_12_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_13_0 = io_out_bits_full_data_13_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_14_0 = io_out_bits_full_data_14_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_full_data_15_0 = io_out_bits_full_data_15_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_0_0 = io_out_bits_data_0_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_1_0 = io_out_bits_data_1_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_2_0 = io_out_bits_data_2_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_3_0 = io_out_bits_data_3_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_4_0 = io_out_bits_data_4_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_5_0 = io_out_bits_data_5_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_6_0 = io_out_bits_data_6_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_7_0 = io_out_bits_data_7_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_8_0 = io_out_bits_data_8_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_9_0 = io_out_bits_data_9_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_10_0 = io_out_bits_data_10_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_11_0 = io_out_bits_data_11_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_12_0 = io_out_bits_data_12_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_13_0 = io_out_bits_data_13_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_14_0 = io_out_bits_data_14_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_data_15_0 = io_out_bits_data_15_0_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_acc_bank_id = io_out_bits_acc_bank_id_0; // @[AccumulatorScale.scala:88:7] assign io_out_bits_fromDMA = io_out_bits_fromDMA_0; // @[AccumulatorScale.scala:88:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus : output auto : { coupler_to_streamingPassthrough_tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_device_named_uart_0_control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst pbus_clock_groups of ClockGroupAggregator_pbus inst clockGroup of ClockGroup_1 inst fixedClockNode of FixedClockBroadcast_3 inst broadcast of BundleBridgeNexus_NoOutput_1 inst fixer of TLFIFOFixer_1 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s7k1z3u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_pbus_out_i1_o3_a29d64s7k1z3u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s7k1z3u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_pbus connect atomics.clock, childClock connect atomics.reset, childReset inst buffer_1 of TLBuffer_a29d64s7k1z3u_1 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bootaddressreg of TLInterconnectCoupler_pbus_to_bootaddressreg connect coupler_to_bootaddressreg.clock, childClock connect coupler_to_bootaddressreg.reset, childReset inst coupler_to_device_named_uart_0 of TLInterconnectCoupler_pbus_to_device_named_uart_0 connect coupler_to_device_named_uart_0.clock, childClock connect coupler_to_device_named_uart_0.reset, childReset inst coupler_to_streamingPassthrough of TLInterconnectCoupler_pbus_to_streamingPassthrough connect coupler_to_streamingPassthrough.clock, childClock connect coupler_to_streamingPassthrough.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_8 connect monitor.clock, childClock connect monitor.reset, childReset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect clockGroup.auto.in, pbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect coupler_to_bootaddressreg.auto.tl_in, out_xbar.auto.anon_out_0 connect coupler_to_device_named_uart_0.auto.tl_in, out_xbar.auto.anon_out_1 connect coupler_to_streamingPassthrough.auto.tl_in, out_xbar.auto.anon_out_2 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.d, nodeIn.d connect nodeIn.a.bits, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.bits connect nodeIn.a.valid, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.valid connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.ready, nodeIn.a.ready connect bus_xingIn, auto.bus_xing_in connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1 connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2 connect coupler_to_device_named_uart_0.auto.control_xing_out.d, auto.coupler_to_device_named_uart_0_control_xing_out.d connect auto.coupler_to_device_named_uart_0_control_xing_out.a.bits, coupler_to_device_named_uart_0.auto.control_xing_out.a.bits connect auto.coupler_to_device_named_uart_0_control_xing_out.a.valid, coupler_to_device_named_uart_0.auto.control_xing_out.a.valid connect coupler_to_device_named_uart_0.auto.control_xing_out.a.ready, auto.coupler_to_device_named_uart_0_control_xing_out.a.ready connect coupler_to_streamingPassthrough.auto.tl_out.d, auto.coupler_to_streamingPassthrough_tl_out.d connect auto.coupler_to_streamingPassthrough_tl_out.a.bits, coupler_to_streamingPassthrough.auto.tl_out.a.bits connect auto.coupler_to_streamingPassthrough_tl_out.a.valid, coupler_to_streamingPassthrough.auto.tl_out.a.valid connect coupler_to_streamingPassthrough.auto.tl_out.a.ready, auto.coupler_to_streamingPassthrough_tl_out.a.ready regreset bootAddrReg : UInt<64>, childClock, childReset, UInt<64>(0h80000000) node pad = or(bootAddrReg, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node bootAddrReg_lo_lo = cat(newBytes[1], newBytes[0]) node bootAddrReg_lo_hi = cat(newBytes[3], newBytes[2]) node bootAddrReg_lo = cat(bootAddrReg_lo_hi, bootAddrReg_lo_lo) node bootAddrReg_hi_lo = cat(newBytes[5], newBytes[4]) node bootAddrReg_hi_hi = cat(newBytes[7], newBytes[6]) node bootAddrReg_hi = cat(bootAddrReg_hi_hi, bootAddrReg_hi_lo) node _bootAddrReg_T = cat(bootAddrReg_hi, bootAddrReg_lo) connect bootAddrReg, _bootAddrReg_T wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[8] wire out_wivalid : UInt<1>[8] wire out_roready : UInt<1>[8] wire out_woready : UInt<1>[8] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready when out_f_woready : connect newBytes[0], _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_8 = bits(_out_T_7, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_9 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_1 when out_f_woready_1 : connect newBytes[1], _out_T_9 node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_12 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_8, UInt<8>(0h0)) node out_prepend = cat(oldBytes[1], _out_prepend_T) node _out_T_14 = or(out_prepend, UInt<16>(0h0)) node _out_T_15 = bits(_out_T_14, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_16 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_2 when out_f_woready_2 : connect newBytes[2], _out_T_16 node _out_T_17 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_18 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_19 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_15, UInt<16>(0h0)) node out_prepend_1 = cat(oldBytes[2], _out_prepend_T_1) node _out_T_21 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_22 = bits(_out_T_21, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_23 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_3 when out_f_woready_3 : connect newBytes[3], _out_T_23 node _out_T_24 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_25 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_26 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_27 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_22, UInt<24>(0h0)) node out_prepend_2 = cat(oldBytes[3], _out_prepend_T_2) node _out_T_28 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_29 = bits(_out_T_28, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 39, 32) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 39, 32) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 39, 32) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 39, 32) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_30 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_4 when out_f_woready_4 : connect newBytes[4], _out_T_30 node _out_T_31 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_29, UInt<32>(0h0)) node out_prepend_3 = cat(oldBytes[4], _out_prepend_T_3) node _out_T_35 = or(out_prepend_3, UInt<40>(0h0)) node _out_T_36 = bits(_out_T_35, 39, 0) node _out_rimask_T_5 = bits(out_frontMask, 47, 40) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 47, 40) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 47, 40) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 47, 40) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_37 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_5 when out_f_woready_5 : connect newBytes[5], _out_T_37 node _out_T_38 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_36, UInt<40>(0h0)) node out_prepend_4 = cat(oldBytes[5], _out_prepend_T_4) node _out_T_42 = or(out_prepend_4, UInt<48>(0h0)) node _out_T_43 = bits(_out_T_42, 47, 0) node _out_rimask_T_6 = bits(out_frontMask, 55, 48) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 55, 48) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 55, 48) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 55, 48) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_44 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_6 when out_f_woready_6 : connect newBytes[6], _out_T_44 node _out_T_45 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_46 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_47 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_48 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_43, UInt<48>(0h0)) node out_prepend_5 = cat(oldBytes[6], _out_prepend_T_5) node _out_T_49 = or(out_prepend_5, UInt<56>(0h0)) node _out_T_50 = bits(_out_T_49, 55, 0) node _out_rimask_T_7 = bits(out_frontMask, 63, 56) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 63, 56) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 63, 56) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 63, 56) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_51 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_7 when out_f_woready_7 : connect newBytes[7], _out_T_51 node _out_T_52 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_53 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_54 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_55 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_50, UInt<56>(0h0)) node out_prepend_6 = cat(oldBytes[7], _out_prepend_T_6) node _out_T_56 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_57 = bits(_out_T_56, 63, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_3 connect out_rivalid[6], _out_rifireMux_T_3 connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_4 connect out_wivalid[6], _out_wifireMux_T_4 connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_3 connect out_roready[6], _out_rofireMux_T_3 connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_4 connect out_woready[6], _out_wofireMux_T_4 connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<64>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_57 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset	module PeripheryBus_pbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_streamingPassthrough_tl_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_streamingPassthrough_tl_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_streamingPassthrough_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_streamingPassthrough_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_streamingPassthrough_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coupler_to_streamingPassthrough_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [13:0] auto_coupler_to_streamingPassthrough_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_streamingPassthrough_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_streamingPassthrough_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_streamingPassthrough_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_streamingPassthrough_tl_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_streamingPassthrough_tl_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_streamingPassthrough_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_streamingPassthrough_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coupler_to_streamingPassthrough_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_streamingPassthrough_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_woready_7; // @[RegisterRouter.scala:87:24] wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_param; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_size; // @[LazyScope.scala:98:27] wire [10:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_source; // @[LazyScope.scala:98:27] wire [12:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_fragmenter_anon_out_d_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _buffer_1_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_1_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [28:0] _buffer_1_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_1_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_1_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_d_ready; // @[Buffer.scala:75:28] wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [28:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_in_a_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_in_d_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_in_d_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_in_d_bits_source; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_in_d_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] reg [63:0] pad; // @[BootAddrReg.scala:27:34] wire in_bits_read = _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_1 = _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_address[11:3] == 9'h0; // @[RegisterRouter.scala:75:19, :87:24] wire valids_0 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire valids_1 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire valids_2 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire valids_3 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire valids_4 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire valids_5 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire valids_6 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire valids_7 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[7]; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_valid & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_d_ready & ~in_bits_read & _out_T_1; // @[RegisterRouter.scala:74:36, :87:24] wire [2:0] nodeIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] always @(posedge _fixedClockNode_auto_anon_out_0_clock) begin // @[ClockGroup.scala:115:114] if (_fixedClockNode_auto_anon_out_0_reset) // @[ClockGroup.scala:115:114] pad <= 64'h80000000; // @[BootAddrReg.scala:27:34] else if (valids_0 \| valids_1 \| valids_2 \| valids_3 \| valids_4 \| valids_5 \| valids_6 \| valids_7) // @[RegisterRouter.scala:87:24] pad <= {valids_7 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[63:56] : pad[63:56], valids_6 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[55:48] : pad[55:48], valids_5 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[47:40] : pad[47:40], valids_4 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[39:32] : pad[39:32], valids_3 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[31:24] : pad[31:24], valids_2 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[23:16] : pad[23:16], valids_1 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[15:8] : pad[15:8], valids_0 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[7:0] : pad[7:0]}; // @[BootAddrReg.scala:27:34] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module BundleBridgeNexus_NoOutput_10 : output auto : { } wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset	module BundleBridgeNexus_NoOutput_10(); // @[BundleBridgeNexus.scala:20:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_189 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_341 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_189( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_341 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLDToNoC_6 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, egress_id : UInt}}} inst q of Queue1_TLBundleD_a29d64s7k1z4u_1 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 5, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 5, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo_hi = cat(q.io.deq.bits.source, q.io.deq.bits.sink) node const_lo = cat(const_lo_hi, q.io.deq.bits.denied) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.source, UInt<7>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 6, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.source, 7) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<7>(0h7f)) node io_flit_bits_egress_id_requestOH_0 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) connect io.flit.bits.egress_id, UInt<1>(0h1) node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_sink_T = or(io.protocol.bits.sink, UInt<1>(0h0)) connect q.io.enq.bits.sink, _q_io_enq_bits_sink_T	module TLDToNoC_6( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [20:0] _tail_beats1_decode_T = 21'h3F << _q_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire [2:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0; // @[package.scala:243:{46,71,76}] reg [2:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 3'h1 \| tail_beats1 == 3'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 3'h0; // @[Edges.scala:229:27] tail_counter <= 3'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0) : head_counter - 3'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 3'h0 ? tail_beats1 : tail_counter - 3'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLAToNoC_7 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst q of Queue1_TLBundleA_a32d64s6k5z4c_7 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) node _head_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2) node head_beats1_opdata = eq(_head_beats1_opdata_T, UInt<1>(0h0)) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) node _tail_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2) node tail_beats1_opdata = eq(_tail_beats1_opdata_T, UInt<1>(0h0)) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body_hi = cat(q.io.deq.bits.mask, q.io.deq.bits.data) node body = cat(body_hi, q.io.deq.bits.corrupt) node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<33>(0h8c000000))) node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_5 = xor(q.io.deq.bits.address, UInt<17>(0h10000)) node _io_flit_bits_egress_id_requestOH_T_6 = cvt(_io_flit_bits_egress_id_requestOH_T_5) node _io_flit_bits_egress_id_requestOH_T_7 = and(_io_flit_bits_egress_id_requestOH_T_6, asSInt(UInt<33>(0h8c011000))) node _io_flit_bits_egress_id_requestOH_T_8 = asSInt(_io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = eq(_io_flit_bits_egress_id_requestOH_T_8, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_10 = xor(q.io.deq.bits.address, UInt<28>(0hc000000)) node _io_flit_bits_egress_id_requestOH_T_11 = cvt(_io_flit_bits_egress_id_requestOH_T_10) node _io_flit_bits_egress_id_requestOH_T_12 = and(_io_flit_bits_egress_id_requestOH_T_11, asSInt(UInt<33>(0h8c000000))) node _io_flit_bits_egress_id_requestOH_T_13 = asSInt(_io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = eq(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_15 = or(_io_flit_bits_egress_id_requestOH_T_4, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_T_16 = or(_io_flit_bits_egress_id_requestOH_T_15, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16) node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<28>(0h8000000)) node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18) node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<33>(0h8c0100c0))) node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20) node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_23 = xor(q.io.deq.bits.address, UInt<32>(0h80000000)) node _io_flit_bits_egress_id_requestOH_T_24 = cvt(_io_flit_bits_egress_id_requestOH_T_23) node _io_flit_bits_egress_id_requestOH_T_25 = and(_io_flit_bits_egress_id_requestOH_T_24, asSInt(UInt<33>(0h800000c0))) node _io_flit_bits_egress_id_requestOH_T_26 = asSInt(_io_flit_bits_egress_id_requestOH_T_25) node _io_flit_bits_egress_id_requestOH_T_27 = eq(_io_flit_bits_egress_id_requestOH_T_26, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_28 = or(_io_flit_bits_egress_id_requestOH_T_22, _io_flit_bits_egress_id_requestOH_T_27) node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28) node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_requestOH_T_30 = xor(q.io.deq.bits.address, UInt<28>(0h8000040)) node _io_flit_bits_egress_id_requestOH_T_31 = cvt(_io_flit_bits_egress_id_requestOH_T_30) node _io_flit_bits_egress_id_requestOH_T_32 = and(_io_flit_bits_egress_id_requestOH_T_31, asSInt(UInt<33>(0h8c0100c0))) node _io_flit_bits_egress_id_requestOH_T_33 = asSInt(_io_flit_bits_egress_id_requestOH_T_32) node _io_flit_bits_egress_id_requestOH_T_34 = eq(_io_flit_bits_egress_id_requestOH_T_33, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_35 = xor(q.io.deq.bits.address, UInt<32>(0h80000040)) node _io_flit_bits_egress_id_requestOH_T_36 = cvt(_io_flit_bits_egress_id_requestOH_T_35) node _io_flit_bits_egress_id_requestOH_T_37 = and(_io_flit_bits_egress_id_requestOH_T_36, asSInt(UInt<33>(0h800000c0))) node _io_flit_bits_egress_id_requestOH_T_38 = asSInt(_io_flit_bits_egress_id_requestOH_T_37) node _io_flit_bits_egress_id_requestOH_T_39 = eq(_io_flit_bits_egress_id_requestOH_T_38, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_40 = or(_io_flit_bits_egress_id_requestOH_T_34, _io_flit_bits_egress_id_requestOH_T_39) node _io_flit_bits_egress_id_requestOH_T_41 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_40) node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_41) node _io_flit_bits_egress_id_requestOH_T_42 = xor(q.io.deq.bits.address, UInt<28>(0h8000080)) node _io_flit_bits_egress_id_requestOH_T_43 = cvt(_io_flit_bits_egress_id_requestOH_T_42) node _io_flit_bits_egress_id_requestOH_T_44 = and(_io_flit_bits_egress_id_requestOH_T_43, asSInt(UInt<33>(0h8c0100c0))) node _io_flit_bits_egress_id_requestOH_T_45 = asSInt(_io_flit_bits_egress_id_requestOH_T_44) node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_47 = xor(q.io.deq.bits.address, UInt<32>(0h80000080)) node _io_flit_bits_egress_id_requestOH_T_48 = cvt(_io_flit_bits_egress_id_requestOH_T_47) node _io_flit_bits_egress_id_requestOH_T_49 = and(_io_flit_bits_egress_id_requestOH_T_48, asSInt(UInt<33>(0h800000c0))) node _io_flit_bits_egress_id_requestOH_T_50 = asSInt(_io_flit_bits_egress_id_requestOH_T_49) node _io_flit_bits_egress_id_requestOH_T_51 = eq(_io_flit_bits_egress_id_requestOH_T_50, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_52 = or(_io_flit_bits_egress_id_requestOH_T_46, _io_flit_bits_egress_id_requestOH_T_51) node _io_flit_bits_egress_id_requestOH_T_53 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_52) node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_53) node _io_flit_bits_egress_id_requestOH_T_54 = xor(q.io.deq.bits.address, UInt<28>(0h80000c0)) node _io_flit_bits_egress_id_requestOH_T_55 = cvt(_io_flit_bits_egress_id_requestOH_T_54) node _io_flit_bits_egress_id_requestOH_T_56 = and(_io_flit_bits_egress_id_requestOH_T_55, asSInt(UInt<33>(0h8c0100c0))) node _io_flit_bits_egress_id_requestOH_T_57 = asSInt(_io_flit_bits_egress_id_requestOH_T_56) node _io_flit_bits_egress_id_requestOH_T_58 = eq(_io_flit_bits_egress_id_requestOH_T_57, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_59 = xor(q.io.deq.bits.address, UInt<32>(0h800000c0)) node _io_flit_bits_egress_id_requestOH_T_60 = cvt(_io_flit_bits_egress_id_requestOH_T_59) node _io_flit_bits_egress_id_requestOH_T_61 = and(_io_flit_bits_egress_id_requestOH_T_60, asSInt(UInt<33>(0h800000c0))) node _io_flit_bits_egress_id_requestOH_T_62 = asSInt(_io_flit_bits_egress_id_requestOH_T_61) node _io_flit_bits_egress_id_requestOH_T_63 = eq(_io_flit_bits_egress_id_requestOH_T_62, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_64 = or(_io_flit_bits_egress_id_requestOH_T_58, _io_flit_bits_egress_id_requestOH_T_63) node _io_flit_bits_egress_id_requestOH_T_65 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_64) node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_65) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0h9), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0hb), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<4>(0hd), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<4>(0hf), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h11), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node _has_body_opdata_T = bits(q.io.deq.bits.opcode, 2, 2) node has_body_opdata = eq(_has_body_opdata_T, UInt<1>(0h0)) node _has_body_T = not(q.io.deq.bits.mask) node _has_body_T_1 = neq(_has_body_T, UInt<1>(0h0)) node _has_body_T_2 = or(has_body_opdata, _has_body_T_1) connect has_body, _has_body_T_2 connect q.io.enq, io.protocol node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h24)) connect q.io.enq.bits.source, _q_io_enq_bits_source_T	module TLAToNoC_7( // @[TilelinkAdapters.scala:112:7] input clock, // @[TilelinkAdapters.scala:112:7] input reset, // @[TilelinkAdapters.scala:112:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}] wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}] wire q_io_deq_ready = io_flit_ready & (is_body \| _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 \| tail_beats1 == 9'h0) & (is_body \| _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}] wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31] wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31] wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31] assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}] wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7] if (reset) begin // @[TilelinkAdapters.scala:112:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7] end else begin // @[TilelinkAdapters.scala:112:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_196 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_196( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLAToNoC_9 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst q of Queue1_TLBundleA_a29d64s7k1z4u connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) node _head_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2) node head_beats1_opdata = eq(_head_beats1_opdata_T, UInt<1>(0h0)) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) node _tail_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2) node tail_beats1_opdata = eq(_tail_beats1_opdata_T, UInt<1>(0h0)) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body_hi = cat(q.io.deq.bits.mask, q.io.deq.bits.data) node body = cat(body_hi, q.io.deq.bits.corrupt) node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<14>(0h3000)) node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<30>(0h1a113000))) node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4) node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_5) node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<26>(0h2010000)) node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<30>(0h1a113000))) node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8) node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10) node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11) node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<13>(0h1000)) node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<30>(0h1a113000))) node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_17 = xor(q.io.deq.bits.address, UInt<29>(0h10000000)) node _io_flit_bits_egress_id_requestOH_T_18 = cvt(_io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = and(_io_flit_bits_egress_id_requestOH_T_18, asSInt(UInt<30>(0h1a113000))) node _io_flit_bits_egress_id_requestOH_T_20 = asSInt(_io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_requestOH_T_21 = eq(_io_flit_bits_egress_id_requestOH_T_20, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_22 = or(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_21) node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22) node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23) node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<26>(0h2000000)) node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<30>(0h1a110000))) node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26) node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28) node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_requestOH_T_30 = xor(q.io.deq.bits.address, UInt<28>(0h8000000)) node _io_flit_bits_egress_id_requestOH_T_31 = cvt(_io_flit_bits_egress_id_requestOH_T_30) node _io_flit_bits_egress_id_requestOH_T_32 = and(_io_flit_bits_egress_id_requestOH_T_31, asSInt(UInt<30>(0h18000000))) node _io_flit_bits_egress_id_requestOH_T_33 = asSInt(_io_flit_bits_egress_id_requestOH_T_32) node _io_flit_bits_egress_id_requestOH_T_34 = eq(_io_flit_bits_egress_id_requestOH_T_33, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_35 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_34) node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_35) node _io_flit_bits_egress_id_requestOH_T_36 = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_37 = cvt(_io_flit_bits_egress_id_requestOH_T_36) node _io_flit_bits_egress_id_requestOH_T_38 = and(_io_flit_bits_egress_id_requestOH_T_37, asSInt(UInt<30>(0h1a113000))) node _io_flit_bits_egress_id_requestOH_T_39 = asSInt(_io_flit_bits_egress_id_requestOH_T_38) node _io_flit_bits_egress_id_requestOH_T_40 = eq(_io_flit_bits_egress_id_requestOH_T_39, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_41 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_40) node io_flit_bits_egress_id_requestOH_5 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_41) node _io_flit_bits_egress_id_requestOH_T_42 = xor(q.io.deq.bits.address, UInt<17>(0h10000)) node _io_flit_bits_egress_id_requestOH_T_43 = cvt(_io_flit_bits_egress_id_requestOH_T_42) node _io_flit_bits_egress_id_requestOH_T_44 = and(_io_flit_bits_egress_id_requestOH_T_43, asSInt(UInt<30>(0h1a110000))) node _io_flit_bits_egress_id_requestOH_T_45 = asSInt(_io_flit_bits_egress_id_requestOH_T_44) node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_47 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_46) node io_flit_bits_egress_id_requestOH_6 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_47) node _io_flit_bits_egress_id_requestOH_T_48 = xor(q.io.deq.bits.address, UInt<21>(0h100000)) node _io_flit_bits_egress_id_requestOH_T_49 = cvt(_io_flit_bits_egress_id_requestOH_T_48) node _io_flit_bits_egress_id_requestOH_T_50 = and(_io_flit_bits_egress_id_requestOH_T_49, asSInt(UInt<30>(0h1a103000))) node _io_flit_bits_egress_id_requestOH_T_51 = asSInt(_io_flit_bits_egress_id_requestOH_T_50) node _io_flit_bits_egress_id_requestOH_T_52 = eq(_io_flit_bits_egress_id_requestOH_T_51, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_53 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_52) node io_flit_bits_egress_id_requestOH_7 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_53) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<2>(0h2), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<3>(0h5), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<4>(0h8), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<4>(0hb), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<4>(0he), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = mux(io_flit_bits_egress_id_requestOH_5, UInt<5>(0h11), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_6 = mux(io_flit_bits_egress_id_requestOH_6, UInt<5>(0h14), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_7 = mux(io_flit_bits_egress_id_requestOH_7, UInt<5>(0h17), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_9 = or(_io_flit_bits_egress_id_T_8, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_10 = or(_io_flit_bits_egress_id_T_9, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_11 = or(_io_flit_bits_egress_id_T_10, _io_flit_bits_egress_id_T_4) node _io_flit_bits_egress_id_T_12 = or(_io_flit_bits_egress_id_T_11, _io_flit_bits_egress_id_T_5) node _io_flit_bits_egress_id_T_13 = or(_io_flit_bits_egress_id_T_12, _io_flit_bits_egress_id_T_6) node _io_flit_bits_egress_id_T_14 = or(_io_flit_bits_egress_id_T_13, _io_flit_bits_egress_id_T_7) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_14 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node _has_body_opdata_T = bits(q.io.deq.bits.opcode, 2, 2) node has_body_opdata = eq(_has_body_opdata_T, UInt<1>(0h0)) node _has_body_T = not(q.io.deq.bits.mask) node _has_body_T_1 = neq(_has_body_T, UInt<1>(0h0)) node _has_body_T_2 = or(has_body_opdata, _has_body_T_1) connect has_body, _has_body_T_2 connect q.io.enq, io.protocol node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<1>(0h0)) connect q.io.enq.bits.source, _q_io_enq_bits_source_T	module TLAToNoC_9( // @[TilelinkAdapters.scala:112:7] input clock, // @[TilelinkAdapters.scala:112:7] input reset, // @[TilelinkAdapters.scala:112:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [28:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}] wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [28:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}] wire q_io_deq_ready = io_flit_ready & (is_body \| _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 \| tail_beats1 == 9'h0) & (is_body \| _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}] wire [9:0] _GEN_0 = _q_io_deq_bits_address[25:16] ^ 10'h201; // @[Parameters.scala:137:31] assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}] wire _GEN_1 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7] if (reset) begin // @[TilelinkAdapters.scala:112:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7] end else begin // @[TilelinkAdapters.scala:112:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN_1 & io_flit_bits_tail_0) & (_GEN_1 & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module CLINT : input clock : Clock input reset : Reset output auto : { int_out_3 : UInt<1>[2], int_out_2 : UInt<1>[2], int_out_1 : UInt<1>[2], int_out_0 : UInt<1>[2], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip rtcTick : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_55 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire intnodeOut : UInt<1>[2] invalidate intnodeOut[0] invalidate intnodeOut[1] wire x1_intnodeOut : UInt<1>[2] invalidate x1_intnodeOut[0] invalidate x1_intnodeOut[1] wire x1_intnodeOut_1 : UInt<1>[2] invalidate x1_intnodeOut_1[0] invalidate x1_intnodeOut_1[1] wire x1_intnodeOut_2 : UInt<1>[2] invalidate x1_intnodeOut_2[0] invalidate x1_intnodeOut_2[1] connect nodeIn, auto.in connect auto.int_out_0, intnodeOut connect auto.int_out_1, x1_intnodeOut connect auto.int_out_2, x1_intnodeOut_1 connect auto.int_out_3, x1_intnodeOut_2 regreset time : UInt<64>, clock, reset, UInt<64>(0h0) when io.rtcTick : node _time_T = add(time, UInt<1>(0h1)) node _time_T_1 = tail(_time_T, 1) connect time, _time_T_1 reg timecmp_0 : UInt<64>, clock reg timecmp_1 : UInt<64>, clock reg timecmp_2 : UInt<64>, clock reg timecmp_3 : UInt<64>, clock regreset ipi_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ipi_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ipi_2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ipi_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _intnodeOut_0_T = bits(ipi_0, 0, 0) connect intnodeOut[0], _intnodeOut_0_T node _intnodeOut_1_T = geq(time, timecmp_0) connect intnodeOut[1], _intnodeOut_1_T node _intnodeOut_0_T_1 = bits(ipi_1, 0, 0) connect x1_intnodeOut[0], _intnodeOut_0_T_1 node _intnodeOut_1_T_1 = geq(time, timecmp_1) connect x1_intnodeOut[1], _intnodeOut_1_T_1 node _intnodeOut_0_T_2 = bits(ipi_2, 0, 0) connect x1_intnodeOut_1[0], _intnodeOut_0_T_2 node _intnodeOut_1_T_2 = geq(time, timecmp_2) connect x1_intnodeOut_1[1], _intnodeOut_1_T_2 node _intnodeOut_0_T_3 = bits(ipi_3, 0, 0) connect x1_intnodeOut_2[0], _intnodeOut_0_T_3 node _intnodeOut_1_T_3 = geq(time, timecmp_3) connect x1_intnodeOut_2[1], _intnodeOut_1_T_3 node pad = or(timecmp_0, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node timecmp_0_lo_lo = cat(newBytes[1], newBytes[0]) node timecmp_0_lo_hi = cat(newBytes[3], newBytes[2]) node timecmp_0_lo = cat(timecmp_0_lo_hi, timecmp_0_lo_lo) node timecmp_0_hi_lo = cat(newBytes[5], newBytes[4]) node timecmp_0_hi_hi = cat(newBytes[7], newBytes[6]) node timecmp_0_hi = cat(timecmp_0_hi_hi, timecmp_0_hi_lo) node _timecmp_0_T = cat(timecmp_0_hi, timecmp_0_lo) connect timecmp_0, _timecmp_0_T node pad_1 = or(timecmp_1, UInt<64>(0h0)) node _oldBytes_T_8 = bits(pad_1, 7, 0) node _oldBytes_T_9 = bits(pad_1, 15, 8) node _oldBytes_T_10 = bits(pad_1, 23, 16) node _oldBytes_T_11 = bits(pad_1, 31, 24) node _oldBytes_T_12 = bits(pad_1, 39, 32) node _oldBytes_T_13 = bits(pad_1, 47, 40) node _oldBytes_T_14 = bits(pad_1, 55, 48) node _oldBytes_T_15 = bits(pad_1, 63, 56) wire oldBytes_1 : UInt<8>[8] connect oldBytes_1[0], _oldBytes_T_8 connect oldBytes_1[1], _oldBytes_T_9 connect oldBytes_1[2], _oldBytes_T_10 connect oldBytes_1[3], _oldBytes_T_11 connect oldBytes_1[4], _oldBytes_T_12 connect oldBytes_1[5], _oldBytes_T_13 connect oldBytes_1[6], _oldBytes_T_14 connect oldBytes_1[7], _oldBytes_T_15 wire newBytes_1 : UInt<8>[8] connect newBytes_1, oldBytes_1 wire _valids_WIRE_1 : UInt<1>[8] connect _valids_WIRE_1[0], UInt<1>(0h0) connect _valids_WIRE_1[1], UInt<1>(0h0) connect _valids_WIRE_1[2], UInt<1>(0h0) connect _valids_WIRE_1[3], UInt<1>(0h0) connect _valids_WIRE_1[4], UInt<1>(0h0) connect _valids_WIRE_1[5], UInt<1>(0h0) connect _valids_WIRE_1[6], UInt<1>(0h0) connect _valids_WIRE_1[7], UInt<1>(0h0) wire valids_1 : UInt<1>[8] connect valids_1, _valids_WIRE_1 node _T_7 = or(valids_1[0], valids_1[1]) node _T_8 = or(_T_7, valids_1[2]) node _T_9 = or(_T_8, valids_1[3]) node _T_10 = or(_T_9, valids_1[4]) node _T_11 = or(_T_10, valids_1[5]) node _T_12 = or(_T_11, valids_1[6]) node _T_13 = or(_T_12, valids_1[7]) when _T_13 : node timecmp_1_lo_lo = cat(newBytes_1[1], newBytes_1[0]) node timecmp_1_lo_hi = cat(newBytes_1[3], newBytes_1[2]) node timecmp_1_lo = cat(timecmp_1_lo_hi, timecmp_1_lo_lo) node timecmp_1_hi_lo = cat(newBytes_1[5], newBytes_1[4]) node timecmp_1_hi_hi = cat(newBytes_1[7], newBytes_1[6]) node timecmp_1_hi = cat(timecmp_1_hi_hi, timecmp_1_hi_lo) node _timecmp_1_T = cat(timecmp_1_hi, timecmp_1_lo) connect timecmp_1, _timecmp_1_T node pad_2 = or(timecmp_2, UInt<64>(0h0)) node _oldBytes_T_16 = bits(pad_2, 7, 0) node _oldBytes_T_17 = bits(pad_2, 15, 8) node _oldBytes_T_18 = bits(pad_2, 23, 16) node _oldBytes_T_19 = bits(pad_2, 31, 24) node _oldBytes_T_20 = bits(pad_2, 39, 32) node _oldBytes_T_21 = bits(pad_2, 47, 40) node _oldBytes_T_22 = bits(pad_2, 55, 48) node _oldBytes_T_23 = bits(pad_2, 63, 56) wire oldBytes_2 : UInt<8>[8] connect oldBytes_2[0], _oldBytes_T_16 connect oldBytes_2[1], _oldBytes_T_17 connect oldBytes_2[2], _oldBytes_T_18 connect oldBytes_2[3], _oldBytes_T_19 connect oldBytes_2[4], _oldBytes_T_20 connect oldBytes_2[5], _oldBytes_T_21 connect oldBytes_2[6], _oldBytes_T_22 connect oldBytes_2[7], _oldBytes_T_23 wire newBytes_2 : UInt<8>[8] connect newBytes_2, oldBytes_2 wire _valids_WIRE_2 : UInt<1>[8] connect _valids_WIRE_2[0], UInt<1>(0h0) connect _valids_WIRE_2[1], UInt<1>(0h0) connect _valids_WIRE_2[2], UInt<1>(0h0) connect _valids_WIRE_2[3], UInt<1>(0h0) connect _valids_WIRE_2[4], UInt<1>(0h0) connect _valids_WIRE_2[5], UInt<1>(0h0) connect _valids_WIRE_2[6], UInt<1>(0h0) connect _valids_WIRE_2[7], UInt<1>(0h0) wire valids_2 : UInt<1>[8] connect valids_2, _valids_WIRE_2 node _T_14 = or(valids_2[0], valids_2[1]) node _T_15 = or(_T_14, valids_2[2]) node _T_16 = or(_T_15, valids_2[3]) node _T_17 = or(_T_16, valids_2[4]) node _T_18 = or(_T_17, valids_2[5]) node _T_19 = or(_T_18, valids_2[6]) node _T_20 = or(_T_19, valids_2[7]) when _T_20 : node timecmp_2_lo_lo = cat(newBytes_2[1], newBytes_2[0]) node timecmp_2_lo_hi = cat(newBytes_2[3], newBytes_2[2]) node timecmp_2_lo = cat(timecmp_2_lo_hi, timecmp_2_lo_lo) node timecmp_2_hi_lo = cat(newBytes_2[5], newBytes_2[4]) node timecmp_2_hi_hi = cat(newBytes_2[7], newBytes_2[6]) node timecmp_2_hi = cat(timecmp_2_hi_hi, timecmp_2_hi_lo) node _timecmp_2_T = cat(timecmp_2_hi, timecmp_2_lo) connect timecmp_2, _timecmp_2_T node pad_3 = or(timecmp_3, UInt<64>(0h0)) node _oldBytes_T_24 = bits(pad_3, 7, 0) node _oldBytes_T_25 = bits(pad_3, 15, 8) node _oldBytes_T_26 = bits(pad_3, 23, 16) node _oldBytes_T_27 = bits(pad_3, 31, 24) node _oldBytes_T_28 = bits(pad_3, 39, 32) node _oldBytes_T_29 = bits(pad_3, 47, 40) node _oldBytes_T_30 = bits(pad_3, 55, 48) node _oldBytes_T_31 = bits(pad_3, 63, 56) wire oldBytes_3 : UInt<8>[8] connect oldBytes_3[0], _oldBytes_T_24 connect oldBytes_3[1], _oldBytes_T_25 connect oldBytes_3[2], _oldBytes_T_26 connect oldBytes_3[3], _oldBytes_T_27 connect oldBytes_3[4], _oldBytes_T_28 connect oldBytes_3[5], _oldBytes_T_29 connect oldBytes_3[6], _oldBytes_T_30 connect oldBytes_3[7], _oldBytes_T_31 wire newBytes_3 : UInt<8>[8] connect newBytes_3, oldBytes_3 wire _valids_WIRE_3 : UInt<1>[8] connect _valids_WIRE_3[0], UInt<1>(0h0) connect _valids_WIRE_3[1], UInt<1>(0h0) connect _valids_WIRE_3[2], UInt<1>(0h0) connect _valids_WIRE_3[3], UInt<1>(0h0) connect _valids_WIRE_3[4], UInt<1>(0h0) connect _valids_WIRE_3[5], UInt<1>(0h0) connect _valids_WIRE_3[6], UInt<1>(0h0) connect _valids_WIRE_3[7], UInt<1>(0h0) wire valids_3 : UInt<1>[8] connect valids_3, _valids_WIRE_3 node _T_21 = or(valids_3[0], valids_3[1]) node _T_22 = or(_T_21, valids_3[2]) node _T_23 = or(_T_22, valids_3[3]) node _T_24 = or(_T_23, valids_3[4]) node _T_25 = or(_T_24, valids_3[5]) node _T_26 = or(_T_25, valids_3[6]) node _T_27 = or(_T_26, valids_3[7]) when _T_27 : node timecmp_3_lo_lo = cat(newBytes_3[1], newBytes_3[0]) node timecmp_3_lo_hi = cat(newBytes_3[3], newBytes_3[2]) node timecmp_3_lo = cat(timecmp_3_lo_hi, timecmp_3_lo_lo) node timecmp_3_hi_lo = cat(newBytes_3[5], newBytes_3[4]) node timecmp_3_hi_hi = cat(newBytes_3[7], newBytes_3[6]) node timecmp_3_hi = cat(timecmp_3_hi_hi, timecmp_3_hi_lo) node _timecmp_3_T = cat(timecmp_3_hi, timecmp_3_lo) connect timecmp_3, _timecmp_3_T node pad_4 = or(time, UInt<64>(0h0)) node _oldBytes_T_32 = bits(pad_4, 7, 0) node _oldBytes_T_33 = bits(pad_4, 15, 8) node _oldBytes_T_34 = bits(pad_4, 23, 16) node _oldBytes_T_35 = bits(pad_4, 31, 24) node _oldBytes_T_36 = bits(pad_4, 39, 32) node _oldBytes_T_37 = bits(pad_4, 47, 40) node _oldBytes_T_38 = bits(pad_4, 55, 48) node _oldBytes_T_39 = bits(pad_4, 63, 56) wire oldBytes_4 : UInt<8>[8] connect oldBytes_4[0], _oldBytes_T_32 connect oldBytes_4[1], _oldBytes_T_33 connect oldBytes_4[2], _oldBytes_T_34 connect oldBytes_4[3], _oldBytes_T_35 connect oldBytes_4[4], _oldBytes_T_36 connect oldBytes_4[5], _oldBytes_T_37 connect oldBytes_4[6], _oldBytes_T_38 connect oldBytes_4[7], _oldBytes_T_39 wire newBytes_4 : UInt<8>[8] connect newBytes_4, oldBytes_4 wire _valids_WIRE_4 : UInt<1>[8] connect _valids_WIRE_4[0], UInt<1>(0h0) connect _valids_WIRE_4[1], UInt<1>(0h0) connect _valids_WIRE_4[2], UInt<1>(0h0) connect _valids_WIRE_4[3], UInt<1>(0h0) connect _valids_WIRE_4[4], UInt<1>(0h0) connect _valids_WIRE_4[5], UInt<1>(0h0) connect _valids_WIRE_4[6], UInt<1>(0h0) connect _valids_WIRE_4[7], UInt<1>(0h0) wire valids_4 : UInt<1>[8] connect valids_4, _valids_WIRE_4 node _T_28 = or(valids_4[0], valids_4[1]) node _T_29 = or(_T_28, valids_4[2]) node _T_30 = or(_T_29, valids_4[3]) node _T_31 = or(_T_30, valids_4[4]) node _T_32 = or(_T_31, valids_4[5]) node _T_33 = or(_T_32, valids_4[6]) node _T_34 = or(_T_33, valids_4[7]) when _T_34 : node time_lo_lo = cat(newBytes_4[1], newBytes_4[0]) node time_lo_hi = cat(newBytes_4[3], newBytes_4[2]) node time_lo = cat(time_lo_hi, time_lo_lo) node time_hi_lo = cat(newBytes_4[5], newBytes_4[4]) node time_hi_hi = cat(newBytes_4[7], newBytes_4[6]) node time_hi = cat(time_hi_hi, time_hi_lo) node _time_T_2 = cat(time_hi, time_lo) connect time, _time_T_2 wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<13>(0h803)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<13>(0h0)) node _out_T_1 = eq(out_bindex, UInt<13>(0h0)) node _out_T_2 = eq(out_findex, UInt<13>(0h0)) node _out_T_3 = eq(out_bindex, UInt<13>(0h0)) node _out_T_4 = eq(out_findex, UInt<13>(0h0)) node _out_T_5 = eq(out_bindex, UInt<13>(0h0)) node _out_T_6 = eq(out_findex, UInt<13>(0h17fc)) node _out_T_7 = eq(out_bindex, UInt<13>(0h17fc)) node _out_T_8 = eq(out_findex, UInt<13>(0h0)) node _out_T_9 = eq(out_bindex, UInt<13>(0h0)) node _out_T_10 = eq(out_findex, UInt<13>(0h0)) node _out_T_11 = eq(out_bindex, UInt<13>(0h0)) node _out_T_12 = eq(out_findex, UInt<13>(0h0)) node _out_T_13 = eq(out_bindex, UInt<13>(0h0)) wire out_rivalid : UInt<1>[48] wire out_wivalid : UInt<1>[48] wire out_roready : UInt<1>[48] wire out_woready : UInt<1>[48] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_14 = bits(out_front.bits.data, 0, 0) when out_f_woready : connect ipi_0, _out_T_14 node _out_T_15 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_16 = and(UInt<1>(0h1), out_f_roready) node _out_T_17 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_18 = and(UInt<1>(0h1), out_f_woready) node _out_T_19 = eq(out_rimask, UInt<1>(0h0)) node _out_T_20 = eq(out_wimask, UInt<1>(0h0)) node _out_T_21 = eq(out_romask, UInt<1>(0h0)) node _out_T_22 = eq(out_womask, UInt<1>(0h0)) node _out_T_23 = or(ipi_0, UInt<1>(0h0)) node _out_T_24 = bits(_out_T_23, 0, 0) node _out_rimask_T_1 = bits(out_frontMask, 31, 1) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 31, 1) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 31, 1) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 31, 1) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_25 = bits(out_front.bits.data, 31, 1) node _out_T_26 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_27 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_28 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_29 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_30 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_31 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_24, UInt<1>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_32 = or(out_prepend, UInt<32>(0h0)) node _out_T_33 = bits(_out_T_32, 31, 0) node _out_rimask_T_2 = bits(out_frontMask, 32, 32) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 32, 32) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 32, 32) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 32, 32) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_34 = bits(out_front.bits.data, 32, 32) when out_f_woready_2 : connect ipi_1, _out_T_34 node _out_T_35 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_36 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_37 = and(out_f_wivalid_2, UInt<1>(0h1)) node _out_T_38 = and(UInt<1>(0h1), out_f_woready_2) node _out_T_39 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_40 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_41 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_42 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_33, UInt<32>(0h0)) node out_prepend_1 = cat(ipi_1, _out_prepend_T_1) node _out_T_43 = or(out_prepend_1, UInt<33>(0h0)) node _out_T_44 = bits(_out_T_43, 32, 0) node _out_rimask_T_3 = bits(out_frontMask, 63, 33) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 63, 33) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 63, 33) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 63, 33) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_45 = bits(out_front.bits.data, 63, 33) node _out_T_46 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_47 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_48 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_49 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_50 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_51 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_44, UInt<33>(0h0)) node out_prepend_2 = cat(UInt<1>(0h0), _out_prepend_T_2) node _out_T_52 = or(out_prepend_2, UInt<64>(0h0)) node _out_T_53 = bits(_out_T_52, 63, 0) node _out_rimask_T_4 = bits(out_frontMask, 7, 0) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 7, 0) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 7, 0) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 7, 0) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_54 = bits(out_front.bits.data, 7, 0) connect valids_1[0], out_f_woready_4 when out_f_woready_4 : connect newBytes_1[0], _out_T_54 node _out_T_55 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_56 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_57 = and(out_f_wivalid_4, UInt<1>(0h1)) node _out_T_58 = and(UInt<1>(0h1), out_f_woready_4) node _out_T_59 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_60 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_61 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_62 = eq(out_womask_4, UInt<1>(0h0)) node _out_T_63 = or(oldBytes_1[0], UInt<8>(0h0)) node _out_T_64 = bits(_out_T_63, 7, 0) node _out_rimask_T_5 = bits(out_frontMask, 15, 8) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 15, 8) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 15, 8) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 15, 8) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_65 = bits(out_front.bits.data, 15, 8) connect valids_1[1], out_f_woready_5 when out_f_woready_5 : connect newBytes_1[1], _out_T_65 node _out_T_66 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_67 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_68 = and(out_f_wivalid_5, UInt<1>(0h1)) node _out_T_69 = and(UInt<1>(0h1), out_f_woready_5) node _out_T_70 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_71 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_72 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_73 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_64, UInt<8>(0h0)) node out_prepend_3 = cat(oldBytes_1[1], _out_prepend_T_3) node _out_T_74 = or(out_prepend_3, UInt<16>(0h0)) node _out_T_75 = bits(_out_T_74, 15, 0) node _out_rimask_T_6 = bits(out_frontMask, 23, 16) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 23, 16) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 23, 16) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 23, 16) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_76 = bits(out_front.bits.data, 23, 16) connect valids_1[2], out_f_woready_6 when out_f_woready_6 : connect newBytes_1[2], _out_T_76 node _out_T_77 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_78 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_79 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_80 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_81 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_82 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_83 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_84 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_75, UInt<16>(0h0)) node out_prepend_4 = cat(oldBytes_1[2], _out_prepend_T_4) node _out_T_85 = or(out_prepend_4, UInt<24>(0h0)) node _out_T_86 = bits(_out_T_85, 23, 0) node _out_rimask_T_7 = bits(out_frontMask, 31, 24) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 31, 24) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 31, 24) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 31, 24) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_87 = bits(out_front.bits.data, 31, 24) connect valids_1[3], out_f_woready_7 when out_f_woready_7 : connect newBytes_1[3], _out_T_87 node _out_T_88 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_89 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_90 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_91 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_92 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_93 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_94 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_95 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_86, UInt<24>(0h0)) node out_prepend_5 = cat(oldBytes_1[3], _out_prepend_T_5) node _out_T_96 = or(out_prepend_5, UInt<32>(0h0)) node _out_T_97 = bits(_out_T_96, 31, 0) node _out_rimask_T_8 = bits(out_frontMask, 39, 32) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 39, 32) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 39, 32) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 39, 32) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_98 = bits(out_front.bits.data, 39, 32) connect valids_1[4], out_f_woready_8 when out_f_woready_8 : connect newBytes_1[4], _out_T_98 node _out_T_99 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_100 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_101 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_102 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_103 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_104 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_105 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_106 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_97, UInt<32>(0h0)) node out_prepend_6 = cat(oldBytes_1[4], _out_prepend_T_6) node _out_T_107 = or(out_prepend_6, UInt<40>(0h0)) node _out_T_108 = bits(_out_T_107, 39, 0) node _out_rimask_T_9 = bits(out_frontMask, 47, 40) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 47, 40) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 47, 40) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 47, 40) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_109 = bits(out_front.bits.data, 47, 40) connect valids_1[5], out_f_woready_9 when out_f_woready_9 : connect newBytes_1[5], _out_T_109 node _out_T_110 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_111 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_112 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_113 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_114 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_115 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_116 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_117 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_108, UInt<40>(0h0)) node out_prepend_7 = cat(oldBytes_1[5], _out_prepend_T_7) node _out_T_118 = or(out_prepend_7, UInt<48>(0h0)) node _out_T_119 = bits(_out_T_118, 47, 0) node _out_rimask_T_10 = bits(out_frontMask, 55, 48) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 55, 48) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 55, 48) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 55, 48) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_120 = bits(out_front.bits.data, 55, 48) connect valids_1[6], out_f_woready_10 when out_f_woready_10 : connect newBytes_1[6], _out_T_120 node _out_T_121 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_122 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_123 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_124 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_125 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_126 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_127 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_128 = eq(out_womask_10, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_119, UInt<48>(0h0)) node out_prepend_8 = cat(oldBytes_1[6], _out_prepend_T_8) node _out_T_129 = or(out_prepend_8, UInt<56>(0h0)) node _out_T_130 = bits(_out_T_129, 55, 0) node _out_rimask_T_11 = bits(out_frontMask, 63, 56) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 63, 56) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 63, 56) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 63, 56) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_131 = bits(out_front.bits.data, 63, 56) connect valids_1[7], out_f_woready_11 when out_f_woready_11 : connect newBytes_1[7], _out_T_131 node _out_T_132 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_133 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_134 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_135 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_136 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_137 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_138 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_139 = eq(out_womask_11, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_130, UInt<56>(0h0)) node out_prepend_9 = cat(oldBytes_1[7], _out_prepend_T_9) node _out_T_140 = or(out_prepend_9, UInt<64>(0h0)) node _out_T_141 = bits(_out_T_140, 63, 0) node _out_rimask_T_12 = bits(out_frontMask, 0, 0) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 0, 0) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 0, 0) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 0, 0) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_142 = bits(out_front.bits.data, 0, 0) when out_f_woready_12 : connect ipi_2, _out_T_142 node _out_T_143 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_144 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_145 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_146 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_147 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_148 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_149 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_150 = eq(out_womask_12, UInt<1>(0h0)) node _out_T_151 = or(ipi_2, UInt<1>(0h0)) node _out_T_152 = bits(_out_T_151, 0, 0) node _out_rimask_T_13 = bits(out_frontMask, 31, 1) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 31, 1) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 31, 1) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 31, 1) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_153 = bits(out_front.bits.data, 31, 1) node _out_T_154 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_155 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_156 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_157 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_158 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_159 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_152, UInt<1>(0h0)) node out_prepend_10 = cat(UInt<1>(0h0), _out_prepend_T_10) node _out_T_160 = or(out_prepend_10, UInt<32>(0h0)) node _out_T_161 = bits(_out_T_160, 31, 0) node _out_rimask_T_14 = bits(out_frontMask, 32, 32) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 32, 32) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 32, 32) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 32, 32) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_162 = bits(out_front.bits.data, 32, 32) when out_f_woready_14 : connect ipi_3, _out_T_162 node _out_T_163 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_164 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_165 = and(out_f_wivalid_14, UInt<1>(0h1)) node _out_T_166 = and(UInt<1>(0h1), out_f_woready_14) node _out_T_167 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_168 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_169 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_170 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_161, UInt<32>(0h0)) node out_prepend_11 = cat(ipi_3, _out_prepend_T_11) node _out_T_171 = or(out_prepend_11, UInt<33>(0h0)) node _out_T_172 = bits(_out_T_171, 32, 0) node _out_rimask_T_15 = bits(out_frontMask, 63, 33) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 63, 33) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 63, 33) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 63, 33) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_173 = bits(out_front.bits.data, 63, 33) node _out_T_174 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_175 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_176 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_177 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_178 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_179 = eq(out_womask_15, UInt<1>(0h0)) node _out_prepend_T_12 = or(_out_T_172, UInt<33>(0h0)) node out_prepend_12 = cat(UInt<1>(0h0), _out_prepend_T_12) node _out_T_180 = or(out_prepend_12, UInt<64>(0h0)) node _out_T_181 = bits(_out_T_180, 63, 0) node _out_rimask_T_16 = bits(out_frontMask, 7, 0) node out_rimask_16 = orr(_out_rimask_T_16) node _out_wimask_T_16 = bits(out_frontMask, 7, 0) node out_wimask_16 = andr(_out_wimask_T_16) node _out_romask_T_16 = bits(out_backMask, 7, 0) node out_romask_16 = orr(_out_romask_T_16) node _out_womask_T_16 = bits(out_backMask, 7, 0) node out_womask_16 = andr(_out_womask_T_16) node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16) node out_f_roready_16 = and(out_roready[16], out_romask_16) node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16) node out_f_woready_16 = and(out_woready[16], out_womask_16) node _out_T_182 = bits(out_front.bits.data, 7, 0) connect valids_4[0], out_f_woready_16 when out_f_woready_16 : connect newBytes_4[0], _out_T_182 node _out_T_183 = and(out_f_rivalid_16, UInt<1>(0h1)) node _out_T_184 = and(UInt<1>(0h1), out_f_roready_16) node _out_T_185 = and(out_f_wivalid_16, UInt<1>(0h1)) node _out_T_186 = and(UInt<1>(0h1), out_f_woready_16) node _out_T_187 = eq(out_rimask_16, UInt<1>(0h0)) node _out_T_188 = eq(out_wimask_16, UInt<1>(0h0)) node _out_T_189 = eq(out_romask_16, UInt<1>(0h0)) node _out_T_190 = eq(out_womask_16, UInt<1>(0h0)) node _out_T_191 = or(oldBytes_4[0], UInt<8>(0h0)) node _out_T_192 = bits(_out_T_191, 7, 0) node _out_rimask_T_17 = bits(out_frontMask, 15, 8) node out_rimask_17 = orr(_out_rimask_T_17) node _out_wimask_T_17 = bits(out_frontMask, 15, 8) node out_wimask_17 = andr(_out_wimask_T_17) node _out_romask_T_17 = bits(out_backMask, 15, 8) node out_romask_17 = orr(_out_romask_T_17) node _out_womask_T_17 = bits(out_backMask, 15, 8) node out_womask_17 = andr(_out_womask_T_17) node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17) node out_f_roready_17 = and(out_roready[17], out_romask_17) node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17) node out_f_woready_17 = and(out_woready[17], out_womask_17) node _out_T_193 = bits(out_front.bits.data, 15, 8) connect valids_4[1], out_f_woready_17 when out_f_woready_17 : connect newBytes_4[1], _out_T_193 node _out_T_194 = and(out_f_rivalid_17, UInt<1>(0h1)) node _out_T_195 = and(UInt<1>(0h1), out_f_roready_17) node _out_T_196 = and(out_f_wivalid_17, UInt<1>(0h1)) node _out_T_197 = and(UInt<1>(0h1), out_f_woready_17) node _out_T_198 = eq(out_rimask_17, UInt<1>(0h0)) node _out_T_199 = eq(out_wimask_17, UInt<1>(0h0)) node _out_T_200 = eq(out_romask_17, UInt<1>(0h0)) node _out_T_201 = eq(out_womask_17, UInt<1>(0h0)) node _out_prepend_T_13 = or(_out_T_192, UInt<8>(0h0)) node out_prepend_13 = cat(oldBytes_4[1], _out_prepend_T_13) node _out_T_202 = or(out_prepend_13, UInt<16>(0h0)) node _out_T_203 = bits(_out_T_202, 15, 0) node _out_rimask_T_18 = bits(out_frontMask, 23, 16) node out_rimask_18 = orr(_out_rimask_T_18) node _out_wimask_T_18 = bits(out_frontMask, 23, 16) node out_wimask_18 = andr(_out_wimask_T_18) node _out_romask_T_18 = bits(out_backMask, 23, 16) node out_romask_18 = orr(_out_romask_T_18) node _out_womask_T_18 = bits(out_backMask, 23, 16) node out_womask_18 = andr(_out_womask_T_18) node out_f_rivalid_18 = and(out_rivalid[18], out_rimask_18) node out_f_roready_18 = and(out_roready[18], out_romask_18) node out_f_wivalid_18 = and(out_wivalid[18], out_wimask_18) node out_f_woready_18 = and(out_woready[18], out_womask_18) node _out_T_204 = bits(out_front.bits.data, 23, 16) connect valids_4[2], out_f_woready_18 when out_f_woready_18 : connect newBytes_4[2], _out_T_204 node _out_T_205 = and(out_f_rivalid_18, UInt<1>(0h1)) node _out_T_206 = and(UInt<1>(0h1), out_f_roready_18) node _out_T_207 = and(out_f_wivalid_18, UInt<1>(0h1)) node _out_T_208 = and(UInt<1>(0h1), out_f_woready_18) node _out_T_209 = eq(out_rimask_18, UInt<1>(0h0)) node _out_T_210 = eq(out_wimask_18, UInt<1>(0h0)) node _out_T_211 = eq(out_romask_18, UInt<1>(0h0)) node _out_T_212 = eq(out_womask_18, UInt<1>(0h0)) node _out_prepend_T_14 = or(_out_T_203, UInt<16>(0h0)) node out_prepend_14 = cat(oldBytes_4[2], _out_prepend_T_14) node _out_T_213 = or(out_prepend_14, UInt<24>(0h0)) node _out_T_214 = bits(_out_T_213, 23, 0) node _out_rimask_T_19 = bits(out_frontMask, 31, 24) node out_rimask_19 = orr(_out_rimask_T_19) node _out_wimask_T_19 = bits(out_frontMask, 31, 24) node out_wimask_19 = andr(_out_wimask_T_19) node _out_romask_T_19 = bits(out_backMask, 31, 24) node out_romask_19 = orr(_out_romask_T_19) node _out_womask_T_19 = bits(out_backMask, 31, 24) node out_womask_19 = andr(_out_womask_T_19) node out_f_rivalid_19 = and(out_rivalid[19], out_rimask_19) node out_f_roready_19 = and(out_roready[19], out_romask_19) node out_f_wivalid_19 = and(out_wivalid[19], out_wimask_19) node out_f_woready_19 = and(out_woready[19], out_womask_19) node _out_T_215 = bits(out_front.bits.data, 31, 24) connect valids_4[3], out_f_woready_19 when out_f_woready_19 : connect newBytes_4[3], _out_T_215 node _out_T_216 = and(out_f_rivalid_19, UInt<1>(0h1)) node _out_T_217 = and(UInt<1>(0h1), out_f_roready_19) node _out_T_218 = and(out_f_wivalid_19, UInt<1>(0h1)) node _out_T_219 = and(UInt<1>(0h1), out_f_woready_19) node _out_T_220 = eq(out_rimask_19, UInt<1>(0h0)) node _out_T_221 = eq(out_wimask_19, UInt<1>(0h0)) node _out_T_222 = eq(out_romask_19, UInt<1>(0h0)) node _out_T_223 = eq(out_womask_19, UInt<1>(0h0)) node _out_prepend_T_15 = or(_out_T_214, UInt<24>(0h0)) node out_prepend_15 = cat(oldBytes_4[3], _out_prepend_T_15) node _out_T_224 = or(out_prepend_15, UInt<32>(0h0)) node _out_T_225 = bits(_out_T_224, 31, 0) node _out_rimask_T_20 = bits(out_frontMask, 39, 32) node out_rimask_20 = orr(_out_rimask_T_20) node _out_wimask_T_20 = bits(out_frontMask, 39, 32) node out_wimask_20 = andr(_out_wimask_T_20) node _out_romask_T_20 = bits(out_backMask, 39, 32) node out_romask_20 = orr(_out_romask_T_20) node _out_womask_T_20 = bits(out_backMask, 39, 32) node out_womask_20 = andr(_out_womask_T_20) node out_f_rivalid_20 = and(out_rivalid[20], out_rimask_20) node out_f_roready_20 = and(out_roready[20], out_romask_20) node out_f_wivalid_20 = and(out_wivalid[20], out_wimask_20) node out_f_woready_20 = and(out_woready[20], out_womask_20) node _out_T_226 = bits(out_front.bits.data, 39, 32) connect valids_4[4], out_f_woready_20 when out_f_woready_20 : connect newBytes_4[4], _out_T_226 node _out_T_227 = and(out_f_rivalid_20, UInt<1>(0h1)) node _out_T_228 = and(UInt<1>(0h1), out_f_roready_20) node _out_T_229 = and(out_f_wivalid_20, UInt<1>(0h1)) node _out_T_230 = and(UInt<1>(0h1), out_f_woready_20) node _out_T_231 = eq(out_rimask_20, UInt<1>(0h0)) node _out_T_232 = eq(out_wimask_20, UInt<1>(0h0)) node _out_T_233 = eq(out_romask_20, UInt<1>(0h0)) node _out_T_234 = eq(out_womask_20, UInt<1>(0h0)) node _out_prepend_T_16 = or(_out_T_225, UInt<32>(0h0)) node out_prepend_16 = cat(oldBytes_4[4], _out_prepend_T_16) node _out_T_235 = or(out_prepend_16, UInt<40>(0h0)) node _out_T_236 = bits(_out_T_235, 39, 0) node _out_rimask_T_21 = bits(out_frontMask, 47, 40) node out_rimask_21 = orr(_out_rimask_T_21) node _out_wimask_T_21 = bits(out_frontMask, 47, 40) node out_wimask_21 = andr(_out_wimask_T_21) node _out_romask_T_21 = bits(out_backMask, 47, 40) node out_romask_21 = orr(_out_romask_T_21) node _out_womask_T_21 = bits(out_backMask, 47, 40) node out_womask_21 = andr(_out_womask_T_21) node out_f_rivalid_21 = and(out_rivalid[21], out_rimask_21) node out_f_roready_21 = and(out_roready[21], out_romask_21) node out_f_wivalid_21 = and(out_wivalid[21], out_wimask_21) node out_f_woready_21 = and(out_woready[21], out_womask_21) node _out_T_237 = bits(out_front.bits.data, 47, 40) connect valids_4[5], out_f_woready_21 when out_f_woready_21 : connect newBytes_4[5], _out_T_237 node _out_T_238 = and(out_f_rivalid_21, UInt<1>(0h1)) node _out_T_239 = and(UInt<1>(0h1), out_f_roready_21) node _out_T_240 = and(out_f_wivalid_21, UInt<1>(0h1)) node _out_T_241 = and(UInt<1>(0h1), out_f_woready_21) node _out_T_242 = eq(out_rimask_21, UInt<1>(0h0)) node _out_T_243 = eq(out_wimask_21, UInt<1>(0h0)) node _out_T_244 = eq(out_romask_21, UInt<1>(0h0)) node _out_T_245 = eq(out_womask_21, UInt<1>(0h0)) node _out_prepend_T_17 = or(_out_T_236, UInt<40>(0h0)) node out_prepend_17 = cat(oldBytes_4[5], _out_prepend_T_17) node _out_T_246 = or(out_prepend_17, UInt<48>(0h0)) node _out_T_247 = bits(_out_T_246, 47, 0) node _out_rimask_T_22 = bits(out_frontMask, 55, 48) node out_rimask_22 = orr(_out_rimask_T_22) node _out_wimask_T_22 = bits(out_frontMask, 55, 48) node out_wimask_22 = andr(_out_wimask_T_22) node _out_romask_T_22 = bits(out_backMask, 55, 48) node out_romask_22 = orr(_out_romask_T_22) node _out_womask_T_22 = bits(out_backMask, 55, 48) node out_womask_22 = andr(_out_womask_T_22) node out_f_rivalid_22 = and(out_rivalid[22], out_rimask_22) node out_f_roready_22 = and(out_roready[22], out_romask_22) node out_f_wivalid_22 = and(out_wivalid[22], out_wimask_22) node out_f_woready_22 = and(out_woready[22], out_womask_22) node _out_T_248 = bits(out_front.bits.data, 55, 48) connect valids_4[6], out_f_woready_22 when out_f_woready_22 : connect newBytes_4[6], _out_T_248 node _out_T_249 = and(out_f_rivalid_22, UInt<1>(0h1)) node _out_T_250 = and(UInt<1>(0h1), out_f_roready_22) node _out_T_251 = and(out_f_wivalid_22, UInt<1>(0h1)) node _out_T_252 = and(UInt<1>(0h1), out_f_woready_22) node _out_T_253 = eq(out_rimask_22, UInt<1>(0h0)) node _out_T_254 = eq(out_wimask_22, UInt<1>(0h0)) node _out_T_255 = eq(out_romask_22, UInt<1>(0h0)) node _out_T_256 = eq(out_womask_22, UInt<1>(0h0)) node _out_prepend_T_18 = or(_out_T_247, UInt<48>(0h0)) node out_prepend_18 = cat(oldBytes_4[6], _out_prepend_T_18) node _out_T_257 = or(out_prepend_18, UInt<56>(0h0)) node _out_T_258 = bits(_out_T_257, 55, 0) node _out_rimask_T_23 = bits(out_frontMask, 63, 56) node out_rimask_23 = orr(_out_rimask_T_23) node _out_wimask_T_23 = bits(out_frontMask, 63, 56) node out_wimask_23 = andr(_out_wimask_T_23) node _out_romask_T_23 = bits(out_backMask, 63, 56) node out_romask_23 = orr(_out_romask_T_23) node _out_womask_T_23 = bits(out_backMask, 63, 56) node out_womask_23 = andr(_out_womask_T_23) node out_f_rivalid_23 = and(out_rivalid[23], out_rimask_23) node out_f_roready_23 = and(out_roready[23], out_romask_23) node out_f_wivalid_23 = and(out_wivalid[23], out_wimask_23) node out_f_woready_23 = and(out_woready[23], out_womask_23) node _out_T_259 = bits(out_front.bits.data, 63, 56) connect valids_4[7], out_f_woready_23 when out_f_woready_23 : connect newBytes_4[7], _out_T_259 node _out_T_260 = and(out_f_rivalid_23, UInt<1>(0h1)) node _out_T_261 = and(UInt<1>(0h1), out_f_roready_23) node _out_T_262 = and(out_f_wivalid_23, UInt<1>(0h1)) node _out_T_263 = and(UInt<1>(0h1), out_f_woready_23) node _out_T_264 = eq(out_rimask_23, UInt<1>(0h0)) node _out_T_265 = eq(out_wimask_23, UInt<1>(0h0)) node _out_T_266 = eq(out_romask_23, UInt<1>(0h0)) node _out_T_267 = eq(out_womask_23, UInt<1>(0h0)) node _out_prepend_T_19 = or(_out_T_258, UInt<56>(0h0)) node out_prepend_19 = cat(oldBytes_4[7], _out_prepend_T_19) node _out_T_268 = or(out_prepend_19, UInt<64>(0h0)) node _out_T_269 = bits(_out_T_268, 63, 0) node _out_rimask_T_24 = bits(out_frontMask, 7, 0) node out_rimask_24 = orr(_out_rimask_T_24) node _out_wimask_T_24 = bits(out_frontMask, 7, 0) node out_wimask_24 = andr(_out_wimask_T_24) node _out_romask_T_24 = bits(out_backMask, 7, 0) node out_romask_24 = orr(_out_romask_T_24) node _out_womask_T_24 = bits(out_backMask, 7, 0) node out_womask_24 = andr(_out_womask_T_24) node out_f_rivalid_24 = and(out_rivalid[24], out_rimask_24) node out_f_roready_24 = and(out_roready[24], out_romask_24) node out_f_wivalid_24 = and(out_wivalid[24], out_wimask_24) node out_f_woready_24 = and(out_woready[24], out_womask_24) node _out_T_270 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready_24 when out_f_woready_24 : connect newBytes[0], _out_T_270 node _out_T_271 = and(out_f_rivalid_24, UInt<1>(0h1)) node _out_T_272 = and(UInt<1>(0h1), out_f_roready_24) node _out_T_273 = and(out_f_wivalid_24, UInt<1>(0h1)) node _out_T_274 = and(UInt<1>(0h1), out_f_woready_24) node _out_T_275 = eq(out_rimask_24, UInt<1>(0h0)) node _out_T_276 = eq(out_wimask_24, UInt<1>(0h0)) node _out_T_277 = eq(out_romask_24, UInt<1>(0h0)) node _out_T_278 = eq(out_womask_24, UInt<1>(0h0)) node _out_T_279 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_280 = bits(_out_T_279, 7, 0) node _out_rimask_T_25 = bits(out_frontMask, 15, 8) node out_rimask_25 = orr(_out_rimask_T_25) node _out_wimask_T_25 = bits(out_frontMask, 15, 8) node out_wimask_25 = andr(_out_wimask_T_25) node _out_romask_T_25 = bits(out_backMask, 15, 8) node out_romask_25 = orr(_out_romask_T_25) node _out_womask_T_25 = bits(out_backMask, 15, 8) node out_womask_25 = andr(_out_womask_T_25) node out_f_rivalid_25 = and(out_rivalid[25], out_rimask_25) node out_f_roready_25 = and(out_roready[25], out_romask_25) node out_f_wivalid_25 = and(out_wivalid[25], out_wimask_25) node out_f_woready_25 = and(out_woready[25], out_womask_25) node _out_T_281 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_25 when out_f_woready_25 : connect newBytes[1], _out_T_281 node _out_T_282 = and(out_f_rivalid_25, UInt<1>(0h1)) node _out_T_283 = and(UInt<1>(0h1), out_f_roready_25) node _out_T_284 = and(out_f_wivalid_25, UInt<1>(0h1)) node _out_T_285 = and(UInt<1>(0h1), out_f_woready_25) node _out_T_286 = eq(out_rimask_25, UInt<1>(0h0)) node _out_T_287 = eq(out_wimask_25, UInt<1>(0h0)) node _out_T_288 = eq(out_romask_25, UInt<1>(0h0)) node _out_T_289 = eq(out_womask_25, UInt<1>(0h0)) node _out_prepend_T_20 = or(_out_T_280, UInt<8>(0h0)) node out_prepend_20 = cat(oldBytes[1], _out_prepend_T_20) node _out_T_290 = or(out_prepend_20, UInt<16>(0h0)) node _out_T_291 = bits(_out_T_290, 15, 0) node _out_rimask_T_26 = bits(out_frontMask, 23, 16) node out_rimask_26 = orr(_out_rimask_T_26) node _out_wimask_T_26 = bits(out_frontMask, 23, 16) node out_wimask_26 = andr(_out_wimask_T_26) node _out_romask_T_26 = bits(out_backMask, 23, 16) node out_romask_26 = orr(_out_romask_T_26) node _out_womask_T_26 = bits(out_backMask, 23, 16) node out_womask_26 = andr(_out_womask_T_26) node out_f_rivalid_26 = and(out_rivalid[26], out_rimask_26) node out_f_roready_26 = and(out_roready[26], out_romask_26) node out_f_wivalid_26 = and(out_wivalid[26], out_wimask_26) node out_f_woready_26 = and(out_woready[26], out_womask_26) node _out_T_292 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_26 when out_f_woready_26 : connect newBytes[2], _out_T_292 node _out_T_293 = and(out_f_rivalid_26, UInt<1>(0h1)) node _out_T_294 = and(UInt<1>(0h1), out_f_roready_26) node _out_T_295 = and(out_f_wivalid_26, UInt<1>(0h1)) node _out_T_296 = and(UInt<1>(0h1), out_f_woready_26) node _out_T_297 = eq(out_rimask_26, UInt<1>(0h0)) node _out_T_298 = eq(out_wimask_26, UInt<1>(0h0)) node _out_T_299 = eq(out_romask_26, UInt<1>(0h0)) node _out_T_300 = eq(out_womask_26, UInt<1>(0h0)) node _out_prepend_T_21 = or(_out_T_291, UInt<16>(0h0)) node out_prepend_21 = cat(oldBytes[2], _out_prepend_T_21) node _out_T_301 = or(out_prepend_21, UInt<24>(0h0)) node _out_T_302 = bits(_out_T_301, 23, 0) node _out_rimask_T_27 = bits(out_frontMask, 31, 24) node out_rimask_27 = orr(_out_rimask_T_27) node _out_wimask_T_27 = bits(out_frontMask, 31, 24) node out_wimask_27 = andr(_out_wimask_T_27) node _out_romask_T_27 = bits(out_backMask, 31, 24) node out_romask_27 = orr(_out_romask_T_27) node _out_womask_T_27 = bits(out_backMask, 31, 24) node out_womask_27 = andr(_out_womask_T_27) node out_f_rivalid_27 = and(out_rivalid[27], out_rimask_27) node out_f_roready_27 = and(out_roready[27], out_romask_27) node out_f_wivalid_27 = and(out_wivalid[27], out_wimask_27) node out_f_woready_27 = and(out_woready[27], out_womask_27) node _out_T_303 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_27 when out_f_woready_27 : connect newBytes[3], _out_T_303 node _out_T_304 = and(out_f_rivalid_27, UInt<1>(0h1)) node _out_T_305 = and(UInt<1>(0h1), out_f_roready_27) node _out_T_306 = and(out_f_wivalid_27, UInt<1>(0h1)) node _out_T_307 = and(UInt<1>(0h1), out_f_woready_27) node _out_T_308 = eq(out_rimask_27, UInt<1>(0h0)) node _out_T_309 = eq(out_wimask_27, UInt<1>(0h0)) node _out_T_310 = eq(out_romask_27, UInt<1>(0h0)) node _out_T_311 = eq(out_womask_27, UInt<1>(0h0)) node _out_prepend_T_22 = or(_out_T_302, UInt<24>(0h0)) node out_prepend_22 = cat(oldBytes[3], _out_prepend_T_22) node _out_T_312 = or(out_prepend_22, UInt<32>(0h0)) node _out_T_313 = bits(_out_T_312, 31, 0) node _out_rimask_T_28 = bits(out_frontMask, 39, 32) node out_rimask_28 = orr(_out_rimask_T_28) node _out_wimask_T_28 = bits(out_frontMask, 39, 32) node out_wimask_28 = andr(_out_wimask_T_28) node _out_romask_T_28 = bits(out_backMask, 39, 32) node out_romask_28 = orr(_out_romask_T_28) node _out_womask_T_28 = bits(out_backMask, 39, 32) node out_womask_28 = andr(_out_womask_T_28) node out_f_rivalid_28 = and(out_rivalid[28], out_rimask_28) node out_f_roready_28 = and(out_roready[28], out_romask_28) node out_f_wivalid_28 = and(out_wivalid[28], out_wimask_28) node out_f_woready_28 = and(out_woready[28], out_womask_28) node _out_T_314 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_28 when out_f_woready_28 : connect newBytes[4], _out_T_314 node _out_T_315 = and(out_f_rivalid_28, UInt<1>(0h1)) node _out_T_316 = and(UInt<1>(0h1), out_f_roready_28) node _out_T_317 = and(out_f_wivalid_28, UInt<1>(0h1)) node _out_T_318 = and(UInt<1>(0h1), out_f_woready_28) node _out_T_319 = eq(out_rimask_28, UInt<1>(0h0)) node _out_T_320 = eq(out_wimask_28, UInt<1>(0h0)) node _out_T_321 = eq(out_romask_28, UInt<1>(0h0)) node _out_T_322 = eq(out_womask_28, UInt<1>(0h0)) node _out_prepend_T_23 = or(_out_T_313, UInt<32>(0h0)) node out_prepend_23 = cat(oldBytes[4], _out_prepend_T_23) node _out_T_323 = or(out_prepend_23, UInt<40>(0h0)) node _out_T_324 = bits(_out_T_323, 39, 0) node _out_rimask_T_29 = bits(out_frontMask, 47, 40) node out_rimask_29 = orr(_out_rimask_T_29) node _out_wimask_T_29 = bits(out_frontMask, 47, 40) node out_wimask_29 = andr(_out_wimask_T_29) node _out_romask_T_29 = bits(out_backMask, 47, 40) node out_romask_29 = orr(_out_romask_T_29) node _out_womask_T_29 = bits(out_backMask, 47, 40) node out_womask_29 = andr(_out_womask_T_29) node out_f_rivalid_29 = and(out_rivalid[29], out_rimask_29) node out_f_roready_29 = and(out_roready[29], out_romask_29) node out_f_wivalid_29 = and(out_wivalid[29], out_wimask_29) node out_f_woready_29 = and(out_woready[29], out_womask_29) node _out_T_325 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_29 when out_f_woready_29 : connect newBytes[5], _out_T_325 node _out_T_326 = and(out_f_rivalid_29, UInt<1>(0h1)) node _out_T_327 = and(UInt<1>(0h1), out_f_roready_29) node _out_T_328 = and(out_f_wivalid_29, UInt<1>(0h1)) node _out_T_329 = and(UInt<1>(0h1), out_f_woready_29) node _out_T_330 = eq(out_rimask_29, UInt<1>(0h0)) node _out_T_331 = eq(out_wimask_29, UInt<1>(0h0)) node _out_T_332 = eq(out_romask_29, UInt<1>(0h0)) node _out_T_333 = eq(out_womask_29, UInt<1>(0h0)) node _out_prepend_T_24 = or(_out_T_324, UInt<40>(0h0)) node out_prepend_24 = cat(oldBytes[5], _out_prepend_T_24) node _out_T_334 = or(out_prepend_24, UInt<48>(0h0)) node _out_T_335 = bits(_out_T_334, 47, 0) node _out_rimask_T_30 = bits(out_frontMask, 55, 48) node out_rimask_30 = orr(_out_rimask_T_30) node _out_wimask_T_30 = bits(out_frontMask, 55, 48) node out_wimask_30 = andr(_out_wimask_T_30) node _out_romask_T_30 = bits(out_backMask, 55, 48) node out_romask_30 = orr(_out_romask_T_30) node _out_womask_T_30 = bits(out_backMask, 55, 48) node out_womask_30 = andr(_out_womask_T_30) node out_f_rivalid_30 = and(out_rivalid[30], out_rimask_30) node out_f_roready_30 = and(out_roready[30], out_romask_30) node out_f_wivalid_30 = and(out_wivalid[30], out_wimask_30) node out_f_woready_30 = and(out_woready[30], out_womask_30) node _out_T_336 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_30 when out_f_woready_30 : connect newBytes[6], _out_T_336 node _out_T_337 = and(out_f_rivalid_30, UInt<1>(0h1)) node _out_T_338 = and(UInt<1>(0h1), out_f_roready_30) node _out_T_339 = and(out_f_wivalid_30, UInt<1>(0h1)) node _out_T_340 = and(UInt<1>(0h1), out_f_woready_30) node _out_T_341 = eq(out_rimask_30, UInt<1>(0h0)) node _out_T_342 = eq(out_wimask_30, UInt<1>(0h0)) node _out_T_343 = eq(out_romask_30, UInt<1>(0h0)) node _out_T_344 = eq(out_womask_30, UInt<1>(0h0)) node _out_prepend_T_25 = or(_out_T_335, UInt<48>(0h0)) node out_prepend_25 = cat(oldBytes[6], _out_prepend_T_25) node _out_T_345 = or(out_prepend_25, UInt<56>(0h0)) node _out_T_346 = bits(_out_T_345, 55, 0) node _out_rimask_T_31 = bits(out_frontMask, 63, 56) node out_rimask_31 = orr(_out_rimask_T_31) node _out_wimask_T_31 = bits(out_frontMask, 63, 56) node out_wimask_31 = andr(_out_wimask_T_31) node _out_romask_T_31 = bits(out_backMask, 63, 56) node out_romask_31 = orr(_out_romask_T_31) node _out_womask_T_31 = bits(out_backMask, 63, 56) node out_womask_31 = andr(_out_womask_T_31) node out_f_rivalid_31 = and(out_rivalid[31], out_rimask_31) node out_f_roready_31 = and(out_roready[31], out_romask_31) node out_f_wivalid_31 = and(out_wivalid[31], out_wimask_31) node out_f_woready_31 = and(out_woready[31], out_womask_31) node _out_T_347 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_31 when out_f_woready_31 : connect newBytes[7], _out_T_347 node _out_T_348 = and(out_f_rivalid_31, UInt<1>(0h1)) node _out_T_349 = and(UInt<1>(0h1), out_f_roready_31) node _out_T_350 = and(out_f_wivalid_31, UInt<1>(0h1)) node _out_T_351 = and(UInt<1>(0h1), out_f_woready_31) node _out_T_352 = eq(out_rimask_31, UInt<1>(0h0)) node _out_T_353 = eq(out_wimask_31, UInt<1>(0h0)) node _out_T_354 = eq(out_romask_31, UInt<1>(0h0)) node _out_T_355 = eq(out_womask_31, UInt<1>(0h0)) node _out_prepend_T_26 = or(_out_T_346, UInt<56>(0h0)) node out_prepend_26 = cat(oldBytes[7], _out_prepend_T_26) node _out_T_356 = or(out_prepend_26, UInt<64>(0h0)) node _out_T_357 = bits(_out_T_356, 63, 0) node _out_rimask_T_32 = bits(out_frontMask, 7, 0) node out_rimask_32 = orr(_out_rimask_T_32) node _out_wimask_T_32 = bits(out_frontMask, 7, 0) node out_wimask_32 = andr(_out_wimask_T_32) node _out_romask_T_32 = bits(out_backMask, 7, 0) node out_romask_32 = orr(_out_romask_T_32) node _out_womask_T_32 = bits(out_backMask, 7, 0) node out_womask_32 = andr(_out_womask_T_32) node out_f_rivalid_32 = and(out_rivalid[32], out_rimask_32) node out_f_roready_32 = and(out_roready[32], out_romask_32) node out_f_wivalid_32 = and(out_wivalid[32], out_wimask_32) node out_f_woready_32 = and(out_woready[32], out_womask_32) node _out_T_358 = bits(out_front.bits.data, 7, 0) connect valids_3[0], out_f_woready_32 when out_f_woready_32 : connect newBytes_3[0], _out_T_358 node _out_T_359 = and(out_f_rivalid_32, UInt<1>(0h1)) node _out_T_360 = and(UInt<1>(0h1), out_f_roready_32) node _out_T_361 = and(out_f_wivalid_32, UInt<1>(0h1)) node _out_T_362 = and(UInt<1>(0h1), out_f_woready_32) node _out_T_363 = eq(out_rimask_32, UInt<1>(0h0)) node _out_T_364 = eq(out_wimask_32, UInt<1>(0h0)) node _out_T_365 = eq(out_romask_32, UInt<1>(0h0)) node _out_T_366 = eq(out_womask_32, UInt<1>(0h0)) node _out_T_367 = or(oldBytes_3[0], UInt<8>(0h0)) node _out_T_368 = bits(_out_T_367, 7, 0) node _out_rimask_T_33 = bits(out_frontMask, 15, 8) node out_rimask_33 = orr(_out_rimask_T_33) node _out_wimask_T_33 = bits(out_frontMask, 15, 8) node out_wimask_33 = andr(_out_wimask_T_33) node _out_romask_T_33 = bits(out_backMask, 15, 8) node out_romask_33 = orr(_out_romask_T_33) node _out_womask_T_33 = bits(out_backMask, 15, 8) node out_womask_33 = andr(_out_womask_T_33) node out_f_rivalid_33 = and(out_rivalid[33], out_rimask_33) node out_f_roready_33 = and(out_roready[33], out_romask_33) node out_f_wivalid_33 = and(out_wivalid[33], out_wimask_33) node out_f_woready_33 = and(out_woready[33], out_womask_33) node _out_T_369 = bits(out_front.bits.data, 15, 8) connect valids_3[1], out_f_woready_33 when out_f_woready_33 : connect newBytes_3[1], _out_T_369 node _out_T_370 = and(out_f_rivalid_33, UInt<1>(0h1)) node _out_T_371 = and(UInt<1>(0h1), out_f_roready_33) node _out_T_372 = and(out_f_wivalid_33, UInt<1>(0h1)) node _out_T_373 = and(UInt<1>(0h1), out_f_woready_33) node _out_T_374 = eq(out_rimask_33, UInt<1>(0h0)) node _out_T_375 = eq(out_wimask_33, UInt<1>(0h0)) node _out_T_376 = eq(out_romask_33, UInt<1>(0h0)) node _out_T_377 = eq(out_womask_33, UInt<1>(0h0)) node _out_prepend_T_27 = or(_out_T_368, UInt<8>(0h0)) node out_prepend_27 = cat(oldBytes_3[1], _out_prepend_T_27) node _out_T_378 = or(out_prepend_27, UInt<16>(0h0)) node _out_T_379 = bits(_out_T_378, 15, 0) node _out_rimask_T_34 = bits(out_frontMask, 23, 16) node out_rimask_34 = orr(_out_rimask_T_34) node _out_wimask_T_34 = bits(out_frontMask, 23, 16) node out_wimask_34 = andr(_out_wimask_T_34) node _out_romask_T_34 = bits(out_backMask, 23, 16) node out_romask_34 = orr(_out_romask_T_34) node _out_womask_T_34 = bits(out_backMask, 23, 16) node out_womask_34 = andr(_out_womask_T_34) node out_f_rivalid_34 = and(out_rivalid[34], out_rimask_34) node out_f_roready_34 = and(out_roready[34], out_romask_34) node out_f_wivalid_34 = and(out_wivalid[34], out_wimask_34) node out_f_woready_34 = and(out_woready[34], out_womask_34) node _out_T_380 = bits(out_front.bits.data, 23, 16) connect valids_3[2], out_f_woready_34 when out_f_woready_34 : connect newBytes_3[2], _out_T_380 node _out_T_381 = and(out_f_rivalid_34, UInt<1>(0h1)) node _out_T_382 = and(UInt<1>(0h1), out_f_roready_34) node _out_T_383 = and(out_f_wivalid_34, UInt<1>(0h1)) node _out_T_384 = and(UInt<1>(0h1), out_f_woready_34) node _out_T_385 = eq(out_rimask_34, UInt<1>(0h0)) node _out_T_386 = eq(out_wimask_34, UInt<1>(0h0)) node _out_T_387 = eq(out_romask_34, UInt<1>(0h0)) node _out_T_388 = eq(out_womask_34, UInt<1>(0h0)) node _out_prepend_T_28 = or(_out_T_379, UInt<16>(0h0)) node out_prepend_28 = cat(oldBytes_3[2], _out_prepend_T_28) node _out_T_389 = or(out_prepend_28, UInt<24>(0h0)) node _out_T_390 = bits(_out_T_389, 23, 0) node _out_rimask_T_35 = bits(out_frontMask, 31, 24) node out_rimask_35 = orr(_out_rimask_T_35) node _out_wimask_T_35 = bits(out_frontMask, 31, 24) node out_wimask_35 = andr(_out_wimask_T_35) node _out_romask_T_35 = bits(out_backMask, 31, 24) node out_romask_35 = orr(_out_romask_T_35) node _out_womask_T_35 = bits(out_backMask, 31, 24) node out_womask_35 = andr(_out_womask_T_35) node out_f_rivalid_35 = and(out_rivalid[35], out_rimask_35) node out_f_roready_35 = and(out_roready[35], out_romask_35) node out_f_wivalid_35 = and(out_wivalid[35], out_wimask_35) node out_f_woready_35 = and(out_woready[35], out_womask_35) node _out_T_391 = bits(out_front.bits.data, 31, 24) connect valids_3[3], out_f_woready_35 when out_f_woready_35 : connect newBytes_3[3], _out_T_391 node _out_T_392 = and(out_f_rivalid_35, UInt<1>(0h1)) node _out_T_393 = and(UInt<1>(0h1), out_f_roready_35) node _out_T_394 = and(out_f_wivalid_35, UInt<1>(0h1)) node _out_T_395 = and(UInt<1>(0h1), out_f_woready_35) node _out_T_396 = eq(out_rimask_35, UInt<1>(0h0)) node _out_T_397 = eq(out_wimask_35, UInt<1>(0h0)) node _out_T_398 = eq(out_romask_35, UInt<1>(0h0)) node _out_T_399 = eq(out_womask_35, UInt<1>(0h0)) node _out_prepend_T_29 = or(_out_T_390, UInt<24>(0h0)) node out_prepend_29 = cat(oldBytes_3[3], _out_prepend_T_29) node _out_T_400 = or(out_prepend_29, UInt<32>(0h0)) node _out_T_401 = bits(_out_T_400, 31, 0) node _out_rimask_T_36 = bits(out_frontMask, 39, 32) node out_rimask_36 = orr(_out_rimask_T_36) node _out_wimask_T_36 = bits(out_frontMask, 39, 32) node out_wimask_36 = andr(_out_wimask_T_36) node _out_romask_T_36 = bits(out_backMask, 39, 32) node out_romask_36 = orr(_out_romask_T_36) node _out_womask_T_36 = bits(out_backMask, 39, 32) node out_womask_36 = andr(_out_womask_T_36) node out_f_rivalid_36 = and(out_rivalid[36], out_rimask_36) node out_f_roready_36 = and(out_roready[36], out_romask_36) node out_f_wivalid_36 = and(out_wivalid[36], out_wimask_36) node out_f_woready_36 = and(out_woready[36], out_womask_36) node _out_T_402 = bits(out_front.bits.data, 39, 32) connect valids_3[4], out_f_woready_36 when out_f_woready_36 : connect newBytes_3[4], _out_T_402 node _out_T_403 = and(out_f_rivalid_36, UInt<1>(0h1)) node _out_T_404 = and(UInt<1>(0h1), out_f_roready_36) node _out_T_405 = and(out_f_wivalid_36, UInt<1>(0h1)) node _out_T_406 = and(UInt<1>(0h1), out_f_woready_36) node _out_T_407 = eq(out_rimask_36, UInt<1>(0h0)) node _out_T_408 = eq(out_wimask_36, UInt<1>(0h0)) node _out_T_409 = eq(out_romask_36, UInt<1>(0h0)) node _out_T_410 = eq(out_womask_36, UInt<1>(0h0)) node _out_prepend_T_30 = or(_out_T_401, UInt<32>(0h0)) node out_prepend_30 = cat(oldBytes_3[4], _out_prepend_T_30) node _out_T_411 = or(out_prepend_30, UInt<40>(0h0)) node _out_T_412 = bits(_out_T_411, 39, 0) node _out_rimask_T_37 = bits(out_frontMask, 47, 40) node out_rimask_37 = orr(_out_rimask_T_37) node _out_wimask_T_37 = bits(out_frontMask, 47, 40) node out_wimask_37 = andr(_out_wimask_T_37) node _out_romask_T_37 = bits(out_backMask, 47, 40) node out_romask_37 = orr(_out_romask_T_37) node _out_womask_T_37 = bits(out_backMask, 47, 40) node out_womask_37 = andr(_out_womask_T_37) node out_f_rivalid_37 = and(out_rivalid[37], out_rimask_37) node out_f_roready_37 = and(out_roready[37], out_romask_37) node out_f_wivalid_37 = and(out_wivalid[37], out_wimask_37) node out_f_woready_37 = and(out_woready[37], out_womask_37) node _out_T_413 = bits(out_front.bits.data, 47, 40) connect valids_3[5], out_f_woready_37 when out_f_woready_37 : connect newBytes_3[5], _out_T_413 node _out_T_414 = and(out_f_rivalid_37, UInt<1>(0h1)) node _out_T_415 = and(UInt<1>(0h1), out_f_roready_37) node _out_T_416 = and(out_f_wivalid_37, UInt<1>(0h1)) node _out_T_417 = and(UInt<1>(0h1), out_f_woready_37) node _out_T_418 = eq(out_rimask_37, UInt<1>(0h0)) node _out_T_419 = eq(out_wimask_37, UInt<1>(0h0)) node _out_T_420 = eq(out_romask_37, UInt<1>(0h0)) node _out_T_421 = eq(out_womask_37, UInt<1>(0h0)) node _out_prepend_T_31 = or(_out_T_412, UInt<40>(0h0)) node out_prepend_31 = cat(oldBytes_3[5], _out_prepend_T_31) node _out_T_422 = or(out_prepend_31, UInt<48>(0h0)) node _out_T_423 = bits(_out_T_422, 47, 0) node _out_rimask_T_38 = bits(out_frontMask, 55, 48) node out_rimask_38 = orr(_out_rimask_T_38) node _out_wimask_T_38 = bits(out_frontMask, 55, 48) node out_wimask_38 = andr(_out_wimask_T_38) node _out_romask_T_38 = bits(out_backMask, 55, 48) node out_romask_38 = orr(_out_romask_T_38) node _out_womask_T_38 = bits(out_backMask, 55, 48) node out_womask_38 = andr(_out_womask_T_38) node out_f_rivalid_38 = and(out_rivalid[38], out_rimask_38) node out_f_roready_38 = and(out_roready[38], out_romask_38) node out_f_wivalid_38 = and(out_wivalid[38], out_wimask_38) node out_f_woready_38 = and(out_woready[38], out_womask_38) node _out_T_424 = bits(out_front.bits.data, 55, 48) connect valids_3[6], out_f_woready_38 when out_f_woready_38 : connect newBytes_3[6], _out_T_424 node _out_T_425 = and(out_f_rivalid_38, UInt<1>(0h1)) node _out_T_426 = and(UInt<1>(0h1), out_f_roready_38) node _out_T_427 = and(out_f_wivalid_38, UInt<1>(0h1)) node _out_T_428 = and(UInt<1>(0h1), out_f_woready_38) node _out_T_429 = eq(out_rimask_38, UInt<1>(0h0)) node _out_T_430 = eq(out_wimask_38, UInt<1>(0h0)) node _out_T_431 = eq(out_romask_38, UInt<1>(0h0)) node _out_T_432 = eq(out_womask_38, UInt<1>(0h0)) node _out_prepend_T_32 = or(_out_T_423, UInt<48>(0h0)) node out_prepend_32 = cat(oldBytes_3[6], _out_prepend_T_32) node _out_T_433 = or(out_prepend_32, UInt<56>(0h0)) node _out_T_434 = bits(_out_T_433, 55, 0) node _out_rimask_T_39 = bits(out_frontMask, 63, 56) node out_rimask_39 = orr(_out_rimask_T_39) node _out_wimask_T_39 = bits(out_frontMask, 63, 56) node out_wimask_39 = andr(_out_wimask_T_39) node _out_romask_T_39 = bits(out_backMask, 63, 56) node out_romask_39 = orr(_out_romask_T_39) node _out_womask_T_39 = bits(out_backMask, 63, 56) node out_womask_39 = andr(_out_womask_T_39) node out_f_rivalid_39 = and(out_rivalid[39], out_rimask_39) node out_f_roready_39 = and(out_roready[39], out_romask_39) node out_f_wivalid_39 = and(out_wivalid[39], out_wimask_39) node out_f_woready_39 = and(out_woready[39], out_womask_39) node _out_T_435 = bits(out_front.bits.data, 63, 56) connect valids_3[7], out_f_woready_39 when out_f_woready_39 : connect newBytes_3[7], _out_T_435 node _out_T_436 = and(out_f_rivalid_39, UInt<1>(0h1)) node _out_T_437 = and(UInt<1>(0h1), out_f_roready_39) node _out_T_438 = and(out_f_wivalid_39, UInt<1>(0h1)) node _out_T_439 = and(UInt<1>(0h1), out_f_woready_39) node _out_T_440 = eq(out_rimask_39, UInt<1>(0h0)) node _out_T_441 = eq(out_wimask_39, UInt<1>(0h0)) node _out_T_442 = eq(out_romask_39, UInt<1>(0h0)) node _out_T_443 = eq(out_womask_39, UInt<1>(0h0)) node _out_prepend_T_33 = or(_out_T_434, UInt<56>(0h0)) node out_prepend_33 = cat(oldBytes_3[7], _out_prepend_T_33) node _out_T_444 = or(out_prepend_33, UInt<64>(0h0)) node _out_T_445 = bits(_out_T_444, 63, 0) node _out_rimask_T_40 = bits(out_frontMask, 7, 0) node out_rimask_40 = orr(_out_rimask_T_40) node _out_wimask_T_40 = bits(out_frontMask, 7, 0) node out_wimask_40 = andr(_out_wimask_T_40) node _out_romask_T_40 = bits(out_backMask, 7, 0) node out_romask_40 = orr(_out_romask_T_40) node _out_womask_T_40 = bits(out_backMask, 7, 0) node out_womask_40 = andr(_out_womask_T_40) node out_f_rivalid_40 = and(out_rivalid[40], out_rimask_40) node out_f_roready_40 = and(out_roready[40], out_romask_40) node out_f_wivalid_40 = and(out_wivalid[40], out_wimask_40) node out_f_woready_40 = and(out_woready[40], out_womask_40) node _out_T_446 = bits(out_front.bits.data, 7, 0) connect valids_2[0], out_f_woready_40 when out_f_woready_40 : connect newBytes_2[0], _out_T_446 node _out_T_447 = and(out_f_rivalid_40, UInt<1>(0h1)) node _out_T_448 = and(UInt<1>(0h1), out_f_roready_40) node _out_T_449 = and(out_f_wivalid_40, UInt<1>(0h1)) node _out_T_450 = and(UInt<1>(0h1), out_f_woready_40) node _out_T_451 = eq(out_rimask_40, UInt<1>(0h0)) node _out_T_452 = eq(out_wimask_40, UInt<1>(0h0)) node _out_T_453 = eq(out_romask_40, UInt<1>(0h0)) node _out_T_454 = eq(out_womask_40, UInt<1>(0h0)) node _out_T_455 = or(oldBytes_2[0], UInt<8>(0h0)) node _out_T_456 = bits(_out_T_455, 7, 0) node _out_rimask_T_41 = bits(out_frontMask, 15, 8) node out_rimask_41 = orr(_out_rimask_T_41) node _out_wimask_T_41 = bits(out_frontMask, 15, 8) node out_wimask_41 = andr(_out_wimask_T_41) node _out_romask_T_41 = bits(out_backMask, 15, 8) node out_romask_41 = orr(_out_romask_T_41) node _out_womask_T_41 = bits(out_backMask, 15, 8) node out_womask_41 = andr(_out_womask_T_41) node out_f_rivalid_41 = and(out_rivalid[41], out_rimask_41) node out_f_roready_41 = and(out_roready[41], out_romask_41) node out_f_wivalid_41 = and(out_wivalid[41], out_wimask_41) node out_f_woready_41 = and(out_woready[41], out_womask_41) node _out_T_457 = bits(out_front.bits.data, 15, 8) connect valids_2[1], out_f_woready_41 when out_f_woready_41 : connect newBytes_2[1], _out_T_457 node _out_T_458 = and(out_f_rivalid_41, UInt<1>(0h1)) node _out_T_459 = and(UInt<1>(0h1), out_f_roready_41) node _out_T_460 = and(out_f_wivalid_41, UInt<1>(0h1)) node _out_T_461 = and(UInt<1>(0h1), out_f_woready_41) node _out_T_462 = eq(out_rimask_41, UInt<1>(0h0)) node _out_T_463 = eq(out_wimask_41, UInt<1>(0h0)) node _out_T_464 = eq(out_romask_41, UInt<1>(0h0)) node _out_T_465 = eq(out_womask_41, UInt<1>(0h0)) node _out_prepend_T_34 = or(_out_T_456, UInt<8>(0h0)) node out_prepend_34 = cat(oldBytes_2[1], _out_prepend_T_34) node _out_T_466 = or(out_prepend_34, UInt<16>(0h0)) node _out_T_467 = bits(_out_T_466, 15, 0) node _out_rimask_T_42 = bits(out_frontMask, 23, 16) node out_rimask_42 = orr(_out_rimask_T_42) node _out_wimask_T_42 = bits(out_frontMask, 23, 16) node out_wimask_42 = andr(_out_wimask_T_42) node _out_romask_T_42 = bits(out_backMask, 23, 16) node out_romask_42 = orr(_out_romask_T_42) node _out_womask_T_42 = bits(out_backMask, 23, 16) node out_womask_42 = andr(_out_womask_T_42) node out_f_rivalid_42 = and(out_rivalid[42], out_rimask_42) node out_f_roready_42 = and(out_roready[42], out_romask_42) node out_f_wivalid_42 = and(out_wivalid[42], out_wimask_42) node out_f_woready_42 = and(out_woready[42], out_womask_42) node _out_T_468 = bits(out_front.bits.data, 23, 16) connect valids_2[2], out_f_woready_42 when out_f_woready_42 : connect newBytes_2[2], _out_T_468 node _out_T_469 = and(out_f_rivalid_42, UInt<1>(0h1)) node _out_T_470 = and(UInt<1>(0h1), out_f_roready_42) node _out_T_471 = and(out_f_wivalid_42, UInt<1>(0h1)) node _out_T_472 = and(UInt<1>(0h1), out_f_woready_42) node _out_T_473 = eq(out_rimask_42, UInt<1>(0h0)) node _out_T_474 = eq(out_wimask_42, UInt<1>(0h0)) node _out_T_475 = eq(out_romask_42, UInt<1>(0h0)) node _out_T_476 = eq(out_womask_42, UInt<1>(0h0)) node _out_prepend_T_35 = or(_out_T_467, UInt<16>(0h0)) node out_prepend_35 = cat(oldBytes_2[2], _out_prepend_T_35) node _out_T_477 = or(out_prepend_35, UInt<24>(0h0)) node _out_T_478 = bits(_out_T_477, 23, 0) node _out_rimask_T_43 = bits(out_frontMask, 31, 24) node out_rimask_43 = orr(_out_rimask_T_43) node _out_wimask_T_43 = bits(out_frontMask, 31, 24) node out_wimask_43 = andr(_out_wimask_T_43) node _out_romask_T_43 = bits(out_backMask, 31, 24) node out_romask_43 = orr(_out_romask_T_43) node _out_womask_T_43 = bits(out_backMask, 31, 24) node out_womask_43 = andr(_out_womask_T_43) node out_f_rivalid_43 = and(out_rivalid[43], out_rimask_43) node out_f_roready_43 = and(out_roready[43], out_romask_43) node out_f_wivalid_43 = and(out_wivalid[43], out_wimask_43) node out_f_woready_43 = and(out_woready[43], out_womask_43) node _out_T_479 = bits(out_front.bits.data, 31, 24) connect valids_2[3], out_f_woready_43 when out_f_woready_43 : connect newBytes_2[3], _out_T_479 node _out_T_480 = and(out_f_rivalid_43, UInt<1>(0h1)) node _out_T_481 = and(UInt<1>(0h1), out_f_roready_43) node _out_T_482 = and(out_f_wivalid_43, UInt<1>(0h1)) node _out_T_483 = and(UInt<1>(0h1), out_f_woready_43) node _out_T_484 = eq(out_rimask_43, UInt<1>(0h0)) node _out_T_485 = eq(out_wimask_43, UInt<1>(0h0)) node _out_T_486 = eq(out_romask_43, UInt<1>(0h0)) node _out_T_487 = eq(out_womask_43, UInt<1>(0h0)) node _out_prepend_T_36 = or(_out_T_478, UInt<24>(0h0)) node out_prepend_36 = cat(oldBytes_2[3], _out_prepend_T_36) node _out_T_488 = or(out_prepend_36, UInt<32>(0h0)) node _out_T_489 = bits(_out_T_488, 31, 0) node _out_rimask_T_44 = bits(out_frontMask, 39, 32) node out_rimask_44 = orr(_out_rimask_T_44) node _out_wimask_T_44 = bits(out_frontMask, 39, 32) node out_wimask_44 = andr(_out_wimask_T_44) node _out_romask_T_44 = bits(out_backMask, 39, 32) node out_romask_44 = orr(_out_romask_T_44) node _out_womask_T_44 = bits(out_backMask, 39, 32) node out_womask_44 = andr(_out_womask_T_44) node out_f_rivalid_44 = and(out_rivalid[44], out_rimask_44) node out_f_roready_44 = and(out_roready[44], out_romask_44) node out_f_wivalid_44 = and(out_wivalid[44], out_wimask_44) node out_f_woready_44 = and(out_woready[44], out_womask_44) node _out_T_490 = bits(out_front.bits.data, 39, 32) connect valids_2[4], out_f_woready_44 when out_f_woready_44 : connect newBytes_2[4], _out_T_490 node _out_T_491 = and(out_f_rivalid_44, UInt<1>(0h1)) node _out_T_492 = and(UInt<1>(0h1), out_f_roready_44) node _out_T_493 = and(out_f_wivalid_44, UInt<1>(0h1)) node _out_T_494 = and(UInt<1>(0h1), out_f_woready_44) node _out_T_495 = eq(out_rimask_44, UInt<1>(0h0)) node _out_T_496 = eq(out_wimask_44, UInt<1>(0h0)) node _out_T_497 = eq(out_romask_44, UInt<1>(0h0)) node _out_T_498 = eq(out_womask_44, UInt<1>(0h0)) node _out_prepend_T_37 = or(_out_T_489, UInt<32>(0h0)) node out_prepend_37 = cat(oldBytes_2[4], _out_prepend_T_37) node _out_T_499 = or(out_prepend_37, UInt<40>(0h0)) node _out_T_500 = bits(_out_T_499, 39, 0) node _out_rimask_T_45 = bits(out_frontMask, 47, 40) node out_rimask_45 = orr(_out_rimask_T_45) node _out_wimask_T_45 = bits(out_frontMask, 47, 40) node out_wimask_45 = andr(_out_wimask_T_45) node _out_romask_T_45 = bits(out_backMask, 47, 40) node out_romask_45 = orr(_out_romask_T_45) node _out_womask_T_45 = bits(out_backMask, 47, 40) node out_womask_45 = andr(_out_womask_T_45) node out_f_rivalid_45 = and(out_rivalid[45], out_rimask_45) node out_f_roready_45 = and(out_roready[45], out_romask_45) node out_f_wivalid_45 = and(out_wivalid[45], out_wimask_45) node out_f_woready_45 = and(out_woready[45], out_womask_45) node _out_T_501 = bits(out_front.bits.data, 47, 40) connect valids_2[5], out_f_woready_45 when out_f_woready_45 : connect newBytes_2[5], _out_T_501 node _out_T_502 = and(out_f_rivalid_45, UInt<1>(0h1)) node _out_T_503 = and(UInt<1>(0h1), out_f_roready_45) node _out_T_504 = and(out_f_wivalid_45, UInt<1>(0h1)) node _out_T_505 = and(UInt<1>(0h1), out_f_woready_45) node _out_T_506 = eq(out_rimask_45, UInt<1>(0h0)) node _out_T_507 = eq(out_wimask_45, UInt<1>(0h0)) node _out_T_508 = eq(out_romask_45, UInt<1>(0h0)) node _out_T_509 = eq(out_womask_45, UInt<1>(0h0)) node _out_prepend_T_38 = or(_out_T_500, UInt<40>(0h0)) node out_prepend_38 = cat(oldBytes_2[5], _out_prepend_T_38) node _out_T_510 = or(out_prepend_38, UInt<48>(0h0)) node _out_T_511 = bits(_out_T_510, 47, 0) node _out_rimask_T_46 = bits(out_frontMask, 55, 48) node out_rimask_46 = orr(_out_rimask_T_46) node _out_wimask_T_46 = bits(out_frontMask, 55, 48) node out_wimask_46 = andr(_out_wimask_T_46) node _out_romask_T_46 = bits(out_backMask, 55, 48) node out_romask_46 = orr(_out_romask_T_46) node _out_womask_T_46 = bits(out_backMask, 55, 48) node out_womask_46 = andr(_out_womask_T_46) node out_f_rivalid_46 = and(out_rivalid[46], out_rimask_46) node out_f_roready_46 = and(out_roready[46], out_romask_46) node out_f_wivalid_46 = and(out_wivalid[46], out_wimask_46) node out_f_woready_46 = and(out_woready[46], out_womask_46) node _out_T_512 = bits(out_front.bits.data, 55, 48) connect valids_2[6], out_f_woready_46 when out_f_woready_46 : connect newBytes_2[6], _out_T_512 node _out_T_513 = and(out_f_rivalid_46, UInt<1>(0h1)) node _out_T_514 = and(UInt<1>(0h1), out_f_roready_46) node _out_T_515 = and(out_f_wivalid_46, UInt<1>(0h1)) node _out_T_516 = and(UInt<1>(0h1), out_f_woready_46) node _out_T_517 = eq(out_rimask_46, UInt<1>(0h0)) node _out_T_518 = eq(out_wimask_46, UInt<1>(0h0)) node _out_T_519 = eq(out_romask_46, UInt<1>(0h0)) node _out_T_520 = eq(out_womask_46, UInt<1>(0h0)) node _out_prepend_T_39 = or(_out_T_511, UInt<48>(0h0)) node out_prepend_39 = cat(oldBytes_2[6], _out_prepend_T_39) node _out_T_521 = or(out_prepend_39, UInt<56>(0h0)) node _out_T_522 = bits(_out_T_521, 55, 0) node _out_rimask_T_47 = bits(out_frontMask, 63, 56) node out_rimask_47 = orr(_out_rimask_T_47) node _out_wimask_T_47 = bits(out_frontMask, 63, 56) node out_wimask_47 = andr(_out_wimask_T_47) node _out_romask_T_47 = bits(out_backMask, 63, 56) node out_romask_47 = orr(_out_romask_T_47) node _out_womask_T_47 = bits(out_backMask, 63, 56) node out_womask_47 = andr(_out_womask_T_47) node out_f_rivalid_47 = and(out_rivalid[47], out_rimask_47) node out_f_roready_47 = and(out_roready[47], out_romask_47) node out_f_wivalid_47 = and(out_wivalid[47], out_wimask_47) node out_f_woready_47 = and(out_woready[47], out_womask_47) node _out_T_523 = bits(out_front.bits.data, 63, 56) connect valids_2[7], out_f_woready_47 when out_f_woready_47 : connect newBytes_2[7], _out_T_523 node _out_T_524 = and(out_f_rivalid_47, UInt<1>(0h1)) node _out_T_525 = and(UInt<1>(0h1), out_f_roready_47) node _out_T_526 = and(out_f_wivalid_47, UInt<1>(0h1)) node _out_T_527 = and(UInt<1>(0h1), out_f_woready_47) node _out_T_528 = eq(out_rimask_47, UInt<1>(0h0)) node _out_T_529 = eq(out_wimask_47, UInt<1>(0h0)) node _out_T_530 = eq(out_romask_47, UInt<1>(0h0)) node _out_T_531 = eq(out_womask_47, UInt<1>(0h0)) node _out_prepend_T_40 = or(_out_T_522, UInt<56>(0h0)) node out_prepend_40 = cat(oldBytes_2[7], _out_prepend_T_40) node _out_T_532 = or(out_prepend_40, UInt<64>(0h0)) node _out_T_533 = bits(_out_T_532, 63, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12) node out_iindex_hi = cat(_out_iindex_T_11, _out_iindex_T_1) node out_iindex = cat(out_iindex_hi, _out_iindex_T) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_oindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_oindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_oindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_oindex_T_12 = bits(out_front.bits.index, 12, 12) node out_oindex_hi = cat(_out_oindex_T_11, _out_oindex_T_1) node out_oindex = cat(out_oindex_hi, _out_oindex_T) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node out_frontSel_4 = bits(_out_frontSel_T, 4, 4) node out_frontSel_5 = bits(_out_frontSel_T, 5, 5) node out_frontSel_6 = bits(_out_frontSel_T, 6, 6) node out_frontSel_7 = bits(_out_frontSel_T, 7, 7) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node out_backSel_4 = bits(_out_backSel_T, 4, 4) node out_backSel_5 = bits(_out_backSel_T, 5, 5) node out_backSel_6 = bits(_out_backSel_T, 6, 6) node out_backSel_7 = bits(_out_backSel_T, 7, 7) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_4) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[15], _out_rifireMux_T_7 connect out_rivalid[14], _out_rifireMux_T_7 connect out_rivalid[13], _out_rifireMux_T_7 connect out_rivalid[12], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, UInt<1>(0h1)) connect out_rifireMux_out_2, UInt<1>(0h1) node _out_rifireMux_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[23], _out_rifireMux_T_15 connect out_rivalid[22], _out_rifireMux_T_15 connect out_rivalid[21], _out_rifireMux_T_15 connect out_rivalid[20], _out_rifireMux_T_15 connect out_rivalid[19], _out_rifireMux_T_15 connect out_rivalid[18], _out_rifireMux_T_15 connect out_rivalid[17], _out_rifireMux_T_15 connect out_rivalid[16], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) wire out_rifireMux_out_4 : UInt<1> node _out_rifireMux_T_18 = and(_out_rifireMux_T_1, out_frontSel_4) node _out_rifireMux_T_19 = and(_out_rifireMux_T_18, _out_T_8) connect out_rifireMux_out_4, UInt<1>(0h1) connect out_rivalid[31], _out_rifireMux_T_19 connect out_rivalid[30], _out_rifireMux_T_19 connect out_rivalid[29], _out_rifireMux_T_19 connect out_rivalid[28], _out_rifireMux_T_19 connect out_rivalid[27], _out_rifireMux_T_19 connect out_rivalid[26], _out_rifireMux_T_19 connect out_rivalid[25], _out_rifireMux_T_19 connect out_rivalid[24], _out_rifireMux_T_19 node _out_rifireMux_T_20 = eq(_out_T_8, UInt<1>(0h0)) node _out_rifireMux_T_21 = or(out_rifireMux_out_4, _out_rifireMux_T_20) wire out_rifireMux_out_5 : UInt<1> node _out_rifireMux_T_22 = and(_out_rifireMux_T_1, out_frontSel_5) node _out_rifireMux_T_23 = and(_out_rifireMux_T_22, _out_T_2) connect out_rifireMux_out_5, UInt<1>(0h1) connect out_rivalid[11], _out_rifireMux_T_23 connect out_rivalid[10], _out_rifireMux_T_23 connect out_rivalid[9], _out_rifireMux_T_23 connect out_rivalid[8], _out_rifireMux_T_23 connect out_rivalid[7], _out_rifireMux_T_23 connect out_rivalid[6], _out_rifireMux_T_23 connect out_rivalid[5], _out_rifireMux_T_23 connect out_rivalid[4], _out_rifireMux_T_23 node _out_rifireMux_T_24 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_25 = or(out_rifireMux_out_5, _out_rifireMux_T_24) wire out_rifireMux_out_6 : UInt<1> node _out_rifireMux_T_26 = and(_out_rifireMux_T_1, out_frontSel_6) node _out_rifireMux_T_27 = and(_out_rifireMux_T_26, _out_T_12) connect out_rifireMux_out_6, UInt<1>(0h1) connect out_rivalid[47], _out_rifireMux_T_27 connect out_rivalid[46], _out_rifireMux_T_27 connect out_rivalid[45], _out_rifireMux_T_27 connect out_rivalid[44], _out_rifireMux_T_27 connect out_rivalid[43], _out_rifireMux_T_27 connect out_rivalid[42], _out_rifireMux_T_27 connect out_rivalid[41], _out_rifireMux_T_27 connect out_rivalid[40], _out_rifireMux_T_27 node _out_rifireMux_T_28 = eq(_out_T_12, UInt<1>(0h0)) node _out_rifireMux_T_29 = or(out_rifireMux_out_6, _out_rifireMux_T_28) wire out_rifireMux_out_7 : UInt<1> node _out_rifireMux_T_30 = and(_out_rifireMux_T_1, out_frontSel_7) node _out_rifireMux_T_31 = and(_out_rifireMux_T_30, _out_T_10) connect out_rifireMux_out_7, UInt<1>(0h1) connect out_rivalid[39], _out_rifireMux_T_31 connect out_rivalid[38], _out_rifireMux_T_31 connect out_rivalid[37], _out_rifireMux_T_31 connect out_rivalid[36], _out_rifireMux_T_31 connect out_rivalid[35], _out_rifireMux_T_31 connect out_rivalid[34], _out_rifireMux_T_31 connect out_rivalid[33], _out_rifireMux_T_31 connect out_rivalid[32], _out_rifireMux_T_31 node _out_rifireMux_T_32 = eq(_out_T_10, UInt<1>(0h0)) node _out_rifireMux_T_33 = or(out_rifireMux_out_7, _out_rifireMux_T_32) node _out_rifireMux_T_34 = geq(out_iindex, UInt<4>(0h8)) wire _out_rifireMux_WIRE : UInt<1>[8] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 connect _out_rifireMux_WIRE[4], _out_rifireMux_T_21 connect _out_rifireMux_WIRE[5], _out_rifireMux_T_25 connect _out_rifireMux_WIRE[6], _out_rifireMux_T_29 connect _out_rifireMux_WIRE[7], _out_rifireMux_T_33 node out_rifireMux = mux(_out_rifireMux_T_34, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_4) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[15], _out_wifireMux_T_8 connect out_wivalid[14], _out_wifireMux_T_8 connect out_wivalid[13], _out_wifireMux_T_8 connect out_wivalid[12], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, UInt<1>(0h1)) connect out_wifireMux_out_2, UInt<1>(0h1) node _out_wifireMux_T_13 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6) connect out_wifireMux_out_3, UInt<1>(0h1) connect out_wivalid[23], _out_wifireMux_T_16 connect out_wivalid[22], _out_wifireMux_T_16 connect out_wivalid[21], _out_wifireMux_T_16 connect out_wivalid[20], _out_wifireMux_T_16 connect out_wivalid[19], _out_wifireMux_T_16 connect out_wivalid[18], _out_wifireMux_T_16 connect out_wivalid[17], _out_wifireMux_T_16 connect out_wivalid[16], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) wire out_wifireMux_out_4 : UInt<1> node _out_wifireMux_T_19 = and(_out_wifireMux_T_2, out_frontSel_4) node _out_wifireMux_T_20 = and(_out_wifireMux_T_19, _out_T_8) connect out_wifireMux_out_4, UInt<1>(0h1) connect out_wivalid[31], _out_wifireMux_T_20 connect out_wivalid[30], _out_wifireMux_T_20 connect out_wivalid[29], _out_wifireMux_T_20 connect out_wivalid[28], _out_wifireMux_T_20 connect out_wivalid[27], _out_wifireMux_T_20 connect out_wivalid[26], _out_wifireMux_T_20 connect out_wivalid[25], _out_wifireMux_T_20 connect out_wivalid[24], _out_wifireMux_T_20 node _out_wifireMux_T_21 = eq(_out_T_8, UInt<1>(0h0)) node _out_wifireMux_T_22 = or(out_wifireMux_out_4, _out_wifireMux_T_21) wire out_wifireMux_out_5 : UInt<1> node _out_wifireMux_T_23 = and(_out_wifireMux_T_2, out_frontSel_5) node _out_wifireMux_T_24 = and(_out_wifireMux_T_23, _out_T_2) connect out_wifireMux_out_5, UInt<1>(0h1) connect out_wivalid[11], _out_wifireMux_T_24 connect out_wivalid[10], _out_wifireMux_T_24 connect out_wivalid[9], _out_wifireMux_T_24 connect out_wivalid[8], _out_wifireMux_T_24 connect out_wivalid[7], _out_wifireMux_T_24 connect out_wivalid[6], _out_wifireMux_T_24 connect out_wivalid[5], _out_wifireMux_T_24 connect out_wivalid[4], _out_wifireMux_T_24 node _out_wifireMux_T_25 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_26 = or(out_wifireMux_out_5, _out_wifireMux_T_25) wire out_wifireMux_out_6 : UInt<1> node _out_wifireMux_T_27 = and(_out_wifireMux_T_2, out_frontSel_6) node _out_wifireMux_T_28 = and(_out_wifireMux_T_27, _out_T_12) connect out_wifireMux_out_6, UInt<1>(0h1) connect out_wivalid[47], _out_wifireMux_T_28 connect out_wivalid[46], _out_wifireMux_T_28 connect out_wivalid[45], _out_wifireMux_T_28 connect out_wivalid[44], _out_wifireMux_T_28 connect out_wivalid[43], _out_wifireMux_T_28 connect out_wivalid[42], _out_wifireMux_T_28 connect out_wivalid[41], _out_wifireMux_T_28 connect out_wivalid[40], _out_wifireMux_T_28 node _out_wifireMux_T_29 = eq(_out_T_12, UInt<1>(0h0)) node _out_wifireMux_T_30 = or(out_wifireMux_out_6, _out_wifireMux_T_29) wire out_wifireMux_out_7 : UInt<1> node _out_wifireMux_T_31 = and(_out_wifireMux_T_2, out_frontSel_7) node _out_wifireMux_T_32 = and(_out_wifireMux_T_31, _out_T_10) connect out_wifireMux_out_7, UInt<1>(0h1) connect out_wivalid[39], _out_wifireMux_T_32 connect out_wivalid[38], _out_wifireMux_T_32 connect out_wivalid[37], _out_wifireMux_T_32 connect out_wivalid[36], _out_wifireMux_T_32 connect out_wivalid[35], _out_wifireMux_T_32 connect out_wivalid[34], _out_wifireMux_T_32 connect out_wivalid[33], _out_wifireMux_T_32 connect out_wivalid[32], _out_wifireMux_T_32 node _out_wifireMux_T_33 = eq(_out_T_10, UInt<1>(0h0)) node _out_wifireMux_T_34 = or(out_wifireMux_out_7, _out_wifireMux_T_33) node _out_wifireMux_T_35 = geq(out_iindex, UInt<4>(0h8)) wire _out_wifireMux_WIRE : UInt<1>[8] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 connect _out_wifireMux_WIRE[4], _out_wifireMux_T_22 connect _out_wifireMux_WIRE[5], _out_wifireMux_T_26 connect _out_wifireMux_WIRE[6], _out_wifireMux_T_30 connect _out_wifireMux_WIRE[7], _out_wifireMux_T_34 node out_wifireMux = mux(_out_wifireMux_T_35, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_5) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[15], _out_rofireMux_T_7 connect out_roready[14], _out_rofireMux_T_7 connect out_roready[13], _out_rofireMux_T_7 connect out_roready[12], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, UInt<1>(0h1)) connect out_rofireMux_out_2, UInt<1>(0h1) node _out_rofireMux_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[23], _out_rofireMux_T_15 connect out_roready[22], _out_rofireMux_T_15 connect out_roready[21], _out_rofireMux_T_15 connect out_roready[20], _out_rofireMux_T_15 connect out_roready[19], _out_rofireMux_T_15 connect out_roready[18], _out_rofireMux_T_15 connect out_roready[17], _out_rofireMux_T_15 connect out_roready[16], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) wire out_rofireMux_out_4 : UInt<1> node _out_rofireMux_T_18 = and(_out_rofireMux_T_1, out_backSel_4) node _out_rofireMux_T_19 = and(_out_rofireMux_T_18, _out_T_9) connect out_rofireMux_out_4, UInt<1>(0h1) connect out_roready[31], _out_rofireMux_T_19 connect out_roready[30], _out_rofireMux_T_19 connect out_roready[29], _out_rofireMux_T_19 connect out_roready[28], _out_rofireMux_T_19 connect out_roready[27], _out_rofireMux_T_19 connect out_roready[26], _out_rofireMux_T_19 connect out_roready[25], _out_rofireMux_T_19 connect out_roready[24], _out_rofireMux_T_19 node _out_rofireMux_T_20 = eq(_out_T_9, UInt<1>(0h0)) node _out_rofireMux_T_21 = or(out_rofireMux_out_4, _out_rofireMux_T_20) wire out_rofireMux_out_5 : UInt<1> node _out_rofireMux_T_22 = and(_out_rofireMux_T_1, out_backSel_5) node _out_rofireMux_T_23 = and(_out_rofireMux_T_22, _out_T_3) connect out_rofireMux_out_5, UInt<1>(0h1) connect out_roready[11], _out_rofireMux_T_23 connect out_roready[10], _out_rofireMux_T_23 connect out_roready[9], _out_rofireMux_T_23 connect out_roready[8], _out_rofireMux_T_23 connect out_roready[7], _out_rofireMux_T_23 connect out_roready[6], _out_rofireMux_T_23 connect out_roready[5], _out_rofireMux_T_23 connect out_roready[4], _out_rofireMux_T_23 node _out_rofireMux_T_24 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_25 = or(out_rofireMux_out_5, _out_rofireMux_T_24) wire out_rofireMux_out_6 : UInt<1> node _out_rofireMux_T_26 = and(_out_rofireMux_T_1, out_backSel_6) node _out_rofireMux_T_27 = and(_out_rofireMux_T_26, _out_T_13) connect out_rofireMux_out_6, UInt<1>(0h1) connect out_roready[47], _out_rofireMux_T_27 connect out_roready[46], _out_rofireMux_T_27 connect out_roready[45], _out_rofireMux_T_27 connect out_roready[44], _out_rofireMux_T_27 connect out_roready[43], _out_rofireMux_T_27 connect out_roready[42], _out_rofireMux_T_27 connect out_roready[41], _out_rofireMux_T_27 connect out_roready[40], _out_rofireMux_T_27 node _out_rofireMux_T_28 = eq(_out_T_13, UInt<1>(0h0)) node _out_rofireMux_T_29 = or(out_rofireMux_out_6, _out_rofireMux_T_28) wire out_rofireMux_out_7 : UInt<1> node _out_rofireMux_T_30 = and(_out_rofireMux_T_1, out_backSel_7) node _out_rofireMux_T_31 = and(_out_rofireMux_T_30, _out_T_11) connect out_rofireMux_out_7, UInt<1>(0h1) connect out_roready[39], _out_rofireMux_T_31 connect out_roready[38], _out_rofireMux_T_31 connect out_roready[37], _out_rofireMux_T_31 connect out_roready[36], _out_rofireMux_T_31 connect out_roready[35], _out_rofireMux_T_31 connect out_roready[34], _out_rofireMux_T_31 connect out_roready[33], _out_rofireMux_T_31 connect out_roready[32], _out_rofireMux_T_31 node _out_rofireMux_T_32 = eq(_out_T_11, UInt<1>(0h0)) node _out_rofireMux_T_33 = or(out_rofireMux_out_7, _out_rofireMux_T_32) node _out_rofireMux_T_34 = geq(out_oindex, UInt<4>(0h8)) wire _out_rofireMux_WIRE : UInt<1>[8] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 connect _out_rofireMux_WIRE[4], _out_rofireMux_T_21 connect _out_rofireMux_WIRE[5], _out_rofireMux_T_25 connect _out_rofireMux_WIRE[6], _out_rofireMux_T_29 connect _out_rofireMux_WIRE[7], _out_rofireMux_T_33 node out_rofireMux = mux(_out_rofireMux_T_34, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_5) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[15], _out_wofireMux_T_8 connect out_woready[14], _out_wofireMux_T_8 connect out_woready[13], _out_wofireMux_T_8 connect out_woready[12], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, UInt<1>(0h1)) connect out_wofireMux_out_2, UInt<1>(0h1) node _out_wofireMux_T_13 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7) connect out_wofireMux_out_3, UInt<1>(0h1) connect out_woready[23], _out_wofireMux_T_16 connect out_woready[22], _out_wofireMux_T_16 connect out_woready[21], _out_wofireMux_T_16 connect out_woready[20], _out_wofireMux_T_16 connect out_woready[19], _out_wofireMux_T_16 connect out_woready[18], _out_wofireMux_T_16 connect out_woready[17], _out_wofireMux_T_16 connect out_woready[16], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) wire out_wofireMux_out_4 : UInt<1> node _out_wofireMux_T_19 = and(_out_wofireMux_T_2, out_backSel_4) node _out_wofireMux_T_20 = and(_out_wofireMux_T_19, _out_T_9) connect out_wofireMux_out_4, UInt<1>(0h1) connect out_woready[31], _out_wofireMux_T_20 connect out_woready[30], _out_wofireMux_T_20 connect out_woready[29], _out_wofireMux_T_20 connect out_woready[28], _out_wofireMux_T_20 connect out_woready[27], _out_wofireMux_T_20 connect out_woready[26], _out_wofireMux_T_20 connect out_woready[25], _out_wofireMux_T_20 connect out_woready[24], _out_wofireMux_T_20 node _out_wofireMux_T_21 = eq(_out_T_9, UInt<1>(0h0)) node _out_wofireMux_T_22 = or(out_wofireMux_out_4, _out_wofireMux_T_21) wire out_wofireMux_out_5 : UInt<1> node _out_wofireMux_T_23 = and(_out_wofireMux_T_2, out_backSel_5) node _out_wofireMux_T_24 = and(_out_wofireMux_T_23, _out_T_3) connect out_wofireMux_out_5, UInt<1>(0h1) connect out_woready[11], _out_wofireMux_T_24 connect out_woready[10], _out_wofireMux_T_24 connect out_woready[9], _out_wofireMux_T_24 connect out_woready[8], _out_wofireMux_T_24 connect out_woready[7], _out_wofireMux_T_24 connect out_woready[6], _out_wofireMux_T_24 connect out_woready[5], _out_wofireMux_T_24 connect out_woready[4], _out_wofireMux_T_24 node _out_wofireMux_T_25 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_26 = or(out_wofireMux_out_5, _out_wofireMux_T_25) wire out_wofireMux_out_6 : UInt<1> node _out_wofireMux_T_27 = and(_out_wofireMux_T_2, out_backSel_6) node _out_wofireMux_T_28 = and(_out_wofireMux_T_27, _out_T_13) connect out_wofireMux_out_6, UInt<1>(0h1) connect out_woready[47], _out_wofireMux_T_28 connect out_woready[46], _out_wofireMux_T_28 connect out_woready[45], _out_wofireMux_T_28 connect out_woready[44], _out_wofireMux_T_28 connect out_woready[43], _out_wofireMux_T_28 connect out_woready[42], _out_wofireMux_T_28 connect out_woready[41], _out_wofireMux_T_28 connect out_woready[40], _out_wofireMux_T_28 node _out_wofireMux_T_29 = eq(_out_T_13, UInt<1>(0h0)) node _out_wofireMux_T_30 = or(out_wofireMux_out_6, _out_wofireMux_T_29) wire out_wofireMux_out_7 : UInt<1> node _out_wofireMux_T_31 = and(_out_wofireMux_T_2, out_backSel_7) node _out_wofireMux_T_32 = and(_out_wofireMux_T_31, _out_T_11) connect out_wofireMux_out_7, UInt<1>(0h1) connect out_woready[39], _out_wofireMux_T_32 connect out_woready[38], _out_wofireMux_T_32 connect out_woready[37], _out_wofireMux_T_32 connect out_woready[36], _out_wofireMux_T_32 connect out_woready[35], _out_wofireMux_T_32 connect out_woready[34], _out_wofireMux_T_32 connect out_woready[33], _out_wofireMux_T_32 connect out_woready[32], _out_wofireMux_T_32 node _out_wofireMux_T_33 = eq(_out_T_11, UInt<1>(0h0)) node _out_wofireMux_T_34 = or(out_wofireMux_out_7, _out_wofireMux_T_33) node _out_wofireMux_T_35 = geq(out_oindex, UInt<4>(0h8)) wire _out_wofireMux_WIRE : UInt<1>[8] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 connect _out_wofireMux_WIRE[4], _out_wofireMux_T_22 connect _out_wofireMux_WIRE[5], _out_wofireMux_T_26 connect _out_wofireMux_WIRE[6], _out_wofireMux_T_30 connect _out_wofireMux_WIRE[7], _out_wofireMux_T_34 node out_wofireMux = mux(_out_wofireMux_T_35, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<4>(0h8)) wire _out_out_bits_data_WIRE : UInt<1>[8] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_5 connect _out_out_bits_data_WIRE[2], UInt<1>(0h1) connect _out_out_bits_data_WIRE[3], _out_T_7 connect _out_out_bits_data_WIRE[4], _out_T_9 connect _out_out_bits_data_WIRE[5], _out_T_3 connect _out_out_bits_data_WIRE[6], _out_T_13 connect _out_out_bits_data_WIRE[7], _out_T_11 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<4>(0h8)) wire _out_out_bits_data_WIRE_1 : UInt<64>[8] connect _out_out_bits_data_WIRE_1[0], _out_T_53 connect _out_out_bits_data_WIRE_1[1], _out_T_181 connect _out_out_bits_data_WIRE_1[2], UInt<1>(0h0) connect _out_out_bits_data_WIRE_1[3], _out_T_269 connect _out_out_bits_data_WIRE_1[4], _out_T_357 connect _out_out_bits_data_WIRE_1[5], _out_T_141 connect _out_out_bits_data_WIRE_1[6], _out_T_533 connect _out_out_bits_data_WIRE_1[7], _out_T_445 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_3_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_3_1, // @[LazyModuleImp.scala:107:25] output auto_int_out_2_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_2_1, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_1, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h17FC; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_34 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_12 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_34 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_13 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_35 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire x1_intnodeOut_2_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire x1_intnodeOut_2_1; // @[MixedNode.scala:542:17] wire x1_intnodeOut_1_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_1_1; // @[MixedNode.scala:542:17] wire x1_intnodeOut_0; // @[MixedNode.scala:542:17] wire x1_intnodeOut_1; // @[MixedNode.scala:542:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_3_0_0; // @[CLINT.scala:65:9] wire auto_int_out_3_1_0; // @[CLINT.scala:65:9] wire auto_int_out_2_0_0; // @[CLINT.scala:65:9] wire auto_int_out_2_1_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_1_0; // @[CLINT.scala:65:9] wire auto_int_out_0_0_0; // @[CLINT.scala:65:9] wire auto_int_out_0_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [11:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [11:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [11:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_0_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] wire _intnodeOut_0_T_1; // @[CLINT.scala:82:37] assign auto_int_out_1_0_0 = x1_intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T_1; // @[CLINT.scala:83:43] assign auto_int_out_1_1_0 = x1_intnodeOut_1; // @[CLINT.scala:65:9] wire _intnodeOut_0_T_2; // @[CLINT.scala:82:37] assign auto_int_out_2_0_0 = x1_intnodeOut_1_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T_2; // @[CLINT.scala:83:43] assign auto_int_out_2_1_0 = x1_intnodeOut_1_1; // @[CLINT.scala:65:9] wire _intnodeOut_0_T_3; // @[CLINT.scala:82:37] assign auto_int_out_3_0_0 = x1_intnodeOut_2_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T_3; // @[CLINT.scala:83:43] assign auto_int_out_3_1_0 = x1_intnodeOut_2_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_4 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg [63:0] timecmp_1; // @[CLINT.scala:77:41] wire [63:0] pad_1 = timecmp_1; // @[RegField.scala:150:19] reg [63:0] timecmp_2; // @[CLINT.scala:77:41] wire [63:0] pad_2 = timecmp_2; // @[RegField.scala:150:19] reg [63:0] timecmp_3; // @[CLINT.scala:77:41] wire [63:0] pad_3 = timecmp_3; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_23 = ipi_0; // @[RegisterRouter.scala:87:24] reg ipi_1; // @[CLINT.scala:78:41] assign _intnodeOut_0_T_1 = ipi_1; // @[CLINT.scala:78:41, :82:37] reg ipi_2; // @[CLINT.scala:78:41] assign _intnodeOut_0_T_2 = ipi_2; // @[CLINT.scala:78:41, :82:37] wire _out_T_151 = ipi_2; // @[RegisterRouter.scala:87:24] reg ipi_3; // @[CLINT.scala:78:41] assign _intnodeOut_0_T_3 = ipi_3; // @[CLINT.scala:78:41, :82:37] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] assign x1_intnodeOut_0 = _intnodeOut_0_T_1; // @[CLINT.scala:82:37] assign _intnodeOut_1_T_1 = time_0 >= timecmp_1; // @[CLINT.scala:73:23, :77:41, :83:43] assign x1_intnodeOut_1 = _intnodeOut_1_T_1; // @[CLINT.scala:83:43] assign x1_intnodeOut_1_0 = _intnodeOut_0_T_2; // @[CLINT.scala:82:37] assign _intnodeOut_1_T_2 = time_0 >= timecmp_2; // @[CLINT.scala:73:23, :77:41, :83:43] assign x1_intnodeOut_1_1 = _intnodeOut_1_T_2; // @[CLINT.scala:83:43] assign x1_intnodeOut_2_0 = _intnodeOut_0_T_3; // @[CLINT.scala:82:37] assign _intnodeOut_1_T_3 = time_0 >= timecmp_3; // @[CLINT.scala:73:23, :77:41, :83:43] assign x1_intnodeOut_2_1 = _intnodeOut_1_T_3; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_279 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_24; // @[RegisterRouter.scala:87:24] wire out_f_woready_25; // @[RegisterRouter.scala:87:24] wire out_f_woready_26; // @[RegisterRouter.scala:87:24] wire out_f_woready_27; // @[RegisterRouter.scala:87:24] wire out_f_woready_28; // @[RegisterRouter.scala:87:24] wire out_f_woready_29; // @[RegisterRouter.scala:87:24] wire out_f_woready_30; // @[RegisterRouter.scala:87:24] wire out_f_woready_31; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_63 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] timecmp_1_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_1_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_1_lo = {timecmp_1_lo_hi, timecmp_1_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_1_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_1_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_1_hi = {timecmp_1_hi_hi, timecmp_1_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_1_T = {timecmp_1_hi, timecmp_1_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_16 = pad_2[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2_0 = _oldBytes_T_16; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_17 = pad_2[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2_1 = _oldBytes_T_17; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_18 = pad_2[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2_2 = _oldBytes_T_18; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_19 = pad_2[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2_3 = _oldBytes_T_19; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_20 = pad_2[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2_4 = _oldBytes_T_20; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_21 = pad_2[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2_5 = _oldBytes_T_21; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_22 = pad_2[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2_6 = _oldBytes_T_22; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_23 = pad_2[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2_7 = _oldBytes_T_23; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_455 = oldBytes_2_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_2_0; // @[RegField.scala:152:31] wire [7:0] newBytes_2_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2_2; // @[RegField.scala:152:31] wire [7:0] newBytes_2_3; // @[RegField.scala:152:31] wire [7:0] newBytes_2_4; // @[RegField.scala:152:31] wire [7:0] newBytes_2_5; // @[RegField.scala:152:31] wire [7:0] newBytes_2_6; // @[RegField.scala:152:31] wire [7:0] newBytes_2_7; // @[RegField.scala:152:31] wire out_f_woready_40; // @[RegisterRouter.scala:87:24] wire out_f_woready_41; // @[RegisterRouter.scala:87:24] wire out_f_woready_42; // @[RegisterRouter.scala:87:24] wire out_f_woready_43; // @[RegisterRouter.scala:87:24] wire out_f_woready_44; // @[RegisterRouter.scala:87:24] wire out_f_woready_45; // @[RegisterRouter.scala:87:24] wire out_f_woready_46; // @[RegisterRouter.scala:87:24] wire out_f_woready_47; // @[RegisterRouter.scala:87:24] wire valids_2_0; // @[RegField.scala:153:29] wire valids_2_1; // @[RegField.scala:153:29] wire valids_2_2; // @[RegField.scala:153:29] wire valids_2_3; // @[RegField.scala:153:29] wire valids_2_4; // @[RegField.scala:153:29] wire valids_2_5; // @[RegField.scala:153:29] wire valids_2_6; // @[RegField.scala:153:29] wire valids_2_7; // @[RegField.scala:153:29] wire [15:0] timecmp_2_lo_lo = {newBytes_2_1, newBytes_2_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_2_lo_hi = {newBytes_2_3, newBytes_2_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_2_lo = {timecmp_2_lo_hi, timecmp_2_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_2_hi_lo = {newBytes_2_5, newBytes_2_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_2_hi_hi = {newBytes_2_7, newBytes_2_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_2_hi = {timecmp_2_hi_hi, timecmp_2_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_2_T = {timecmp_2_hi, timecmp_2_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_24 = pad_3[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3_0 = _oldBytes_T_24; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_25 = pad_3[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3_1 = _oldBytes_T_25; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_26 = pad_3[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3_2 = _oldBytes_T_26; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_27 = pad_3[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3_3 = _oldBytes_T_27; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_28 = pad_3[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3_4 = _oldBytes_T_28; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_29 = pad_3[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3_5 = _oldBytes_T_29; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_30 = pad_3[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3_6 = _oldBytes_T_30; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_31 = pad_3[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3_7 = _oldBytes_T_31; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_367 = oldBytes_3_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_3_0; // @[RegField.scala:152:31] wire [7:0] newBytes_3_1; // @[RegField.scala:152:31] wire [7:0] newBytes_3_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3_3; // @[RegField.scala:152:31] wire [7:0] newBytes_3_4; // @[RegField.scala:152:31] wire [7:0] newBytes_3_5; // @[RegField.scala:152:31] wire [7:0] newBytes_3_6; // @[RegField.scala:152:31] wire [7:0] newBytes_3_7; // @[RegField.scala:152:31] wire out_f_woready_32; // @[RegisterRouter.scala:87:24] wire out_f_woready_33; // @[RegisterRouter.scala:87:24] wire out_f_woready_34; // @[RegisterRouter.scala:87:24] wire out_f_woready_35; // @[RegisterRouter.scala:87:24] wire out_f_woready_36; // @[RegisterRouter.scala:87:24] wire out_f_woready_37; // @[RegisterRouter.scala:87:24] wire out_f_woready_38; // @[RegisterRouter.scala:87:24] wire out_f_woready_39; // @[RegisterRouter.scala:87:24] wire valids_3_0; // @[RegField.scala:153:29] wire valids_3_1; // @[RegField.scala:153:29] wire valids_3_2; // @[RegField.scala:153:29] wire valids_3_3; // @[RegField.scala:153:29] wire valids_3_4; // @[RegField.scala:153:29] wire valids_3_5; // @[RegField.scala:153:29] wire valids_3_6; // @[RegField.scala:153:29] wire valids_3_7; // @[RegField.scala:153:29] wire [15:0] timecmp_3_lo_lo = {newBytes_3_1, newBytes_3_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_3_lo_hi = {newBytes_3_3, newBytes_3_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_3_lo = {timecmp_3_lo_hi, timecmp_3_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_3_hi_lo = {newBytes_3_5, newBytes_3_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_3_hi_hi = {newBytes_3_7, newBytes_3_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_3_hi = {timecmp_3_hi_hi, timecmp_3_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_3_T = {timecmp_3_hi, timecmp_3_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_32 = pad_4[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4_0 = _oldBytes_T_32; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_33 = pad_4[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4_1 = _oldBytes_T_33; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_34 = pad_4[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4_2 = _oldBytes_T_34; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_35 = pad_4[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4_3 = _oldBytes_T_35; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_36 = pad_4[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4_4 = _oldBytes_T_36; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_37 = pad_4[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4_5 = _oldBytes_T_37; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_38 = pad_4[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4_6 = _oldBytes_T_38; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_39 = pad_4[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4_7 = _oldBytes_T_39; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_191 = oldBytes_4_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_4_0; // @[RegField.scala:152:31] wire [7:0] newBytes_4_1; // @[RegField.scala:152:31] wire [7:0] newBytes_4_2; // @[RegField.scala:152:31] wire [7:0] newBytes_4_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4_4; // @[RegField.scala:152:31] wire [7:0] newBytes_4_5; // @[RegField.scala:152:31] wire [7:0] newBytes_4_6; // @[RegField.scala:152:31] wire [7:0] newBytes_4_7; // @[RegField.scala:152:31] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire out_f_woready_18; // @[RegisterRouter.scala:87:24] wire out_f_woready_19; // @[RegisterRouter.scala:87:24] wire out_f_woready_20; // @[RegisterRouter.scala:87:24] wire out_f_woready_21; // @[RegisterRouter.scala:87:24] wire out_f_woready_22; // @[RegisterRouter.scala:87:24] wire out_f_woready_23; // @[RegisterRouter.scala:87:24] wire valids_4_0; // @[RegField.scala:153:29] wire valids_4_1; // @[RegField.scala:153:29] wire valids_4_2; // @[RegField.scala:153:29] wire valids_4_3; // @[RegField.scala:153:29] wire valids_4_4; // @[RegField.scala:153:29] wire valids_4_5; // @[RegField.scala:153:29] wire valids_4_6; // @[RegField.scala:153:29] wire valids_4_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_4_1, newBytes_4_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_4_3, newBytes_4_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_4_5, newBytes_4_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_4_7, newBytes_4_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h17FC; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_12; // @[RegisterRouter.scala:87:24] assign _out_T_12 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_13; // @[RegisterRouter.scala:87:24] assign _out_T_13 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_5 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_T_6 = out_findex == 13'h17FC; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_bindex == 13'h17FC; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_4 = _out_T_9; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_7 = _out_T_11; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_6 = _out_T_13; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_rivalid_18; // @[RegisterRouter.scala:87:24] wire out_rivalid_19; // @[RegisterRouter.scala:87:24] wire out_rivalid_20; // @[RegisterRouter.scala:87:24] wire out_rivalid_21; // @[RegisterRouter.scala:87:24] wire out_rivalid_22; // @[RegisterRouter.scala:87:24] wire out_rivalid_23; // @[RegisterRouter.scala:87:24] wire out_rivalid_24; // @[RegisterRouter.scala:87:24] wire out_rivalid_25; // @[RegisterRouter.scala:87:24] wire out_rivalid_26; // @[RegisterRouter.scala:87:24] wire out_rivalid_27; // @[RegisterRouter.scala:87:24] wire out_rivalid_28; // @[RegisterRouter.scala:87:24] wire out_rivalid_29; // @[RegisterRouter.scala:87:24] wire out_rivalid_30; // @[RegisterRouter.scala:87:24] wire out_rivalid_31; // @[RegisterRouter.scala:87:24] wire out_rivalid_32; // @[RegisterRouter.scala:87:24] wire out_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_rivalid_42; // @[RegisterRouter.scala:87:24] wire out_rivalid_43; // @[RegisterRouter.scala:87:24] wire out_rivalid_44; // @[RegisterRouter.scala:87:24] wire out_rivalid_45; // @[RegisterRouter.scala:87:24] wire out_rivalid_46; // @[RegisterRouter.scala:87:24] wire out_rivalid_47; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire out_wivalid_18; // @[RegisterRouter.scala:87:24] wire out_wivalid_19; // @[RegisterRouter.scala:87:24] wire out_wivalid_20; // @[RegisterRouter.scala:87:24] wire out_wivalid_21; // @[RegisterRouter.scala:87:24] wire out_wivalid_22; // @[RegisterRouter.scala:87:24] wire out_wivalid_23; // @[RegisterRouter.scala:87:24] wire out_wivalid_24; // @[RegisterRouter.scala:87:24] wire out_wivalid_25; // @[RegisterRouter.scala:87:24] wire out_wivalid_26; // @[RegisterRouter.scala:87:24] wire out_wivalid_27; // @[RegisterRouter.scala:87:24] wire out_wivalid_28; // @[RegisterRouter.scala:87:24] wire out_wivalid_29; // @[RegisterRouter.scala:87:24] wire out_wivalid_30; // @[RegisterRouter.scala:87:24] wire out_wivalid_31; // @[RegisterRouter.scala:87:24] wire out_wivalid_32; // @[RegisterRouter.scala:87:24] wire out_wivalid_33; // @[RegisterRouter.scala:87:24] wire out_wivalid_34; // @[RegisterRouter.scala:87:24] wire out_wivalid_35; // @[RegisterRouter.scala:87:24] wire out_wivalid_36; // @[RegisterRouter.scala:87:24] wire out_wivalid_37; // @[RegisterRouter.scala:87:24] wire out_wivalid_38; // @[RegisterRouter.scala:87:24] wire out_wivalid_39; // @[RegisterRouter.scala:87:24] wire out_wivalid_40; // @[RegisterRouter.scala:87:24] wire out_wivalid_41; // @[RegisterRouter.scala:87:24] wire out_wivalid_42; // @[RegisterRouter.scala:87:24] wire out_wivalid_43; // @[RegisterRouter.scala:87:24] wire out_wivalid_44; // @[RegisterRouter.scala:87:24] wire out_wivalid_45; // @[RegisterRouter.scala:87:24] wire out_wivalid_46; // @[RegisterRouter.scala:87:24] wire out_wivalid_47; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire out_roready_18; // @[RegisterRouter.scala:87:24] wire out_roready_19; // @[RegisterRouter.scala:87:24] wire out_roready_20; // @[RegisterRouter.scala:87:24] wire out_roready_21; // @[RegisterRouter.scala:87:24] wire out_roready_22; // @[RegisterRouter.scala:87:24] wire out_roready_23; // @[RegisterRouter.scala:87:24] wire out_roready_24; // @[RegisterRouter.scala:87:24] wire out_roready_25; // @[RegisterRouter.scala:87:24] wire out_roready_26; // @[RegisterRouter.scala:87:24] wire out_roready_27; // @[RegisterRouter.scala:87:24] wire out_roready_28; // @[RegisterRouter.scala:87:24] wire out_roready_29; // @[RegisterRouter.scala:87:24] wire out_roready_30; // @[RegisterRouter.scala:87:24] wire out_roready_31; // @[RegisterRouter.scala:87:24] wire out_roready_32; // @[RegisterRouter.scala:87:24] wire out_roready_33; // @[RegisterRouter.scala:87:24] wire out_roready_34; // @[RegisterRouter.scala:87:24] wire out_roready_35; // @[RegisterRouter.scala:87:24] wire out_roready_36; // @[RegisterRouter.scala:87:24] wire out_roready_37; // @[RegisterRouter.scala:87:24] wire out_roready_38; // @[RegisterRouter.scala:87:24] wire out_roready_39; // @[RegisterRouter.scala:87:24] wire out_roready_40; // @[RegisterRouter.scala:87:24] wire out_roready_41; // @[RegisterRouter.scala:87:24] wire out_roready_42; // @[RegisterRouter.scala:87:24] wire out_roready_43; // @[RegisterRouter.scala:87:24] wire out_roready_44; // @[RegisterRouter.scala:87:24] wire out_roready_45; // @[RegisterRouter.scala:87:24] wire out_roready_46; // @[RegisterRouter.scala:87:24] wire out_roready_47; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire out_woready_18; // @[RegisterRouter.scala:87:24] wire out_woready_19; // @[RegisterRouter.scala:87:24] wire out_woready_20; // @[RegisterRouter.scala:87:24] wire out_woready_21; // @[RegisterRouter.scala:87:24] wire out_woready_22; // @[RegisterRouter.scala:87:24] wire out_woready_23; // @[RegisterRouter.scala:87:24] wire out_woready_24; // @[RegisterRouter.scala:87:24] wire out_woready_25; // @[RegisterRouter.scala:87:24] wire out_woready_26; // @[RegisterRouter.scala:87:24] wire out_woready_27; // @[RegisterRouter.scala:87:24] wire out_woready_28; // @[RegisterRouter.scala:87:24] wire out_woready_29; // @[RegisterRouter.scala:87:24] wire out_woready_30; // @[RegisterRouter.scala:87:24] wire out_woready_31; // @[RegisterRouter.scala:87:24] wire out_woready_32; // @[RegisterRouter.scala:87:24] wire out_woready_33; // @[RegisterRouter.scala:87:24] wire out_woready_34; // @[RegisterRouter.scala:87:24] wire out_woready_35; // @[RegisterRouter.scala:87:24] wire out_woready_36; // @[RegisterRouter.scala:87:24] wire out_woready_37; // @[RegisterRouter.scala:87:24] wire out_woready_38; // @[RegisterRouter.scala:87:24] wire out_woready_39; // @[RegisterRouter.scala:87:24] wire out_woready_40; // @[RegisterRouter.scala:87:24] wire out_woready_41; // @[RegisterRouter.scala:87:24] wire out_woready_42; // @[RegisterRouter.scala:87:24] wire out_woready_43; // @[RegisterRouter.scala:87:24] wire out_woready_44; // @[RegisterRouter.scala:87:24] wire out_woready_45; // @[RegisterRouter.scala:87:24] wire out_woready_46; // @[RegisterRouter.scala:87:24] wire out_woready_47; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_12 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_12 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_12 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_12 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_15 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_17 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_14 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_142 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_24 = _out_T_23; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_24; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_13 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_13 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_13 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_13 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_25 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_153 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_32 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_33 = _out_T_32; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_1 = _out_T_33; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_2 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_2 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_14 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_14 = out_frontMask[32]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire _out_romask_T_2 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_2 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_14 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_14 = out_backMask[32]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_35 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_36 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_37 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_40 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_41 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_1 = {ipi_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_43 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_44 = _out_T_43; // @[RegisterRouter.scala:87:24] wire [32:0] _out_prepend_T_2 = _out_T_44; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_3 = out_frontMask[63:33]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_3 = out_frontMask[63:33]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_15 = out_frontMask[63:33]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_15 = out_frontMask[63:33]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_3 = out_backMask[63:33]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_3 = out_backMask[63:33]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_15 = out_backMask[63:33]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_15 = out_backMask[63:33]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_46 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_47 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_45 = out_front_bits_data[63:33]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_173 = out_front_bits_data[63:33]; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_49 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_2 = {1'h0, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_52 = {30'h0, out_prepend_2}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_53 = _out_T_52; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_53; // @[MuxLiteral.scala:49:48] wire [7:0] _out_rimask_T_4 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_24 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_24 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_32 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_32 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_40 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_40 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_24 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_24 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_32 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_32 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_40 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_40 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_57 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_58 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_54 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_182 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_270 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_358 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_446 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_4 ? _out_T_54 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_59 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_60 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_61 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_62 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_64 = _out_T_63; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_3 = _out_T_64; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_25 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_25 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_33 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_33 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_41 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_41 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_25 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_25 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_33 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_33 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_41 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_41 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_68 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_69 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_65 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_193 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_281 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_369 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_457 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_5 ? _out_T_65 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_70 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_71 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_72 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_73 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_3 = {oldBytes_1_1, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_74 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_75 = _out_T_74; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_4 = _out_T_75; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_18 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_18 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_26 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_26 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_34 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_34 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_42 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_42 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_18 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_18 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_26 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_26 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_34 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_34 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_42 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_42 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_79 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_80 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_76 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_204 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_292 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_380 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_468 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_6 ? _out_T_76 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_81 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_82 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_83 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_84 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_4 = {oldBytes_1_2, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_85 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_86 = _out_T_85; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_5 = _out_T_86; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_19 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_19 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_27 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_27 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_35 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_35 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_43 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_43 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = \|_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_19 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_19 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_27 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_27 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_35 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_35 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_43 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_43 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = \|_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_90 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_91 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_87 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_215 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_303 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_391 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_479 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_7 ? _out_T_87 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_93 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_94 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_95 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_5 = {oldBytes_1_3, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_96 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_97 = _out_T_96; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_6 = _out_T_97; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_20 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_20 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_28 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_28 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_36 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_36 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_44 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_44 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_20 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_20 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_28 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_28 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_36 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_36 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_44 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_44 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_101 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_102 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_98 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_226 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_314 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_402 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_490 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_8 ? _out_T_98 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_103 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_104 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_105 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_106 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_6 = {oldBytes_1_4, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_107 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_108 = _out_T_107; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_7 = _out_T_108; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_21 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_21 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_29 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_29 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_37 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_37 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_45 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_45 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_21 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_21 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_29 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_29 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_37 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_37 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_45 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_45 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_112 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_113 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_109 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_237 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_325 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_413 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_501 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_9 ? _out_T_109 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_114 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_115 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_116 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_117 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_7 = {oldBytes_1_5, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_118 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_119 = _out_T_118; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_8 = _out_T_119; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_22 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_22 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_30 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_30 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_38 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_38 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_46 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_46 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_10 = \|_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_22 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_22 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_30 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_30 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_38 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_38 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_46 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_46 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_10 = \|_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_123 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_124 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_120 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_248 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_336 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_424 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_512 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_10 ? _out_T_120 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_125 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_126 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_127 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_128 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_8 = {oldBytes_1_6, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_129 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_130 = _out_T_129; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_9 = _out_T_130; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_23 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_23 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_31 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_31 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_39 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_39 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_47 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_47 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = \|_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_23 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_23 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_31 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_31 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_39 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_39 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_47 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_47 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_11 = \|_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_134 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_135 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_131 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_259 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_347 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_435 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_523 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_11 ? _out_T_131 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_136 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_137 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_138 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_139 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_9 = {oldBytes_1_7, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_140 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_141 = _out_T_140; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_5 = _out_T_141; // @[MuxLiteral.scala:49:48] wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_145 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_146 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_147 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_148 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_149 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_150 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire _out_T_152 = _out_T_151; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_10 = _out_T_152; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = \|_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = \|_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] wire _out_T_156 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_157 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_158 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_159 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_10 = {1'h0, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_160 = {30'h0, out_prepend_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_161 = _out_T_160; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_161; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_163 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_167 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_168 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_169 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_170 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_11 = {ipi_3, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_171 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [32:0] _out_T_172 = _out_T_171; // @[RegisterRouter.scala:87:24] wire [32:0] _out_prepend_T_12 = _out_T_172; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = \|_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = \|_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_174 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_178 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_179 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [33:0] out_prepend_12 = {1'h0, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_180 = {30'h0, out_prepend_12}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_181 = _out_T_180; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_181; // @[MuxLiteral.scala:49:48] wire out_rimask_16 = \|_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = \|_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_185 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_4_0 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_4_0 = out_f_woready_16 ? _out_T_182 : oldBytes_4_0; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_189 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_190 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_192 = _out_T_191; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_13 = _out_T_192; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = \|_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = \|_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_196 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_4_1 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_4_1 = out_f_woready_17 ? _out_T_193 : oldBytes_4_1; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_200 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_201 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_13 = {oldBytes_4_1, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_202 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_203 = _out_T_202; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_14 = _out_T_203; // @[RegisterRouter.scala:87:24] wire out_rimask_18 = \|_out_rimask_T_18; // @[RegisterRouter.scala:87:24] wire out_wimask_18 = &_out_wimask_T_18; // @[RegisterRouter.scala:87:24] wire out_romask_18 = \|_out_romask_T_18; // @[RegisterRouter.scala:87:24] wire out_womask_18 = &_out_womask_T_18; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_18 = out_rivalid_18 & out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_205 = out_f_rivalid_18; // @[RegisterRouter.scala:87:24] wire out_f_roready_18 = out_roready_18 & out_romask_18; // @[RegisterRouter.scala:87:24] wire _out_T_206 = out_f_roready_18; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_18 = out_wivalid_18 & out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_207 = out_f_wivalid_18; // @[RegisterRouter.scala:87:24] assign out_f_woready_18 = out_woready_18 & out_womask_18; // @[RegisterRouter.scala:87:24] assign valids_4_2 = out_f_woready_18; // @[RegisterRouter.scala:87:24] wire _out_T_208 = out_f_woready_18; // @[RegisterRouter.scala:87:24] assign newBytes_4_2 = out_f_woready_18 ? _out_T_204 : oldBytes_4_2; // @[RegisterRouter.scala:87:24] wire _out_T_209 = ~out_rimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_210 = ~out_wimask_18; // @[RegisterRouter.scala:87:24] wire _out_T_211 = ~out_romask_18; // @[RegisterRouter.scala:87:24] wire _out_T_212 = ~out_womask_18; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_14 = {oldBytes_4_2, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_213 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_214 = _out_T_213; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_15 = _out_T_214; // @[RegisterRouter.scala:87:24] wire out_rimask_19 = \|_out_rimask_T_19; // @[RegisterRouter.scala:87:24] wire out_wimask_19 = &_out_wimask_T_19; // @[RegisterRouter.scala:87:24] wire out_romask_19 = \|_out_romask_T_19; // @[RegisterRouter.scala:87:24] wire out_womask_19 = &_out_womask_T_19; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_19 = out_rivalid_19 & out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_216 = out_f_rivalid_19; // @[RegisterRouter.scala:87:24] wire out_f_roready_19 = out_roready_19 & out_romask_19; // @[RegisterRouter.scala:87:24] wire _out_T_217 = out_f_roready_19; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_19 = out_wivalid_19 & out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_218 = out_f_wivalid_19; // @[RegisterRouter.scala:87:24] assign out_f_woready_19 = out_woready_19 & out_womask_19; // @[RegisterRouter.scala:87:24] assign valids_4_3 = out_f_woready_19; // @[RegisterRouter.scala:87:24] wire _out_T_219 = out_f_woready_19; // @[RegisterRouter.scala:87:24] assign newBytes_4_3 = out_f_woready_19 ? _out_T_215 : oldBytes_4_3; // @[RegisterRouter.scala:87:24] wire _out_T_220 = ~out_rimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_221 = ~out_wimask_19; // @[RegisterRouter.scala:87:24] wire _out_T_222 = ~out_romask_19; // @[RegisterRouter.scala:87:24] wire _out_T_223 = ~out_womask_19; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_15 = {oldBytes_4_3, _out_prepend_T_15}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_224 = out_prepend_15; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_225 = _out_T_224; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_16 = _out_T_225; // @[RegisterRouter.scala:87:24] wire out_rimask_20 = \|_out_rimask_T_20; // @[RegisterRouter.scala:87:24] wire out_wimask_20 = &_out_wimask_T_20; // @[RegisterRouter.scala:87:24] wire out_romask_20 = \|_out_romask_T_20; // @[RegisterRouter.scala:87:24] wire out_womask_20 = &_out_womask_T_20; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_20 = out_rivalid_20 & out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_227 = out_f_rivalid_20; // @[RegisterRouter.scala:87:24] wire out_f_roready_20 = out_roready_20 & out_romask_20; // @[RegisterRouter.scala:87:24] wire _out_T_228 = out_f_roready_20; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_20 = out_wivalid_20 & out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_229 = out_f_wivalid_20; // @[RegisterRouter.scala:87:24] assign out_f_woready_20 = out_woready_20 & out_womask_20; // @[RegisterRouter.scala:87:24] assign valids_4_4 = out_f_woready_20; // @[RegisterRouter.scala:87:24] wire _out_T_230 = out_f_woready_20; // @[RegisterRouter.scala:87:24] assign newBytes_4_4 = out_f_woready_20 ? _out_T_226 : oldBytes_4_4; // @[RegisterRouter.scala:87:24] wire _out_T_231 = ~out_rimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_232 = ~out_wimask_20; // @[RegisterRouter.scala:87:24] wire _out_T_233 = ~out_romask_20; // @[RegisterRouter.scala:87:24] wire _out_T_234 = ~out_womask_20; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_16 = {oldBytes_4_4, _out_prepend_T_16}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_235 = out_prepend_16; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_236 = _out_T_235; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_17 = _out_T_236; // @[RegisterRouter.scala:87:24] wire out_rimask_21 = \|_out_rimask_T_21; // @[RegisterRouter.scala:87:24] wire out_wimask_21 = &_out_wimask_T_21; // @[RegisterRouter.scala:87:24] wire out_romask_21 = \|_out_romask_T_21; // @[RegisterRouter.scala:87:24] wire out_womask_21 = &_out_womask_T_21; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_21 = out_rivalid_21 & out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_238 = out_f_rivalid_21; // @[RegisterRouter.scala:87:24] wire out_f_roready_21 = out_roready_21 & out_romask_21; // @[RegisterRouter.scala:87:24] wire _out_T_239 = out_f_roready_21; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_21 = out_wivalid_21 & out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_240 = out_f_wivalid_21; // @[RegisterRouter.scala:87:24] assign out_f_woready_21 = out_woready_21 & out_womask_21; // @[RegisterRouter.scala:87:24] assign valids_4_5 = out_f_woready_21; // @[RegisterRouter.scala:87:24] wire _out_T_241 = out_f_woready_21; // @[RegisterRouter.scala:87:24] assign newBytes_4_5 = out_f_woready_21 ? _out_T_237 : oldBytes_4_5; // @[RegisterRouter.scala:87:24] wire _out_T_242 = ~out_rimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_243 = ~out_wimask_21; // @[RegisterRouter.scala:87:24] wire _out_T_244 = ~out_romask_21; // @[RegisterRouter.scala:87:24] wire _out_T_245 = ~out_womask_21; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_17 = {oldBytes_4_5, _out_prepend_T_17}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_246 = out_prepend_17; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_247 = _out_T_246; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_18 = _out_T_247; // @[RegisterRouter.scala:87:24] wire out_rimask_22 = \|_out_rimask_T_22; // @[RegisterRouter.scala:87:24] wire out_wimask_22 = &_out_wimask_T_22; // @[RegisterRouter.scala:87:24] wire out_romask_22 = \|_out_romask_T_22; // @[RegisterRouter.scala:87:24] wire out_womask_22 = &_out_womask_T_22; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_22 = out_rivalid_22 & out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_249 = out_f_rivalid_22; // @[RegisterRouter.scala:87:24] wire out_f_roready_22 = out_roready_22 & out_romask_22; // @[RegisterRouter.scala:87:24] wire _out_T_250 = out_f_roready_22; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_22 = out_wivalid_22 & out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_251 = out_f_wivalid_22; // @[RegisterRouter.scala:87:24] assign out_f_woready_22 = out_woready_22 & out_womask_22; // @[RegisterRouter.scala:87:24] assign valids_4_6 = out_f_woready_22; // @[RegisterRouter.scala:87:24] wire _out_T_252 = out_f_woready_22; // @[RegisterRouter.scala:87:24] assign newBytes_4_6 = out_f_woready_22 ? _out_T_248 : oldBytes_4_6; // @[RegisterRouter.scala:87:24] wire _out_T_253 = ~out_rimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_254 = ~out_wimask_22; // @[RegisterRouter.scala:87:24] wire _out_T_255 = ~out_romask_22; // @[RegisterRouter.scala:87:24] wire _out_T_256 = ~out_womask_22; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_18 = {oldBytes_4_6, _out_prepend_T_18}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_257 = out_prepend_18; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_258 = _out_T_257; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_19 = _out_T_258; // @[RegisterRouter.scala:87:24] wire out_rimask_23 = \|_out_rimask_T_23; // @[RegisterRouter.scala:87:24] wire out_wimask_23 = &_out_wimask_T_23; // @[RegisterRouter.scala:87:24] wire out_romask_23 = \|_out_romask_T_23; // @[RegisterRouter.scala:87:24] wire out_womask_23 = &_out_womask_T_23; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_23 = out_rivalid_23 & out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_260 = out_f_rivalid_23; // @[RegisterRouter.scala:87:24] wire out_f_roready_23 = out_roready_23 & out_romask_23; // @[RegisterRouter.scala:87:24] wire _out_T_261 = out_f_roready_23; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_23 = out_wivalid_23 & out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_262 = out_f_wivalid_23; // @[RegisterRouter.scala:87:24] assign out_f_woready_23 = out_woready_23 & out_womask_23; // @[RegisterRouter.scala:87:24] assign valids_4_7 = out_f_woready_23; // @[RegisterRouter.scala:87:24] wire _out_T_263 = out_f_woready_23; // @[RegisterRouter.scala:87:24] assign newBytes_4_7 = out_f_woready_23 ? _out_T_259 : oldBytes_4_7; // @[RegisterRouter.scala:87:24] wire _out_T_264 = ~out_rimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_265 = ~out_wimask_23; // @[RegisterRouter.scala:87:24] wire _out_T_266 = ~out_romask_23; // @[RegisterRouter.scala:87:24] wire _out_T_267 = ~out_womask_23; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_19 = {oldBytes_4_7, _out_prepend_T_19}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_268 = out_prepend_19; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_269 = _out_T_268; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_3 = _out_T_269; // @[MuxLiteral.scala:49:48] wire out_rimask_24 = \|_out_rimask_T_24; // @[RegisterRouter.scala:87:24] wire out_wimask_24 = &_out_wimask_T_24; // @[RegisterRouter.scala:87:24] wire out_romask_24 = \|_out_romask_T_24; // @[RegisterRouter.scala:87:24] wire out_womask_24 = &_out_womask_T_24; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_24 = out_rivalid_24 & out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_271 = out_f_rivalid_24; // @[RegisterRouter.scala:87:24] wire out_f_roready_24 = out_roready_24 & out_romask_24; // @[RegisterRouter.scala:87:24] wire _out_T_272 = out_f_roready_24; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_24 = out_wivalid_24 & out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_273 = out_f_wivalid_24; // @[RegisterRouter.scala:87:24] assign out_f_woready_24 = out_woready_24 & out_womask_24; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_24; // @[RegisterRouter.scala:87:24] wire _out_T_274 = out_f_woready_24; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_24 ? _out_T_270 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_275 = ~out_rimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_276 = ~out_wimask_24; // @[RegisterRouter.scala:87:24] wire _out_T_277 = ~out_romask_24; // @[RegisterRouter.scala:87:24] wire _out_T_278 = ~out_womask_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_280 = _out_T_279; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_20 = _out_T_280; // @[RegisterRouter.scala:87:24] wire out_rimask_25 = \|_out_rimask_T_25; // @[RegisterRouter.scala:87:24] wire out_wimask_25 = &_out_wimask_T_25; // @[RegisterRouter.scala:87:24] wire out_romask_25 = \|_out_romask_T_25; // @[RegisterRouter.scala:87:24] wire out_womask_25 = &_out_womask_T_25; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_25 = out_rivalid_25 & out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_282 = out_f_rivalid_25; // @[RegisterRouter.scala:87:24] wire out_f_roready_25 = out_roready_25 & out_romask_25; // @[RegisterRouter.scala:87:24] wire _out_T_283 = out_f_roready_25; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_25 = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_284 = out_f_wivalid_25; // @[RegisterRouter.scala:87:24] assign out_f_woready_25 = out_woready_25 & out_womask_25; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_25; // @[RegisterRouter.scala:87:24] wire _out_T_285 = out_f_woready_25; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_25 ? _out_T_281 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_286 = ~out_rimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_287 = ~out_wimask_25; // @[RegisterRouter.scala:87:24] wire _out_T_288 = ~out_romask_25; // @[RegisterRouter.scala:87:24] wire _out_T_289 = ~out_womask_25; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_20 = {oldBytes_1, _out_prepend_T_20}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_290 = out_prepend_20; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_291 = _out_T_290; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_21 = _out_T_291; // @[RegisterRouter.scala:87:24] wire out_rimask_26 = \|_out_rimask_T_26; // @[RegisterRouter.scala:87:24] wire out_wimask_26 = &_out_wimask_T_26; // @[RegisterRouter.scala:87:24] wire out_romask_26 = \|_out_romask_T_26; // @[RegisterRouter.scala:87:24] wire out_womask_26 = &_out_womask_T_26; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_26 = out_rivalid_26 & out_rimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_293 = out_f_rivalid_26; // @[RegisterRouter.scala:87:24] wire out_f_roready_26 = out_roready_26 & out_romask_26; // @[RegisterRouter.scala:87:24] wire _out_T_294 = out_f_roready_26; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_26 = out_wivalid_26 & out_wimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_295 = out_f_wivalid_26; // @[RegisterRouter.scala:87:24] assign out_f_woready_26 = out_woready_26 & out_womask_26; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_26; // @[RegisterRouter.scala:87:24] wire _out_T_296 = out_f_woready_26; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_26 ? _out_T_292 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_297 = ~out_rimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_298 = ~out_wimask_26; // @[RegisterRouter.scala:87:24] wire _out_T_299 = ~out_romask_26; // @[RegisterRouter.scala:87:24] wire _out_T_300 = ~out_womask_26; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_21 = {oldBytes_2, _out_prepend_T_21}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_301 = out_prepend_21; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_302 = _out_T_301; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_22 = _out_T_302; // @[RegisterRouter.scala:87:24] wire out_rimask_27 = \|_out_rimask_T_27; // @[RegisterRouter.scala:87:24] wire out_wimask_27 = &_out_wimask_T_27; // @[RegisterRouter.scala:87:24] wire out_romask_27 = \|_out_romask_T_27; // @[RegisterRouter.scala:87:24] wire out_womask_27 = &_out_womask_T_27; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_27 = out_rivalid_27 & out_rimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_304 = out_f_rivalid_27; // @[RegisterRouter.scala:87:24] wire out_f_roready_27 = out_roready_27 & out_romask_27; // @[RegisterRouter.scala:87:24] wire _out_T_305 = out_f_roready_27; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_27 = out_wivalid_27 & out_wimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_306 = out_f_wivalid_27; // @[RegisterRouter.scala:87:24] assign out_f_woready_27 = out_woready_27 & out_womask_27; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_27; // @[RegisterRouter.scala:87:24] wire _out_T_307 = out_f_woready_27; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_27 ? _out_T_303 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_308 = ~out_rimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_309 = ~out_wimask_27; // @[RegisterRouter.scala:87:24] wire _out_T_310 = ~out_romask_27; // @[RegisterRouter.scala:87:24] wire _out_T_311 = ~out_womask_27; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_22 = {oldBytes_3, _out_prepend_T_22}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_312 = out_prepend_22; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_313 = _out_T_312; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_23 = _out_T_313; // @[RegisterRouter.scala:87:24] wire out_rimask_28 = \|_out_rimask_T_28; // @[RegisterRouter.scala:87:24] wire out_wimask_28 = &_out_wimask_T_28; // @[RegisterRouter.scala:87:24] wire out_romask_28 = \|_out_romask_T_28; // @[RegisterRouter.scala:87:24] wire out_womask_28 = &_out_womask_T_28; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_28 = out_rivalid_28 & out_rimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_315 = out_f_rivalid_28; // @[RegisterRouter.scala:87:24] wire out_f_roready_28 = out_roready_28 & out_romask_28; // @[RegisterRouter.scala:87:24] wire _out_T_316 = out_f_roready_28; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_28 = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_317 = out_f_wivalid_28; // @[RegisterRouter.scala:87:24] assign out_f_woready_28 = out_woready_28 & out_womask_28; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_28; // @[RegisterRouter.scala:87:24] wire _out_T_318 = out_f_woready_28; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_28 ? _out_T_314 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_319 = ~out_rimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_320 = ~out_wimask_28; // @[RegisterRouter.scala:87:24] wire _out_T_321 = ~out_romask_28; // @[RegisterRouter.scala:87:24] wire _out_T_322 = ~out_womask_28; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_23 = {oldBytes_4, _out_prepend_T_23}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_323 = out_prepend_23; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_324 = _out_T_323; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_24 = _out_T_324; // @[RegisterRouter.scala:87:24] wire out_rimask_29 = \|_out_rimask_T_29; // @[RegisterRouter.scala:87:24] wire out_wimask_29 = &_out_wimask_T_29; // @[RegisterRouter.scala:87:24] wire out_romask_29 = \|_out_romask_T_29; // @[RegisterRouter.scala:87:24] wire out_womask_29 = &_out_womask_T_29; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_29 = out_rivalid_29 & out_rimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_326 = out_f_rivalid_29; // @[RegisterRouter.scala:87:24] wire out_f_roready_29 = out_roready_29 & out_romask_29; // @[RegisterRouter.scala:87:24] wire _out_T_327 = out_f_roready_29; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_29 = out_wivalid_29 & out_wimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_328 = out_f_wivalid_29; // @[RegisterRouter.scala:87:24] assign out_f_woready_29 = out_woready_29 & out_womask_29; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_29; // @[RegisterRouter.scala:87:24] wire _out_T_329 = out_f_woready_29; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_29 ? _out_T_325 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_330 = ~out_rimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_331 = ~out_wimask_29; // @[RegisterRouter.scala:87:24] wire _out_T_332 = ~out_romask_29; // @[RegisterRouter.scala:87:24] wire _out_T_333 = ~out_womask_29; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_24 = {oldBytes_5, _out_prepend_T_24}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_334 = out_prepend_24; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_335 = _out_T_334; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_25 = _out_T_335; // @[RegisterRouter.scala:87:24] wire out_rimask_30 = \|_out_rimask_T_30; // @[RegisterRouter.scala:87:24] wire out_wimask_30 = &_out_wimask_T_30; // @[RegisterRouter.scala:87:24] wire out_romask_30 = \|_out_romask_T_30; // @[RegisterRouter.scala:87:24] wire out_womask_30 = &_out_womask_T_30; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_30 = out_rivalid_30 & out_rimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_337 = out_f_rivalid_30; // @[RegisterRouter.scala:87:24] wire out_f_roready_30 = out_roready_30 & out_romask_30; // @[RegisterRouter.scala:87:24] wire _out_T_338 = out_f_roready_30; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_30 = out_wivalid_30 & out_wimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_339 = out_f_wivalid_30; // @[RegisterRouter.scala:87:24] assign out_f_woready_30 = out_woready_30 & out_womask_30; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_30; // @[RegisterRouter.scala:87:24] wire _out_T_340 = out_f_woready_30; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_30 ? _out_T_336 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_341 = ~out_rimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_342 = ~out_wimask_30; // @[RegisterRouter.scala:87:24] wire _out_T_343 = ~out_romask_30; // @[RegisterRouter.scala:87:24] wire _out_T_344 = ~out_womask_30; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_25 = {oldBytes_6, _out_prepend_T_25}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_345 = out_prepend_25; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_346 = _out_T_345; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_26 = _out_T_346; // @[RegisterRouter.scala:87:24] wire out_rimask_31 = \|_out_rimask_T_31; // @[RegisterRouter.scala:87:24] wire out_wimask_31 = &_out_wimask_T_31; // @[RegisterRouter.scala:87:24] wire out_romask_31 = \|_out_romask_T_31; // @[RegisterRouter.scala:87:24] wire out_womask_31 = &_out_womask_T_31; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_31 = out_rivalid_31 & out_rimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_348 = out_f_rivalid_31; // @[RegisterRouter.scala:87:24] wire out_f_roready_31 = out_roready_31 & out_romask_31; // @[RegisterRouter.scala:87:24] wire _out_T_349 = out_f_roready_31; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_31 = out_wivalid_31 & out_wimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_350 = out_f_wivalid_31; // @[RegisterRouter.scala:87:24] assign out_f_woready_31 = out_woready_31 & out_womask_31; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_31; // @[RegisterRouter.scala:87:24] wire _out_T_351 = out_f_woready_31; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_31 ? _out_T_347 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_352 = ~out_rimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_353 = ~out_wimask_31; // @[RegisterRouter.scala:87:24] wire _out_T_354 = ~out_romask_31; // @[RegisterRouter.scala:87:24] wire _out_T_355 = ~out_womask_31; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_26 = {oldBytes_7, _out_prepend_T_26}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_356 = out_prepend_26; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_357 = _out_T_356; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_4 = _out_T_357; // @[MuxLiteral.scala:49:48] wire out_rimask_32 = \|_out_rimask_T_32; // @[RegisterRouter.scala:87:24] wire out_wimask_32 = &_out_wimask_T_32; // @[RegisterRouter.scala:87:24] wire out_romask_32 = \|_out_romask_T_32; // @[RegisterRouter.scala:87:24] wire out_womask_32 = &_out_womask_T_32; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_32 = out_rivalid_32 & out_rimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_359 = out_f_rivalid_32; // @[RegisterRouter.scala:87:24] wire out_f_roready_32 = out_roready_32 & out_romask_32; // @[RegisterRouter.scala:87:24] wire _out_T_360 = out_f_roready_32; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_32 = out_wivalid_32 & out_wimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_361 = out_f_wivalid_32; // @[RegisterRouter.scala:87:24] assign out_f_woready_32 = out_woready_32 & out_womask_32; // @[RegisterRouter.scala:87:24] assign valids_3_0 = out_f_woready_32; // @[RegisterRouter.scala:87:24] wire _out_T_362 = out_f_woready_32; // @[RegisterRouter.scala:87:24] assign newBytes_3_0 = out_f_woready_32 ? _out_T_358 : oldBytes_3_0; // @[RegisterRouter.scala:87:24] wire _out_T_363 = ~out_rimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_364 = ~out_wimask_32; // @[RegisterRouter.scala:87:24] wire _out_T_365 = ~out_romask_32; // @[RegisterRouter.scala:87:24] wire _out_T_366 = ~out_womask_32; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_368 = _out_T_367; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_27 = _out_T_368; // @[RegisterRouter.scala:87:24] wire out_rimask_33 = \|_out_rimask_T_33; // @[RegisterRouter.scala:87:24] wire out_wimask_33 = &_out_wimask_T_33; // @[RegisterRouter.scala:87:24] wire out_romask_33 = \|_out_romask_T_33; // @[RegisterRouter.scala:87:24] wire out_womask_33 = &_out_womask_T_33; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_33 = out_rivalid_33 & out_rimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_370 = out_f_rivalid_33; // @[RegisterRouter.scala:87:24] wire out_f_roready_33 = out_roready_33 & out_romask_33; // @[RegisterRouter.scala:87:24] wire _out_T_371 = out_f_roready_33; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_33 = out_wivalid_33 & out_wimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_372 = out_f_wivalid_33; // @[RegisterRouter.scala:87:24] assign out_f_woready_33 = out_woready_33 & out_womask_33; // @[RegisterRouter.scala:87:24] assign valids_3_1 = out_f_woready_33; // @[RegisterRouter.scala:87:24] wire _out_T_373 = out_f_woready_33; // @[RegisterRouter.scala:87:24] assign newBytes_3_1 = out_f_woready_33 ? _out_T_369 : oldBytes_3_1; // @[RegisterRouter.scala:87:24] wire _out_T_374 = ~out_rimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_375 = ~out_wimask_33; // @[RegisterRouter.scala:87:24] wire _out_T_376 = ~out_romask_33; // @[RegisterRouter.scala:87:24] wire _out_T_377 = ~out_womask_33; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_27 = {oldBytes_3_1, _out_prepend_T_27}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_378 = out_prepend_27; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_379 = _out_T_378; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_28 = _out_T_379; // @[RegisterRouter.scala:87:24] wire out_rimask_34 = \|_out_rimask_T_34; // @[RegisterRouter.scala:87:24] wire out_wimask_34 = &_out_wimask_T_34; // @[RegisterRouter.scala:87:24] wire out_romask_34 = \|_out_romask_T_34; // @[RegisterRouter.scala:87:24] wire out_womask_34 = &_out_womask_T_34; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_34 = out_rivalid_34 & out_rimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_381 = out_f_rivalid_34; // @[RegisterRouter.scala:87:24] wire out_f_roready_34 = out_roready_34 & out_romask_34; // @[RegisterRouter.scala:87:24] wire _out_T_382 = out_f_roready_34; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_34 = out_wivalid_34 & out_wimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_383 = out_f_wivalid_34; // @[RegisterRouter.scala:87:24] assign out_f_woready_34 = out_woready_34 & out_womask_34; // @[RegisterRouter.scala:87:24] assign valids_3_2 = out_f_woready_34; // @[RegisterRouter.scala:87:24] wire _out_T_384 = out_f_woready_34; // @[RegisterRouter.scala:87:24] assign newBytes_3_2 = out_f_woready_34 ? _out_T_380 : oldBytes_3_2; // @[RegisterRouter.scala:87:24] wire _out_T_385 = ~out_rimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_386 = ~out_wimask_34; // @[RegisterRouter.scala:87:24] wire _out_T_387 = ~out_romask_34; // @[RegisterRouter.scala:87:24] wire _out_T_388 = ~out_womask_34; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_28 = {oldBytes_3_2, _out_prepend_T_28}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_389 = out_prepend_28; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_390 = _out_T_389; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_29 = _out_T_390; // @[RegisterRouter.scala:87:24] wire out_rimask_35 = \|_out_rimask_T_35; // @[RegisterRouter.scala:87:24] wire out_wimask_35 = &_out_wimask_T_35; // @[RegisterRouter.scala:87:24] wire out_romask_35 = \|_out_romask_T_35; // @[RegisterRouter.scala:87:24] wire out_womask_35 = &_out_womask_T_35; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_35 = out_rivalid_35 & out_rimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_392 = out_f_rivalid_35; // @[RegisterRouter.scala:87:24] wire out_f_roready_35 = out_roready_35 & out_romask_35; // @[RegisterRouter.scala:87:24] wire _out_T_393 = out_f_roready_35; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_35 = out_wivalid_35 & out_wimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_394 = out_f_wivalid_35; // @[RegisterRouter.scala:87:24] assign out_f_woready_35 = out_woready_35 & out_womask_35; // @[RegisterRouter.scala:87:24] assign valids_3_3 = out_f_woready_35; // @[RegisterRouter.scala:87:24] wire _out_T_395 = out_f_woready_35; // @[RegisterRouter.scala:87:24] assign newBytes_3_3 = out_f_woready_35 ? _out_T_391 : oldBytes_3_3; // @[RegisterRouter.scala:87:24] wire _out_T_396 = ~out_rimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_397 = ~out_wimask_35; // @[RegisterRouter.scala:87:24] wire _out_T_398 = ~out_romask_35; // @[RegisterRouter.scala:87:24] wire _out_T_399 = ~out_womask_35; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_29 = {oldBytes_3_3, _out_prepend_T_29}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_400 = out_prepend_29; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_401 = _out_T_400; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_30 = _out_T_401; // @[RegisterRouter.scala:87:24] wire out_rimask_36 = \|_out_rimask_T_36; // @[RegisterRouter.scala:87:24] wire out_wimask_36 = &_out_wimask_T_36; // @[RegisterRouter.scala:87:24] wire out_romask_36 = \|_out_romask_T_36; // @[RegisterRouter.scala:87:24] wire out_womask_36 = &_out_womask_T_36; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_36 = out_rivalid_36 & out_rimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_403 = out_f_rivalid_36; // @[RegisterRouter.scala:87:24] wire out_f_roready_36 = out_roready_36 & out_romask_36; // @[RegisterRouter.scala:87:24] wire _out_T_404 = out_f_roready_36; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_36 = out_wivalid_36 & out_wimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_405 = out_f_wivalid_36; // @[RegisterRouter.scala:87:24] assign out_f_woready_36 = out_woready_36 & out_womask_36; // @[RegisterRouter.scala:87:24] assign valids_3_4 = out_f_woready_36; // @[RegisterRouter.scala:87:24] wire _out_T_406 = out_f_woready_36; // @[RegisterRouter.scala:87:24] assign newBytes_3_4 = out_f_woready_36 ? _out_T_402 : oldBytes_3_4; // @[RegisterRouter.scala:87:24] wire _out_T_407 = ~out_rimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_408 = ~out_wimask_36; // @[RegisterRouter.scala:87:24] wire _out_T_409 = ~out_romask_36; // @[RegisterRouter.scala:87:24] wire _out_T_410 = ~out_womask_36; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_30 = {oldBytes_3_4, _out_prepend_T_30}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_411 = out_prepend_30; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_412 = _out_T_411; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_31 = _out_T_412; // @[RegisterRouter.scala:87:24] wire out_rimask_37 = \|_out_rimask_T_37; // @[RegisterRouter.scala:87:24] wire out_wimask_37 = &_out_wimask_T_37; // @[RegisterRouter.scala:87:24] wire out_romask_37 = \|_out_romask_T_37; // @[RegisterRouter.scala:87:24] wire out_womask_37 = &_out_womask_T_37; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_37 = out_rivalid_37 & out_rimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_414 = out_f_rivalid_37; // @[RegisterRouter.scala:87:24] wire out_f_roready_37 = out_roready_37 & out_romask_37; // @[RegisterRouter.scala:87:24] wire _out_T_415 = out_f_roready_37; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_37 = out_wivalid_37 & out_wimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_416 = out_f_wivalid_37; // @[RegisterRouter.scala:87:24] assign out_f_woready_37 = out_woready_37 & out_womask_37; // @[RegisterRouter.scala:87:24] assign valids_3_5 = out_f_woready_37; // @[RegisterRouter.scala:87:24] wire _out_T_417 = out_f_woready_37; // @[RegisterRouter.scala:87:24] assign newBytes_3_5 = out_f_woready_37 ? _out_T_413 : oldBytes_3_5; // @[RegisterRouter.scala:87:24] wire _out_T_418 = ~out_rimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_419 = ~out_wimask_37; // @[RegisterRouter.scala:87:24] wire _out_T_420 = ~out_romask_37; // @[RegisterRouter.scala:87:24] wire _out_T_421 = ~out_womask_37; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_31 = {oldBytes_3_5, _out_prepend_T_31}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_422 = out_prepend_31; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_423 = _out_T_422; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_32 = _out_T_423; // @[RegisterRouter.scala:87:24] wire out_rimask_38 = \|_out_rimask_T_38; // @[RegisterRouter.scala:87:24] wire out_wimask_38 = &_out_wimask_T_38; // @[RegisterRouter.scala:87:24] wire out_romask_38 = \|_out_romask_T_38; // @[RegisterRouter.scala:87:24] wire out_womask_38 = &_out_womask_T_38; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_38 = out_rivalid_38 & out_rimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_425 = out_f_rivalid_38; // @[RegisterRouter.scala:87:24] wire out_f_roready_38 = out_roready_38 & out_romask_38; // @[RegisterRouter.scala:87:24] wire _out_T_426 = out_f_roready_38; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_38 = out_wivalid_38 & out_wimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_427 = out_f_wivalid_38; // @[RegisterRouter.scala:87:24] assign out_f_woready_38 = out_woready_38 & out_womask_38; // @[RegisterRouter.scala:87:24] assign valids_3_6 = out_f_woready_38; // @[RegisterRouter.scala:87:24] wire _out_T_428 = out_f_woready_38; // @[RegisterRouter.scala:87:24] assign newBytes_3_6 = out_f_woready_38 ? _out_T_424 : oldBytes_3_6; // @[RegisterRouter.scala:87:24] wire _out_T_429 = ~out_rimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_430 = ~out_wimask_38; // @[RegisterRouter.scala:87:24] wire _out_T_431 = ~out_romask_38; // @[RegisterRouter.scala:87:24] wire _out_T_432 = ~out_womask_38; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_32 = {oldBytes_3_6, _out_prepend_T_32}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_433 = out_prepend_32; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_434 = _out_T_433; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_33 = _out_T_434; // @[RegisterRouter.scala:87:24] wire out_rimask_39 = \|_out_rimask_T_39; // @[RegisterRouter.scala:87:24] wire out_wimask_39 = &_out_wimask_T_39; // @[RegisterRouter.scala:87:24] wire out_romask_39 = \|_out_romask_T_39; // @[RegisterRouter.scala:87:24] wire out_womask_39 = &_out_womask_T_39; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_39 = out_rivalid_39 & out_rimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_436 = out_f_rivalid_39; // @[RegisterRouter.scala:87:24] wire out_f_roready_39 = out_roready_39 & out_romask_39; // @[RegisterRouter.scala:87:24] wire _out_T_437 = out_f_roready_39; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_39 = out_wivalid_39 & out_wimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_438 = out_f_wivalid_39; // @[RegisterRouter.scala:87:24] assign out_f_woready_39 = out_woready_39 & out_womask_39; // @[RegisterRouter.scala:87:24] assign valids_3_7 = out_f_woready_39; // @[RegisterRouter.scala:87:24] wire _out_T_439 = out_f_woready_39; // @[RegisterRouter.scala:87:24] assign newBytes_3_7 = out_f_woready_39 ? _out_T_435 : oldBytes_3_7; // @[RegisterRouter.scala:87:24] wire _out_T_440 = ~out_rimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_441 = ~out_wimask_39; // @[RegisterRouter.scala:87:24] wire _out_T_442 = ~out_romask_39; // @[RegisterRouter.scala:87:24] wire _out_T_443 = ~out_womask_39; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_33 = {oldBytes_3_7, _out_prepend_T_33}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_444 = out_prepend_33; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_445 = _out_T_444; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_7 = _out_T_445; // @[MuxLiteral.scala:49:48] wire out_rimask_40 = \|_out_rimask_T_40; // @[RegisterRouter.scala:87:24] wire out_wimask_40 = &_out_wimask_T_40; // @[RegisterRouter.scala:87:24] wire out_romask_40 = \|_out_romask_T_40; // @[RegisterRouter.scala:87:24] wire out_womask_40 = &_out_womask_T_40; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_40 = out_rivalid_40 & out_rimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_447 = out_f_rivalid_40; // @[RegisterRouter.scala:87:24] wire out_f_roready_40 = out_roready_40 & out_romask_40; // @[RegisterRouter.scala:87:24] wire _out_T_448 = out_f_roready_40; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_40 = out_wivalid_40 & out_wimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_449 = out_f_wivalid_40; // @[RegisterRouter.scala:87:24] assign out_f_woready_40 = out_woready_40 & out_womask_40; // @[RegisterRouter.scala:87:24] assign valids_2_0 = out_f_woready_40; // @[RegisterRouter.scala:87:24] wire _out_T_450 = out_f_woready_40; // @[RegisterRouter.scala:87:24] assign newBytes_2_0 = out_f_woready_40 ? _out_T_446 : oldBytes_2_0; // @[RegisterRouter.scala:87:24] wire _out_T_451 = ~out_rimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_452 = ~out_wimask_40; // @[RegisterRouter.scala:87:24] wire _out_T_453 = ~out_romask_40; // @[RegisterRouter.scala:87:24] wire _out_T_454 = ~out_womask_40; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_456 = _out_T_455; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_34 = _out_T_456; // @[RegisterRouter.scala:87:24] wire out_rimask_41 = \|_out_rimask_T_41; // @[RegisterRouter.scala:87:24] wire out_wimask_41 = &_out_wimask_T_41; // @[RegisterRouter.scala:87:24] wire out_romask_41 = \|_out_romask_T_41; // @[RegisterRouter.scala:87:24] wire out_womask_41 = &_out_womask_T_41; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_41 = out_rivalid_41 & out_rimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_458 = out_f_rivalid_41; // @[RegisterRouter.scala:87:24] wire out_f_roready_41 = out_roready_41 & out_romask_41; // @[RegisterRouter.scala:87:24] wire _out_T_459 = out_f_roready_41; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_41 = out_wivalid_41 & out_wimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_460 = out_f_wivalid_41; // @[RegisterRouter.scala:87:24] assign out_f_woready_41 = out_woready_41 & out_womask_41; // @[RegisterRouter.scala:87:24] assign valids_2_1 = out_f_woready_41; // @[RegisterRouter.scala:87:24] wire _out_T_461 = out_f_woready_41; // @[RegisterRouter.scala:87:24] assign newBytes_2_1 = out_f_woready_41 ? _out_T_457 : oldBytes_2_1; // @[RegisterRouter.scala:87:24] wire _out_T_462 = ~out_rimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_463 = ~out_wimask_41; // @[RegisterRouter.scala:87:24] wire _out_T_464 = ~out_romask_41; // @[RegisterRouter.scala:87:24] wire _out_T_465 = ~out_womask_41; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_34 = {oldBytes_2_1, _out_prepend_T_34}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_466 = out_prepend_34; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_467 = _out_T_466; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_35 = _out_T_467; // @[RegisterRouter.scala:87:24] wire out_rimask_42 = \|_out_rimask_T_42; // @[RegisterRouter.scala:87:24] wire out_wimask_42 = &_out_wimask_T_42; // @[RegisterRouter.scala:87:24] wire out_romask_42 = \|_out_romask_T_42; // @[RegisterRouter.scala:87:24] wire out_womask_42 = &_out_womask_T_42; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_42 = out_rivalid_42 & out_rimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_469 = out_f_rivalid_42; // @[RegisterRouter.scala:87:24] wire out_f_roready_42 = out_roready_42 & out_romask_42; // @[RegisterRouter.scala:87:24] wire _out_T_470 = out_f_roready_42; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_42 = out_wivalid_42 & out_wimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_471 = out_f_wivalid_42; // @[RegisterRouter.scala:87:24] assign out_f_woready_42 = out_woready_42 & out_womask_42; // @[RegisterRouter.scala:87:24] assign valids_2_2 = out_f_woready_42; // @[RegisterRouter.scala:87:24] wire _out_T_472 = out_f_woready_42; // @[RegisterRouter.scala:87:24] assign newBytes_2_2 = out_f_woready_42 ? _out_T_468 : oldBytes_2_2; // @[RegisterRouter.scala:87:24] wire _out_T_473 = ~out_rimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_474 = ~out_wimask_42; // @[RegisterRouter.scala:87:24] wire _out_T_475 = ~out_romask_42; // @[RegisterRouter.scala:87:24] wire _out_T_476 = ~out_womask_42; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_35 = {oldBytes_2_2, _out_prepend_T_35}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_477 = out_prepend_35; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_478 = _out_T_477; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_36 = _out_T_478; // @[RegisterRouter.scala:87:24] wire out_rimask_43 = \|_out_rimask_T_43; // @[RegisterRouter.scala:87:24] wire out_wimask_43 = &_out_wimask_T_43; // @[RegisterRouter.scala:87:24] wire out_romask_43 = \|_out_romask_T_43; // @[RegisterRouter.scala:87:24] wire out_womask_43 = &_out_womask_T_43; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_43 = out_rivalid_43 & out_rimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_480 = out_f_rivalid_43; // @[RegisterRouter.scala:87:24] wire out_f_roready_43 = out_roready_43 & out_romask_43; // @[RegisterRouter.scala:87:24] wire _out_T_481 = out_f_roready_43; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_43 = out_wivalid_43 & out_wimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_482 = out_f_wivalid_43; // @[RegisterRouter.scala:87:24] assign out_f_woready_43 = out_woready_43 & out_womask_43; // @[RegisterRouter.scala:87:24] assign valids_2_3 = out_f_woready_43; // @[RegisterRouter.scala:87:24] wire _out_T_483 = out_f_woready_43; // @[RegisterRouter.scala:87:24] assign newBytes_2_3 = out_f_woready_43 ? _out_T_479 : oldBytes_2_3; // @[RegisterRouter.scala:87:24] wire _out_T_484 = ~out_rimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_485 = ~out_wimask_43; // @[RegisterRouter.scala:87:24] wire _out_T_486 = ~out_romask_43; // @[RegisterRouter.scala:87:24] wire _out_T_487 = ~out_womask_43; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_36 = {oldBytes_2_3, _out_prepend_T_36}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_488 = out_prepend_36; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_489 = _out_T_488; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_37 = _out_T_489; // @[RegisterRouter.scala:87:24] wire out_rimask_44 = \|_out_rimask_T_44; // @[RegisterRouter.scala:87:24] wire out_wimask_44 = &_out_wimask_T_44; // @[RegisterRouter.scala:87:24] wire out_romask_44 = \|_out_romask_T_44; // @[RegisterRouter.scala:87:24] wire out_womask_44 = &_out_womask_T_44; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_44 = out_rivalid_44 & out_rimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_491 = out_f_rivalid_44; // @[RegisterRouter.scala:87:24] wire out_f_roready_44 = out_roready_44 & out_romask_44; // @[RegisterRouter.scala:87:24] wire _out_T_492 = out_f_roready_44; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_44 = out_wivalid_44 & out_wimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_493 = out_f_wivalid_44; // @[RegisterRouter.scala:87:24] assign out_f_woready_44 = out_woready_44 & out_womask_44; // @[RegisterRouter.scala:87:24] assign valids_2_4 = out_f_woready_44; // @[RegisterRouter.scala:87:24] wire _out_T_494 = out_f_woready_44; // @[RegisterRouter.scala:87:24] assign newBytes_2_4 = out_f_woready_44 ? _out_T_490 : oldBytes_2_4; // @[RegisterRouter.scala:87:24] wire _out_T_495 = ~out_rimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_496 = ~out_wimask_44; // @[RegisterRouter.scala:87:24] wire _out_T_497 = ~out_romask_44; // @[RegisterRouter.scala:87:24] wire _out_T_498 = ~out_womask_44; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_37 = {oldBytes_2_4, _out_prepend_T_37}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_499 = out_prepend_37; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_500 = _out_T_499; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_38 = _out_T_500; // @[RegisterRouter.scala:87:24] wire out_rimask_45 = \|_out_rimask_T_45; // @[RegisterRouter.scala:87:24] wire out_wimask_45 = &_out_wimask_T_45; // @[RegisterRouter.scala:87:24] wire out_romask_45 = \|_out_romask_T_45; // @[RegisterRouter.scala:87:24] wire out_womask_45 = &_out_womask_T_45; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_45 = out_rivalid_45 & out_rimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_502 = out_f_rivalid_45; // @[RegisterRouter.scala:87:24] wire out_f_roready_45 = out_roready_45 & out_romask_45; // @[RegisterRouter.scala:87:24] wire _out_T_503 = out_f_roready_45; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_45 = out_wivalid_45 & out_wimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_504 = out_f_wivalid_45; // @[RegisterRouter.scala:87:24] assign out_f_woready_45 = out_woready_45 & out_womask_45; // @[RegisterRouter.scala:87:24] assign valids_2_5 = out_f_woready_45; // @[RegisterRouter.scala:87:24] wire _out_T_505 = out_f_woready_45; // @[RegisterRouter.scala:87:24] assign newBytes_2_5 = out_f_woready_45 ? _out_T_501 : oldBytes_2_5; // @[RegisterRouter.scala:87:24] wire _out_T_506 = ~out_rimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_507 = ~out_wimask_45; // @[RegisterRouter.scala:87:24] wire _out_T_508 = ~out_romask_45; // @[RegisterRouter.scala:87:24] wire _out_T_509 = ~out_womask_45; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_38 = {oldBytes_2_5, _out_prepend_T_38}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_510 = out_prepend_38; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_511 = _out_T_510; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_39 = _out_T_511; // @[RegisterRouter.scala:87:24] wire out_rimask_46 = \|_out_rimask_T_46; // @[RegisterRouter.scala:87:24] wire out_wimask_46 = &_out_wimask_T_46; // @[RegisterRouter.scala:87:24] wire out_romask_46 = \|_out_romask_T_46; // @[RegisterRouter.scala:87:24] wire out_womask_46 = &_out_womask_T_46; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_46 = out_rivalid_46 & out_rimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_513 = out_f_rivalid_46; // @[RegisterRouter.scala:87:24] wire out_f_roready_46 = out_roready_46 & out_romask_46; // @[RegisterRouter.scala:87:24] wire _out_T_514 = out_f_roready_46; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_46 = out_wivalid_46 & out_wimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_515 = out_f_wivalid_46; // @[RegisterRouter.scala:87:24] assign out_f_woready_46 = out_woready_46 & out_womask_46; // @[RegisterRouter.scala:87:24] assign valids_2_6 = out_f_woready_46; // @[RegisterRouter.scala:87:24] wire _out_T_516 = out_f_woready_46; // @[RegisterRouter.scala:87:24] assign newBytes_2_6 = out_f_woready_46 ? _out_T_512 : oldBytes_2_6; // @[RegisterRouter.scala:87:24] wire _out_T_517 = ~out_rimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_518 = ~out_wimask_46; // @[RegisterRouter.scala:87:24] wire _out_T_519 = ~out_romask_46; // @[RegisterRouter.scala:87:24] wire _out_T_520 = ~out_womask_46; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_39 = {oldBytes_2_6, _out_prepend_T_39}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_521 = out_prepend_39; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_522 = _out_T_521; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_40 = _out_T_522; // @[RegisterRouter.scala:87:24] wire out_rimask_47 = \|_out_rimask_T_47; // @[RegisterRouter.scala:87:24] wire out_wimask_47 = &_out_wimask_T_47; // @[RegisterRouter.scala:87:24] wire out_romask_47 = \|_out_romask_T_47; // @[RegisterRouter.scala:87:24] wire out_womask_47 = &_out_womask_T_47; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_47 = out_rivalid_47 & out_rimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_524 = out_f_rivalid_47; // @[RegisterRouter.scala:87:24] wire out_f_roready_47 = out_roready_47 & out_romask_47; // @[RegisterRouter.scala:87:24] wire _out_T_525 = out_f_roready_47; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_47 = out_wivalid_47 & out_wimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_526 = out_f_wivalid_47; // @[RegisterRouter.scala:87:24] assign out_f_woready_47 = out_woready_47 & out_womask_47; // @[RegisterRouter.scala:87:24] assign valids_2_7 = out_f_woready_47; // @[RegisterRouter.scala:87:24] wire _out_T_527 = out_f_woready_47; // @[RegisterRouter.scala:87:24] assign newBytes_2_7 = out_f_woready_47 ? _out_T_523 : oldBytes_2_7; // @[RegisterRouter.scala:87:24] wire _out_T_528 = ~out_rimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_529 = ~out_wimask_47; // @[RegisterRouter.scala:87:24] wire _out_T_530 = ~out_romask_47; // @[RegisterRouter.scala:87:24] wire _out_T_531 = ~out_womask_47; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_40 = {oldBytes_2_7, _out_prepend_T_40}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_532 = out_prepend_40; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_533 = _out_T_532; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_6 = _out_T_533; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex_hi = {_out_iindex_T_11, _out_iindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_iindex = {out_iindex_hi, _out_iindex_T}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex_hi = {_out_oindex_T_11, _out_oindex_T_1}; // @[RegisterRouter.scala:87:24] wire [2:0] out_oindex = {out_oindex_hi, _out_oindex_T}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontSel_T = 8'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire out_frontSel_4 = _out_frontSel_T[4]; // @[OneHot.scala:58:35] wire out_frontSel_5 = _out_frontSel_T[5]; // @[OneHot.scala:58:35] wire out_frontSel_6 = _out_frontSel_T[6]; // @[OneHot.scala:58:35] wire out_frontSel_7 = _out_frontSel_T[7]; // @[OneHot.scala:58:35] wire [7:0] _out_backSel_T = 8'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire out_backSel_4 = _out_backSel_T[4]; // @[OneHot.scala:58:35] wire out_backSel_5 = _out_backSel_T[5]; // @[OneHot.scala:58:35] wire out_backSel_6 = _out_backSel_T[6]; // @[OneHot.scala:58:35] wire out_backSel_7 = _out_backSel_T[7]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11 = _out_rifireMux_T_10; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_rivalid_18 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_rivalid_19 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_rivalid_20 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_rivalid_21 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_rivalid_22 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_rivalid_23 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = _out_rifireMux_T_1 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_19 = _out_rifireMux_T_18 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_rivalid_24 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_25 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_26 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_27 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_28 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_29 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_30 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_rivalid_31 = _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_20 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_22 = _out_rifireMux_T_1 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_23 = _out_rifireMux_T_22 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_24 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_26 = _out_rifireMux_T_1 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_27 = _out_rifireMux_T_26 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_rivalid_40 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_41 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_42 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_43 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_44 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_45 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_46 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_rivalid_47 = _out_rifireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_30 = _out_rifireMux_T_1 & out_frontSel_7; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_31 = _out_rifireMux_T_30 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_rivalid_32 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_33 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_34 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_35 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_36 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_37 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_38 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_rivalid_39 = _out_rifireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12 = _out_wifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_18 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_19 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_20 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_21 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_22 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_wivalid_23 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = _out_wifireMux_T_2 & out_frontSel_4; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_20 = _out_wifireMux_T_19 & _out_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_24 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_25 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_26 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_27 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_28 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_29 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_30 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_wivalid_31 = _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_21 = ~_out_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_23 = _out_wifireMux_T_2 & out_frontSel_5; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_24 = _out_wifireMux_T_23 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_25 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_27 = _out_wifireMux_T_2 & out_frontSel_6; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_28 = _out_wifireMux_T_27 & _out_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_40 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_41 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_42 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_43 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_44 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_45 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_46 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_wivalid_47 = _out_wifireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = ~_out_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_31 = _out_wifireMux_T_2 & out_frontSel_7; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_32 = _out_wifireMux_T_31 & _out_T_10; // @[RegisterRouter.scala:87:24] assign out_wivalid_32 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_33 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_34 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_35 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_36 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_37 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_38 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_wivalid_39 = _out_wifireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = ~_out_T_10; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11 = _out_rofireMux_T_10; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_18 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_19 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_20 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_21 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_22 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] assign out_roready_23 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = _out_rofireMux_T_1 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_19 = _out_rofireMux_T_18 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_roready_24 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_25 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_26 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_27 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_28 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_29 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_30 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] assign out_roready_31 = _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_20 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_22 = _out_rofireMux_T_1 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_23 = _out_rofireMux_T_22 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_24 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_26 = _out_rofireMux_T_1 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_27 = _out_rofireMux_T_26 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_roready_40 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_41 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_42 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_43 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_44 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_45 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_46 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] assign out_roready_47 = _out_rofireMux_T_27; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_30 = _out_rofireMux_T_1 & out_backSel_7; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_31 = _out_rofireMux_T_30 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_32 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_33 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_34 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_35 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_36 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_37 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_38 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] assign out_roready_39 = _out_rofireMux_T_31; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = ~_out_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12 = _out_wofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_woready_18 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_woready_19 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_woready_20 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_woready_21 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_woready_22 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] assign out_woready_23 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = _out_wofireMux_T_2 & out_backSel_4; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_20 = _out_wofireMux_T_19 & _out_T_9; // @[RegisterRouter.scala:87:24] assign out_woready_24 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_25 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_26 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_27 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_28 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_29 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_30 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] assign out_woready_31 = _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_21 = ~_out_T_9; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_23 = _out_wofireMux_T_2 & out_backSel_5; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_24 = _out_wofireMux_T_23 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_25 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_27 = _out_wofireMux_T_2 & out_backSel_6; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_28 = _out_wofireMux_T_27 & _out_T_13; // @[RegisterRouter.scala:87:24] assign out_woready_40 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_41 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_42 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_43 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_44 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_45 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_46 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] assign out_woready_47 = _out_wofireMux_T_28; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = ~_out_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_31 = _out_wofireMux_T_2 & out_backSel_7; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_32 = _out_wofireMux_T_31 & _out_T_11; // @[RegisterRouter.scala:87:24] assign out_woready_32 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_33 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_34 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_35 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_36 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_37 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_38 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] assign out_woready_39 = _out_wofireMux_T_32; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = ~_out_T_11; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [7:0] _GEN_4 = {{_out_out_bits_data_WIRE_7}, {_out_out_bits_data_WIRE_6}, {_out_out_bits_data_WIRE_5}, {_out_out_bits_data_WIRE_4}, {_out_out_bits_data_WIRE_3}, {1'h1}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [7:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_7}, {_out_out_bits_data_WIRE_1_6}, {_out_out_bits_data_WIRE_1_5}, {_out_out_bits_data_WIRE_1_4}, {_out_out_bits_data_WIRE_1_3}, {64'h0}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] ipi_1 <= 1'h0; // @[CLINT.scala:78:41] ipi_2 <= 1'h0; // @[CLINT.scala:78:41] ipi_3 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_4_0 \| valids_4_1 \| valids_4_2 \| valids_4_3 \| valids_4_4 \| valids_4_5 \| valids_4_6 \| valids_4_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_14; // @[RegisterRouter.scala:87:24] if (out_f_woready_2) // @[RegisterRouter.scala:87:24] ipi_1 <= _out_T_34; // @[RegisterRouter.scala:87:24] if (out_f_woready_12) // @[RegisterRouter.scala:87:24] ipi_2 <= _out_T_142; // @[RegisterRouter.scala:87:24] if (out_f_woready_14) // @[RegisterRouter.scala:87:24] ipi_3 <= _out_T_162; // @[RegisterRouter.scala:87:24] end if (valids_0 \| valids_1 \| valids_2 \| valids_3 \| valids_4 \| valids_5 \| valids_6 \| valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] if (valids_1_0 \| valids_1_1 \| valids_1_2 \| valids_1_3 \| valids_1_4 \| valids_1_5 \| valids_1_6 \| valids_1_7) // @[RegField.scala:153:29, :154:27] timecmp_1 <= _timecmp_1_T; // @[RegField.scala:154:52] if (valids_2_0 \| valids_2_1 \| valids_2_2 \| valids_2_3 \| valids_2_4 \| valids_2_5 \| valids_2_6 \| valids_2_7) // @[RegField.scala:153:29, :154:27] timecmp_2 <= _timecmp_2_T; // @[RegField.scala:154:52] if (valids_3_0 \| valids_3_1 \| valids_3_2 \| valids_3_3 \| valids_3_4 \| valids_3_5 \| valids_3_6 \| valids_3_7) // @[RegField.scala:153:29, :154:27] timecmp_3 <= _timecmp_3_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_55 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_3_0 = auto_int_out_3_0_0; // @[CLINT.scala:65:9] assign auto_int_out_3_1 = auto_int_out_3_1_0; // @[CLINT.scala:65:9] assign auto_int_out_2_0 = auto_int_out_2_0_0; // @[CLINT.scala:65:9] assign auto_int_out_2_1 = auto_int_out_2_1_0; // @[CLINT.scala:65:9] assign auto_int_out_1_0 = auto_int_out_1_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1_1 = auto_int_out_1_1_0; // @[CLINT.scala:65:9] assign auto_int_out_0_0 = auto_int_out_0_0_0; // @[CLINT.scala:65:9] assign auto_int_out_0_1 = auto_int_out_0_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_196 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_356 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_196( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_356 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_24 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h11)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 node _source_ok_T_30 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[2]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[3]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[4]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[5]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[6]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[7]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_37, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = and(_T_11, _T_24) node _T_105 = and(_T_104, _T_37) node _T_106 = and(_T_105, _T_50) node _T_107 = and(_T_106, _T_63) node _T_108 = and(_T_107, _T_71) node _T_109 = and(_T_108, _T_79) node _T_110 = and(_T_109, _T_87) node _T_111 = and(_T_110, _T_95) node _T_112 = and(_T_111, _T_103) node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(_T_112, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_112, UInt<1>(0h1), "") : assert_1 node _T_116 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_116 : node _T_117 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_118 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<1>(0h0)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_4) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_127 = shr(io.in.a.bits.source, 2) node _T_128 = eq(_T_127, UInt<1>(0h1)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_5) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_132 = and(_T_130, _T_131) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_133 = shr(io.in.a.bits.source, 2) node _T_134 = eq(_T_133, UInt<2>(0h2)) node _T_135 = leq(UInt<1>(0h0), uncommonBits_6) node _T_136 = and(_T_134, _T_135) node _T_137 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_138 = and(_T_136, _T_137) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<2>(0h3)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_7) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_120, _T_126) node _T_151 = or(_T_150, _T_132) node _T_152 = or(_T_151, _T_138) node _T_153 = or(_T_152, _T_144) node _T_154 = or(_T_153, _T_145) node _T_155 = or(_T_154, _T_146) node _T_156 = or(_T_155, _T_147) node _T_157 = or(_T_156, _T_148) node _T_158 = or(_T_157, _T_149) node _T_159 = and(_T_119, _T_158) node _T_160 = or(UInt<1>(0h0), _T_159) node _T_161 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<17>(0h10000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = and(_T_161, _T_166) node _T_168 = or(UInt<1>(0h0), _T_167) node _T_169 = and(_T_160, _T_168) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_169, UInt<1>(0h1), "") : assert_2 node _T_173 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_174 = shr(io.in.a.bits.source, 2) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = leq(UInt<1>(0h0), uncommonBits_8) node _T_177 = and(_T_175, _T_176) node _T_178 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_179 = and(_T_177, _T_178) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_180 = shr(io.in.a.bits.source, 2) node _T_181 = eq(_T_180, UInt<1>(0h1)) node _T_182 = leq(UInt<1>(0h0), uncommonBits_9) node _T_183 = and(_T_181, _T_182) node _T_184 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_185 = and(_T_183, _T_184) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_186 = shr(io.in.a.bits.source, 2) node _T_187 = eq(_T_186, UInt<2>(0h2)) node _T_188 = leq(UInt<1>(0h0), uncommonBits_10) node _T_189 = and(_T_187, _T_188) node _T_190 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_191 = and(_T_189, _T_190) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_192 = shr(io.in.a.bits.source, 2) node _T_193 = eq(_T_192, UInt<2>(0h3)) node _T_194 = leq(UInt<1>(0h0), uncommonBits_11) node _T_195 = and(_T_193, _T_194) node _T_196 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_201 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_202 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_173 connect _WIRE[1], _T_179 connect _WIRE[2], _T_185 connect _WIRE[3], _T_191 connect _WIRE[4], _T_197 connect _WIRE[5], _T_198 connect _WIRE[6], _T_199 connect _WIRE[7], _T_200 connect _WIRE[8], _T_201 connect _WIRE[9], _T_202 node _T_203 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_204 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[6], _T_203, UInt<1>(0h0)) node _T_211 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_213 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = or(_T_204, _T_205) node _T_215 = or(_T_214, _T_206) node _T_216 = or(_T_215, _T_207) node _T_217 = or(_T_216, _T_208) node _T_218 = or(_T_217, _T_209) node _T_219 = or(_T_218, _T_210) node _T_220 = or(_T_219, _T_211) node _T_221 = or(_T_220, _T_212) node _T_222 = or(_T_221, _T_213) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_222 node _T_223 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_224 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_225 = and(_T_223, _T_224) node _T_226 = or(UInt<1>(0h0), _T_225) node _T_227 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<17>(0h10000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = and(_T_226, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = and(_WIRE_1, _T_233) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_234, UInt<1>(0h1), "") : assert_3 node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(source_ok, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_241 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : node _T_244 = eq(_T_241, UInt<1>(0h0)) when _T_244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_241, UInt<1>(0h1), "") : assert_5 node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(is_aligned, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_248, UInt<1>(0h1), "") : assert_7 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_253, UInt<1>(0h1), "") : assert_8 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_257, UInt<1>(0h1), "") : assert_9 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_12) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_13) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h2)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_14) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h3)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_15) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _T_290 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_294 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_295 = or(_T_265, _T_271) node _T_296 = or(_T_295, _T_277) node _T_297 = or(_T_296, _T_283) node _T_298 = or(_T_297, _T_289) node _T_299 = or(_T_298, _T_290) node _T_300 = or(_T_299, _T_291) node _T_301 = or(_T_300, _T_292) node _T_302 = or(_T_301, _T_293) node _T_303 = or(_T_302, _T_294) node _T_304 = and(_T_264, _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_307 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<17>(0h10000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = and(_T_306, _T_311) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = and(_T_305, _T_313) node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(_T_314, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_314, UInt<1>(0h1), "") : assert_10 node _T_318 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<1>(0h0)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_16) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_325 = shr(io.in.a.bits.source, 2) node _T_326 = eq(_T_325, UInt<1>(0h1)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_17) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_330 = and(_T_328, _T_329) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<2>(0h2)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_18) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_337 = shr(io.in.a.bits.source, 2) node _T_338 = eq(_T_337, UInt<2>(0h3)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_19) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_347 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_318 connect _WIRE_2[1], _T_324 connect _WIRE_2[2], _T_330 connect _WIRE_2[3], _T_336 connect _WIRE_2[4], _T_342 connect _WIRE_2[5], _T_343 connect _WIRE_2[6], _T_344 connect _WIRE_2[7], _T_345 connect _WIRE_2[8], _T_346 connect _WIRE_2[9], _T_347 node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_349 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_350 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_351 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_352 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_353 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_354 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = mux(_WIRE_2[6], _T_348, UInt<1>(0h0)) node _T_356 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = or(_T_349, _T_350) node _T_360 = or(_T_359, _T_351) node _T_361 = or(_T_360, _T_352) node _T_362 = or(_T_361, _T_353) node _T_363 = or(_T_362, _T_354) node _T_364 = or(_T_363, _T_355) node _T_365 = or(_T_364, _T_356) node _T_366 = or(_T_365, _T_357) node _T_367 = or(_T_366, _T_358) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_367 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = and(_T_371, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = and(_WIRE_3, _T_378) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_379, UInt<1>(0h1), "") : assert_11 node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(source_ok, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_386, UInt<1>(0h1), "") : assert_13 node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(is_aligned, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_393, UInt<1>(0h1), "") : assert_15 node _T_397 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_397, UInt<1>(0h1), "") : assert_16 node _T_401 = not(io.in.a.bits.mask) node _T_402 = eq(_T_401, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_402, UInt<1>(0h1), "") : assert_17 node _T_406 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_406, UInt<1>(0h1), "") : assert_18 node _T_410 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_410 : node _T_411 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_412 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_413 = and(_T_411, _T_412) node _T_414 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_20) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h1)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_21) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h2)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_22) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h3)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_23) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_444 = or(_T_414, _T_420) node _T_445 = or(_T_444, _T_426) node _T_446 = or(_T_445, _T_432) node _T_447 = or(_T_446, _T_438) node _T_448 = or(_T_447, _T_439) node _T_449 = or(_T_448, _T_440) node _T_450 = or(_T_449, _T_441) node _T_451 = or(_T_450, _T_442) node _T_452 = or(_T_451, _T_443) node _T_453 = and(_T_413, _T_452) node _T_454 = or(UInt<1>(0h0), _T_453) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_454, UInt<1>(0h1), "") : assert_19 node _T_458 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_459 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_460 = and(_T_458, _T_459) node _T_461 = or(UInt<1>(0h0), _T_460) node _T_462 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = and(_T_461, _T_466) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_468, UInt<1>(0h1), "") : assert_20 node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(source_ok, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(is_aligned, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_478 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_T_478, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_478, UInt<1>(0h1), "") : assert_23 node _T_482 = eq(io.in.a.bits.mask, mask) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_482, UInt<1>(0h1), "") : assert_24 node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_486, UInt<1>(0h1), "") : assert_25 node _T_490 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_490 : node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_493 = and(_T_491, _T_492) node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_495 = shr(io.in.a.bits.source, 2) node _T_496 = eq(_T_495, UInt<1>(0h0)) node _T_497 = leq(UInt<1>(0h0), uncommonBits_24) node _T_498 = and(_T_496, _T_497) node _T_499 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_500 = and(_T_498, _T_499) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_501 = shr(io.in.a.bits.source, 2) node _T_502 = eq(_T_501, UInt<1>(0h1)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_25) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<2>(0h2)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_26) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<2>(0h3)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_27) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_524 = or(_T_494, _T_500) node _T_525 = or(_T_524, _T_506) node _T_526 = or(_T_525, _T_512) node _T_527 = or(_T_526, _T_518) node _T_528 = or(_T_527, _T_519) node _T_529 = or(_T_528, _T_520) node _T_530 = or(_T_529, _T_521) node _T_531 = or(_T_530, _T_522) node _T_532 = or(_T_531, _T_523) node _T_533 = and(_T_493, _T_532) node _T_534 = or(UInt<1>(0h0), _T_533) node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_537 = and(_T_535, _T_536) node _T_538 = or(UInt<1>(0h0), _T_537) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<17>(0h10000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = and(_T_538, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = and(_T_534, _T_545) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_546, UInt<1>(0h1), "") : assert_26 node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(source_ok, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(is_aligned, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_556 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_556, UInt<1>(0h1), "") : assert_29 node _T_560 = eq(io.in.a.bits.mask, mask) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_560, UInt<1>(0h1), "") : assert_30 node _T_564 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_564 : node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_567 = and(_T_565, _T_566) node _T_568 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_569 = shr(io.in.a.bits.source, 2) node _T_570 = eq(_T_569, UInt<1>(0h0)) node _T_571 = leq(UInt<1>(0h0), uncommonBits_28) node _T_572 = and(_T_570, _T_571) node _T_573 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_574 = and(_T_572, _T_573) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_575 = shr(io.in.a.bits.source, 2) node _T_576 = eq(_T_575, UInt<1>(0h1)) node _T_577 = leq(UInt<1>(0h0), uncommonBits_29) node _T_578 = and(_T_576, _T_577) node _T_579 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_580 = and(_T_578, _T_579) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_581 = shr(io.in.a.bits.source, 2) node _T_582 = eq(_T_581, UInt<2>(0h2)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_30) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_587 = shr(io.in.a.bits.source, 2) node _T_588 = eq(_T_587, UInt<2>(0h3)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_31) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_592 = and(_T_590, _T_591) node _T_593 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_597 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_598 = or(_T_568, _T_574) node _T_599 = or(_T_598, _T_580) node _T_600 = or(_T_599, _T_586) node _T_601 = or(_T_600, _T_592) node _T_602 = or(_T_601, _T_593) node _T_603 = or(_T_602, _T_594) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_596) node _T_606 = or(_T_605, _T_597) node _T_607 = and(_T_567, _T_606) node _T_608 = or(UInt<1>(0h0), _T_607) node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_611 = and(_T_609, _T_610) node _T_612 = or(UInt<1>(0h0), _T_611) node _T_613 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = and(_T_608, _T_619) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_620, UInt<1>(0h1), "") : assert_31 node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(source_ok, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(is_aligned, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_630 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_630, UInt<1>(0h1), "") : assert_34 node _T_634 = not(mask) node _T_635 = and(io.in.a.bits.mask, _T_634) node _T_636 = eq(_T_635, UInt<1>(0h0)) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_636, UInt<1>(0h1), "") : assert_35 node _T_640 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_645 = shr(io.in.a.bits.source, 2) node _T_646 = eq(_T_645, UInt<1>(0h0)) node _T_647 = leq(UInt<1>(0h0), uncommonBits_32) node _T_648 = and(_T_646, _T_647) node _T_649 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_650 = and(_T_648, _T_649) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_651 = shr(io.in.a.bits.source, 2) node _T_652 = eq(_T_651, UInt<1>(0h1)) node _T_653 = leq(UInt<1>(0h0), uncommonBits_33) node _T_654 = and(_T_652, _T_653) node _T_655 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_656 = and(_T_654, _T_655) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_657 = shr(io.in.a.bits.source, 2) node _T_658 = eq(_T_657, UInt<2>(0h2)) node _T_659 = leq(UInt<1>(0h0), uncommonBits_34) node _T_660 = and(_T_658, _T_659) node _T_661 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_662 = and(_T_660, _T_661) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_663 = shr(io.in.a.bits.source, 2) node _T_664 = eq(_T_663, UInt<2>(0h3)) node _T_665 = leq(UInt<1>(0h0), uncommonBits_35) node _T_666 = and(_T_664, _T_665) node _T_667 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_668 = and(_T_666, _T_667) node _T_669 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_673 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_674 = or(_T_644, _T_650) node _T_675 = or(_T_674, _T_656) node _T_676 = or(_T_675, _T_662) node _T_677 = or(_T_676, _T_668) node _T_678 = or(_T_677, _T_669) node _T_679 = or(_T_678, _T_670) node _T_680 = or(_T_679, _T_671) node _T_681 = or(_T_680, _T_672) node _T_682 = or(_T_681, _T_673) node _T_683 = and(_T_643, _T_682) node _T_684 = or(UInt<1>(0h0), _T_683) node _T_685 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_686 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<17>(0h10000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_T_684, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_693, UInt<1>(0h1), "") : assert_36 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(is_aligned, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_703 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_703, UInt<1>(0h1), "") : assert_39 node _T_707 = eq(io.in.a.bits.mask, mask) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_707, UInt<1>(0h1), "") : assert_40 node _T_711 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_711 : node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_714 = and(_T_712, _T_713) node _T_715 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_716 = shr(io.in.a.bits.source, 2) node _T_717 = eq(_T_716, UInt<1>(0h0)) node _T_718 = leq(UInt<1>(0h0), uncommonBits_36) node _T_719 = and(_T_717, _T_718) node _T_720 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_722 = shr(io.in.a.bits.source, 2) node _T_723 = eq(_T_722, UInt<1>(0h1)) node _T_724 = leq(UInt<1>(0h0), uncommonBits_37) node _T_725 = and(_T_723, _T_724) node _T_726 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_727 = and(_T_725, _T_726) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_728 = shr(io.in.a.bits.source, 2) node _T_729 = eq(_T_728, UInt<2>(0h2)) node _T_730 = leq(UInt<1>(0h0), uncommonBits_38) node _T_731 = and(_T_729, _T_730) node _T_732 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_733 = and(_T_731, _T_732) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_734 = shr(io.in.a.bits.source, 2) node _T_735 = eq(_T_734, UInt<2>(0h3)) node _T_736 = leq(UInt<1>(0h0), uncommonBits_39) node _T_737 = and(_T_735, _T_736) node _T_738 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _T_740 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_744 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_745 = or(_T_715, _T_721) node _T_746 = or(_T_745, _T_727) node _T_747 = or(_T_746, _T_733) node _T_748 = or(_T_747, _T_739) node _T_749 = or(_T_748, _T_740) node _T_750 = or(_T_749, _T_741) node _T_751 = or(_T_750, _T_742) node _T_752 = or(_T_751, _T_743) node _T_753 = or(_T_752, _T_744) node _T_754 = and(_T_714, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_757 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_758 = cvt(_T_757) node _T_759 = and(_T_758, asSInt(UInt<17>(0h10000))) node _T_760 = asSInt(_T_759) node _T_761 = eq(_T_760, asSInt(UInt<1>(0h0))) node _T_762 = and(_T_756, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = and(_T_755, _T_763) node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_T_764, UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_764, UInt<1>(0h1), "") : assert_41 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(source_ok, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(is_aligned, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_774 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_774, UInt<1>(0h1), "") : assert_44 node _T_778 = eq(io.in.a.bits.mask, mask) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_778, UInt<1>(0h1), "") : assert_45 node _T_782 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_782 : node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_785 = and(_T_783, _T_784) node _T_786 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_787 = shr(io.in.a.bits.source, 2) node _T_788 = eq(_T_787, UInt<1>(0h0)) node _T_789 = leq(UInt<1>(0h0), uncommonBits_40) node _T_790 = and(_T_788, _T_789) node _T_791 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_792 = and(_T_790, _T_791) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_793 = shr(io.in.a.bits.source, 2) node _T_794 = eq(_T_793, UInt<1>(0h1)) node _T_795 = leq(UInt<1>(0h0), uncommonBits_41) node _T_796 = and(_T_794, _T_795) node _T_797 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_798 = and(_T_796, _T_797) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_799 = shr(io.in.a.bits.source, 2) node _T_800 = eq(_T_799, UInt<2>(0h2)) node _T_801 = leq(UInt<1>(0h0), uncommonBits_42) node _T_802 = and(_T_800, _T_801) node _T_803 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_804 = and(_T_802, _T_803) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_805 = shr(io.in.a.bits.source, 2) node _T_806 = eq(_T_805, UInt<2>(0h3)) node _T_807 = leq(UInt<1>(0h0), uncommonBits_43) node _T_808 = and(_T_806, _T_807) node _T_809 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_810 = and(_T_808, _T_809) node _T_811 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_814 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_815 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_816 = or(_T_786, _T_792) node _T_817 = or(_T_816, _T_798) node _T_818 = or(_T_817, _T_804) node _T_819 = or(_T_818, _T_810) node _T_820 = or(_T_819, _T_811) node _T_821 = or(_T_820, _T_812) node _T_822 = or(_T_821, _T_813) node _T_823 = or(_T_822, _T_814) node _T_824 = or(_T_823, _T_815) node _T_825 = and(_T_785, _T_824) node _T_826 = or(UInt<1>(0h0), _T_825) node _T_827 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_828 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_829 = cvt(_T_828) node _T_830 = and(_T_829, asSInt(UInt<17>(0h10000))) node _T_831 = asSInt(_T_830) node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) node _T_833 = and(_T_827, _T_832) node _T_834 = or(UInt<1>(0h0), _T_833) node _T_835 = and(_T_826, _T_834) node _T_836 = asUInt(reset) node _T_837 = eq(_T_836, UInt<1>(0h0)) when _T_837 : node _T_838 = eq(_T_835, UInt<1>(0h0)) when _T_838 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_835, UInt<1>(0h1), "") : assert_46 node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(source_ok, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(is_aligned, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_845 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_845, UInt<1>(0h1), "") : assert_49 node _T_849 = eq(io.in.a.bits.mask, mask) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_849, UInt<1>(0h1), "") : assert_50 node _T_853 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_853, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_857 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_857, UInt<1>(0h1), "") : assert_52 node _source_ok_T_38 = eq(io.in.d.bits.source, UInt<5>(0h11)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_39 = shr(io.in.d.bits.source, 2) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h0)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h1)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h2)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h3)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_38 connect _source_ok_WIRE_1[1], _source_ok_T_44 connect _source_ok_WIRE_1[2], _source_ok_T_50 connect _source_ok_WIRE_1[3], _source_ok_T_56 connect _source_ok_WIRE_1[4], _source_ok_T_62 connect _source_ok_WIRE_1[5], _source_ok_T_63 connect _source_ok_WIRE_1[6], _source_ok_T_64 connect _source_ok_WIRE_1[7], _source_ok_T_65 connect _source_ok_WIRE_1[8], _source_ok_T_66 connect _source_ok_WIRE_1[9], _source_ok_T_67 node _source_ok_T_68 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[2]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[3]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[4]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[5]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[6]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[7]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_75, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_861 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_861 : node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(source_ok_1, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_865, UInt<1>(0h1), "") : assert_54 node _T_869 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_869, UInt<1>(0h1), "") : assert_55 node _T_873 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_873, UInt<1>(0h1), "") : assert_56 node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_878 = asUInt(reset) node _T_879 = eq(_T_878, UInt<1>(0h0)) when _T_879 : node _T_880 = eq(_T_877, UInt<1>(0h0)) when _T_880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_877, UInt<1>(0h1), "") : assert_57 node _T_881 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_881 : node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(source_ok_1, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(sink_ok, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_888 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_888, UInt<1>(0h1), "") : assert_60 node _T_892 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_892, UInt<1>(0h1), "") : assert_61 node _T_896 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_896, UInt<1>(0h1), "") : assert_62 node _T_900 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_900, UInt<1>(0h1), "") : assert_63 node _T_904 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_905 = or(UInt<1>(0h0), _T_904) node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(_T_905, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_905, UInt<1>(0h1), "") : assert_64 node _T_909 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_909 : node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(source_ok_1, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(sink_ok, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_916 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_916, UInt<1>(0h1), "") : assert_67 node _T_920 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_920, UInt<1>(0h1), "") : assert_68 node _T_924 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_924, UInt<1>(0h1), "") : assert_69 node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_929 = or(_T_928, io.in.d.bits.corrupt) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_929, UInt<1>(0h1), "") : assert_70 node _T_933 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_934, UInt<1>(0h1), "") : assert_71 node _T_938 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_938 : node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(source_ok_1, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_942 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_942, UInt<1>(0h1), "") : assert_73 node _T_946 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_946, UInt<1>(0h1), "") : assert_74 node _T_950 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_951 = or(UInt<1>(0h0), _T_950) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_951, UInt<1>(0h1), "") : assert_75 node _T_955 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_955 : node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(source_ok_1, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_959, UInt<1>(0h1), "") : assert_77 node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_964 = or(_T_963, io.in.d.bits.corrupt) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_964, UInt<1>(0h1), "") : assert_78 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_969, UInt<1>(0h1), "") : assert_79 node _T_973 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_977 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_977, UInt<1>(0h1), "") : assert_81 node _T_981 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_981, UInt<1>(0h1), "") : assert_82 node _T_985 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_986 = or(UInt<1>(0h0), _T_985) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_986, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<26>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_990 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_990, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_994 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_994, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_998 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_998, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1002 = eq(a_first, UInt<1>(0h0)) node _T_1003 = and(io.in.a.valid, _T_1002) when _T_1003 : node _T_1004 = eq(io.in.a.bits.opcode, opcode) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_87 node _T_1008 = eq(io.in.a.bits.param, param) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_88 node _T_1012 = eq(io.in.a.bits.size, size) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_89 node _T_1016 = eq(io.in.a.bits.source, source) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_90 node _T_1020 = eq(io.in.a.bits.address, address) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_91 node _T_1024 = and(io.in.a.ready, io.in.a.valid) node _T_1025 = and(_T_1024, a_first) when _T_1025 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1026 = eq(d_first, UInt<1>(0h0)) node _T_1027 = and(io.in.d.valid, _T_1026) when _T_1027 : node _T_1028 = eq(io.in.d.bits.opcode, opcode_1) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_92 node _T_1032 = eq(io.in.d.bits.param, param_1) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_93 node _T_1036 = eq(io.in.d.bits.size, size_1) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_94 node _T_1040 = eq(io.in.d.bits.source, source_1) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_95 node _T_1044 = eq(io.in.d.bits.sink, sink) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_96 node _T_1048 = eq(io.in.d.bits.denied, denied) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_97 node _T_1052 = and(io.in.d.ready, io.in.d.valid) node _T_1053 = and(_T_1052, d_first) when _T_1053 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1054 = and(io.in.a.valid, a_first_1) node _T_1055 = and(_T_1054, UInt<1>(0h1)) when _T_1055 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1056 = and(io.in.a.ready, io.in.a.valid) node _T_1057 = and(_T_1056, a_first_1) node _T_1058 = and(_T_1057, UInt<1>(0h1)) when _T_1058 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1059 = dshr(inflight, io.in.a.bits.source) node _T_1060 = bits(_T_1059, 0, 0) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1065 = and(io.in.d.valid, d_first_1) node _T_1066 = and(_T_1065, UInt<1>(0h1)) node _T_1067 = eq(d_release_ack, UInt<1>(0h0)) node _T_1068 = and(_T_1066, _T_1067) when _T_1068 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1069 = and(io.in.d.ready, io.in.d.valid) node _T_1070 = and(_T_1069, d_first_1) node _T_1071 = and(_T_1070, UInt<1>(0h1)) node _T_1072 = eq(d_release_ack, UInt<1>(0h0)) node _T_1073 = and(_T_1071, _T_1072) when _T_1073 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1074 = and(io.in.d.valid, d_first_1) node _T_1075 = and(_T_1074, UInt<1>(0h1)) node _T_1076 = eq(d_release_ack, UInt<1>(0h0)) node _T_1077 = and(_T_1075, _T_1076) when _T_1077 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1078 = dshr(inflight, io.in.d.bits.source) node _T_1079 = bits(_T_1078, 0, 0) node _T_1080 = or(_T_1079, same_cycle_resp) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1084 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1085 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1086 = or(_T_1084, _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_100 node _T_1090 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_101 else : node _T_1094 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1095 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1096 = or(_T_1094, _T_1095) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_102 node _T_1100 = eq(io.in.d.bits.size, a_size_lookup) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_103 node _T_1104 = and(io.in.d.valid, d_first_1) node _T_1105 = and(_T_1104, a_first_1) node _T_1106 = and(_T_1105, io.in.a.valid) node _T_1107 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = eq(d_release_ack, UInt<1>(0h0)) node _T_1110 = and(_T_1108, _T_1109) when _T_1110 : node _T_1111 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1112 = or(_T_1111, io.in.a.ready) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_48 node _T_1116 = orr(inflight) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) node _T_1118 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1119 = or(_T_1117, _T_1118) node _T_1120 = lt(watchdog, plusarg_reader.out) node _T_1121 = or(_T_1119, _T_1120) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1125 = and(io.in.a.ready, io.in.a.valid) node _T_1126 = and(io.in.d.ready, io.in.d.valid) node _T_1127 = or(_T_1125, _T_1126) when _T_1127 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1128 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1129 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1130 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1131 = and(_T_1129, _T_1130) node _T_1132 = and(_T_1128, _T_1131) when _T_1132 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1133 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1134 = and(_T_1133, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1135 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1136 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1137 = and(_T_1135, _T_1136) node _T_1138 = and(_T_1134, _T_1137) when _T_1138 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1139 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_2) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = and(_T_1146, d_release_ack_1) when _T_1147 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1148 = and(io.in.d.ready, io.in.d.valid) node _T_1149 = and(_T_1148, d_first_2) node _T_1150 = and(_T_1149, UInt<1>(0h1)) node _T_1151 = and(_T_1150, d_release_ack_1) when _T_1151 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1152 = and(io.in.d.valid, d_first_2) node _T_1153 = and(_T_1152, UInt<1>(0h1)) node _T_1154 = and(_T_1153, d_release_ack_1) when _T_1154 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1155 = dshr(inflight_1, io.in.d.bits.source) node _T_1156 = bits(_T_1155, 0, 0) node _T_1157 = or(_T_1156, same_cycle_resp_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1161 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_108 else : node _T_1165 = eq(io.in.d.bits.size, c_size_lookup) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_109 node _T_1169 = and(io.in.d.valid, d_first_2) node _T_1170 = and(_T_1169, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1171 = and(_T_1170, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1172 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1173 = and(_T_1171, _T_1172) node _T_1174 = and(_T_1173, d_release_ack_1) node _T_1175 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1176 = and(_T_1174, _T_1175) when _T_1176 : node _T_1177 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<26>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1178 = or(_T_1177, _WIRE_27.ready) node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(_T_1178, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1178, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_49 node _T_1182 = orr(inflight_1) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) node _T_1184 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1185 = or(_T_1183, _T_1184) node _T_1186 = lt(watchdog_1, plusarg_reader_1.out) node _T_1187 = or(_T_1185, _T_1186) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<26>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1191 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1192 = and(io.in.d.ready, io.in.d.valid) node _T_1193 = or(_T_1191, _T_1192) when _T_1193 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_24( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_27 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 3) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<2>(0h2)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<3>(0h7)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 3) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<2>(0h3)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<3>(0h7)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<1>(0h0)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<1>(0h1)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 2) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 2) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h3)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_36 connect _source_ok_WIRE[7], _source_ok_T_37 connect _source_ok_WIRE[8], _source_ok_T_38 connect _source_ok_WIRE[9], _source_ok_T_39 node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_47, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_12 = shr(io.in.a.bits.source, 3) node _T_13 = eq(_T_12, UInt<2>(0h2)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<3>(0h7)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_25 = shr(io.in.a.bits.source, 3) node _T_26 = eq(_T_25, UInt<2>(0h3)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<3>(0h7)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<1>(0h1)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_64 = shr(io.in.a.bits.source, 2) node _T_65 = eq(_T_64, UInt<2>(0h2)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_77 = shr(io.in.a.bits.source, 2) node _T_78 = eq(_T_77, UInt<2>(0h3)) node _T_79 = leq(UInt<1>(0h0), uncommonBits_5) node _T_80 = and(_T_78, _T_79) node _T_81 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(_T_82, UInt<1>(0h0)) node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = or(_T_83, _T_88) node _T_90 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_93 = cvt(_T_92) node _T_94 = and(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = asSInt(_T_94) node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0))) node _T_97 = or(_T_91, _T_96) node _T_98 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _T_114 = and(_T_11, _T_24) node _T_115 = and(_T_114, _T_37) node _T_116 = and(_T_115, _T_50) node _T_117 = and(_T_116, _T_63) node _T_118 = and(_T_117, _T_76) node _T_119 = and(_T_118, _T_89) node _T_120 = and(_T_119, _T_97) node _T_121 = and(_T_120, _T_105) node _T_122 = and(_T_121, _T_113) node _T_123 = asUInt(reset) node _T_124 = eq(_T_123, UInt<1>(0h0)) when _T_124 : node _T_125 = eq(_T_122, UInt<1>(0h0)) when _T_125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_122, UInt<1>(0h1), "") : assert_1 node _T_126 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_126 : node _T_127 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_128 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_129 = and(_T_127, _T_128) node _T_130 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_131 = shr(io.in.a.bits.source, 3) node _T_132 = eq(_T_131, UInt<2>(0h2)) node _T_133 = leq(UInt<1>(0h0), uncommonBits_6) node _T_134 = and(_T_132, _T_133) node _T_135 = leq(uncommonBits_6, UInt<3>(0h7)) node _T_136 = and(_T_134, _T_135) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_137 = shr(io.in.a.bits.source, 3) node _T_138 = eq(_T_137, UInt<2>(0h3)) node _T_139 = leq(UInt<1>(0h0), uncommonBits_7) node _T_140 = and(_T_138, _T_139) node _T_141 = leq(uncommonBits_7, UInt<3>(0h7)) node _T_142 = and(_T_140, _T_141) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_143 = shr(io.in.a.bits.source, 2) node _T_144 = eq(_T_143, UInt<1>(0h0)) node _T_145 = leq(UInt<1>(0h0), uncommonBits_8) node _T_146 = and(_T_144, _T_145) node _T_147 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_148 = and(_T_146, _T_147) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_149 = shr(io.in.a.bits.source, 2) node _T_150 = eq(_T_149, UInt<1>(0h1)) node _T_151 = leq(UInt<1>(0h0), uncommonBits_9) node _T_152 = and(_T_150, _T_151) node _T_153 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_154 = and(_T_152, _T_153) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_155 = shr(io.in.a.bits.source, 2) node _T_156 = eq(_T_155, UInt<2>(0h2)) node _T_157 = leq(UInt<1>(0h0), uncommonBits_10) node _T_158 = and(_T_156, _T_157) node _T_159 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_160 = and(_T_158, _T_159) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_161 = shr(io.in.a.bits.source, 2) node _T_162 = eq(_T_161, UInt<2>(0h3)) node _T_163 = leq(UInt<1>(0h0), uncommonBits_11) node _T_164 = and(_T_162, _T_163) node _T_165 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_166 = and(_T_164, _T_165) node _T_167 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_168 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_169 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_170 = or(_T_130, _T_136) node _T_171 = or(_T_170, _T_142) node _T_172 = or(_T_171, _T_148) node _T_173 = or(_T_172, _T_154) node _T_174 = or(_T_173, _T_160) node _T_175 = or(_T_174, _T_166) node _T_176 = or(_T_175, _T_167) node _T_177 = or(_T_176, _T_168) node _T_178 = or(_T_177, _T_169) node _T_179 = and(_T_129, _T_178) node _T_180 = or(UInt<1>(0h0), _T_179) node _T_181 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_182 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<13>(0h1000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = and(_T_181, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_180, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_189, UInt<1>(0h1), "") : assert_2 node _T_193 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_194 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_195 = and(_T_193, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<13>(0h1000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = and(_T_196, _T_201) node _T_203 = or(UInt<1>(0h0), _T_202) node _T_204 = and(UInt<1>(0h0), _T_203) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_204, UInt<1>(0h1), "") : assert_3 node _T_208 = asUInt(reset) node _T_209 = eq(_T_208, UInt<1>(0h0)) when _T_209 : node _T_210 = eq(source_ok, UInt<1>(0h0)) when _T_210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_211 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_211, UInt<1>(0h1), "") : assert_5 node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(is_aligned, UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_218 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_218, UInt<1>(0h1), "") : assert_7 node _T_222 = not(io.in.a.bits.mask) node _T_223 = eq(_T_222, UInt<1>(0h0)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_223, UInt<1>(0h1), "") : assert_8 node _T_227 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_228 = asUInt(reset) node _T_229 = eq(_T_228, UInt<1>(0h0)) when _T_229 : node _T_230 = eq(_T_227, UInt<1>(0h0)) when _T_230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_227, UInt<1>(0h1), "") : assert_9 node _T_231 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_231 : node _T_232 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_233 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_236 = shr(io.in.a.bits.source, 3) node _T_237 = eq(_T_236, UInt<2>(0h2)) node _T_238 = leq(UInt<1>(0h0), uncommonBits_12) node _T_239 = and(_T_237, _T_238) node _T_240 = leq(uncommonBits_12, UInt<3>(0h7)) node _T_241 = and(_T_239, _T_240) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_242 = shr(io.in.a.bits.source, 3) node _T_243 = eq(_T_242, UInt<2>(0h3)) node _T_244 = leq(UInt<1>(0h0), uncommonBits_13) node _T_245 = and(_T_243, _T_244) node _T_246 = leq(uncommonBits_13, UInt<3>(0h7)) node _T_247 = and(_T_245, _T_246) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_248 = shr(io.in.a.bits.source, 2) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = leq(UInt<1>(0h0), uncommonBits_14) node _T_251 = and(_T_249, _T_250) node _T_252 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_253 = and(_T_251, _T_252) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_254 = shr(io.in.a.bits.source, 2) node _T_255 = eq(_T_254, UInt<1>(0h1)) node _T_256 = leq(UInt<1>(0h0), uncommonBits_15) node _T_257 = and(_T_255, _T_256) node _T_258 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_259 = and(_T_257, _T_258) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_260 = shr(io.in.a.bits.source, 2) node _T_261 = eq(_T_260, UInt<2>(0h2)) node _T_262 = leq(UInt<1>(0h0), uncommonBits_16) node _T_263 = and(_T_261, _T_262) node _T_264 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_265 = and(_T_263, _T_264) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<2>(0h3)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_17) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_273 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_274 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_275 = or(_T_235, _T_241) node _T_276 = or(_T_275, _T_247) node _T_277 = or(_T_276, _T_253) node _T_278 = or(_T_277, _T_259) node _T_279 = or(_T_278, _T_265) node _T_280 = or(_T_279, _T_271) node _T_281 = or(_T_280, _T_272) node _T_282 = or(_T_281, _T_273) node _T_283 = or(_T_282, _T_274) node _T_284 = and(_T_234, _T_283) node _T_285 = or(UInt<1>(0h0), _T_284) node _T_286 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_287 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_288 = cvt(_T_287) node _T_289 = and(_T_288, asSInt(UInt<13>(0h1000))) node _T_290 = asSInt(_T_289) node _T_291 = eq(_T_290, asSInt(UInt<1>(0h0))) node _T_292 = and(_T_286, _T_291) node _T_293 = or(UInt<1>(0h0), _T_292) node _T_294 = and(_T_285, _T_293) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_294, UInt<1>(0h1), "") : assert_10 node _T_298 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_299 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_300 = and(_T_298, _T_299) node _T_301 = or(UInt<1>(0h0), _T_300) node _T_302 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_303 = cvt(_T_302) node _T_304 = and(_T_303, asSInt(UInt<13>(0h1000))) node _T_305 = asSInt(_T_304) node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0))) node _T_307 = and(_T_301, _T_306) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = and(UInt<1>(0h0), _T_308) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_309, UInt<1>(0h1), "") : assert_11 node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(source_ok, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_316 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_317 = asUInt(reset) node _T_318 = eq(_T_317, UInt<1>(0h0)) when _T_318 : node _T_319 = eq(_T_316, UInt<1>(0h0)) when _T_319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_316, UInt<1>(0h1), "") : assert_13 node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(is_aligned, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_323 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(_T_323, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_323, UInt<1>(0h1), "") : assert_15 node _T_327 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_327, UInt<1>(0h1), "") : assert_16 node _T_331 = not(io.in.a.bits.mask) node _T_332 = eq(_T_331, UInt<1>(0h0)) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_332, UInt<1>(0h1), "") : assert_17 node _T_336 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_337 = asUInt(reset) node _T_338 = eq(_T_337, UInt<1>(0h0)) when _T_338 : node _T_339 = eq(_T_336, UInt<1>(0h0)) when _T_339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_336, UInt<1>(0h1), "") : assert_18 node _T_340 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_340 : node _T_341 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_342 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0) node _T_345 = shr(io.in.a.bits.source, 3) node _T_346 = eq(_T_345, UInt<2>(0h2)) node _T_347 = leq(UInt<1>(0h0), uncommonBits_18) node _T_348 = and(_T_346, _T_347) node _T_349 = leq(uncommonBits_18, UInt<3>(0h7)) node _T_350 = and(_T_348, _T_349) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_351 = shr(io.in.a.bits.source, 3) node _T_352 = eq(_T_351, UInt<2>(0h3)) node _T_353 = leq(UInt<1>(0h0), uncommonBits_19) node _T_354 = and(_T_352, _T_353) node _T_355 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_356 = and(_T_354, _T_355) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_357 = shr(io.in.a.bits.source, 2) node _T_358 = eq(_T_357, UInt<1>(0h0)) node _T_359 = leq(UInt<1>(0h0), uncommonBits_20) node _T_360 = and(_T_358, _T_359) node _T_361 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_362 = and(_T_360, _T_361) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_363 = shr(io.in.a.bits.source, 2) node _T_364 = eq(_T_363, UInt<1>(0h1)) node _T_365 = leq(UInt<1>(0h0), uncommonBits_21) node _T_366 = and(_T_364, _T_365) node _T_367 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_368 = and(_T_366, _T_367) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_369 = shr(io.in.a.bits.source, 2) node _T_370 = eq(_T_369, UInt<2>(0h2)) node _T_371 = leq(UInt<1>(0h0), uncommonBits_22) node _T_372 = and(_T_370, _T_371) node _T_373 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_374 = and(_T_372, _T_373) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_375 = shr(io.in.a.bits.source, 2) node _T_376 = eq(_T_375, UInt<2>(0h3)) node _T_377 = leq(UInt<1>(0h0), uncommonBits_23) node _T_378 = and(_T_376, _T_377) node _T_379 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_380 = and(_T_378, _T_379) node _T_381 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_382 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_383 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_384 = or(_T_344, _T_350) node _T_385 = or(_T_384, _T_356) node _T_386 = or(_T_385, _T_362) node _T_387 = or(_T_386, _T_368) node _T_388 = or(_T_387, _T_374) node _T_389 = or(_T_388, _T_380) node _T_390 = or(_T_389, _T_381) node _T_391 = or(_T_390, _T_382) node _T_392 = or(_T_391, _T_383) node _T_393 = and(_T_343, _T_392) node _T_394 = or(UInt<1>(0h0), _T_393) node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_T_394, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_394, UInt<1>(0h1), "") : assert_19 node _T_398 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_399 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_400 = and(_T_398, _T_399) node _T_401 = or(UInt<1>(0h0), _T_400) node _T_402 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = and(_T_401, _T_406) node _T_408 = or(UInt<1>(0h0), _T_407) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_408, UInt<1>(0h1), "") : assert_20 node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(source_ok, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(is_aligned, UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_418 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_418, UInt<1>(0h1), "") : assert_23 node _T_422 = eq(io.in.a.bits.mask, mask) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_422, UInt<1>(0h1), "") : assert_24 node _T_426 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_426, UInt<1>(0h1), "") : assert_25 node _T_430 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_430 : node _T_431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_432 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_435 = shr(io.in.a.bits.source, 3) node _T_436 = eq(_T_435, UInt<2>(0h2)) node _T_437 = leq(UInt<1>(0h0), uncommonBits_24) node _T_438 = and(_T_436, _T_437) node _T_439 = leq(uncommonBits_24, UInt<3>(0h7)) node _T_440 = and(_T_438, _T_439) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0) node _T_441 = shr(io.in.a.bits.source, 3) node _T_442 = eq(_T_441, UInt<2>(0h3)) node _T_443 = leq(UInt<1>(0h0), uncommonBits_25) node _T_444 = and(_T_442, _T_443) node _T_445 = leq(uncommonBits_25, UInt<3>(0h7)) node _T_446 = and(_T_444, _T_445) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_447 = shr(io.in.a.bits.source, 2) node _T_448 = eq(_T_447, UInt<1>(0h0)) node _T_449 = leq(UInt<1>(0h0), uncommonBits_26) node _T_450 = and(_T_448, _T_449) node _T_451 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_452 = and(_T_450, _T_451) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_453 = shr(io.in.a.bits.source, 2) node _T_454 = eq(_T_453, UInt<1>(0h1)) node _T_455 = leq(UInt<1>(0h0), uncommonBits_27) node _T_456 = and(_T_454, _T_455) node _T_457 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_458 = and(_T_456, _T_457) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_459 = shr(io.in.a.bits.source, 2) node _T_460 = eq(_T_459, UInt<2>(0h2)) node _T_461 = leq(UInt<1>(0h0), uncommonBits_28) node _T_462 = and(_T_460, _T_461) node _T_463 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_464 = and(_T_462, _T_463) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_465 = shr(io.in.a.bits.source, 2) node _T_466 = eq(_T_465, UInt<2>(0h3)) node _T_467 = leq(UInt<1>(0h0), uncommonBits_29) node _T_468 = and(_T_466, _T_467) node _T_469 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_470 = and(_T_468, _T_469) node _T_471 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_472 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_473 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_474 = or(_T_434, _T_440) node _T_475 = or(_T_474, _T_446) node _T_476 = or(_T_475, _T_452) node _T_477 = or(_T_476, _T_458) node _T_478 = or(_T_477, _T_464) node _T_479 = or(_T_478, _T_470) node _T_480 = or(_T_479, _T_471) node _T_481 = or(_T_480, _T_472) node _T_482 = or(_T_481, _T_473) node _T_483 = and(_T_433, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_486 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_487 = and(_T_485, _T_486) node _T_488 = or(UInt<1>(0h0), _T_487) node _T_489 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_490 = cvt(_T_489) node _T_491 = and(_T_490, asSInt(UInt<13>(0h1000))) node _T_492 = asSInt(_T_491) node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0))) node _T_494 = and(_T_488, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = and(_T_484, _T_495) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_496, UInt<1>(0h1), "") : assert_26 node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(source_ok, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(is_aligned, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_506 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_T_506, UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_506, UInt<1>(0h1), "") : assert_29 node _T_510 = eq(io.in.a.bits.mask, mask) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_510, UInt<1>(0h1), "") : assert_30 node _T_514 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_514 : node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_517 = and(_T_515, _T_516) node _T_518 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 2, 0) node _T_519 = shr(io.in.a.bits.source, 3) node _T_520 = eq(_T_519, UInt<2>(0h2)) node _T_521 = leq(UInt<1>(0h0), uncommonBits_30) node _T_522 = and(_T_520, _T_521) node _T_523 = leq(uncommonBits_30, UInt<3>(0h7)) node _T_524 = and(_T_522, _T_523) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 2, 0) node _T_525 = shr(io.in.a.bits.source, 3) node _T_526 = eq(_T_525, UInt<2>(0h3)) node _T_527 = leq(UInt<1>(0h0), uncommonBits_31) node _T_528 = and(_T_526, _T_527) node _T_529 = leq(uncommonBits_31, UInt<3>(0h7)) node _T_530 = and(_T_528, _T_529) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_531 = shr(io.in.a.bits.source, 2) node _T_532 = eq(_T_531, UInt<1>(0h0)) node _T_533 = leq(UInt<1>(0h0), uncommonBits_32) node _T_534 = and(_T_532, _T_533) node _T_535 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_536 = and(_T_534, _T_535) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_537 = shr(io.in.a.bits.source, 2) node _T_538 = eq(_T_537, UInt<1>(0h1)) node _T_539 = leq(UInt<1>(0h0), uncommonBits_33) node _T_540 = and(_T_538, _T_539) node _T_541 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_542 = and(_T_540, _T_541) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_543 = shr(io.in.a.bits.source, 2) node _T_544 = eq(_T_543, UInt<2>(0h2)) node _T_545 = leq(UInt<1>(0h0), uncommonBits_34) node _T_546 = and(_T_544, _T_545) node _T_547 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_548 = and(_T_546, _T_547) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_549 = shr(io.in.a.bits.source, 2) node _T_550 = eq(_T_549, UInt<2>(0h3)) node _T_551 = leq(UInt<1>(0h0), uncommonBits_35) node _T_552 = and(_T_550, _T_551) node _T_553 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_554 = and(_T_552, _T_553) node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_557 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_558 = or(_T_518, _T_524) node _T_559 = or(_T_558, _T_530) node _T_560 = or(_T_559, _T_536) node _T_561 = or(_T_560, _T_542) node _T_562 = or(_T_561, _T_548) node _T_563 = or(_T_562, _T_554) node _T_564 = or(_T_563, _T_555) node _T_565 = or(_T_564, _T_556) node _T_566 = or(_T_565, _T_557) node _T_567 = and(_T_517, _T_566) node _T_568 = or(UInt<1>(0h0), _T_567) node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_570 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<13>(0h1000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = and(_T_572, _T_577) node _T_579 = or(UInt<1>(0h0), _T_578) node _T_580 = and(_T_568, _T_579) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_580, UInt<1>(0h1), "") : assert_31 node _T_584 = asUInt(reset) node _T_585 = eq(_T_584, UInt<1>(0h0)) when _T_585 : node _T_586 = eq(source_ok, UInt<1>(0h0)) when _T_586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(is_aligned, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_590 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(_T_590, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_590, UInt<1>(0h1), "") : assert_34 node _T_594 = not(mask) node _T_595 = and(io.in.a.bits.mask, _T_594) node _T_596 = eq(_T_595, UInt<1>(0h0)) node _T_597 = asUInt(reset) node _T_598 = eq(_T_597, UInt<1>(0h0)) when _T_598 : node _T_599 = eq(_T_596, UInt<1>(0h0)) when _T_599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_596, UInt<1>(0h1), "") : assert_35 node _T_600 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_600 : node _T_601 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_602 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 2, 0) node _T_605 = shr(io.in.a.bits.source, 3) node _T_606 = eq(_T_605, UInt<2>(0h2)) node _T_607 = leq(UInt<1>(0h0), uncommonBits_36) node _T_608 = and(_T_606, _T_607) node _T_609 = leq(uncommonBits_36, UInt<3>(0h7)) node _T_610 = and(_T_608, _T_609) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 2, 0) node _T_611 = shr(io.in.a.bits.source, 3) node _T_612 = eq(_T_611, UInt<2>(0h3)) node _T_613 = leq(UInt<1>(0h0), uncommonBits_37) node _T_614 = and(_T_612, _T_613) node _T_615 = leq(uncommonBits_37, UInt<3>(0h7)) node _T_616 = and(_T_614, _T_615) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_617 = shr(io.in.a.bits.source, 2) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = leq(UInt<1>(0h0), uncommonBits_38) node _T_620 = and(_T_618, _T_619) node _T_621 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_622 = and(_T_620, _T_621) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_623 = shr(io.in.a.bits.source, 2) node _T_624 = eq(_T_623, UInt<1>(0h1)) node _T_625 = leq(UInt<1>(0h0), uncommonBits_39) node _T_626 = and(_T_624, _T_625) node _T_627 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_629 = shr(io.in.a.bits.source, 2) node _T_630 = eq(_T_629, UInt<2>(0h2)) node _T_631 = leq(UInt<1>(0h0), uncommonBits_40) node _T_632 = and(_T_630, _T_631) node _T_633 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_634 = and(_T_632, _T_633) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_635 = shr(io.in.a.bits.source, 2) node _T_636 = eq(_T_635, UInt<2>(0h3)) node _T_637 = leq(UInt<1>(0h0), uncommonBits_41) node _T_638 = and(_T_636, _T_637) node _T_639 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_640 = and(_T_638, _T_639) node _T_641 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_642 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_643 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_644 = or(_T_604, _T_610) node _T_645 = or(_T_644, _T_616) node _T_646 = or(_T_645, _T_622) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_634) node _T_649 = or(_T_648, _T_640) node _T_650 = or(_T_649, _T_641) node _T_651 = or(_T_650, _T_642) node _T_652 = or(_T_651, _T_643) node _T_653 = and(_T_603, _T_652) node _T_654 = or(UInt<1>(0h0), _T_653) node _T_655 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_656 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_660 = cvt(_T_659) node _T_661 = and(_T_660, asSInt(UInt<13>(0h1000))) node _T_662 = asSInt(_T_661) node _T_663 = eq(_T_662, asSInt(UInt<1>(0h0))) node _T_664 = and(_T_658, _T_663) node _T_665 = or(UInt<1>(0h0), _T_664) node _T_666 = and(_T_654, _T_665) node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(_T_666, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_666, UInt<1>(0h1), "") : assert_36 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(source_ok, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(is_aligned, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_676 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_676, UInt<1>(0h1), "") : assert_39 node _T_680 = eq(io.in.a.bits.mask, mask) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_680, UInt<1>(0h1), "") : assert_40 node _T_684 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_684 : node _T_685 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_686 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 2, 0) node _T_689 = shr(io.in.a.bits.source, 3) node _T_690 = eq(_T_689, UInt<2>(0h2)) node _T_691 = leq(UInt<1>(0h0), uncommonBits_42) node _T_692 = and(_T_690, _T_691) node _T_693 = leq(uncommonBits_42, UInt<3>(0h7)) node _T_694 = and(_T_692, _T_693) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 2, 0) node _T_695 = shr(io.in.a.bits.source, 3) node _T_696 = eq(_T_695, UInt<2>(0h3)) node _T_697 = leq(UInt<1>(0h0), uncommonBits_43) node _T_698 = and(_T_696, _T_697) node _T_699 = leq(uncommonBits_43, UInt<3>(0h7)) node _T_700 = and(_T_698, _T_699) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_701 = shr(io.in.a.bits.source, 2) node _T_702 = eq(_T_701, UInt<1>(0h0)) node _T_703 = leq(UInt<1>(0h0), uncommonBits_44) node _T_704 = and(_T_702, _T_703) node _T_705 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_706 = and(_T_704, _T_705) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_707 = shr(io.in.a.bits.source, 2) node _T_708 = eq(_T_707, UInt<1>(0h1)) node _T_709 = leq(UInt<1>(0h0), uncommonBits_45) node _T_710 = and(_T_708, _T_709) node _T_711 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_712 = and(_T_710, _T_711) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_713 = shr(io.in.a.bits.source, 2) node _T_714 = eq(_T_713, UInt<2>(0h2)) node _T_715 = leq(UInt<1>(0h0), uncommonBits_46) node _T_716 = and(_T_714, _T_715) node _T_717 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_718 = and(_T_716, _T_717) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_719 = shr(io.in.a.bits.source, 2) node _T_720 = eq(_T_719, UInt<2>(0h3)) node _T_721 = leq(UInt<1>(0h0), uncommonBits_47) node _T_722 = and(_T_720, _T_721) node _T_723 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_726 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_727 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_728 = or(_T_688, _T_694) node _T_729 = or(_T_728, _T_700) node _T_730 = or(_T_729, _T_706) node _T_731 = or(_T_730, _T_712) node _T_732 = or(_T_731, _T_718) node _T_733 = or(_T_732, _T_724) node _T_734 = or(_T_733, _T_725) node _T_735 = or(_T_734, _T_726) node _T_736 = or(_T_735, _T_727) node _T_737 = and(_T_687, _T_736) node _T_738 = or(UInt<1>(0h0), _T_737) node _T_739 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_740 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_741 = and(_T_739, _T_740) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_744 = cvt(_T_743) node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000))) node _T_746 = asSInt(_T_745) node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0))) node _T_748 = and(_T_742, _T_747) node _T_749 = or(UInt<1>(0h0), _T_748) node _T_750 = and(_T_738, _T_749) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_750, UInt<1>(0h1), "") : assert_41 node _T_754 = asUInt(reset) node _T_755 = eq(_T_754, UInt<1>(0h0)) when _T_755 : node _T_756 = eq(source_ok, UInt<1>(0h0)) when _T_756 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_757 = asUInt(reset) node _T_758 = eq(_T_757, UInt<1>(0h0)) when _T_758 : node _T_759 = eq(is_aligned, UInt<1>(0h0)) when _T_759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_760 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_761 = asUInt(reset) node _T_762 = eq(_T_761, UInt<1>(0h0)) when _T_762 : node _T_763 = eq(_T_760, UInt<1>(0h0)) when _T_763 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_760, UInt<1>(0h1), "") : assert_44 node _T_764 = eq(io.in.a.bits.mask, mask) node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_T_764, UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_764, UInt<1>(0h1), "") : assert_45 node _T_768 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_768 : node _T_769 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_770 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_771 = and(_T_769, _T_770) node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0) node _T_773 = shr(io.in.a.bits.source, 3) node _T_774 = eq(_T_773, UInt<2>(0h2)) node _T_775 = leq(UInt<1>(0h0), uncommonBits_48) node _T_776 = and(_T_774, _T_775) node _T_777 = leq(uncommonBits_48, UInt<3>(0h7)) node _T_778 = and(_T_776, _T_777) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_779 = shr(io.in.a.bits.source, 3) node _T_780 = eq(_T_779, UInt<2>(0h3)) node _T_781 = leq(UInt<1>(0h0), uncommonBits_49) node _T_782 = and(_T_780, _T_781) node _T_783 = leq(uncommonBits_49, UInt<3>(0h7)) node _T_784 = and(_T_782, _T_783) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_785 = shr(io.in.a.bits.source, 2) node _T_786 = eq(_T_785, UInt<1>(0h0)) node _T_787 = leq(UInt<1>(0h0), uncommonBits_50) node _T_788 = and(_T_786, _T_787) node _T_789 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_790 = and(_T_788, _T_789) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_791 = shr(io.in.a.bits.source, 2) node _T_792 = eq(_T_791, UInt<1>(0h1)) node _T_793 = leq(UInt<1>(0h0), uncommonBits_51) node _T_794 = and(_T_792, _T_793) node _T_795 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_796 = and(_T_794, _T_795) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_797 = shr(io.in.a.bits.source, 2) node _T_798 = eq(_T_797, UInt<2>(0h2)) node _T_799 = leq(UInt<1>(0h0), uncommonBits_52) node _T_800 = and(_T_798, _T_799) node _T_801 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_802 = and(_T_800, _T_801) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_803 = shr(io.in.a.bits.source, 2) node _T_804 = eq(_T_803, UInt<2>(0h3)) node _T_805 = leq(UInt<1>(0h0), uncommonBits_53) node _T_806 = and(_T_804, _T_805) node _T_807 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_808 = and(_T_806, _T_807) node _T_809 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_810 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_811 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_812 = or(_T_772, _T_778) node _T_813 = or(_T_812, _T_784) node _T_814 = or(_T_813, _T_790) node _T_815 = or(_T_814, _T_796) node _T_816 = or(_T_815, _T_802) node _T_817 = or(_T_816, _T_808) node _T_818 = or(_T_817, _T_809) node _T_819 = or(_T_818, _T_810) node _T_820 = or(_T_819, _T_811) node _T_821 = and(_T_771, _T_820) node _T_822 = or(UInt<1>(0h0), _T_821) node _T_823 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_824 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_825 = and(_T_823, _T_824) node _T_826 = or(UInt<1>(0h0), _T_825) node _T_827 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_828 = cvt(_T_827) node _T_829 = and(_T_828, asSInt(UInt<13>(0h1000))) node _T_830 = asSInt(_T_829) node _T_831 = eq(_T_830, asSInt(UInt<1>(0h0))) node _T_832 = and(_T_826, _T_831) node _T_833 = or(UInt<1>(0h0), _T_832) node _T_834 = and(_T_822, _T_833) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_834, UInt<1>(0h1), "") : assert_46 node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(source_ok, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_841 = asUInt(reset) node _T_842 = eq(_T_841, UInt<1>(0h0)) when _T_842 : node _T_843 = eq(is_aligned, UInt<1>(0h0)) when _T_843 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_844 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_845 = asUInt(reset) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(_T_844, UInt<1>(0h0)) when _T_847 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_844, UInt<1>(0h1), "") : assert_49 node _T_848 = eq(io.in.a.bits.mask, mask) node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(_T_848, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_848, UInt<1>(0h1), "") : assert_50 node _T_852 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_853 = asUInt(reset) node _T_854 = eq(_T_853, UInt<1>(0h0)) when _T_854 : node _T_855 = eq(_T_852, UInt<1>(0h0)) when _T_855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_852, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_856 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(_T_856, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_856, UInt<1>(0h1), "") : assert_52 node _source_ok_T_48 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0) node _source_ok_T_49 = shr(io.in.d.bits.source, 3) node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2)) node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<3>(0h7)) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 2, 0) node _source_ok_T_55 = shr(io.in.d.bits.source, 3) node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3)) node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<3>(0h7)) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_61 = shr(io.in.d.bits.source, 2) node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h0)) node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_T_65 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_67 = shr(io.in.d.bits.source, 2) node _source_ok_T_68 = eq(_source_ok_T_67, UInt<1>(0h1)) node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_T_71 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0) node _source_ok_T_73 = shr(io.in.d.bits.source, 2) node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h2)) node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_T_77 = leq(source_ok_uncommonBits_10, UInt<2>(0h3)) node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<2>(0h3)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_11, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_48 connect _source_ok_WIRE_1[1], _source_ok_T_54 connect _source_ok_WIRE_1[2], _source_ok_T_60 connect _source_ok_WIRE_1[3], _source_ok_T_66 connect _source_ok_WIRE_1[4], _source_ok_T_72 connect _source_ok_WIRE_1[5], _source_ok_T_78 connect _source_ok_WIRE_1[6], _source_ok_T_84 connect _source_ok_WIRE_1[7], _source_ok_T_85 connect _source_ok_WIRE_1[8], _source_ok_T_86 connect _source_ok_WIRE_1[9], _source_ok_T_87 node _source_ok_T_88 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE_1[2]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE_1[3]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE_1[4]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[5]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[6]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[7]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_95, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_860 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_860 : node _T_861 = asUInt(reset) node _T_862 = eq(_T_861, UInt<1>(0h0)) when _T_862 : node _T_863 = eq(source_ok_1, UInt<1>(0h0)) when _T_863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_864 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(_T_864, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_864, UInt<1>(0h1), "") : assert_54 node _T_868 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_868, UInt<1>(0h1), "") : assert_55 node _T_872 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_872, UInt<1>(0h1), "") : assert_56 node _T_876 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(_T_876, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_876, UInt<1>(0h1), "") : assert_57 node _T_880 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_880 : node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(source_ok_1, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(sink_ok, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_887 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_T_887, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_887, UInt<1>(0h1), "") : assert_60 node _T_891 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_891, UInt<1>(0h1), "") : assert_61 node _T_895 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_895, UInt<1>(0h1), "") : assert_62 node _T_899 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_900 = asUInt(reset) node _T_901 = eq(_T_900, UInt<1>(0h0)) when _T_901 : node _T_902 = eq(_T_899, UInt<1>(0h0)) when _T_902 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_899, UInt<1>(0h1), "") : assert_63 node _T_903 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_904 = or(UInt<1>(0h1), _T_903) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_904, UInt<1>(0h1), "") : assert_64 node _T_908 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_908 : node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(source_ok_1, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(sink_ok, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_915 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_915, UInt<1>(0h1), "") : assert_67 node _T_919 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_919, UInt<1>(0h1), "") : assert_68 node _T_923 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_924 = asUInt(reset) node _T_925 = eq(_T_924, UInt<1>(0h0)) when _T_925 : node _T_926 = eq(_T_923, UInt<1>(0h0)) when _T_926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_923, UInt<1>(0h1), "") : assert_69 node _T_927 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_928 = or(_T_927, io.in.d.bits.corrupt) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_928, UInt<1>(0h1), "") : assert_70 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = or(UInt<1>(0h1), _T_932) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_933, UInt<1>(0h1), "") : assert_71 node _T_937 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_937 : node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(source_ok_1, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_941 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_941, UInt<1>(0h1), "") : assert_73 node _T_945 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_945, UInt<1>(0h1), "") : assert_74 node _T_949 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_950 = or(UInt<1>(0h1), _T_949) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_950, UInt<1>(0h1), "") : assert_75 node _T_954 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_954 : node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(source_ok_1, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_958 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_958, UInt<1>(0h1), "") : assert_77 node _T_962 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_963 = or(_T_962, io.in.d.bits.corrupt) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_963, UInt<1>(0h1), "") : assert_78 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = or(UInt<1>(0h1), _T_967) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_968, UInt<1>(0h1), "") : assert_79 node _T_972 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_972 : node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(source_ok_1, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_976 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_976, UInt<1>(0h1), "") : assert_81 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_980, UInt<1>(0h1), "") : assert_82 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_985, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<14>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_989 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_989, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<14>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_993 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_993, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_997 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_997, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1001 = eq(a_first, UInt<1>(0h0)) node _T_1002 = and(io.in.a.valid, _T_1001) when _T_1002 : node _T_1003 = eq(io.in.a.bits.opcode, opcode) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_87 node _T_1007 = eq(io.in.a.bits.param, param) node _T_1008 = asUInt(reset) node _T_1009 = eq(_T_1008, UInt<1>(0h0)) when _T_1009 : node _T_1010 = eq(_T_1007, UInt<1>(0h0)) when _T_1010 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1007, UInt<1>(0h1), "") : assert_88 node _T_1011 = eq(io.in.a.bits.size, size) node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(_T_1011, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1011, UInt<1>(0h1), "") : assert_89 node _T_1015 = eq(io.in.a.bits.source, source) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_90 node _T_1019 = eq(io.in.a.bits.address, address) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_91 node _T_1023 = and(io.in.a.ready, io.in.a.valid) node _T_1024 = and(_T_1023, a_first) when _T_1024 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1025 = eq(d_first, UInt<1>(0h0)) node _T_1026 = and(io.in.d.valid, _T_1025) when _T_1026 : node _T_1027 = eq(io.in.d.bits.opcode, opcode_1) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_92 node _T_1031 = eq(io.in.d.bits.param, param_1) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_93 node _T_1035 = eq(io.in.d.bits.size, size_1) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_94 node _T_1039 = eq(io.in.d.bits.source, source_1) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_95 node _T_1043 = eq(io.in.d.bits.sink, sink) node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(_T_1043, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1043, UInt<1>(0h1), "") : assert_96 node _T_1047 = eq(io.in.d.bits.denied, denied) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_97 node _T_1051 = and(io.in.d.ready, io.in.d.valid) node _T_1052 = and(_T_1051, d_first) when _T_1052 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<1032> connect a_sizes_set, UInt<1032>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1053 = and(io.in.a.valid, a_first_1) node _T_1054 = and(_T_1053, UInt<1>(0h1)) when _T_1054 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1055 = and(io.in.a.ready, io.in.a.valid) node _T_1056 = and(_T_1055, a_first_1) node _T_1057 = and(_T_1056, UInt<1>(0h1)) when _T_1057 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1058 = dshr(inflight, io.in.a.bits.source) node _T_1059 = bits(_T_1058, 0, 0) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<1032> connect d_sizes_clr, UInt<1032>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1064 = and(io.in.d.valid, d_first_1) node _T_1065 = and(_T_1064, UInt<1>(0h1)) node _T_1066 = eq(d_release_ack, UInt<1>(0h0)) node _T_1067 = and(_T_1065, _T_1066) when _T_1067 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1068 = and(io.in.d.ready, io.in.d.valid) node _T_1069 = and(_T_1068, d_first_1) node _T_1070 = and(_T_1069, UInt<1>(0h1)) node _T_1071 = eq(d_release_ack, UInt<1>(0h0)) node _T_1072 = and(_T_1070, _T_1071) when _T_1072 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1073 = and(io.in.d.valid, d_first_1) node _T_1074 = and(_T_1073, UInt<1>(0h1)) node _T_1075 = eq(d_release_ack, UInt<1>(0h0)) node _T_1076 = and(_T_1074, _T_1075) when _T_1076 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1077 = dshr(inflight, io.in.d.bits.source) node _T_1078 = bits(_T_1077, 0, 0) node _T_1079 = or(_T_1078, same_cycle_resp) node _T_1080 = asUInt(reset) node _T_1081 = eq(_T_1080, UInt<1>(0h0)) when _T_1081 : node _T_1082 = eq(_T_1079, UInt<1>(0h0)) when _T_1082 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1079, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1083 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1084 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1085 = or(_T_1083, _T_1084) node _T_1086 = asUInt(reset) node _T_1087 = eq(_T_1086, UInt<1>(0h0)) when _T_1087 : node _T_1088 = eq(_T_1085, UInt<1>(0h0)) when _T_1088 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1085, UInt<1>(0h1), "") : assert_100 node _T_1089 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_101 else : node _T_1093 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1094 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1095 = or(_T_1093, _T_1094) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_102 node _T_1099 = eq(io.in.d.bits.size, a_size_lookup) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_103 node _T_1103 = and(io.in.d.valid, d_first_1) node _T_1104 = and(_T_1103, a_first_1) node _T_1105 = and(_T_1104, io.in.a.valid) node _T_1106 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = eq(d_release_ack, UInt<1>(0h0)) node _T_1109 = and(_T_1107, _T_1108) when _T_1109 : node _T_1110 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1111 = or(_T_1110, io.in.a.ready) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_104 node _T_1115 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1116 = orr(a_set_wo_ready) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) node _T_1118 = or(_T_1115, _T_1117) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_54 node _T_1122 = orr(inflight) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) node _T_1124 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1125 = or(_T_1123, _T_1124) node _T_1126 = lt(watchdog, plusarg_reader.out) node _T_1127 = or(_T_1125, _T_1126) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1131 = and(io.in.a.ready, io.in.a.valid) node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = or(_T_1131, _T_1132) when _T_1133 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<1032> connect c_sizes_set, UInt<1032>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1134 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<14>(0h0) connect _WIRE_8.bits.source, UInt<8>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1135 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1136 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1137 = and(_T_1135, _T_1136) node _T_1138 = and(_T_1134, _T_1137) when _T_1138 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1139 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1140 = and(_T_1139, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1141 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1142 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1143 = and(_T_1141, _T_1142) node _T_1144 = and(_T_1140, _T_1143) when _T_1144 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1145 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1146 = bits(_T_1145, 0, 0) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<1032> connect d_sizes_clr_1, UInt<1032>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1151 = and(io.in.d.valid, d_first_2) node _T_1152 = and(_T_1151, UInt<1>(0h1)) node _T_1153 = and(_T_1152, d_release_ack_1) when _T_1153 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1154 = and(io.in.d.ready, io.in.d.valid) node _T_1155 = and(_T_1154, d_first_2) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = and(_T_1156, d_release_ack_1) when _T_1157 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1158 = and(io.in.d.valid, d_first_2) node _T_1159 = and(_T_1158, UInt<1>(0h1)) node _T_1160 = and(_T_1159, d_release_ack_1) when _T_1160 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1161 = dshr(inflight_1, io.in.d.bits.source) node _T_1162 = bits(_T_1161, 0, 0) node _T_1163 = or(_T_1162, same_cycle_resp_1) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1167 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_109 else : node _T_1171 = eq(io.in.d.bits.size, c_size_lookup) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_110 node _T_1175 = and(io.in.d.valid, d_first_2) node _T_1176 = and(_T_1175, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1177 = and(_T_1176, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1178 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = and(_T_1179, d_release_ack_1) node _T_1181 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1182 = and(_T_1180, _T_1181) when _T_1182 : node _T_1183 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1184 = or(_T_1183, _WIRE_23.ready) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_111 node _T_1188 = orr(c_set_wo_ready) when _T_1188 : node _T_1189 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_55 node _T_1193 = orr(inflight_1) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) node _T_1195 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1196 = or(_T_1194, _T_1195) node _T_1197 = lt(watchdog_1, plusarg_reader_1.out) node _T_1198 = or(_T_1196, _T_1197) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1202 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1203 = and(io.in.d.ready, io.in.d.valid) node _T_1204 = or(_T_1202, _T_1203) when _T_1204 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_25 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_31 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_14 = _source_ok_T_13 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_47 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_30 = _uncommonBits_T_30[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_31 = _uncommonBits_T_31[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_36 = _uncommonBits_T_36[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_37 = _uncommonBits_T_37[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_42 = _uncommonBits_T_42[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_43 = _uncommonBits_T_43[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_61 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_67 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_73 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_79 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_62 = _source_ok_T_61 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_66; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_68 = _source_ok_T_67 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_74 = _source_ok_T_73 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_80 = _source_ok_T_79 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire _source_ok_T_85 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire _source_ok_T_86 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire _source_ok_T_88 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_89 = _source_ok_T_88 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_90 = _source_ok_T_89 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_91 = _source_ok_T_90 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_95 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _T_1131 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1131; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1131; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1204 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1204; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1204; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1204; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1057 = _T_1131 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1057 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1057 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1057 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1057 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1057 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1103 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1103 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1072 = _T_1204 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1072 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1072 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1072 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1031:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1175 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1175 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1157 = _T_1204 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1157 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1157 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1157 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a22d32s7k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<22>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<22>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<22>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)	module Repeater_TLBundleA_a22d32s7k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [21:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [31:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [21:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [6:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [21:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [31:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [6:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [21:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [31:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [6:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [21:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [31:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [6:0] saved_source; // @[Repeater.scala:21:18] reg [21:0] saved_address; // @[Repeater.scala:21:18] reg [3:0] saved_mask; // @[Repeater.scala:21:18] reg [31:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 \| full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 \| full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_202 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_202( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_365 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_109 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_365( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_109 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s4k1z3u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_33 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a28d64s4k1z3u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a28d64s4k1z3u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLBuffer_a28d64s4k1z3u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_33 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s4k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s4k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_122 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_139 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_122( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_139 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheControl : input clock : Clock input reset : Reset output auto : { flip ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip flush_match : UInt<1>, flush_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, flip flush_resp : UInt<1>} wire ctrlnodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate ctrlnodeIn.d.bits.corrupt invalidate ctrlnodeIn.d.bits.data invalidate ctrlnodeIn.d.bits.denied invalidate ctrlnodeIn.d.bits.sink invalidate ctrlnodeIn.d.bits.source invalidate ctrlnodeIn.d.bits.size invalidate ctrlnodeIn.d.bits.param invalidate ctrlnodeIn.d.bits.opcode invalidate ctrlnodeIn.d.valid invalidate ctrlnodeIn.d.ready invalidate ctrlnodeIn.a.bits.corrupt invalidate ctrlnodeIn.a.bits.data invalidate ctrlnodeIn.a.bits.mask invalidate ctrlnodeIn.a.bits.address invalidate ctrlnodeIn.a.bits.source invalidate ctrlnodeIn.a.bits.size invalidate ctrlnodeIn.a.bits.param invalidate ctrlnodeIn.a.bits.opcode invalidate ctrlnodeIn.a.valid invalidate ctrlnodeIn.a.ready inst monitor of TLMonitor_48 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, ctrlnodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, ctrlnodeIn.d.bits.data connect monitor.io.in.d.bits.denied, ctrlnodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, ctrlnodeIn.d.bits.sink connect monitor.io.in.d.bits.source, ctrlnodeIn.d.bits.source connect monitor.io.in.d.bits.size, ctrlnodeIn.d.bits.size connect monitor.io.in.d.bits.param, ctrlnodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, ctrlnodeIn.d.bits.opcode connect monitor.io.in.d.valid, ctrlnodeIn.d.valid connect monitor.io.in.d.ready, ctrlnodeIn.d.ready connect monitor.io.in.a.bits.corrupt, ctrlnodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, ctrlnodeIn.a.bits.data connect monitor.io.in.a.bits.mask, ctrlnodeIn.a.bits.mask connect monitor.io.in.a.bits.address, ctrlnodeIn.a.bits.address connect monitor.io.in.a.bits.source, ctrlnodeIn.a.bits.source connect monitor.io.in.a.bits.size, ctrlnodeIn.a.bits.size connect monitor.io.in.a.bits.param, ctrlnodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, ctrlnodeIn.a.bits.opcode connect monitor.io.in.a.valid, ctrlnodeIn.a.valid connect monitor.io.in.a.ready, ctrlnodeIn.a.ready connect ctrlnodeIn, auto.ctrl_in regreset flushInValid : UInt<1>, clock, reset, UInt<1>(0h0) reg flushInAddress : UInt<64>, clock regreset flushOutValid : UInt<1>, clock, reset, UInt<1>(0h0) wire flushOutReady : UInt<1> connect flushOutReady, UInt<1>(0h0) when flushOutReady : connect flushOutValid, UInt<1>(0h0) when io.flush_resp : connect flushOutValid, UInt<1>(0h1) when io.flush_req.ready : connect flushInValid, UInt<1>(0h0) connect io.flush_req.valid, flushInValid connect io.flush_req.bits, flushInAddress node _T = eq(io.flush_match, UInt<1>(0h0)) node _T_1 = and(_T, flushInValid) when _T_1 : connect flushInValid, UInt<1>(0h0) connect flushOutValid, UInt<1>(0h1) wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(ctrlnodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(ctrlnodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, ctrlnodeIn.a.bits.data connect in.bits.mask, ctrlnodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, ctrlnodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, ctrlnodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits inst out_back_front_q of Queue1_RegMapperInput_i9_m8 connect out_back_front_q.clock, clock connect out_back_front_q.reset, reset connect out_back_front_q.io.enq, out_front node out_maskMatch = not(UInt<9>(0h48)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_back_front_q.io.deq.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) node _out_T_2 = eq(out_findex, UInt<9>(0h0)) node _out_T_3 = eq(out_bindex, UInt<9>(0h0)) node _out_T_4 = eq(out_findex, UInt<9>(0h0)) node _out_T_5 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[6] wire out_wivalid : UInt<1>[6] wire out_roready : UInt<1>[6] wire out_woready : UInt<1>[6] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_back_front_q.io.deq.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_back_front_q.io.deq.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_back_front_q.io.deq.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_back_front_q.io.deq.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_back_front_q.io.deq.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_back_front_q.io.deq.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_back_front_q.io.deq.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_back_front_q.io.deq.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_6 = bits(out_back_front_q.io.deq.bits.data, 7, 0) node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_8 = and(UInt<1>(0h1), out_f_roready) node _out_T_9 = eq(out_rimask, UInt<1>(0h0)) node _out_T_10 = eq(out_wimask, UInt<1>(0h0)) node _out_T_11 = eq(out_romask, UInt<1>(0h0)) node _out_T_12 = eq(out_womask, UInt<1>(0h0)) node _out_T_13 = or(UInt<1>(0h1), UInt<8>(0h0)) node _out_T_14 = bits(_out_T_13, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_15 = bits(out_back_front_q.io.deq.bits.data, 15, 8) node _out_T_16 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_17 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_18 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_19 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_20 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_14, UInt<8>(0h0)) node out_prepend = cat(UInt<4>(0h8), _out_prepend_T) node _out_T_22 = or(out_prepend, UInt<16>(0h0)) node _out_T_23 = bits(_out_T_22, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_24 = bits(out_back_front_q.io.deq.bits.data, 23, 16) node _out_T_25 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_26 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_27 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_28 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_29 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_30 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_23, UInt<16>(0h0)) node out_prepend_1 = cat(UInt<4>(0ha), _out_prepend_T_1) node _out_T_31 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_32 = bits(_out_T_31, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_33 = bits(out_back_front_q.io.deq.bits.data, 31, 24) node _out_T_34 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_35 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_36 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_37 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_38 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_39 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_32, UInt<24>(0h0)) node out_prepend_2 = cat(UInt<3>(0h6), _out_prepend_T_2) node _out_T_40 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_41 = bits(_out_T_40, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 63, 0) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 63, 0) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 63, 0) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 63, 0) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_42 = bits(out_front.bits.data, 63, 0) when out_f_woready_4 : connect flushOutReady, UInt<1>(0h1) when out_f_wivalid_4 : connect flushInValid, UInt<1>(0h1) node _out_T_43 = eq(flushInValid, UInt<1>(0h0)) node _out_T_44 = and(out_f_wivalid_4, _out_T_43) when _out_T_44 : connect flushInAddress, _out_T_42 node out_f_wiready = eq(flushInValid, UInt<1>(0h0)) node _out_T_45 = and(out_f_wivalid_4, out_f_wiready) node _out_T_46 = and(flushOutValid, out_f_woready_4) node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_49 = or(out_f_wiready, _out_T_48) node _out_T_50 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_51 = eq(out_womask_4, UInt<1>(0h0)) node _out_T_52 = or(flushOutValid, _out_T_51) node _out_T_53 = or(UInt<1>(0h0), UInt<64>(0h0)) node _out_T_54 = bits(_out_T_53, 63, 0) node _out_rimask_T_5 = bits(out_frontMask, 31, 0) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 31, 0) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 31, 0) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 31, 0) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_55 = bits(out_front.bits.data, 31, 0) when out_f_woready_5 : connect flushOutReady, UInt<1>(0h1) when out_f_wivalid_5 : connect flushInValid, UInt<1>(0h1) node _out_T_56 = eq(flushInValid, UInt<1>(0h0)) node _out_T_57 = and(out_f_wivalid_5, _out_T_56) when _out_T_57 : node _out_flushInAddress_T = shl(_out_T_55, 4) connect flushInAddress, _out_flushInAddress_T node out_f_wiready_1 = eq(flushInValid, UInt<1>(0h0)) node _out_T_58 = and(out_f_wivalid_5, out_f_wiready_1) node _out_T_59 = and(flushOutValid, out_f_woready_5) node _out_T_60 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_61 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_62 = or(out_f_wiready_1, _out_T_61) node _out_T_63 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_64 = eq(out_womask_5, UInt<1>(0h0)) node _out_T_65 = or(flushOutValid, _out_T_64) node _out_T_66 = or(UInt<1>(0h0), UInt<32>(0h0)) node _out_T_67 = bits(_out_T_66, 31, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node out_iindex = cat(_out_iindex_T_6, _out_iindex_T_3) node _out_oindex_T = bits(out_back_front_q.io.deq.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_back_front_q.io.deq.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_back_front_q.io.deq.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_back_front_q.io.deq.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_back_front_q.io.deq.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_back_front_q.io.deq.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_back_front_q.io.deq.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_back_front_q.io.deq.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_back_front_q.io.deq.bits.index, 8, 8) node out_oindex = cat(_out_oindex_T_6, _out_oindex_T_3) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, UInt<1>(0h1)) connect out_rifireMux_out_1, UInt<1>(0h1) node _out_rifireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[4], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_4) connect out_rifireMux_out_3, UInt<1>(0h1) connect out_rivalid[5], _out_rifireMux_T_15 node _out_rifireMux_T_16 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, UInt<1>(0h1)) connect out_wifireMux_out_1, UInt<1>(0h1) node _out_wifireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2) node out_wifireMux_all = and(_out_wifireMux_T_12, _out_T_49) connect out_wifireMux_out_2, _out_T_49 connect out_wivalid[4], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_4) node out_wifireMux_all_1 = and(_out_wifireMux_T_16, _out_T_62) connect out_wifireMux_out_3, _out_T_62 connect out_wivalid[5], _out_wifireMux_T_16 node _out_wifireMux_T_17 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_back_front_q.io.deq.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, UInt<1>(0h1)) connect out_rofireMux_out_1, UInt<1>(0h1) node _out_rofireMux_T_8 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[4], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_5) connect out_rofireMux_out_3, UInt<1>(0h1) connect out_roready[5], _out_rofireMux_T_15 node _out_rofireMux_T_16 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_back_front_q.io.deq.valid, out.ready) node _out_wofireMux_T_1 = eq(out_back_front_q.io.deq.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, UInt<1>(0h1)) connect out_wofireMux_out_1, UInt<1>(0h1) node _out_wofireMux_T_9 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3) node out_wofireMux_all = and(_out_wofireMux_T_12, _out_T_52) connect out_wofireMux_out_2, _out_T_52 connect out_woready[4], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_5) node out_wofireMux_all_1 = and(_out_wofireMux_T_16, _out_T_65) connect out_wofireMux_out_3, _out_T_65 connect out_woready[5], _out_wofireMux_T_16 node _out_wofireMux_T_17 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_back_front_q.io.deq.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_q_io_deq_ready_T = and(out.ready, out_oready) connect out_back_front_q.io.deq.ready, _out_front_q_io_deq_ready_T node _out_out_valid_T = and(out_back_front_q.io.deq.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_back_front_q.io.deq.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], UInt<1>(0h1) connect _out_out_bits_data_WIRE[2], _out_T_3 connect _out_out_bits_data_WIRE[3], _out_T_5 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_41 connect _out_out_bits_data_WIRE_1[1], UInt<1>(0h0) connect _out_out_bits_data_WIRE_1[2], _out_T_54 connect _out_out_bits_data_WIRE_1[3], _out_T_67 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_back_front_q.io.deq.bits.extra connect in.valid, ctrlnodeIn.a.valid connect ctrlnodeIn.a.ready, in.ready connect ctrlnodeIn.d.valid, out.valid connect out.ready, ctrlnodeIn.d.ready wire ctrlnodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect ctrlnodeIn_d_bits_d.opcode, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.param, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect ctrlnodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect ctrlnodeIn_d_bits_d.sink, UInt<1>(0h0) connect ctrlnodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate ctrlnodeIn_d_bits_d.data connect ctrlnodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect ctrlnodeIn.d.bits.corrupt, ctrlnodeIn_d_bits_d.corrupt connect ctrlnodeIn.d.bits.data, ctrlnodeIn_d_bits_d.data connect ctrlnodeIn.d.bits.denied, ctrlnodeIn_d_bits_d.denied connect ctrlnodeIn.d.bits.sink, ctrlnodeIn_d_bits_d.sink connect ctrlnodeIn.d.bits.source, ctrlnodeIn_d_bits_d.source connect ctrlnodeIn.d.bits.size, ctrlnodeIn_d_bits_d.size connect ctrlnodeIn.d.bits.param, ctrlnodeIn_d_bits_d.param connect ctrlnodeIn.d.bits.opcode, ctrlnodeIn_d_bits_d.opcode connect ctrlnodeIn.d.bits.data, out.bits.data node _ctrlnodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect ctrlnodeIn.d.bits.opcode, _ctrlnodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_98 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_99 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module InclusiveCacheControl( // @[Control.scala:38:9] input clock, // @[Control.scala:38:9] input reset, // @[Control.scala:38:9] output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_flush_match, // @[Control.scala:39:16] input io_flush_req_ready, // @[Control.scala:39:16] output io_flush_req_valid, // @[Control.scala:39:16] output [63:0] io_flush_req_bits, // @[Control.scala:39:16] input io_flush_resp // @[Control.scala:39:16] ); wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:38:9] wire [10:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:38:9] wire [25:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:38:9] wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:38:9] wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:38:9] wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:38:9] wire io_flush_match_0 = io_flush_match; // @[Control.scala:38:9] wire io_flush_req_ready_0 = io_flush_req_ready; // @[Control.scala:38:9] wire io_flush_resp_0 = io_flush_resp; // @[Control.scala:38:9] wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801}; wire [8:0] out_maskMatch = 9'h1B7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_13 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_14 = 8'h1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T = 8'h1; // @[RegisterRouter.scala:87:24] wire [11:0] out_prepend = 12'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_22 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_23 = 16'h801; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_1 = 16'h801; // @[RegisterRouter.scala:87:24] wire [19:0] out_prepend_1 = 20'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_31 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_32 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_2 = 24'hA0801; // @[RegisterRouter.scala:87:24] wire [26:0] out_prepend_2 = 27'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_40 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_41 = 32'h60A0801; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_66 = 32'h0; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_67 = 32'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h60A0801; // @[MuxLiteral.scala:49:48] wire [2:0] ctrlnodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_T_53 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_54 = 64'h0; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] ctrlnodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:38:9] wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:38:9] wire ctrlnodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire ctrlnodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire ctrlnodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire ctrlnodeIn_a_ready; // @[MixedNode.scala:551:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire ctrlnodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:38:9] wire [2:0] ctrlnodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:38:9] wire [10:0] ctrlnodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:38:9] wire [25:0] ctrlnodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:38:9] wire [7:0] ctrlnodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:38:9] wire [63:0] ctrlnodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:38:9] wire ctrlnodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:38:9] wire ctrlnodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] ctrlnodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] ctrlnodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] ctrlnodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] ctrlnodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] wire [1:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] wire [10:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] wire auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] wire io_flush_req_valid_0; // @[Control.scala:38:9] wire [63:0] io_flush_req_bits_0; // @[Control.scala:38:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_ctrl_in_a_ready_0 = ctrlnodeIn_a_ready; // @[Control.scala:38:9] wire in_valid = ctrlnodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = ctrlnodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = ctrlnodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = ctrlnodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = ctrlnodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = ctrlnodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_valid_0 = ctrlnodeIn_d_valid; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode_0 = ctrlnodeIn_d_bits_opcode; // @[Control.scala:38:9] wire [1:0] ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_size_0 = ctrlnodeIn_d_bits_size; // @[Control.scala:38:9] wire [10:0] ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_ctrl_in_d_bits_source_0 = ctrlnodeIn_d_bits_source; // @[Control.scala:38:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_d_bits_data_0 = ctrlnodeIn_d_bits_data; // @[Control.scala:38:9] reg flushInValid; // @[Control.scala:45:33] assign io_flush_req_valid_0 = flushInValid; // @[Control.scala:38:9, :45:33] reg [63:0] flushInAddress; // @[Control.scala:46:29] assign io_flush_req_bits_0 = flushInAddress; // @[Control.scala:38:9, :46:29] reg flushOutValid; // @[Control.scala:47:33] wire flushOutReady; // @[Control.scala:48:34] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = ctrlnodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = ctrlnodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _ctrlnodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign ctrlnodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_42 = out_front_bits_data; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [8:0] out_findex = out_front_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [63:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask = \|_out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask = \|_out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_6 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire _out_T_9 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_womask; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = \|_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = \|_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_16 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_17 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_15 = _out_back_front_q_io_deq_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = \|_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = \|_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_26 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_24 = _out_back_front_q_io_deq_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = \|_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = \|_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_35 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_33 = _out_back_front_q_io_deq_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire _out_T_36 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_37 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = \|_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = \|_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~flushInValid; // @[Control.scala:45:33, :71:23] wire _out_T_44 = out_f_wivalid_4 & _out_T_43; // @[RegisterRouter.scala:87:24] wire out_f_wiready = ~flushInValid; // @[Control.scala:45:33, :71:23, :72:8] wire _out_T_45 = out_f_wivalid_4 & out_f_wiready; // @[RegisterRouter.scala:87:24] wire _out_T_46 = flushOutValid & out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_wiready \| _out_T_48; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = _out_T_49; // @[RegisterRouter.scala:87:24] wire _out_T_50 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = flushOutValid \| _out_T_51; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = _out_T_52; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_55 = out_front_bits_data[31:0]; // @[RegisterRouter.scala:87:24] assign flushOutReady = out_f_woready_5 \| out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~flushInValid; // @[Control.scala:45:33, :64:23, :71:23] wire _out_T_57 = out_f_wivalid_5 & _out_T_56; // @[RegisterRouter.scala:87:24] wire [35:0] _out_flushInAddress_T = {_out_T_55, 4'h0}; // @[RegisterRouter.scala:87:24] wire out_f_wiready_1 = ~flushInValid; // @[Control.scala:45:33, :65:8, :71:23] wire _out_T_58 = out_f_wivalid_5 & out_f_wiready_1; // @[RegisterRouter.scala:87:24] wire _out_T_59 = flushOutValid & out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wiready_1 \| _out_T_61; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = _out_T_62; // @[RegisterRouter.scala:87:24] wire _out_T_63 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = flushOutValid \| _out_T_64; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = _out_T_65; // @[RegisterRouter.scala:87:24] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_6, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_6, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all = _out_wifireMux_T_12 & _out_T_49; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = out_wifireMux_out_2 \| _out_wifireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_2 = _out_wifireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wifireMux_all_1 = _out_wifireMux_T_16 & _out_T_62; // @[ReduceOthers.scala:47:21] wire _out_wifireMux_T_17 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = out_wifireMux_out_3 \| _out_wifireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_3 = _out_wifireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_3 = {{_out_wifireMux_WIRE_3}, {_out_wifireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wifireMux = _GEN_3[out_iindex]; // @[MuxLiteral.scala:49:10] wire _GEN_4 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all = _out_wofireMux_T_12 & _out_T_52; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = out_wofireMux_out_2 \| _out_wofireMux_T_13; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_2 = _out_wofireMux_T_14; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24] wire out_wofireMux_all_1 = _out_wofireMux_T_16 & _out_T_65; // @[ReduceOthers.scala:47:21] wire _out_wofireMux_T_17 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = out_wofireMux_out_3 \| _out_wofireMux_T_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_3 = _out_wofireMux_T_18; // @[MuxLiteral.scala:49:48] wire [3:0] _GEN_5 = {{_out_wofireMux_WIRE_3}, {_out_wofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}] wire out_wofireMux = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] wire out_iready = out_front_bits_read \| out_wifireMux; // @[MuxLiteral.scala:49:10] wire out_oready = _out_back_front_q_io_deq_bits_read \| out_wofireMux; // @[MuxLiteral.scala:49:10] assign _out_in_ready_T = out_front_ready & out_iready; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign _out_front_valid_T = in_valid & out_iready; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] wire _out_front_q_io_deq_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_6 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_6[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_T_3 = _GEN[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign ctrlnodeIn_d_bits_size = ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_source = ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign ctrlnodeIn_d_bits_opcode = {2'h0, _ctrlnodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] wire _T_1 = ~io_flush_match_0 & flushInValid; // @[Control.scala:38:9, :45:33, :56:{11,27}] always @(posedge clock) begin // @[Control.scala:38:9] if (reset) begin // @[Control.scala:38:9] flushInValid <= 1'h0; // @[Control.scala:45:33] flushOutValid <= 1'h0; // @[Control.scala:47:33] end else begin // @[Control.scala:38:9] flushInValid <= out_f_wivalid_5 \| out_f_wivalid_4 \| ~(_T_1 \| io_flush_req_ready_0) & flushInValid; // @[RegisterRouter.scala:87:24] flushOutValid <= _T_1 \| io_flush_resp_0 \| ~flushOutReady & flushOutValid; // @[Control.scala:38:9, :47:33, :48:34, :50:{26,42}, :51:{26,42}, :56:{27,44}, :58:21] end if (_out_T_57) // @[Control.scala:64:20] flushInAddress <= {28'h0, _out_flushInAddress_T}; // @[Control.scala:46:29, :64:{55,63}] else if (_out_T_44) // @[Control.scala:71:20] flushInAddress <= _out_T_42; // @[RegisterRouter.scala:87:24] always @(posedge) TLMonitor_48 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (ctrlnodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (ctrlnodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (ctrlnodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (ctrlnodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (ctrlnodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (ctrlnodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (ctrlnodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (ctrlnodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (ctrlnodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (ctrlnodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (ctrlnodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (ctrlnodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (ctrlnodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (ctrlnodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (ctrlnodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (ctrlnodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_RegMapperInput_i9_m8 out_back_front_q ( // @[RegisterRouter.scala:87:24] .clock (clock), .reset (reset), .io_enq_ready (out_front_ready), .io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24] .io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24] .io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24] .io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24] .io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24] .io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24] .io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24] .io_deq_valid (_out_back_front_q_io_deq_valid), .io_deq_bits_read (_out_back_front_q_io_deq_bits_read), .io_deq_bits_index (_out_back_front_q_io_deq_bits_index), .io_deq_bits_data (_out_back_front_q_io_deq_bits_data), .io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask), .io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source), .io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size) ); // @[RegisterRouter.scala:87:24] assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9] assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9] assign io_flush_req_valid = io_flush_req_valid_0; // @[Control.scala:38:9] assign io_flush_req_bits = io_flush_req_bits_0; // @[Control.scala:38:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_46 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<27>(0h4000000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = or(_T_38, _T_43) node _T_75 = or(_T_74, _T_48) node _T_76 = or(_T_75, _T_53) node _T_77 = or(_T_76, _T_58) node _T_78 = or(_T_77, _T_63) node _T_79 = or(_T_78, _T_68) node _T_80 = or(_T_79, _T_73) node _T_81 = and(_T_33, _T_80) node _T_82 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_83 = or(UInt<1>(0h0), _T_82) node _T_84 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<17>(0h10000))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<29>(0h10000000))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_88, _T_93) node _T_95 = and(_T_83, _T_94) node _T_96 = or(UInt<1>(0h0), _T_81) node _T_97 = or(_T_96, _T_95) node _T_98 = and(_T_32, _T_97) node _T_99 = asUInt(reset) node _T_100 = eq(_T_99, UInt<1>(0h0)) when _T_100 : node _T_101 = eq(_T_98, UInt<1>(0h0)) when _T_101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_98, UInt<1>(0h1), "") : assert_2 node _T_102 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_103 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_102 connect _WIRE[1], _T_103 node _T_104 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_105 = mux(_WIRE[0], _T_104, UInt<1>(0h0)) node _T_106 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = or(_T_105, _T_106) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_107 node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = or(UInt<1>(0h0), _T_110) node _T_112 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<14>(0h2000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<13>(0h1000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<17>(0h10000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<18>(0h2f000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<17>(0h10000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<13>(0h1000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<17>(0h10000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<27>(0h4000000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<29>(0h10000000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = or(_T_116, _T_121) node _T_163 = or(_T_162, _T_126) node _T_164 = or(_T_163, _T_131) node _T_165 = or(_T_164, _T_136) node _T_166 = or(_T_165, _T_141) node _T_167 = or(_T_166, _T_146) node _T_168 = or(_T_167, _T_151) node _T_169 = or(_T_168, _T_156) node _T_170 = or(_T_169, _T_161) node _T_171 = and(_T_111, _T_170) node _T_172 = or(UInt<1>(0h0), _T_171) node _T_173 = and(_WIRE_1, _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_173, UInt<1>(0h1), "") : assert_3 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(source_ok, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_180 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_180, UInt<1>(0h1), "") : assert_5 node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(is_aligned, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_187 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_187, UInt<1>(0h1), "") : assert_7 node _T_191 = not(io.in.a.bits.mask) node _T_192 = eq(_T_191, UInt<1>(0h0)) node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_T_192, UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_192, UInt<1>(0h1), "") : assert_8 node _T_196 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_197 = asUInt(reset) node _T_198 = eq(_T_197, UInt<1>(0h0)) when _T_198 : node _T_199 = eq(_T_196, UInt<1>(0h0)) when _T_199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_196, UInt<1>(0h1), "") : assert_9 node _T_200 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_200 : node _T_201 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_202 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_205 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_206 = or(_T_204, _T_205) node _T_207 = and(_T_203, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<14>(0h2000))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<17>(0h10000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_226 = cvt(_T_225) node _T_227 = and(_T_226, asSInt(UInt<18>(0h2f000))) node _T_228 = asSInt(_T_227) node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0))) node _T_230 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_231 = cvt(_T_230) node _T_232 = and(_T_231, asSInt(UInt<17>(0h10000))) node _T_233 = asSInt(_T_232) node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0))) node _T_235 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_236 = cvt(_T_235) node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000))) node _T_238 = asSInt(_T_237) node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0))) node _T_240 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<27>(0h4000000))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<13>(0h1000))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = or(_T_214, _T_219) node _T_251 = or(_T_250, _T_224) node _T_252 = or(_T_251, _T_229) node _T_253 = or(_T_252, _T_234) node _T_254 = or(_T_253, _T_239) node _T_255 = or(_T_254, _T_244) node _T_256 = or(_T_255, _T_249) node _T_257 = and(_T_209, _T_256) node _T_258 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_259 = or(UInt<1>(0h0), _T_258) node _T_260 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<17>(0h10000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_266 = cvt(_T_265) node _T_267 = and(_T_266, asSInt(UInt<29>(0h10000000))) node _T_268 = asSInt(_T_267) node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0))) node _T_270 = or(_T_264, _T_269) node _T_271 = and(_T_259, _T_270) node _T_272 = or(UInt<1>(0h0), _T_257) node _T_273 = or(_T_272, _T_271) node _T_274 = and(_T_208, _T_273) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_274, UInt<1>(0h1), "") : assert_10 node _T_278 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_278 connect _WIRE_2[1], _T_279 node _T_280 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_281 = mux(_WIRE_2[0], _T_280, UInt<1>(0h0)) node _T_282 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = or(_T_281, _T_282) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_283 node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_285 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_286 = and(_T_284, _T_285) node _T_287 = or(UInt<1>(0h0), _T_286) node _T_288 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<14>(0h2000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<13>(0h1000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<18>(0h2f000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<13>(0h1000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<17>(0h10000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<27>(0h4000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<29>(0h10000000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = or(_T_292, _T_297) node _T_339 = or(_T_338, _T_302) node _T_340 = or(_T_339, _T_307) node _T_341 = or(_T_340, _T_312) node _T_342 = or(_T_341, _T_317) node _T_343 = or(_T_342, _T_322) node _T_344 = or(_T_343, _T_327) node _T_345 = or(_T_344, _T_332) node _T_346 = or(_T_345, _T_337) node _T_347 = and(_T_287, _T_346) node _T_348 = or(UInt<1>(0h0), _T_347) node _T_349 = and(_WIRE_3, _T_348) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_349, UInt<1>(0h1), "") : assert_11 node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(source_ok, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_356 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_356, UInt<1>(0h1), "") : assert_13 node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(is_aligned, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_363 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_363, UInt<1>(0h1), "") : assert_15 node _T_367 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_367, UInt<1>(0h1), "") : assert_16 node _T_371 = not(io.in.a.bits.mask) node _T_372 = eq(_T_371, UInt<1>(0h0)) node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_T_372, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_372, UInt<1>(0h1), "") : assert_17 node _T_376 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_377 = asUInt(reset) node _T_378 = eq(_T_377, UInt<1>(0h0)) when _T_378 : node _T_379 = eq(_T_376, UInt<1>(0h0)) when _T_379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_376, UInt<1>(0h1), "") : assert_18 node _T_380 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_380 : node _T_381 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_382 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_383 = and(_T_381, _T_382) node _T_384 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_385 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_386 = or(_T_384, _T_385) node _T_387 = and(_T_383, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(_T_388, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_388, UInt<1>(0h1), "") : assert_19 node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = or(UInt<1>(0h0), _T_394) node _T_396 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_397 = cvt(_T_396) node _T_398 = and(_T_397, asSInt(UInt<13>(0h1000))) node _T_399 = asSInt(_T_398) node _T_400 = eq(_T_399, asSInt(UInt<1>(0h0))) node _T_401 = and(_T_395, _T_400) node _T_402 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_403 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_404 = and(_T_402, _T_403) node _T_405 = or(UInt<1>(0h0), _T_404) node _T_406 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_407 = cvt(_T_406) node _T_408 = and(_T_407, asSInt(UInt<14>(0h2000))) node _T_409 = asSInt(_T_408) node _T_410 = eq(_T_409, asSInt(UInt<1>(0h0))) node _T_411 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<17>(0h10000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_417 = cvt(_T_416) node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000))) node _T_419 = asSInt(_T_418) node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0))) node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_422 = cvt(_T_421) node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000))) node _T_424 = asSInt(_T_423) node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0))) node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<17>(0h10000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<27>(0h4000000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<29>(0h10000000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = or(_T_410, _T_415) node _T_452 = or(_T_451, _T_420) node _T_453 = or(_T_452, _T_425) node _T_454 = or(_T_453, _T_430) node _T_455 = or(_T_454, _T_435) node _T_456 = or(_T_455, _T_440) node _T_457 = or(_T_456, _T_445) node _T_458 = or(_T_457, _T_450) node _T_459 = and(_T_405, _T_458) node _T_460 = or(UInt<1>(0h0), _T_401) node _T_461 = or(_T_460, _T_459) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_461, UInt<1>(0h1), "") : assert_20 node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(source_ok, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(is_aligned, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_471 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_471, UInt<1>(0h1), "") : assert_23 node _T_475 = eq(io.in.a.bits.mask, mask) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_475, UInt<1>(0h1), "") : assert_24 node _T_479 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_479, UInt<1>(0h1), "") : assert_25 node _T_483 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_483 : node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_485 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_486 = and(_T_484, _T_485) node _T_487 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_488 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_489 = or(_T_487, _T_488) node _T_490 = and(_T_486, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_493 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_494 = and(_T_492, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<13>(0h1000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = and(_T_495, _T_500) node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_504 = and(_T_502, _T_503) node _T_505 = or(UInt<1>(0h0), _T_504) node _T_506 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<14>(0h2000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<18>(0h2f000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<27>(0h4000000))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<13>(0h1000))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_542 = cvt(_T_541) node _T_543 = and(_T_542, asSInt(UInt<29>(0h10000000))) node _T_544 = asSInt(_T_543) node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0))) node _T_546 = or(_T_510, _T_515) node _T_547 = or(_T_546, _T_520) node _T_548 = or(_T_547, _T_525) node _T_549 = or(_T_548, _T_530) node _T_550 = or(_T_549, _T_535) node _T_551 = or(_T_550, _T_540) node _T_552 = or(_T_551, _T_545) node _T_553 = and(_T_505, _T_552) node _T_554 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_555 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_556 = cvt(_T_555) node _T_557 = and(_T_556, asSInt(UInt<17>(0h10000))) node _T_558 = asSInt(_T_557) node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0))) node _T_560 = and(_T_554, _T_559) node _T_561 = or(UInt<1>(0h0), _T_501) node _T_562 = or(_T_561, _T_553) node _T_563 = or(_T_562, _T_560) node _T_564 = and(_T_491, _T_563) node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(_T_564, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_564, UInt<1>(0h1), "") : assert_26 node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(source_ok, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(is_aligned, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_574 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_574, UInt<1>(0h1), "") : assert_29 node _T_578 = eq(io.in.a.bits.mask, mask) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_578, UInt<1>(0h1), "") : assert_30 node _T_582 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_582 : node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_584 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_585 = and(_T_583, _T_584) node _T_586 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_587 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(_T_585, _T_588) node _T_590 = or(UInt<1>(0h0), _T_589) node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_593 = and(_T_591, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_596 = cvt(_T_595) node _T_597 = and(_T_596, asSInt(UInt<13>(0h1000))) node _T_598 = asSInt(_T_597) node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0))) node _T_600 = and(_T_594, _T_599) node _T_601 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_602 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_603 = and(_T_601, _T_602) node _T_604 = or(UInt<1>(0h0), _T_603) node _T_605 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_606 = cvt(_T_605) node _T_607 = and(_T_606, asSInt(UInt<14>(0h2000))) node _T_608 = asSInt(_T_607) node _T_609 = eq(_T_608, asSInt(UInt<1>(0h0))) node _T_610 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_611 = cvt(_T_610) node _T_612 = and(_T_611, asSInt(UInt<18>(0h2f000))) node _T_613 = asSInt(_T_612) node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0))) node _T_615 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<17>(0h10000))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_626 = cvt(_T_625) node _T_627 = and(_T_626, asSInt(UInt<17>(0h10000))) node _T_628 = asSInt(_T_627) node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0))) node _T_630 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<27>(0h4000000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<29>(0h10000000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = or(_T_609, _T_614) node _T_646 = or(_T_645, _T_619) node _T_647 = or(_T_646, _T_624) node _T_648 = or(_T_647, _T_629) node _T_649 = or(_T_648, _T_634) node _T_650 = or(_T_649, _T_639) node _T_651 = or(_T_650, _T_644) node _T_652 = and(_T_604, _T_651) node _T_653 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_654 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_655 = cvt(_T_654) node _T_656 = and(_T_655, asSInt(UInt<17>(0h10000))) node _T_657 = asSInt(_T_656) node _T_658 = eq(_T_657, asSInt(UInt<1>(0h0))) node _T_659 = and(_T_653, _T_658) node _T_660 = or(UInt<1>(0h0), _T_600) node _T_661 = or(_T_660, _T_652) node _T_662 = or(_T_661, _T_659) node _T_663 = and(_T_590, _T_662) node _T_664 = asUInt(reset) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(_T_663, UInt<1>(0h0)) when _T_666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_663, UInt<1>(0h1), "") : assert_31 node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(source_ok, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(is_aligned, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_673 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_673, UInt<1>(0h1), "") : assert_34 node _T_677 = not(mask) node _T_678 = and(io.in.a.bits.mask, _T_677) node _T_679 = eq(_T_678, UInt<1>(0h0)) node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(_T_679, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_679, UInt<1>(0h1), "") : assert_35 node _T_683 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_683 : node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_685 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_686 = and(_T_684, _T_685) node _T_687 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_688 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_689 = or(_T_687, _T_688) node _T_690 = and(_T_686, _T_689) node _T_691 = or(UInt<1>(0h0), _T_690) node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_693 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _T_695 = or(UInt<1>(0h0), _T_694) node _T_696 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<14>(0h2000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_702 = cvt(_T_701) node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000))) node _T_704 = asSInt(_T_703) node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0))) node _T_706 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<18>(0h2f000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<17>(0h10000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<13>(0h1000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<17>(0h10000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<27>(0h4000000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<29>(0h10000000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = or(_T_700, _T_705) node _T_742 = or(_T_741, _T_710) node _T_743 = or(_T_742, _T_715) node _T_744 = or(_T_743, _T_720) node _T_745 = or(_T_744, _T_725) node _T_746 = or(_T_745, _T_730) node _T_747 = or(_T_746, _T_735) node _T_748 = or(_T_747, _T_740) node _T_749 = and(_T_695, _T_748) node _T_750 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_751 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = and(_T_750, _T_755) node _T_757 = or(UInt<1>(0h0), _T_749) node _T_758 = or(_T_757, _T_756) node _T_759 = and(_T_691, _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_759, UInt<1>(0h1), "") : assert_36 node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(source_ok, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(is_aligned, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_769 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_769, UInt<1>(0h1), "") : assert_39 node _T_773 = eq(io.in.a.bits.mask, mask) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_773, UInt<1>(0h1), "") : assert_40 node _T_777 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_777 : node _T_778 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_779 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_780 = and(_T_778, _T_779) node _T_781 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_782 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_783 = or(_T_781, _T_782) node _T_784 = and(_T_780, _T_783) node _T_785 = or(UInt<1>(0h0), _T_784) node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_787 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<14>(0h2000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<13>(0h1000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<18>(0h2f000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<17>(0h10000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<17>(0h10000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<27>(0h4000000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<29>(0h10000000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = or(_T_794, _T_799) node _T_836 = or(_T_835, _T_804) node _T_837 = or(_T_836, _T_809) node _T_838 = or(_T_837, _T_814) node _T_839 = or(_T_838, _T_819) node _T_840 = or(_T_839, _T_824) node _T_841 = or(_T_840, _T_829) node _T_842 = or(_T_841, _T_834) node _T_843 = and(_T_789, _T_842) node _T_844 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_845 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<17>(0h10000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = and(_T_844, _T_849) node _T_851 = or(UInt<1>(0h0), _T_843) node _T_852 = or(_T_851, _T_850) node _T_853 = and(_T_785, _T_852) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_853, UInt<1>(0h1), "") : assert_41 node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(source_ok, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(is_aligned, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_863 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_863, UInt<1>(0h1), "") : assert_44 node _T_867 = eq(io.in.a.bits.mask, mask) node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(_T_867, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_867, UInt<1>(0h1), "") : assert_45 node _T_871 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_871 : node _T_872 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_873 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_874 = and(_T_872, _T_873) node _T_875 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_876 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_877 = or(_T_875, _T_876) node _T_878 = and(_T_874, _T_877) node _T_879 = or(UInt<1>(0h0), _T_878) node _T_880 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_881 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_882 = and(_T_880, _T_881) node _T_883 = or(UInt<1>(0h0), _T_882) node _T_884 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = and(_T_883, _T_888) node _T_890 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_891 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<14>(0h2000))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<17>(0h10000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<18>(0h2f000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<27>(0h4000000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<13>(0h1000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = or(_T_895, _T_900) node _T_927 = or(_T_926, _T_905) node _T_928 = or(_T_927, _T_910) node _T_929 = or(_T_928, _T_915) node _T_930 = or(_T_929, _T_920) node _T_931 = or(_T_930, _T_925) node _T_932 = and(_T_890, _T_931) node _T_933 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_934 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_935 = and(_T_933, _T_934) node _T_936 = or(UInt<1>(0h0), _T_935) node _T_937 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<29>(0h10000000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = or(_T_941, _T_946) node _T_948 = and(_T_936, _T_947) node _T_949 = or(UInt<1>(0h0), _T_889) node _T_950 = or(_T_949, _T_932) node _T_951 = or(_T_950, _T_948) node _T_952 = and(_T_879, _T_951) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_952, UInt<1>(0h1), "") : assert_46 node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(source_ok, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(is_aligned, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_962 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_962, UInt<1>(0h1), "") : assert_49 node _T_966 = eq(io.in.a.bits.mask, mask) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_966, UInt<1>(0h1), "") : assert_50 node _T_970 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_970, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_974 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_974, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_978 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_978 : node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(source_ok_1, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_982 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_982, UInt<1>(0h1), "") : assert_54 node _T_986 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_986, UInt<1>(0h1), "") : assert_55 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_990, UInt<1>(0h1), "") : assert_56 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_994, UInt<1>(0h1), "") : assert_57 node _T_998 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_998 : node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(source_ok_1, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(sink_ok, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_60 node _T_1009 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_61 node _T_1013 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_62 node _T_1017 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_63 node _T_1021 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1022 = or(UInt<1>(0h1), _T_1021) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_64 node _T_1026 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1026 : node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(source_ok_1, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(sink_ok, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1033 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_67 node _T_1037 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_68 node _T_1041 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_69 node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1046 = or(_T_1045, io.in.d.bits.corrupt) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_70 node _T_1050 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1051 = or(UInt<1>(0h1), _T_1050) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_71 node _T_1055 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1055 : node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(source_ok_1, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1059 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_73 node _T_1063 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_74 node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1068 = or(UInt<1>(0h1), _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_75 node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1072 : node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(source_ok_1, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_77 node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.d.bits.corrupt) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_78 node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1086 = or(UInt<1>(0h1), _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_79 node _T_1090 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1090 : node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok_1, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_81 node _T_1098 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_82 node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1103 = or(UInt<1>(0h1), _T_1102) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1107 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_84 node _T_1111 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) node _T_1113 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1114 = cvt(_T_1113) node _T_1115 = and(_T_1114, asSInt(UInt<1>(0h0))) node _T_1116 = asSInt(_T_1115) node _T_1117 = eq(_T_1116, asSInt(UInt<1>(0h0))) node _T_1118 = or(_T_1112, _T_1117) node _T_1119 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) node _T_1121 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = or(_T_1120, _T_1125) node _T_1127 = and(_T_1118, _T_1126) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3) wire _legal_source_WIRE_1 : UInt<1> connect _legal_source_WIRE_1, _legal_source_T_4 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1131 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1131 : node _T_1132 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1133 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1132 connect _WIRE_4[1], _T_1133 node _T_1134 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1135 = mux(_WIRE_4[0], _T_1134, UInt<1>(0h0)) node _T_1136 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1137 = or(_T_1135, _T_1136) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1137 node _T_1138 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1139 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1140 = and(_T_1138, _T_1139) node _T_1141 = or(UInt<1>(0h0), _T_1140) node _T_1142 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<14>(0h2000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1148 = cvt(_T_1147) node _T_1149 = and(_T_1148, asSInt(UInt<13>(0h1000))) node _T_1150 = asSInt(_T_1149) node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0))) node _T_1152 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<17>(0h10000))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1158 = cvt(_T_1157) node _T_1159 = and(_T_1158, asSInt(UInt<18>(0h2f000))) node _T_1160 = asSInt(_T_1159) node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0))) node _T_1162 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1163 = cvt(_T_1162) node _T_1164 = and(_T_1163, asSInt(UInt<17>(0h10000))) node _T_1165 = asSInt(_T_1164) node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0))) node _T_1167 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1168 = cvt(_T_1167) node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000))) node _T_1170 = asSInt(_T_1169) node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0))) node _T_1172 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1173 = cvt(_T_1172) node _T_1174 = and(_T_1173, asSInt(UInt<17>(0h10000))) node _T_1175 = asSInt(_T_1174) node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0))) node _T_1177 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1178 = cvt(_T_1177) node _T_1179 = and(_T_1178, asSInt(UInt<27>(0h4000000))) node _T_1180 = asSInt(_T_1179) node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1183 = cvt(_T_1182) node _T_1184 = and(_T_1183, asSInt(UInt<13>(0h1000))) node _T_1185 = asSInt(_T_1184) node _T_1186 = eq(_T_1185, asSInt(UInt<1>(0h0))) node _T_1187 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1188 = cvt(_T_1187) node _T_1189 = and(_T_1188, asSInt(UInt<29>(0h10000000))) node _T_1190 = asSInt(_T_1189) node _T_1191 = eq(_T_1190, asSInt(UInt<1>(0h0))) node _T_1192 = or(_T_1146, _T_1151) node _T_1193 = or(_T_1192, _T_1156) node _T_1194 = or(_T_1193, _T_1161) node _T_1195 = or(_T_1194, _T_1166) node _T_1196 = or(_T_1195, _T_1171) node _T_1197 = or(_T_1196, _T_1176) node _T_1198 = or(_T_1197, _T_1181) node _T_1199 = or(_T_1198, _T_1186) node _T_1200 = or(_T_1199, _T_1191) node _T_1201 = and(_T_1141, _T_1200) node _T_1202 = or(UInt<1>(0h0), _T_1201) node _T_1203 = and(_WIRE_5, _T_1202) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86 node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(address_ok, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(legal_source, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1216 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90 node _T_1220 = eq(io.in.b.bits.mask, mask_1) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91 node _T_1224 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92 node _T_1228 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1228 : node _T_1229 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1230 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1231 = and(_T_1229, _T_1230) node _T_1232 = or(UInt<1>(0h0), _T_1231) node _T_1233 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1234 = cvt(_T_1233) node _T_1235 = and(_T_1234, asSInt(UInt<14>(0h2000))) node _T_1236 = asSInt(_T_1235) node _T_1237 = eq(_T_1236, asSInt(UInt<1>(0h0))) node _T_1238 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<13>(0h1000))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<17>(0h10000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<18>(0h2f000))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<17>(0h10000))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<13>(0h1000))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<17>(0h10000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1269 = cvt(_T_1268) node _T_1270 = and(_T_1269, asSInt(UInt<27>(0h4000000))) node _T_1271 = asSInt(_T_1270) node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0))) node _T_1273 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1274 = cvt(_T_1273) node _T_1275 = and(_T_1274, asSInt(UInt<13>(0h1000))) node _T_1276 = asSInt(_T_1275) node _T_1277 = eq(_T_1276, asSInt(UInt<1>(0h0))) node _T_1278 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<29>(0h10000000))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = or(_T_1237, _T_1242) node _T_1284 = or(_T_1283, _T_1247) node _T_1285 = or(_T_1284, _T_1252) node _T_1286 = or(_T_1285, _T_1257) node _T_1287 = or(_T_1286, _T_1262) node _T_1288 = or(_T_1287, _T_1267) node _T_1289 = or(_T_1288, _T_1272) node _T_1290 = or(_T_1289, _T_1277) node _T_1291 = or(_T_1290, _T_1282) node _T_1292 = and(_T_1232, _T_1291) node _T_1293 = or(UInt<1>(0h0), _T_1292) node _T_1294 = and(UInt<1>(0h0), _T_1293) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_93 node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(address_ok, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(legal_source, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1307 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(_T_1307, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1307, UInt<1>(0h1), "") : assert_97 node _T_1311 = eq(io.in.b.bits.mask, mask_1) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_98 node _T_1315 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_99 node _T_1319 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1319 : node _T_1320 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1321 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = or(UInt<1>(0h0), _T_1322) node _T_1324 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<14>(0h2000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1330 = cvt(_T_1329) node _T_1331 = and(_T_1330, asSInt(UInt<13>(0h1000))) node _T_1332 = asSInt(_T_1331) node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0))) node _T_1334 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1335 = cvt(_T_1334) node _T_1336 = and(_T_1335, asSInt(UInt<17>(0h10000))) node _T_1337 = asSInt(_T_1336) node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0))) node _T_1339 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1340 = cvt(_T_1339) node _T_1341 = and(_T_1340, asSInt(UInt<18>(0h2f000))) node _T_1342 = asSInt(_T_1341) node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0))) node _T_1344 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1345 = cvt(_T_1344) node _T_1346 = and(_T_1345, asSInt(UInt<17>(0h10000))) node _T_1347 = asSInt(_T_1346) node _T_1348 = eq(_T_1347, asSInt(UInt<1>(0h0))) node _T_1349 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1350 = cvt(_T_1349) node _T_1351 = and(_T_1350, asSInt(UInt<13>(0h1000))) node _T_1352 = asSInt(_T_1351) node _T_1353 = eq(_T_1352, asSInt(UInt<1>(0h0))) node _T_1354 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1355 = cvt(_T_1354) node _T_1356 = and(_T_1355, asSInt(UInt<17>(0h10000))) node _T_1357 = asSInt(_T_1356) node _T_1358 = eq(_T_1357, asSInt(UInt<1>(0h0))) node _T_1359 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1360 = cvt(_T_1359) node _T_1361 = and(_T_1360, asSInt(UInt<27>(0h4000000))) node _T_1362 = asSInt(_T_1361) node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0))) node _T_1364 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1365 = cvt(_T_1364) node _T_1366 = and(_T_1365, asSInt(UInt<13>(0h1000))) node _T_1367 = asSInt(_T_1366) node _T_1368 = eq(_T_1367, asSInt(UInt<1>(0h0))) node _T_1369 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1370 = cvt(_T_1369) node _T_1371 = and(_T_1370, asSInt(UInt<29>(0h10000000))) node _T_1372 = asSInt(_T_1371) node _T_1373 = eq(_T_1372, asSInt(UInt<1>(0h0))) node _T_1374 = or(_T_1328, _T_1333) node _T_1375 = or(_T_1374, _T_1338) node _T_1376 = or(_T_1375, _T_1343) node _T_1377 = or(_T_1376, _T_1348) node _T_1378 = or(_T_1377, _T_1353) node _T_1379 = or(_T_1378, _T_1358) node _T_1380 = or(_T_1379, _T_1363) node _T_1381 = or(_T_1380, _T_1368) node _T_1382 = or(_T_1381, _T_1373) node _T_1383 = and(_T_1323, _T_1382) node _T_1384 = or(UInt<1>(0h0), _T_1383) node _T_1385 = and(UInt<1>(0h0), _T_1384) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_100 node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(address_ok, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1392 = asUInt(reset) node _T_1393 = eq(_T_1392, UInt<1>(0h0)) when _T_1393 : node _T_1394 = eq(legal_source, UInt<1>(0h0)) when _T_1394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1398 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_104 node _T_1402 = eq(io.in.b.bits.mask, mask_1) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_105 node _T_1406 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1406 : node _T_1407 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1408 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1409 = and(_T_1407, _T_1408) node _T_1410 = or(UInt<1>(0h0), _T_1409) node _T_1411 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1412 = cvt(_T_1411) node _T_1413 = and(_T_1412, asSInt(UInt<14>(0h2000))) node _T_1414 = asSInt(_T_1413) node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0))) node _T_1416 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<17>(0h10000))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1427 = cvt(_T_1426) node _T_1428 = and(_T_1427, asSInt(UInt<18>(0h2f000))) node _T_1429 = asSInt(_T_1428) node _T_1430 = eq(_T_1429, asSInt(UInt<1>(0h0))) node _T_1431 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1432 = cvt(_T_1431) node _T_1433 = and(_T_1432, asSInt(UInt<17>(0h10000))) node _T_1434 = asSInt(_T_1433) node _T_1435 = eq(_T_1434, asSInt(UInt<1>(0h0))) node _T_1436 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1437 = cvt(_T_1436) node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000))) node _T_1439 = asSInt(_T_1438) node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0))) node _T_1441 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1442 = cvt(_T_1441) node _T_1443 = and(_T_1442, asSInt(UInt<17>(0h10000))) node _T_1444 = asSInt(_T_1443) node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0))) node _T_1446 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1447 = cvt(_T_1446) node _T_1448 = and(_T_1447, asSInt(UInt<27>(0h4000000))) node _T_1449 = asSInt(_T_1448) node _T_1450 = eq(_T_1449, asSInt(UInt<1>(0h0))) node _T_1451 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1452 = cvt(_T_1451) node _T_1453 = and(_T_1452, asSInt(UInt<13>(0h1000))) node _T_1454 = asSInt(_T_1453) node _T_1455 = eq(_T_1454, asSInt(UInt<1>(0h0))) node _T_1456 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<29>(0h10000000))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = or(_T_1415, _T_1420) node _T_1462 = or(_T_1461, _T_1425) node _T_1463 = or(_T_1462, _T_1430) node _T_1464 = or(_T_1463, _T_1435) node _T_1465 = or(_T_1464, _T_1440) node _T_1466 = or(_T_1465, _T_1445) node _T_1467 = or(_T_1466, _T_1450) node _T_1468 = or(_T_1467, _T_1455) node _T_1469 = or(_T_1468, _T_1460) node _T_1470 = and(_T_1410, _T_1469) node _T_1471 = or(UInt<1>(0h0), _T_1470) node _T_1472 = and(UInt<1>(0h0), _T_1471) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_106 node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(address_ok, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(legal_source, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1485 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_110 node _T_1489 = not(mask_1) node _T_1490 = and(io.in.b.bits.mask, _T_1489) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_111 node _T_1495 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1495 : node _T_1496 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1497 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = or(UInt<1>(0h0), _T_1498) node _T_1500 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<14>(0h2000))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1506 = cvt(_T_1505) node _T_1507 = and(_T_1506, asSInt(UInt<13>(0h1000))) node _T_1508 = asSInt(_T_1507) node _T_1509 = eq(_T_1508, asSInt(UInt<1>(0h0))) node _T_1510 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1511 = cvt(_T_1510) node _T_1512 = and(_T_1511, asSInt(UInt<17>(0h10000))) node _T_1513 = asSInt(_T_1512) node _T_1514 = eq(_T_1513, asSInt(UInt<1>(0h0))) node _T_1515 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1516 = cvt(_T_1515) node _T_1517 = and(_T_1516, asSInt(UInt<18>(0h2f000))) node _T_1518 = asSInt(_T_1517) node _T_1519 = eq(_T_1518, asSInt(UInt<1>(0h0))) node _T_1520 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1521 = cvt(_T_1520) node _T_1522 = and(_T_1521, asSInt(UInt<17>(0h10000))) node _T_1523 = asSInt(_T_1522) node _T_1524 = eq(_T_1523, asSInt(UInt<1>(0h0))) node _T_1525 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1526 = cvt(_T_1525) node _T_1527 = and(_T_1526, asSInt(UInt<13>(0h1000))) node _T_1528 = asSInt(_T_1527) node _T_1529 = eq(_T_1528, asSInt(UInt<1>(0h0))) node _T_1530 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1531 = cvt(_T_1530) node _T_1532 = and(_T_1531, asSInt(UInt<17>(0h10000))) node _T_1533 = asSInt(_T_1532) node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0))) node _T_1535 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1536 = cvt(_T_1535) node _T_1537 = and(_T_1536, asSInt(UInt<27>(0h4000000))) node _T_1538 = asSInt(_T_1537) node _T_1539 = eq(_T_1538, asSInt(UInt<1>(0h0))) node _T_1540 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1541 = cvt(_T_1540) node _T_1542 = and(_T_1541, asSInt(UInt<13>(0h1000))) node _T_1543 = asSInt(_T_1542) node _T_1544 = eq(_T_1543, asSInt(UInt<1>(0h0))) node _T_1545 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1546 = cvt(_T_1545) node _T_1547 = and(_T_1546, asSInt(UInt<29>(0h10000000))) node _T_1548 = asSInt(_T_1547) node _T_1549 = eq(_T_1548, asSInt(UInt<1>(0h0))) node _T_1550 = or(_T_1504, _T_1509) node _T_1551 = or(_T_1550, _T_1514) node _T_1552 = or(_T_1551, _T_1519) node _T_1553 = or(_T_1552, _T_1524) node _T_1554 = or(_T_1553, _T_1529) node _T_1555 = or(_T_1554, _T_1534) node _T_1556 = or(_T_1555, _T_1539) node _T_1557 = or(_T_1556, _T_1544) node _T_1558 = or(_T_1557, _T_1549) node _T_1559 = and(_T_1499, _T_1558) node _T_1560 = or(UInt<1>(0h0), _T_1559) node _T_1561 = and(UInt<1>(0h0), _T_1560) node _T_1562 = asUInt(reset) node _T_1563 = eq(_T_1562, UInt<1>(0h0)) when _T_1563 : node _T_1564 = eq(_T_1561, UInt<1>(0h0)) when _T_1564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1561, UInt<1>(0h1), "") : assert_112 node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(address_ok, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(legal_source, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1571 = asUInt(reset) node _T_1572 = eq(_T_1571, UInt<1>(0h0)) when _T_1572 : node _T_1573 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1574 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1575 = asUInt(reset) node _T_1576 = eq(_T_1575, UInt<1>(0h0)) when _T_1576 : node _T_1577 = eq(_T_1574, UInt<1>(0h0)) when _T_1577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1574, UInt<1>(0h1), "") : assert_116 node _T_1578 = eq(io.in.b.bits.mask, mask_1) node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(_T_1578, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1578, UInt<1>(0h1), "") : assert_117 node _T_1582 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1582 : node _T_1583 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1584 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1585 = and(_T_1583, _T_1584) node _T_1586 = or(UInt<1>(0h0), _T_1585) node _T_1587 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1588 = cvt(_T_1587) node _T_1589 = and(_T_1588, asSInt(UInt<14>(0h2000))) node _T_1590 = asSInt(_T_1589) node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0))) node _T_1592 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1593 = cvt(_T_1592) node _T_1594 = and(_T_1593, asSInt(UInt<13>(0h1000))) node _T_1595 = asSInt(_T_1594) node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1598 = cvt(_T_1597) node _T_1599 = and(_T_1598, asSInt(UInt<17>(0h10000))) node _T_1600 = asSInt(_T_1599) node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0))) node _T_1602 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<18>(0h2f000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<17>(0h10000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<27>(0h4000000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<13>(0h1000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<29>(0h10000000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = or(_T_1591, _T_1596) node _T_1638 = or(_T_1637, _T_1601) node _T_1639 = or(_T_1638, _T_1606) node _T_1640 = or(_T_1639, _T_1611) node _T_1641 = or(_T_1640, _T_1616) node _T_1642 = or(_T_1641, _T_1621) node _T_1643 = or(_T_1642, _T_1626) node _T_1644 = or(_T_1643, _T_1631) node _T_1645 = or(_T_1644, _T_1636) node _T_1646 = and(_T_1586, _T_1645) node _T_1647 = or(UInt<1>(0h0), _T_1646) node _T_1648 = and(UInt<1>(0h0), _T_1647) node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(_T_1648, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1648, UInt<1>(0h1), "") : assert_118 node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(address_ok, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(legal_source, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1658 = asUInt(reset) node _T_1659 = eq(_T_1658, UInt<1>(0h0)) when _T_1659 : node _T_1660 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1661 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(_T_1661, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1661, UInt<1>(0h1), "") : assert_122 node _T_1665 = eq(io.in.b.bits.mask, mask_1) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_123 node _T_1669 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1669 : node _T_1670 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1671 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1672 = and(_T_1670, _T_1671) node _T_1673 = or(UInt<1>(0h0), _T_1672) node _T_1674 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1675 = cvt(_T_1674) node _T_1676 = and(_T_1675, asSInt(UInt<14>(0h2000))) node _T_1677 = asSInt(_T_1676) node _T_1678 = eq(_T_1677, asSInt(UInt<1>(0h0))) node _T_1679 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1680 = cvt(_T_1679) node _T_1681 = and(_T_1680, asSInt(UInt<13>(0h1000))) node _T_1682 = asSInt(_T_1681) node _T_1683 = eq(_T_1682, asSInt(UInt<1>(0h0))) node _T_1684 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1685 = cvt(_T_1684) node _T_1686 = and(_T_1685, asSInt(UInt<17>(0h10000))) node _T_1687 = asSInt(_T_1686) node _T_1688 = eq(_T_1687, asSInt(UInt<1>(0h0))) node _T_1689 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1690 = cvt(_T_1689) node _T_1691 = and(_T_1690, asSInt(UInt<18>(0h2f000))) node _T_1692 = asSInt(_T_1691) node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0))) node _T_1694 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1695 = cvt(_T_1694) node _T_1696 = and(_T_1695, asSInt(UInt<17>(0h10000))) node _T_1697 = asSInt(_T_1696) node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0))) node _T_1699 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1700 = cvt(_T_1699) node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000))) node _T_1702 = asSInt(_T_1701) node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0))) node _T_1704 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1705 = cvt(_T_1704) node _T_1706 = and(_T_1705, asSInt(UInt<17>(0h10000))) node _T_1707 = asSInt(_T_1706) node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0))) node _T_1709 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1710 = cvt(_T_1709) node _T_1711 = and(_T_1710, asSInt(UInt<27>(0h4000000))) node _T_1712 = asSInt(_T_1711) node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0))) node _T_1714 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1715 = cvt(_T_1714) node _T_1716 = and(_T_1715, asSInt(UInt<13>(0h1000))) node _T_1717 = asSInt(_T_1716) node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0))) node _T_1719 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1720 = cvt(_T_1719) node _T_1721 = and(_T_1720, asSInt(UInt<29>(0h10000000))) node _T_1722 = asSInt(_T_1721) node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0))) node _T_1724 = or(_T_1678, _T_1683) node _T_1725 = or(_T_1724, _T_1688) node _T_1726 = or(_T_1725, _T_1693) node _T_1727 = or(_T_1726, _T_1698) node _T_1728 = or(_T_1727, _T_1703) node _T_1729 = or(_T_1728, _T_1708) node _T_1730 = or(_T_1729, _T_1713) node _T_1731 = or(_T_1730, _T_1718) node _T_1732 = or(_T_1731, _T_1723) node _T_1733 = and(_T_1673, _T_1732) node _T_1734 = or(UInt<1>(0h0), _T_1733) node _T_1735 = and(UInt<1>(0h0), _T_1734) node _T_1736 = asUInt(reset) node _T_1737 = eq(_T_1736, UInt<1>(0h0)) when _T_1737 : node _T_1738 = eq(_T_1735, UInt<1>(0h0)) when _T_1738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1735, UInt<1>(0h1), "") : assert_124 node _T_1739 = asUInt(reset) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) when _T_1740 : node _T_1741 = eq(address_ok, UInt<1>(0h0)) when _T_1741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1742 = asUInt(reset) node _T_1743 = eq(_T_1742, UInt<1>(0h0)) when _T_1743 : node _T_1744 = eq(legal_source, UInt<1>(0h0)) when _T_1744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1745 = asUInt(reset) node _T_1746 = eq(_T_1745, UInt<1>(0h0)) when _T_1746 : node _T_1747 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1748 = eq(io.in.b.bits.mask, mask_1) node _T_1749 = asUInt(reset) node _T_1750 = eq(_T_1749, UInt<1>(0h0)) when _T_1750 : node _T_1751 = eq(_T_1748, UInt<1>(0h0)) when _T_1751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1748, UInt<1>(0h1), "") : assert_128 node _T_1752 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1756 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_130 node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_4 connect _source_ok_WIRE_2[1], _source_ok_T_5 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _T_1760 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1761, _T_1766) node _T_1768 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1771 = cvt(_T_1770) node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = asSInt(_T_1772) node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0))) node _T_1775 = or(_T_1769, _T_1774) node _T_1776 = and(_T_1767, _T_1775) node _T_1777 = asUInt(reset) node _T_1778 = eq(_T_1777, UInt<1>(0h0)) when _T_1778 : node _T_1779 = eq(_T_1776, UInt<1>(0h0)) when _T_1779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1776, UInt<1>(0h1), "") : assert_131 node _T_1780 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1780 : node _T_1781 = asUInt(reset) node _T_1782 = eq(_T_1781, UInt<1>(0h0)) when _T_1782 : node _T_1783 = eq(address_ok_1, UInt<1>(0h0)) when _T_1783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1784 = asUInt(reset) node _T_1785 = eq(_T_1784, UInt<1>(0h0)) when _T_1785 : node _T_1786 = eq(source_ok_2, UInt<1>(0h0)) when _T_1786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1787 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_134 node _T_1791 = asUInt(reset) node _T_1792 = eq(_T_1791, UInt<1>(0h0)) when _T_1792 : node _T_1793 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1794 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_136 node _T_1798 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_137 node _T_1802 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1802 : node _T_1803 = asUInt(reset) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) when _T_1804 : node _T_1805 = eq(address_ok_1, UInt<1>(0h0)) when _T_1805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1806 = asUInt(reset) node _T_1807 = eq(_T_1806, UInt<1>(0h0)) when _T_1807 : node _T_1808 = eq(source_ok_2, UInt<1>(0h0)) when _T_1808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1809 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(_T_1809, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1809, UInt<1>(0h1), "") : assert_140 node _T_1813 = asUInt(reset) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) when _T_1814 : node _T_1815 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1816 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1817 = asUInt(reset) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(_T_1816, UInt<1>(0h0)) when _T_1819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1816, UInt<1>(0h1), "") : assert_142 node _T_1820 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1820 : node _T_1821 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1822 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1825 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1826 = or(_T_1824, _T_1825) node _T_1827 = and(_T_1823, _T_1826) node _T_1828 = or(UInt<1>(0h0), _T_1827) node _T_1829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1830 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1831 = cvt(_T_1830) node _T_1832 = and(_T_1831, asSInt(UInt<14>(0h2000))) node _T_1833 = asSInt(_T_1832) node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1836 = cvt(_T_1835) node _T_1837 = and(_T_1836, asSInt(UInt<13>(0h1000))) node _T_1838 = asSInt(_T_1837) node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0))) node _T_1840 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<17>(0h10000))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1846 = cvt(_T_1845) node _T_1847 = and(_T_1846, asSInt(UInt<18>(0h2f000))) node _T_1848 = asSInt(_T_1847) node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0))) node _T_1850 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1851 = cvt(_T_1850) node _T_1852 = and(_T_1851, asSInt(UInt<17>(0h10000))) node _T_1853 = asSInt(_T_1852) node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0))) node _T_1855 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1856 = cvt(_T_1855) node _T_1857 = and(_T_1856, asSInt(UInt<13>(0h1000))) node _T_1858 = asSInt(_T_1857) node _T_1859 = eq(_T_1858, asSInt(UInt<1>(0h0))) node _T_1860 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1861 = cvt(_T_1860) node _T_1862 = and(_T_1861, asSInt(UInt<27>(0h4000000))) node _T_1863 = asSInt(_T_1862) node _T_1864 = eq(_T_1863, asSInt(UInt<1>(0h0))) node _T_1865 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1866 = cvt(_T_1865) node _T_1867 = and(_T_1866, asSInt(UInt<13>(0h1000))) node _T_1868 = asSInt(_T_1867) node _T_1869 = eq(_T_1868, asSInt(UInt<1>(0h0))) node _T_1870 = or(_T_1834, _T_1839) node _T_1871 = or(_T_1870, _T_1844) node _T_1872 = or(_T_1871, _T_1849) node _T_1873 = or(_T_1872, _T_1854) node _T_1874 = or(_T_1873, _T_1859) node _T_1875 = or(_T_1874, _T_1864) node _T_1876 = or(_T_1875, _T_1869) node _T_1877 = and(_T_1829, _T_1876) node _T_1878 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1879 = or(UInt<1>(0h0), _T_1878) node _T_1880 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1881 = cvt(_T_1880) node _T_1882 = and(_T_1881, asSInt(UInt<17>(0h10000))) node _T_1883 = asSInt(_T_1882) node _T_1884 = eq(_T_1883, asSInt(UInt<1>(0h0))) node _T_1885 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<29>(0h10000000))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = and(_T_1879, _T_1890) node _T_1892 = or(UInt<1>(0h0), _T_1877) node _T_1893 = or(_T_1892, _T_1891) node _T_1894 = and(_T_1828, _T_1893) node _T_1895 = asUInt(reset) node _T_1896 = eq(_T_1895, UInt<1>(0h0)) when _T_1896 : node _T_1897 = eq(_T_1894, UInt<1>(0h0)) when _T_1897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1894, UInt<1>(0h1), "") : assert_143 node _T_1898 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1899 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_1898 connect _WIRE_6[1], _T_1899 node _T_1900 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1901 = mux(_WIRE_6[0], _T_1900, UInt<1>(0h0)) node _T_1902 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1903 = or(_T_1901, _T_1902) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1903 node _T_1904 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1905 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1906 = and(_T_1904, _T_1905) node _T_1907 = or(UInt<1>(0h0), _T_1906) node _T_1908 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<14>(0h2000))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1914 = cvt(_T_1913) node _T_1915 = and(_T_1914, asSInt(UInt<13>(0h1000))) node _T_1916 = asSInt(_T_1915) node _T_1917 = eq(_T_1916, asSInt(UInt<1>(0h0))) node _T_1918 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1919 = cvt(_T_1918) node _T_1920 = and(_T_1919, asSInt(UInt<17>(0h10000))) node _T_1921 = asSInt(_T_1920) node _T_1922 = eq(_T_1921, asSInt(UInt<1>(0h0))) node _T_1923 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1924 = cvt(_T_1923) node _T_1925 = and(_T_1924, asSInt(UInt<18>(0h2f000))) node _T_1926 = asSInt(_T_1925) node _T_1927 = eq(_T_1926, asSInt(UInt<1>(0h0))) node _T_1928 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1929 = cvt(_T_1928) node _T_1930 = and(_T_1929, asSInt(UInt<17>(0h10000))) node _T_1931 = asSInt(_T_1930) node _T_1932 = eq(_T_1931, asSInt(UInt<1>(0h0))) node _T_1933 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1934 = cvt(_T_1933) node _T_1935 = and(_T_1934, asSInt(UInt<13>(0h1000))) node _T_1936 = asSInt(_T_1935) node _T_1937 = eq(_T_1936, asSInt(UInt<1>(0h0))) node _T_1938 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1939 = cvt(_T_1938) node _T_1940 = and(_T_1939, asSInt(UInt<17>(0h10000))) node _T_1941 = asSInt(_T_1940) node _T_1942 = eq(_T_1941, asSInt(UInt<1>(0h0))) node _T_1943 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1944 = cvt(_T_1943) node _T_1945 = and(_T_1944, asSInt(UInt<27>(0h4000000))) node _T_1946 = asSInt(_T_1945) node _T_1947 = eq(_T_1946, asSInt(UInt<1>(0h0))) node _T_1948 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1949 = cvt(_T_1948) node _T_1950 = and(_T_1949, asSInt(UInt<13>(0h1000))) node _T_1951 = asSInt(_T_1950) node _T_1952 = eq(_T_1951, asSInt(UInt<1>(0h0))) node _T_1953 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1954 = cvt(_T_1953) node _T_1955 = and(_T_1954, asSInt(UInt<29>(0h10000000))) node _T_1956 = asSInt(_T_1955) node _T_1957 = eq(_T_1956, asSInt(UInt<1>(0h0))) node _T_1958 = or(_T_1912, _T_1917) node _T_1959 = or(_T_1958, _T_1922) node _T_1960 = or(_T_1959, _T_1927) node _T_1961 = or(_T_1960, _T_1932) node _T_1962 = or(_T_1961, _T_1937) node _T_1963 = or(_T_1962, _T_1942) node _T_1964 = or(_T_1963, _T_1947) node _T_1965 = or(_T_1964, _T_1952) node _T_1966 = or(_T_1965, _T_1957) node _T_1967 = and(_T_1907, _T_1966) node _T_1968 = or(UInt<1>(0h0), _T_1967) node _T_1969 = and(_WIRE_7, _T_1968) node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(_T_1969, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1969, UInt<1>(0h1), "") : assert_144 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(source_ok_2, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1976 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_146 node _T_1980 = asUInt(reset) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) when _T_1981 : node _T_1982 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1983 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_148 node _T_1987 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(_T_1987, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1987, UInt<1>(0h1), "") : assert_149 node _T_1991 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1991 : node _T_1992 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1993 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1994 = and(_T_1992, _T_1993) node _T_1995 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1996 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1997 = or(_T_1995, _T_1996) node _T_1998 = and(_T_1994, _T_1997) node _T_1999 = or(UInt<1>(0h0), _T_1998) node _T_2000 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2001 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2002 = cvt(_T_2001) node _T_2003 = and(_T_2002, asSInt(UInt<14>(0h2000))) node _T_2004 = asSInt(_T_2003) node _T_2005 = eq(_T_2004, asSInt(UInt<1>(0h0))) node _T_2006 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2007 = cvt(_T_2006) node _T_2008 = and(_T_2007, asSInt(UInt<13>(0h1000))) node _T_2009 = asSInt(_T_2008) node _T_2010 = eq(_T_2009, asSInt(UInt<1>(0h0))) node _T_2011 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2012 = cvt(_T_2011) node _T_2013 = and(_T_2012, asSInt(UInt<17>(0h10000))) node _T_2014 = asSInt(_T_2013) node _T_2015 = eq(_T_2014, asSInt(UInt<1>(0h0))) node _T_2016 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2017 = cvt(_T_2016) node _T_2018 = and(_T_2017, asSInt(UInt<18>(0h2f000))) node _T_2019 = asSInt(_T_2018) node _T_2020 = eq(_T_2019, asSInt(UInt<1>(0h0))) node _T_2021 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2022 = cvt(_T_2021) node _T_2023 = and(_T_2022, asSInt(UInt<17>(0h10000))) node _T_2024 = asSInt(_T_2023) node _T_2025 = eq(_T_2024, asSInt(UInt<1>(0h0))) node _T_2026 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2027 = cvt(_T_2026) node _T_2028 = and(_T_2027, asSInt(UInt<13>(0h1000))) node _T_2029 = asSInt(_T_2028) node _T_2030 = eq(_T_2029, asSInt(UInt<1>(0h0))) node _T_2031 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2032 = cvt(_T_2031) node _T_2033 = and(_T_2032, asSInt(UInt<27>(0h4000000))) node _T_2034 = asSInt(_T_2033) node _T_2035 = eq(_T_2034, asSInt(UInt<1>(0h0))) node _T_2036 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2037 = cvt(_T_2036) node _T_2038 = and(_T_2037, asSInt(UInt<13>(0h1000))) node _T_2039 = asSInt(_T_2038) node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0))) node _T_2041 = or(_T_2005, _T_2010) node _T_2042 = or(_T_2041, _T_2015) node _T_2043 = or(_T_2042, _T_2020) node _T_2044 = or(_T_2043, _T_2025) node _T_2045 = or(_T_2044, _T_2030) node _T_2046 = or(_T_2045, _T_2035) node _T_2047 = or(_T_2046, _T_2040) node _T_2048 = and(_T_2000, _T_2047) node _T_2049 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2050 = or(UInt<1>(0h0), _T_2049) node _T_2051 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2052 = cvt(_T_2051) node _T_2053 = and(_T_2052, asSInt(UInt<17>(0h10000))) node _T_2054 = asSInt(_T_2053) node _T_2055 = eq(_T_2054, asSInt(UInt<1>(0h0))) node _T_2056 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2057 = cvt(_T_2056) node _T_2058 = and(_T_2057, asSInt(UInt<29>(0h10000000))) node _T_2059 = asSInt(_T_2058) node _T_2060 = eq(_T_2059, asSInt(UInt<1>(0h0))) node _T_2061 = or(_T_2055, _T_2060) node _T_2062 = and(_T_2050, _T_2061) node _T_2063 = or(UInt<1>(0h0), _T_2048) node _T_2064 = or(_T_2063, _T_2062) node _T_2065 = and(_T_1999, _T_2064) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_150 node _T_2069 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2070 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2069 connect _WIRE_8[1], _T_2070 node _T_2071 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2072 = mux(_WIRE_8[0], _T_2071, UInt<1>(0h0)) node _T_2073 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2074 = or(_T_2072, _T_2073) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2074 node _T_2075 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2076 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2077 = and(_T_2075, _T_2076) node _T_2078 = or(UInt<1>(0h0), _T_2077) node _T_2079 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2080 = cvt(_T_2079) node _T_2081 = and(_T_2080, asSInt(UInt<14>(0h2000))) node _T_2082 = asSInt(_T_2081) node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0))) node _T_2084 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2090 = cvt(_T_2089) node _T_2091 = and(_T_2090, asSInt(UInt<17>(0h10000))) node _T_2092 = asSInt(_T_2091) node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0))) node _T_2094 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<18>(0h2f000))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2100 = cvt(_T_2099) node _T_2101 = and(_T_2100, asSInt(UInt<17>(0h10000))) node _T_2102 = asSInt(_T_2101) node _T_2103 = eq(_T_2102, asSInt(UInt<1>(0h0))) node _T_2104 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2105 = cvt(_T_2104) node _T_2106 = and(_T_2105, asSInt(UInt<13>(0h1000))) node _T_2107 = asSInt(_T_2106) node _T_2108 = eq(_T_2107, asSInt(UInt<1>(0h0))) node _T_2109 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2110 = cvt(_T_2109) node _T_2111 = and(_T_2110, asSInt(UInt<17>(0h10000))) node _T_2112 = asSInt(_T_2111) node _T_2113 = eq(_T_2112, asSInt(UInt<1>(0h0))) node _T_2114 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2115 = cvt(_T_2114) node _T_2116 = and(_T_2115, asSInt(UInt<27>(0h4000000))) node _T_2117 = asSInt(_T_2116) node _T_2118 = eq(_T_2117, asSInt(UInt<1>(0h0))) node _T_2119 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2120 = cvt(_T_2119) node _T_2121 = and(_T_2120, asSInt(UInt<13>(0h1000))) node _T_2122 = asSInt(_T_2121) node _T_2123 = eq(_T_2122, asSInt(UInt<1>(0h0))) node _T_2124 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2125 = cvt(_T_2124) node _T_2126 = and(_T_2125, asSInt(UInt<29>(0h10000000))) node _T_2127 = asSInt(_T_2126) node _T_2128 = eq(_T_2127, asSInt(UInt<1>(0h0))) node _T_2129 = or(_T_2083, _T_2088) node _T_2130 = or(_T_2129, _T_2093) node _T_2131 = or(_T_2130, _T_2098) node _T_2132 = or(_T_2131, _T_2103) node _T_2133 = or(_T_2132, _T_2108) node _T_2134 = or(_T_2133, _T_2113) node _T_2135 = or(_T_2134, _T_2118) node _T_2136 = or(_T_2135, _T_2123) node _T_2137 = or(_T_2136, _T_2128) node _T_2138 = and(_T_2078, _T_2137) node _T_2139 = or(UInt<1>(0h0), _T_2138) node _T_2140 = and(_WIRE_9, _T_2139) node _T_2141 = asUInt(reset) node _T_2142 = eq(_T_2141, UInt<1>(0h0)) when _T_2142 : node _T_2143 = eq(_T_2140, UInt<1>(0h0)) when _T_2143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2140, UInt<1>(0h1), "") : assert_151 node _T_2144 = asUInt(reset) node _T_2145 = eq(_T_2144, UInt<1>(0h0)) when _T_2145 : node _T_2146 = eq(source_ok_2, UInt<1>(0h0)) when _T_2146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2147 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2148 = asUInt(reset) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) when _T_2149 : node _T_2150 = eq(_T_2147, UInt<1>(0h0)) when _T_2150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2147, UInt<1>(0h1), "") : assert_153 node _T_2151 = asUInt(reset) node _T_2152 = eq(_T_2151, UInt<1>(0h0)) when _T_2152 : node _T_2153 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2154 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2155 = asUInt(reset) node _T_2156 = eq(_T_2155, UInt<1>(0h0)) when _T_2156 : node _T_2157 = eq(_T_2154, UInt<1>(0h0)) when _T_2157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2154, UInt<1>(0h1), "") : assert_155 node _T_2158 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2158 : node _T_2159 = asUInt(reset) node _T_2160 = eq(_T_2159, UInt<1>(0h0)) when _T_2160 : node _T_2161 = eq(address_ok_1, UInt<1>(0h0)) when _T_2161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(source_ok_2, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2165 = asUInt(reset) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2168 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2169 = asUInt(reset) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) when _T_2170 : node _T_2171 = eq(_T_2168, UInt<1>(0h0)) when _T_2171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2168, UInt<1>(0h1), "") : assert_159 node _T_2172 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2173 = asUInt(reset) node _T_2174 = eq(_T_2173, UInt<1>(0h0)) when _T_2174 : node _T_2175 = eq(_T_2172, UInt<1>(0h0)) when _T_2175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2172, UInt<1>(0h1), "") : assert_160 node _T_2176 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2176 : node _T_2177 = asUInt(reset) node _T_2178 = eq(_T_2177, UInt<1>(0h0)) when _T_2178 : node _T_2179 = eq(address_ok_1, UInt<1>(0h0)) when _T_2179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(source_ok_2, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2183 = asUInt(reset) node _T_2184 = eq(_T_2183, UInt<1>(0h0)) when _T_2184 : node _T_2185 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2186 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2187 = asUInt(reset) node _T_2188 = eq(_T_2187, UInt<1>(0h0)) when _T_2188 : node _T_2189 = eq(_T_2186, UInt<1>(0h0)) when _T_2189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2186, UInt<1>(0h1), "") : assert_164 node _T_2190 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2190 : node _T_2191 = asUInt(reset) node _T_2192 = eq(_T_2191, UInt<1>(0h0)) when _T_2192 : node _T_2193 = eq(address_ok_1, UInt<1>(0h0)) when _T_2193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2194 = asUInt(reset) node _T_2195 = eq(_T_2194, UInt<1>(0h0)) when _T_2195 : node _T_2196 = eq(source_ok_2, UInt<1>(0h0)) when _T_2196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2197 = asUInt(reset) node _T_2198 = eq(_T_2197, UInt<1>(0h0)) when _T_2198 : node _T_2199 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2200 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2201 = asUInt(reset) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(_T_2200, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2200, UInt<1>(0h1), "") : assert_168 node _T_2204 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2205 = asUInt(reset) node _T_2206 = eq(_T_2205, UInt<1>(0h0)) when _T_2206 : node _T_2207 = eq(_T_2204, UInt<1>(0h0)) when _T_2207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2204, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2211 = eq(a_first, UInt<1>(0h0)) node _T_2212 = and(io.in.a.valid, _T_2211) when _T_2212 : node _T_2213 = eq(io.in.a.bits.opcode, opcode) node _T_2214 = asUInt(reset) node _T_2215 = eq(_T_2214, UInt<1>(0h0)) when _T_2215 : node _T_2216 = eq(_T_2213, UInt<1>(0h0)) when _T_2216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2213, UInt<1>(0h1), "") : assert_171 node _T_2217 = eq(io.in.a.bits.param, param) node _T_2218 = asUInt(reset) node _T_2219 = eq(_T_2218, UInt<1>(0h0)) when _T_2219 : node _T_2220 = eq(_T_2217, UInt<1>(0h0)) when _T_2220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2217, UInt<1>(0h1), "") : assert_172 node _T_2221 = eq(io.in.a.bits.size, size) node _T_2222 = asUInt(reset) node _T_2223 = eq(_T_2222, UInt<1>(0h0)) when _T_2223 : node _T_2224 = eq(_T_2221, UInt<1>(0h0)) when _T_2224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2221, UInt<1>(0h1), "") : assert_173 node _T_2225 = eq(io.in.a.bits.source, source) node _T_2226 = asUInt(reset) node _T_2227 = eq(_T_2226, UInt<1>(0h0)) when _T_2227 : node _T_2228 = eq(_T_2225, UInt<1>(0h0)) when _T_2228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2225, UInt<1>(0h1), "") : assert_174 node _T_2229 = eq(io.in.a.bits.address, address) node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : node _T_2232 = eq(_T_2229, UInt<1>(0h0)) when _T_2232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2229, UInt<1>(0h1), "") : assert_175 node _T_2233 = and(io.in.a.ready, io.in.a.valid) node _T_2234 = and(_T_2233, a_first) when _T_2234 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2235 = eq(d_first, UInt<1>(0h0)) node _T_2236 = and(io.in.d.valid, _T_2235) when _T_2236 : node _T_2237 = eq(io.in.d.bits.opcode, opcode_1) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_176 node _T_2241 = eq(io.in.d.bits.param, param_1) node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(_T_2241, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2241, UInt<1>(0h1), "") : assert_177 node _T_2245 = eq(io.in.d.bits.size, size_1) node _T_2246 = asUInt(reset) node _T_2247 = eq(_T_2246, UInt<1>(0h0)) when _T_2247 : node _T_2248 = eq(_T_2245, UInt<1>(0h0)) when _T_2248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2245, UInt<1>(0h1), "") : assert_178 node _T_2249 = eq(io.in.d.bits.source, source_1) node _T_2250 = asUInt(reset) node _T_2251 = eq(_T_2250, UInt<1>(0h0)) when _T_2251 : node _T_2252 = eq(_T_2249, UInt<1>(0h0)) when _T_2252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2249, UInt<1>(0h1), "") : assert_179 node _T_2253 = eq(io.in.d.bits.sink, sink) node _T_2254 = asUInt(reset) node _T_2255 = eq(_T_2254, UInt<1>(0h0)) when _T_2255 : node _T_2256 = eq(_T_2253, UInt<1>(0h0)) when _T_2256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2253, UInt<1>(0h1), "") : assert_180 node _T_2257 = eq(io.in.d.bits.denied, denied) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_181 node _T_2261 = and(io.in.d.ready, io.in.d.valid) node _T_2262 = and(_T_2261, d_first) when _T_2262 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2263 = eq(b_first, UInt<1>(0h0)) node _T_2264 = and(io.in.b.valid, _T_2263) when _T_2264 : node _T_2265 = eq(io.in.b.bits.opcode, opcode_2) node _T_2266 = asUInt(reset) node _T_2267 = eq(_T_2266, UInt<1>(0h0)) when _T_2267 : node _T_2268 = eq(_T_2265, UInt<1>(0h0)) when _T_2268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2265, UInt<1>(0h1), "") : assert_182 node _T_2269 = eq(io.in.b.bits.param, param_2) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(_T_2269, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2269, UInt<1>(0h1), "") : assert_183 node _T_2273 = eq(io.in.b.bits.size, size_2) node _T_2274 = asUInt(reset) node _T_2275 = eq(_T_2274, UInt<1>(0h0)) when _T_2275 : node _T_2276 = eq(_T_2273, UInt<1>(0h0)) when _T_2276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2273, UInt<1>(0h1), "") : assert_184 node _T_2277 = eq(io.in.b.bits.source, source_2) node _T_2278 = asUInt(reset) node _T_2279 = eq(_T_2278, UInt<1>(0h0)) when _T_2279 : node _T_2280 = eq(_T_2277, UInt<1>(0h0)) when _T_2280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2277, UInt<1>(0h1), "") : assert_185 node _T_2281 = eq(io.in.b.bits.address, address_1) node _T_2282 = asUInt(reset) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : node _T_2284 = eq(_T_2281, UInt<1>(0h0)) when _T_2284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2281, UInt<1>(0h1), "") : assert_186 node _T_2285 = and(io.in.b.ready, io.in.b.valid) node _T_2286 = and(_T_2285, b_first) when _T_2286 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2287 = eq(c_first, UInt<1>(0h0)) node _T_2288 = and(io.in.c.valid, _T_2287) when _T_2288 : node _T_2289 = eq(io.in.c.bits.opcode, opcode_3) node _T_2290 = asUInt(reset) node _T_2291 = eq(_T_2290, UInt<1>(0h0)) when _T_2291 : node _T_2292 = eq(_T_2289, UInt<1>(0h0)) when _T_2292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2289, UInt<1>(0h1), "") : assert_187 node _T_2293 = eq(io.in.c.bits.param, param_3) node _T_2294 = asUInt(reset) node _T_2295 = eq(_T_2294, UInt<1>(0h0)) when _T_2295 : node _T_2296 = eq(_T_2293, UInt<1>(0h0)) when _T_2296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2293, UInt<1>(0h1), "") : assert_188 node _T_2297 = eq(io.in.c.bits.size, size_3) node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : node _T_2300 = eq(_T_2297, UInt<1>(0h0)) when _T_2300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2297, UInt<1>(0h1), "") : assert_189 node _T_2301 = eq(io.in.c.bits.source, source_3) node _T_2302 = asUInt(reset) node _T_2303 = eq(_T_2302, UInt<1>(0h0)) when _T_2303 : node _T_2304 = eq(_T_2301, UInt<1>(0h0)) when _T_2304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2301, UInt<1>(0h1), "") : assert_190 node _T_2305 = eq(io.in.c.bits.address, address_2) node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : node _T_2308 = eq(_T_2305, UInt<1>(0h0)) when _T_2308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2305, UInt<1>(0h1), "") : assert_191 node _T_2309 = and(io.in.c.ready, io.in.c.valid) node _T_2310 = and(_T_2309, c_first) when _T_2310 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2311 = and(io.in.a.valid, a_first_1) node _T_2312 = and(_T_2311, UInt<1>(0h1)) when _T_2312 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2313 = and(io.in.a.ready, io.in.a.valid) node _T_2314 = and(_T_2313, a_first_1) node _T_2315 = and(_T_2314, UInt<1>(0h1)) when _T_2315 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2316 = dshr(inflight, io.in.a.bits.source) node _T_2317 = bits(_T_2316, 0, 0) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) node _T_2319 = asUInt(reset) node _T_2320 = eq(_T_2319, UInt<1>(0h0)) when _T_2320 : node _T_2321 = eq(_T_2318, UInt<1>(0h0)) when _T_2321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2318, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2322 = and(io.in.d.valid, d_first_1) node _T_2323 = and(_T_2322, UInt<1>(0h1)) node _T_2324 = eq(d_release_ack, UInt<1>(0h0)) node _T_2325 = and(_T_2323, _T_2324) when _T_2325 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2326 = and(io.in.d.ready, io.in.d.valid) node _T_2327 = and(_T_2326, d_first_1) node _T_2328 = and(_T_2327, UInt<1>(0h1)) node _T_2329 = eq(d_release_ack, UInt<1>(0h0)) node _T_2330 = and(_T_2328, _T_2329) when _T_2330 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2331 = and(io.in.d.valid, d_first_1) node _T_2332 = and(_T_2331, UInt<1>(0h1)) node _T_2333 = eq(d_release_ack, UInt<1>(0h0)) node _T_2334 = and(_T_2332, _T_2333) when _T_2334 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2335 = dshr(inflight, io.in.d.bits.source) node _T_2336 = bits(_T_2335, 0, 0) node _T_2337 = or(_T_2336, same_cycle_resp) node _T_2338 = asUInt(reset) node _T_2339 = eq(_T_2338, UInt<1>(0h0)) when _T_2339 : node _T_2340 = eq(_T_2337, UInt<1>(0h0)) when _T_2340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2337, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2341 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2342 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2343 = or(_T_2341, _T_2342) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_194 node _T_2347 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2348 = asUInt(reset) node _T_2349 = eq(_T_2348, UInt<1>(0h0)) when _T_2349 : node _T_2350 = eq(_T_2347, UInt<1>(0h0)) when _T_2350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2347, UInt<1>(0h1), "") : assert_195 else : node _T_2351 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2352 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2353 = or(_T_2351, _T_2352) node _T_2354 = asUInt(reset) node _T_2355 = eq(_T_2354, UInt<1>(0h0)) when _T_2355 : node _T_2356 = eq(_T_2353, UInt<1>(0h0)) when _T_2356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2353, UInt<1>(0h1), "") : assert_196 node _T_2357 = eq(io.in.d.bits.size, a_size_lookup) node _T_2358 = asUInt(reset) node _T_2359 = eq(_T_2358, UInt<1>(0h0)) when _T_2359 : node _T_2360 = eq(_T_2357, UInt<1>(0h0)) when _T_2360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2357, UInt<1>(0h1), "") : assert_197 node _T_2361 = and(io.in.d.valid, d_first_1) node _T_2362 = and(_T_2361, a_first_1) node _T_2363 = and(_T_2362, io.in.a.valid) node _T_2364 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2365 = and(_T_2363, _T_2364) node _T_2366 = eq(d_release_ack, UInt<1>(0h0)) node _T_2367 = and(_T_2365, _T_2366) when _T_2367 : node _T_2368 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2369 = or(_T_2368, io.in.a.ready) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(_T_2369, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2369, UInt<1>(0h1), "") : assert_198 node _T_2373 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2374 = orr(a_set_wo_ready) node _T_2375 = eq(_T_2374, UInt<1>(0h0)) node _T_2376 = or(_T_2373, _T_2375) node _T_2377 = asUInt(reset) node _T_2378 = eq(_T_2377, UInt<1>(0h0)) when _T_2378 : node _T_2379 = eq(_T_2376, UInt<1>(0h0)) when _T_2379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2376, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_93 node _T_2380 = orr(inflight) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) node _T_2382 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2383 = or(_T_2381, _T_2382) node _T_2384 = lt(watchdog, plusarg_reader.out) node _T_2385 = or(_T_2383, _T_2384) node _T_2386 = asUInt(reset) node _T_2387 = eq(_T_2386, UInt<1>(0h0)) when _T_2387 : node _T_2388 = eq(_T_2385, UInt<1>(0h0)) when _T_2388 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2385, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2389 = and(io.in.a.ready, io.in.a.valid) node _T_2390 = and(io.in.d.ready, io.in.d.valid) node _T_2391 = or(_T_2389, _T_2390) when _T_2391 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2392 = and(io.in.c.valid, c_first_1) node _T_2393 = bits(io.in.c.bits.opcode, 2, 2) node _T_2394 = bits(io.in.c.bits.opcode, 1, 1) node _T_2395 = and(_T_2393, _T_2394) node _T_2396 = and(_T_2392, _T_2395) when _T_2396 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2397 = and(io.in.c.ready, io.in.c.valid) node _T_2398 = and(_T_2397, c_first_1) node _T_2399 = bits(io.in.c.bits.opcode, 2, 2) node _T_2400 = bits(io.in.c.bits.opcode, 1, 1) node _T_2401 = and(_T_2399, _T_2400) node _T_2402 = and(_T_2398, _T_2401) when _T_2402 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2403 = dshr(inflight_1, io.in.c.bits.source) node _T_2404 = bits(_T_2403, 0, 0) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2409 = and(io.in.d.valid, d_first_2) node _T_2410 = and(_T_2409, UInt<1>(0h1)) node _T_2411 = and(_T_2410, d_release_ack_1) when _T_2411 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2412 = and(io.in.d.ready, io.in.d.valid) node _T_2413 = and(_T_2412, d_first_2) node _T_2414 = and(_T_2413, UInt<1>(0h1)) node _T_2415 = and(_T_2414, d_release_ack_1) when _T_2415 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2416 = and(io.in.d.valid, d_first_2) node _T_2417 = and(_T_2416, UInt<1>(0h1)) node _T_2418 = and(_T_2417, d_release_ack_1) when _T_2418 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2419 = dshr(inflight_1, io.in.d.bits.source) node _T_2420 = bits(_T_2419, 0, 0) node _T_2421 = or(_T_2420, same_cycle_resp_1) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2425 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(_T_2425, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2425, UInt<1>(0h1), "") : assert_203 else : node _T_2429 = eq(io.in.d.bits.size, c_size_lookup) node _T_2430 = asUInt(reset) node _T_2431 = eq(_T_2430, UInt<1>(0h0)) when _T_2431 : node _T_2432 = eq(_T_2429, UInt<1>(0h0)) when _T_2432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2429, UInt<1>(0h1), "") : assert_204 node _T_2433 = and(io.in.d.valid, d_first_2) node _T_2434 = and(_T_2433, c_first_1) node _T_2435 = and(_T_2434, io.in.c.valid) node _T_2436 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2437 = and(_T_2435, _T_2436) node _T_2438 = and(_T_2437, d_release_ack_1) node _T_2439 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2440 = and(_T_2438, _T_2439) when _T_2440 : node _T_2441 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2442 = or(_T_2441, io.in.c.ready) node _T_2443 = asUInt(reset) node _T_2444 = eq(_T_2443, UInt<1>(0h0)) when _T_2444 : node _T_2445 = eq(_T_2442, UInt<1>(0h0)) when _T_2445 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2442, UInt<1>(0h1), "") : assert_205 node _T_2446 = orr(c_set_wo_ready) when _T_2446 : node _T_2447 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_94 node _T_2451 = orr(inflight_1) node _T_2452 = eq(_T_2451, UInt<1>(0h0)) node _T_2453 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2454 = or(_T_2452, _T_2453) node _T_2455 = lt(watchdog_1, plusarg_reader_1.out) node _T_2456 = or(_T_2454, _T_2455) node _T_2457 = asUInt(reset) node _T_2458 = eq(_T_2457, UInt<1>(0h0)) when _T_2458 : node _T_2459 = eq(_T_2456, UInt<1>(0h0)) when _T_2459 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2456, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2460 = and(io.in.c.ready, io.in.c.valid) node _T_2461 = and(io.in.d.ready, io.in.d.valid) node _T_2462 = or(_T_2460, _T_2461) when _T_2462 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2463 = and(io.in.d.ready, io.in.d.valid) node _T_2464 = and(_T_2463, d_first_3) node _T_2465 = bits(io.in.d.bits.opcode, 2, 2) node _T_2466 = bits(io.in.d.bits.opcode, 1, 1) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = and(_T_2465, _T_2467) node _T_2469 = and(_T_2464, _T_2468) when _T_2469 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2470 = dshr(inflight_2, io.in.d.bits.sink) node _T_2471 = bits(_T_2470, 0, 0) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) node _T_2473 = asUInt(reset) node _T_2474 = eq(_T_2473, UInt<1>(0h0)) when _T_2474 : node _T_2475 = eq(_T_2472, UInt<1>(0h0)) when _T_2475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2472, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2476 = and(io.in.e.ready, io.in.e.valid) node _T_2477 = and(_T_2476, UInt<1>(0h1)) node _T_2478 = and(_T_2477, UInt<1>(0h1)) when _T_2478 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2479 = or(d_set, inflight_2) node _T_2480 = dshr(_T_2479, io.in.e.bits.sink) node _T_2481 = bits(_T_2480, 0, 0) node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(_T_2481, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2481, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_95 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_96 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_46( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2389 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2389; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2389; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2463 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2463; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2460 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2460; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2460; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_21 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_22 = 2'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2315 = _T_2389 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2315 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2315 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2315 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2315 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2315 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2361 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_24 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2361 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2330 = _T_2463 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2330 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2330 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2330 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_26 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_27 = 2'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2402 = _T_2460 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2402 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2402 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2402 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2402 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2402 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2433 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2433 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2415 = _T_2463 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2415 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2415 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2415 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2469 = _T_2463 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2469 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2478 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2478 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module TLDToNoC_2 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, egress_id : UInt}}} inst q of Queue1_TLBundleD_a32d64s6k5z4c_2 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 5, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<6>(0h3f), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 5, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo_hi = cat(q.io.deq.bits.source, q.io.deq.bits.sink) node const_lo = cat(const_lo_hi, q.io.deq.bits.denied) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_uncommonBits_T = or(q.io.deq.bits.source, UInt<5>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T, 4, 0) node _io_flit_bits_egress_id_requestOH_T = shr(q.io.deq.bits.source, 5) node _io_flit_bits_egress_id_requestOH_T_1 = eq(_io_flit_bits_egress_id_requestOH_T, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_2 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits) node _io_flit_bits_egress_id_requestOH_T_3 = and(_io_flit_bits_egress_id_requestOH_T_1, _io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = leq(io_flit_bits_egress_id_requestOH_uncommonBits, UInt<5>(0h1f)) node io_flit_bits_egress_id_requestOH_0 = and(_io_flit_bits_egress_id_requestOH_T_3, _io_flit_bits_egress_id_requestOH_T_4) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_1 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_1 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_1, 1, 0) node _io_flit_bits_egress_id_requestOH_T_5 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_6 = eq(_io_flit_bits_egress_id_requestOH_T_5, UInt<4>(0hb)) node _io_flit_bits_egress_id_requestOH_T_7 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_1) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_6, _io_flit_bits_egress_id_requestOH_T_7) node _io_flit_bits_egress_id_requestOH_T_9 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_1, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_1 = and(_io_flit_bits_egress_id_requestOH_T_8, _io_flit_bits_egress_id_requestOH_T_9) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_2 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_2 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_2, 1, 0) node _io_flit_bits_egress_id_requestOH_T_10 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_11 = eq(_io_flit_bits_egress_id_requestOH_T_10, UInt<4>(0ha)) node _io_flit_bits_egress_id_requestOH_T_12 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_2) node _io_flit_bits_egress_id_requestOH_T_13 = and(_io_flit_bits_egress_id_requestOH_T_11, _io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_2, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_2 = and(_io_flit_bits_egress_id_requestOH_T_13, _io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_3 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_3 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_3, 1, 0) node _io_flit_bits_egress_id_requestOH_T_15 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, UInt<4>(0h9)) node _io_flit_bits_egress_id_requestOH_T_17 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_3) node _io_flit_bits_egress_id_requestOH_T_18 = and(_io_flit_bits_egress_id_requestOH_T_16, _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_19 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_3, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_3 = and(_io_flit_bits_egress_id_requestOH_T_18, _io_flit_bits_egress_id_requestOH_T_19) node _io_flit_bits_egress_id_requestOH_uncommonBits_T_4 = or(q.io.deq.bits.source, UInt<2>(0h0)) node io_flit_bits_egress_id_requestOH_uncommonBits_4 = bits(_io_flit_bits_egress_id_requestOH_uncommonBits_T_4, 1, 0) node _io_flit_bits_egress_id_requestOH_T_20 = shr(q.io.deq.bits.source, 2) node _io_flit_bits_egress_id_requestOH_T_21 = eq(_io_flit_bits_egress_id_requestOH_T_20, UInt<4>(0h8)) node _io_flit_bits_egress_id_requestOH_T_22 = leq(UInt<1>(0h0), io_flit_bits_egress_id_requestOH_uncommonBits_4) node _io_flit_bits_egress_id_requestOH_T_23 = and(_io_flit_bits_egress_id_requestOH_T_21, _io_flit_bits_egress_id_requestOH_T_22) node _io_flit_bits_egress_id_requestOH_T_24 = leq(io_flit_bits_egress_id_requestOH_uncommonBits_4, UInt<2>(0h3)) node io_flit_bits_egress_id_requestOH_4 = and(_io_flit_bits_egress_id_requestOH_T_23, _io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<1>(0h1), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<2>(0h3), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<3>(0h5), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<3>(0h7), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<4>(0h9), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<4> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_sink_T = or(io.protocol.bits.sink, UInt<5>(0h10)) connect q.io.enq.bits.sink, _q_io_enq_bits_sink_T	module TLDToNoC_2( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [4:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [20:0] _tail_beats1_decode_T = 21'h3F << _q_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire [2:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0; // @[package.scala:243:{46,71,76}] reg [2:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 3'h1 \| tail_beats1 == 3'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 3'h0; // @[Edges.scala:229:27] tail_counter <= 3'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0) : head_counter - 3'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 3'h0 ? tail_beats1 : tail_counter - 3'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module MSHR_9 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<8>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<8>(0ha0)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<8>(0ha0)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<8>(0ha0)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_9( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [7:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [7:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [7:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [7:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [7:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [7:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [7:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [7:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 8'hA0; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 8'hA0; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [7:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 8'hA0; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_269 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_269( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_24 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid \|\| io.clear \|\| io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1) node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2) node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3) node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2) node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2) node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2) node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2) node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2) node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) node _T_7 = or(_T_6, prs1_wakeups_2) node _T_8 = or(_T_7, prs1_wakeups_3) when _T_8 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_4 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T_4, _next_uop_iw_p1_speculative_child_T_2) node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_3) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<2> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_6 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_4 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T_4, _next_uop_iw_p1_bypass_hint_T_2) node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_3) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_6 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_9 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_10 = or(_T_9, prs1_rebusys_2) node _T_11 = or(_T_10, prs1_rebusys_3) node _T_12 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_13 = neq(_T_12, UInt<1>(0h0)) node _T_14 = or(_T_11, _T_13) node _T_15 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_16 = and(_T_14, _T_15) when _T_16 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_17 = or(prs2_wakeups_0, prs2_wakeups_1) node _T_18 = or(_T_17, prs2_wakeups_2) node _T_19 = or(_T_18, prs2_wakeups_3) when _T_19 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_4 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T_4, _next_uop_iw_p2_speculative_child_T_2) node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_3) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<2> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_6 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_4 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T_4, _next_uop_iw_p2_bypass_hint_T_2) node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_3) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_6 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_20 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_21 = or(_T_20, prs2_rebusys_2) node _T_22 = or(_T_21, prs2_rebusys_3) node _T_23 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_24 = neq(_T_23, UInt<1>(0h0)) node _T_25 = or(_T_22, _T_24) node _T_26 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_27 = and(_T_25, _T_26) when _T_27 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_28 = or(prs3_wakeups_0, prs3_wakeups_1) node _T_29 = or(_T_28, prs3_wakeups_2) node _T_30 = or(_T_29, prs3_wakeups_3) when _T_30 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_4 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T_4, _next_uop_iw_p3_bypass_hint_T_2) node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_3) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_6 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_31 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_32 = and(io.pred_wakeup_port.valid, _T_31) when _T_32 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_33 = eq(io.squash_grant, UInt<1>(0h0)) node _T_34 = and(io.grant, _T_33) when _T_34 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_35 = and(slot_valid, slot_uop.iw_issued) when _T_35 : connect next_valid, rebusied	module IssueSlot_24( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_clear = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_5 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_7 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_5( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_7 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TageTable_1 : input clock : Clock input reset : Reset output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f2_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<7>(0h7f)) when _T : connect doing_reset, UInt<1>(0h0) node _T_1 = shr(io.f1_req_pc, 4) node idx_history = bits(io.f1_req_ghist, 3, 0) node _idx_T = xor(_T_1, idx_history) node s1_hashed_idx = bits(_idx_T, 6, 0) node tag_history = bits(io.f1_req_ghist, 3, 0) node _tag_T = shr(_T_1, 7) node _tag_T_1 = xor(_tag_T, tag_history) node s1_tag = bits(_tag_T_1, 6, 0) smem tage_u_4 : UInt<1>[8] [128] smem tage_table_4 : UInt<11>[4] [128] reg s2_tag : UInt, clock connect s2_tag, s1_tag wire s2_req_rtage : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4] wire s2_req_rus : UInt<1>[8] node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag) node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T) node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2) node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag) node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4) node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6) node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag) node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8) node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10) node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag) node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12) node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14) wire s2_req_rhits : UInt<1>[4] connect s2_req_rhits[0], _s2_req_rhits_T_3 connect s2_req_rhits[1], _s2_req_rhits_T_7 connect s2_req_rhits[2], _s2_req_rhits_T_11 connect s2_req_rhits[3], _s2_req_rhits_T_15 connect io.f2_resp[0].valid, s2_req_rhits[0] node _io_f2_resp_0_bits_u_T = cat(s2_req_rus[1], s2_req_rus[0]) connect io.f2_resp[0].bits.u, _io_f2_resp_0_bits_u_T connect io.f2_resp[0].bits.ctr, s2_req_rtage[0].ctr connect io.f2_resp[1].valid, s2_req_rhits[1] node _io_f2_resp_1_bits_u_T = cat(s2_req_rus[3], s2_req_rus[2]) connect io.f2_resp[1].bits.u, _io_f2_resp_1_bits_u_T connect io.f2_resp[1].bits.ctr, s2_req_rtage[1].ctr connect io.f2_resp[2].valid, s2_req_rhits[2] node _io_f2_resp_2_bits_u_T = cat(s2_req_rus[5], s2_req_rus[4]) connect io.f2_resp[2].bits.u, _io_f2_resp_2_bits_u_T connect io.f2_resp[2].bits.ctr, s2_req_rtage[2].ctr connect io.f2_resp[3].valid, s2_req_rhits[3] node _io_f2_resp_3_bits_u_T = cat(s2_req_rus[7], s2_req_rus[6]) connect io.f2_resp[3].bits.u, _io_f2_resp_3_bits_u_T connect io.f2_resp[3].bits.ctr, s2_req_rtage[3].ctr regreset clear_u_ctr : UInt<19>, clock, reset, UInt<19>(0h0) when doing_reset : connect clear_u_ctr, UInt<1>(0h1) else : node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1)) node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1) connect clear_u_ctr, _clear_u_ctr_T_1 node _doing_clear_u_T = bits(clear_u_ctr, 10, 0) node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0)) node _clear_u_hi_T = bits(clear_u_ctr, 18, 18) node clear_u_hi = eq(_clear_u_hi_T, UInt<1>(0h1)) node _clear_u_lo_T = bits(clear_u_ctr, 18, 18) node clear_u_lo = eq(_clear_u_lo_T, UInt<1>(0h0)) node clear_u_idx = shr(clear_u_ctr, 11) wire _clear_u_mask_WIRE : UInt<1>[8] connect _clear_u_mask_WIRE[0], clear_u_lo connect _clear_u_mask_WIRE[1], clear_u_hi connect _clear_u_mask_WIRE[2], clear_u_lo connect _clear_u_mask_WIRE[3], clear_u_hi connect _clear_u_mask_WIRE[4], clear_u_lo connect _clear_u_mask_WIRE[5], clear_u_hi connect _clear_u_mask_WIRE[6], clear_u_lo connect _clear_u_mask_WIRE[7], clear_u_hi node clear_u_mask_lo_lo = cat(_clear_u_mask_WIRE[1], _clear_u_mask_WIRE[0]) node clear_u_mask_lo_hi = cat(_clear_u_mask_WIRE[3], _clear_u_mask_WIRE[2]) node clear_u_mask_lo = cat(clear_u_mask_lo_hi, clear_u_mask_lo_lo) node clear_u_mask_hi_lo = cat(_clear_u_mask_WIRE[5], _clear_u_mask_WIRE[4]) node clear_u_mask_hi_hi = cat(_clear_u_mask_WIRE[7], _clear_u_mask_WIRE[6]) node clear_u_mask_hi = cat(clear_u_mask_hi_hi, clear_u_mask_hi_lo) node clear_u_mask = cat(clear_u_mask_hi, clear_u_mask_lo) node _T_2 = shr(io.update_pc, 4) node idx_history_1 = bits(io.update_hist, 3, 0) node _idx_T_1 = xor(_T_2, idx_history_1) node update_idx = bits(_idx_T_1, 6, 0) node tag_history_1 = bits(io.update_hist, 3, 0) node _tag_T_2 = shr(_T_2, 7) node _tag_T_3 = xor(_tag_T_2, tag_history_1) node update_tag = bits(_tag_T_3, 6, 0) wire update_wdata : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4] node _wen_T = or(io.update_mask[0], io.update_mask[1]) node _wen_T_1 = or(_wen_T, io.update_mask[2]) node _wen_T_2 = or(_wen_T_1, io.update_mask[3]) node _wen_T_3 = or(doing_reset, _wen_T_2) wire wen : UInt<1> connect wen, _wen_T_3 wire _rdata_WIRE : UInt<7> invalidate _rdata_WIRE when io.f1_req_valid : connect _rdata_WIRE, s1_hashed_idx read mport rdata = tage_table_4[_rdata_WIRE], clock reg REG : UInt<1>, clock connect REG, wen node _T_3 = and(REG, UInt<1>(0h0)) when _T_3 : wire _WIRE : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4] connect _WIRE[0].ctr, UInt<3>(0h0) connect _WIRE[0].tag, UInt<7>(0h0) connect _WIRE[0].valid, UInt<1>(0h0) connect _WIRE[1].ctr, UInt<3>(0h0) connect _WIRE[1].tag, UInt<7>(0h0) connect _WIRE[1].valid, UInt<1>(0h0) connect _WIRE[2].ctr, UInt<3>(0h0) connect _WIRE[2].tag, UInt<7>(0h0) connect _WIRE[2].valid, UInt<1>(0h0) connect _WIRE[3].ctr, UInt<3>(0h0) connect _WIRE[3].tag, UInt<7>(0h0) connect _WIRE[3].valid, UInt<1>(0h0) connect s2_req_rtage, _WIRE else : wire _WIRE_1 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _WIRE_2 : UInt<11> connect _WIRE_2, rdata[0] node _T_4 = bits(_WIRE_2, 2, 0) connect _WIRE_1.ctr, _T_4 node _T_5 = bits(_WIRE_2, 9, 3) connect _WIRE_1.tag, _T_5 node _T_6 = bits(_WIRE_2, 10, 10) connect _WIRE_1.valid, _T_6 wire _WIRE_3 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _WIRE_4 : UInt<11> connect _WIRE_4, rdata[1] node _T_7 = bits(_WIRE_4, 2, 0) connect _WIRE_3.ctr, _T_7 node _T_8 = bits(_WIRE_4, 9, 3) connect _WIRE_3.tag, _T_8 node _T_9 = bits(_WIRE_4, 10, 10) connect _WIRE_3.valid, _T_9 wire _WIRE_5 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _WIRE_6 : UInt<11> connect _WIRE_6, rdata[2] node _T_10 = bits(_WIRE_6, 2, 0) connect _WIRE_5.ctr, _T_10 node _T_11 = bits(_WIRE_6, 9, 3) connect _WIRE_5.tag, _T_11 node _T_12 = bits(_WIRE_6, 10, 10) connect _WIRE_5.valid, _T_12 wire _WIRE_7 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _WIRE_8 : UInt<11> connect _WIRE_8, rdata[3] node _T_13 = bits(_WIRE_8, 2, 0) connect _WIRE_7.ctr, _T_13 node _T_14 = bits(_WIRE_8, 9, 3) connect _WIRE_7.tag, _T_14 node _T_15 = bits(_WIRE_8, 10, 10) connect _WIRE_7.valid, _T_15 wire _WIRE_9 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4] connect _WIRE_9[0].ctr, _WIRE_1.ctr connect _WIRE_9[0].tag, _WIRE_1.tag connect _WIRE_9[0].valid, _WIRE_1.valid connect _WIRE_9[1].ctr, _WIRE_3.ctr connect _WIRE_9[1].tag, _WIRE_3.tag connect _WIRE_9[1].valid, _WIRE_3.valid connect _WIRE_9[2].ctr, _WIRE_5.ctr connect _WIRE_9[2].tag, _WIRE_5.tag connect _WIRE_9[2].valid, _WIRE_5.valid connect _WIRE_9[3].ctr, _WIRE_7.ctr connect _WIRE_9[3].tag, _WIRE_7.tag connect _WIRE_9[3].valid, _WIRE_7.valid connect s2_req_rtage, _WIRE_9 when wen : node widx = mux(doing_reset, reset_idx, update_idx) wire _wdata_WIRE : UInt<11>[4] connect _wdata_WIRE[0], UInt<11>(0h0) connect _wdata_WIRE[1], UInt<11>(0h0) connect _wdata_WIRE[2], UInt<11>(0h0) connect _wdata_WIRE[3], UInt<11>(0h0) node wdata_hi = cat(update_wdata[0].valid, update_wdata[0].tag) node _wdata_T = cat(wdata_hi, update_wdata[0].ctr) node wdata_hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag) node _wdata_T_1 = cat(wdata_hi_1, update_wdata[1].ctr) node wdata_hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag) node _wdata_T_2 = cat(wdata_hi_2, update_wdata[2].ctr) node wdata_hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag) node _wdata_T_3 = cat(wdata_hi_3, update_wdata[3].ctr) wire _wdata_WIRE_1 : UInt<11>[4] connect _wdata_WIRE_1[0], _wdata_T connect _wdata_WIRE_1[1], _wdata_T_1 connect _wdata_WIRE_1[2], _wdata_T_2 connect _wdata_WIRE_1[3], _wdata_T_3 node wdata = mux(doing_reset, _wdata_WIRE, _wdata_WIRE_1) node _wmask_T = not(UInt<4>(0h0)) node wmask_lo = cat(io.update_mask[1], io.update_mask[0]) node wmask_hi = cat(io.update_mask[3], io.update_mask[2]) node _wmask_T_1 = cat(wmask_hi, wmask_lo) node wmask = mux(doing_reset, _wmask_T, _wmask_T_1) node _T_16 = bits(wmask, 0, 0) node _T_17 = bits(wmask, 1, 1) node _T_18 = bits(wmask, 2, 2) node _T_19 = bits(wmask, 3, 3) write mport MPORT = tage_table_4[widx], clock when _T_16 : connect MPORT[0], wdata[0] when _T_17 : connect MPORT[1], wdata[1] when _T_18 : connect MPORT[2], wdata[2] when _T_19 : connect MPORT[3], wdata[3] wire update_u_mask : UInt<1>[8] connect update_u_mask[0], io.update_u_mask[0] connect update_u_mask[1], io.update_u_mask[0] connect update_u_mask[2], io.update_u_mask[1] connect update_u_mask[3], io.update_u_mask[1] connect update_u_mask[4], io.update_u_mask[2] connect update_u_mask[5], io.update_u_mask[2] connect update_u_mask[6], io.update_u_mask[3] connect update_u_mask[7], io.update_u_mask[3] node _update_u_wen_T = or(doing_reset, doing_clear_u) node _update_u_wen_T_1 = or(update_u_mask[0], update_u_mask[1]) node _update_u_wen_T_2 = or(_update_u_wen_T_1, update_u_mask[2]) node _update_u_wen_T_3 = or(_update_u_wen_T_2, update_u_mask[3]) node _update_u_wen_T_4 = or(_update_u_wen_T_3, update_u_mask[4]) node _update_u_wen_T_5 = or(_update_u_wen_T_4, update_u_mask[5]) node _update_u_wen_T_6 = or(_update_u_wen_T_5, update_u_mask[6]) node _update_u_wen_T_7 = or(_update_u_wen_T_6, update_u_mask[7]) node _update_u_wen_T_8 = or(_update_u_wen_T, _update_u_wen_T_7) wire update_u_wen : UInt<1> connect update_u_wen, _update_u_wen_T_8 wire _u_rdata_WIRE : UInt<7> invalidate _u_rdata_WIRE when io.f1_req_valid : connect _u_rdata_WIRE, s1_hashed_idx read mport u_rdata = tage_u_4[_u_rdata_WIRE], clock connect s2_req_rus, u_rdata when update_u_wen : node _widx_T = mux(doing_clear_u, clear_u_idx, update_idx) node widx_1 = mux(doing_reset, reset_idx, _widx_T) node _wdata_T_4 = or(doing_reset, doing_clear_u) wire _wdata_WIRE_2 : UInt<1>[8] connect _wdata_WIRE_2[0], UInt<1>(0h0) connect _wdata_WIRE_2[1], UInt<1>(0h0) connect _wdata_WIRE_2[2], UInt<1>(0h0) connect _wdata_WIRE_2[3], UInt<1>(0h0) connect _wdata_WIRE_2[4], UInt<1>(0h0) connect _wdata_WIRE_2[5], UInt<1>(0h0) connect _wdata_WIRE_2[6], UInt<1>(0h0) connect _wdata_WIRE_2[7], UInt<1>(0h0) node wdata_lo = cat(io.update_u[1], io.update_u[0]) node wdata_hi_4 = cat(io.update_u[3], io.update_u[2]) node _wdata_T_5 = cat(wdata_hi_4, wdata_lo) node _wdata_T_6 = bits(_wdata_T_5, 0, 0) node _wdata_T_7 = bits(_wdata_T_5, 1, 1) node _wdata_T_8 = bits(_wdata_T_5, 2, 2) node _wdata_T_9 = bits(_wdata_T_5, 3, 3) node _wdata_T_10 = bits(_wdata_T_5, 4, 4) node _wdata_T_11 = bits(_wdata_T_5, 5, 5) node _wdata_T_12 = bits(_wdata_T_5, 6, 6) node _wdata_T_13 = bits(_wdata_T_5, 7, 7) wire _wdata_WIRE_3 : UInt<1>[8] connect _wdata_WIRE_3[0], _wdata_T_6 connect _wdata_WIRE_3[1], _wdata_T_7 connect _wdata_WIRE_3[2], _wdata_T_8 connect _wdata_WIRE_3[3], _wdata_T_9 connect _wdata_WIRE_3[4], _wdata_T_10 connect _wdata_WIRE_3[5], _wdata_T_11 connect _wdata_WIRE_3[6], _wdata_T_12 connect _wdata_WIRE_3[7], _wdata_T_13 node wdata_1 = mux(_wdata_T_4, _wdata_WIRE_2, _wdata_WIRE_3) node _wmask_T_2 = not(UInt<8>(0h0)) node wmask_lo_lo = cat(update_u_mask[1], update_u_mask[0]) node wmask_lo_hi = cat(update_u_mask[3], update_u_mask[2]) node wmask_lo_1 = cat(wmask_lo_hi, wmask_lo_lo) node wmask_hi_lo = cat(update_u_mask[5], update_u_mask[4]) node wmask_hi_hi = cat(update_u_mask[7], update_u_mask[6]) node wmask_hi_1 = cat(wmask_hi_hi, wmask_hi_lo) node _wmask_T_3 = cat(wmask_hi_1, wmask_lo_1) node _wmask_T_4 = mux(doing_clear_u, clear_u_mask, _wmask_T_3) node wmask_1 = mux(doing_reset, _wmask_T_2, _wmask_T_4) node _T_20 = bits(wmask_1, 0, 0) node _T_21 = bits(wmask_1, 1, 1) node _T_22 = bits(wmask_1, 2, 2) node _T_23 = bits(wmask_1, 3, 3) node _T_24 = bits(wmask_1, 4, 4) node _T_25 = bits(wmask_1, 5, 5) node _T_26 = bits(wmask_1, 6, 6) node _T_27 = bits(wmask_1, 7, 7) node _T_28 = bits(widx_1, 6, 0) write mport MPORT_1 = tage_u_4[_T_28], clock when _T_20 : connect MPORT_1[0], wdata_1[0] when _T_21 : connect MPORT_1[1], wdata_1[1] when _T_22 : connect MPORT_1[2], wdata_1[2] when _T_23 : connect MPORT_1[3], wdata_1[3] when _T_24 : connect MPORT_1[4], wdata_1[4] when _T_25 : connect MPORT_1[5], wdata_1[5] when _T_26 : connect MPORT_1[6], wdata_1[6] when _T_27 : connect MPORT_1[7], wdata_1[7] reg wrbypass_tags : UInt<7>[2], clock reg wrbypass_idxs : UInt<7>[2], clock reg wrbypass : UInt<3>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag) node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx) node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3) node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6) node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx) node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_4 connect wrbypass_hits[1], _wrbypass_hits_T_9 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1) node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4) node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1) node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8) node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9) node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1) node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14) node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1) node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18) node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19) node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20) node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21) connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22 connect update_wdata[0].valid, UInt<1>(0h1) connect update_wdata[0].tag, update_tag node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1) node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4) node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1) node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8) node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9) node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1) node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14) node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1) node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18) node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19) node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20) node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21) connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22 connect update_wdata[1].valid, UInt<1>(0h1) connect update_wdata[1].tag, update_tag node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1) node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4) node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1) node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8) node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9) node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1) node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14) node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1) node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18) node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19) node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20) node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21) connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22 connect update_wdata[2].valid, UInt<1>(0h1) connect update_wdata[2].tag, update_tag node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1) node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4) node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1) node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8) node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9) node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1) node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14) node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1) node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18) node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19) node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20) node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21) connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22 connect update_wdata[3].valid, UInt<1>(0h1) connect update_wdata[3].tag, update_tag node _T_29 = or(io.update_mask[0], io.update_mask[1]) node _T_30 = or(_T_29, io.update_mask[2]) node _T_31 = or(_T_30, io.update_mask[3]) when _T_31 : node _T_32 = or(wrbypass_hits[0], wrbypass_hits[1]) when _T_32 : wire _WIRE_10 : UInt<3>[4] connect _WIRE_10[0], update_wdata[0].ctr connect _WIRE_10[1], update_wdata[1].ctr connect _WIRE_10[2], update_wdata[2].ctr connect _WIRE_10[3], update_wdata[3].ctr connect wrbypass[wrbypass_hit_idx], _WIRE_10 else : wire _WIRE_11 : UInt<3>[4] connect _WIRE_11[0], update_wdata[0].ctr connect _WIRE_11[1], update_wdata[1].ctr connect _WIRE_11[2], update_wdata[2].ctr connect _WIRE_11[3], update_wdata[3].ctr connect wrbypass[wrbypass_enq_idx], _WIRE_11 connect wrbypass_tags[wrbypass_enq_idx], update_tag connect wrbypass_idxs[wrbypass_enq_idx], update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2	module TageTable_1( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f2_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14] output io_f2_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14] output io_f2_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14] output io_f2_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire [43:0] _tage_table_4_R0_data; // @[tage.scala:90:27] wire [7:0] _tage_u_4_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26] wire [10:0] _wdata_WIRE_0 = 11'h0; // @[tage.scala:130:41] wire [10:0] _wdata_WIRE_1 = 11'h0; // @[tage.scala:130:41] wire [10:0] _wdata_WIRE_2 = 11'h0; // @[tage.scala:130:41] wire [10:0] _wdata_WIRE_3 = 11'h0; // @[tage.scala:130:41] wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34] wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58] wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34] wire s2_req_rhits_0; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_1; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_2; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_3; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34] wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26] wire [7:0] _reset_idx_T = _GEN + {7'h0, doing_reset}; // @[tage.scala:72:28, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [3:0] idx_history = io_f1_req_ghist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [3:0] tag_history = io_f1_req_ghist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [35:0] _idx_T = {io_f1_req_pc_0[39:8], io_f1_req_pc_0[7:4] ^ idx_history}; // @[frontend.scala:149:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99] wire [6:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12] wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:149:35] wire [28:0] _tag_T_1 = {_tag_T[28:4], _tag_T[3:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] s1_tag = _tag_T_1[6:0]; // @[tage.scala:62:{50,64}] wire wdata_1_0; // @[tage.scala:145:20] wire wdata_1_1; // @[tage.scala:145:20] wire wdata_1_2; // @[tage.scala:145:20] wire wdata_1_3; // @[tage.scala:145:20] wire wdata_1_4; // @[tage.scala:145:20] wire wdata_1_5; // @[tage.scala:145:20] wire wdata_1_6; // @[tage.scala:145:20] wire wdata_1_7; // @[tage.scala:145:20] wire s2_req_rus_0 = _tage_u_4_R0_data[0]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_1 = _tage_u_4_R0_data[1]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_2 = _tage_u_4_R0_data[2]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_3 = _tage_u_4_R0_data[3]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_4 = _tage_u_4_R0_data[4]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_5 = _tage_u_4_R0_data[5]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_6 = _tage_u_4_R0_data[6]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_7 = _tage_u_4_R0_data[7]; // @[tage.scala:89:27, :99:24] wire [10:0] wdata_0; // @[tage.scala:130:20] wire [10:0] wdata_1; // @[tage.scala:130:20] wire [10:0] wdata_2; // @[tage.scala:130:20] wire [10:0] wdata_3; // @[tage.scala:130:20] reg [6:0] s2_tag; // @[tage.scala:96:29] assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26] wire s2_req_rtage_0_valid; // @[tage.scala:98:26] wire [6:0] s2_req_rtage_0_tag; // @[tage.scala:98:26] wire s2_req_rtage_1_valid; // @[tage.scala:98:26] wire [6:0] s2_req_rtage_1_tag; // @[tage.scala:98:26] wire s2_req_rtage_2_valid; // @[tage.scala:98:26] wire [6:0] s2_req_rtage_2_tag; // @[tage.scala:98:26] wire s2_req_rtage_3_valid; // @[tage.scala:98:26] wire [6:0] s2_req_rtage_3_tag; // @[tage.scala:98:26] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29] assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29] assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29] assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29] assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31] wire _clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31, :114:31] wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}] wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}] wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109] wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109] wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109] wire [3:0] idx_history_1 = io_update_hist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [3:0] tag_history_1 = io_update_hist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [35:0] _idx_T_1 = {io_update_pc_0[39:8], io_update_pc_0[7:4] ^ idx_history_1}; // @[frontend.scala:149:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:149:35] wire [28:0] _tag_T_3 = {_tag_T_2[28:4], _tag_T_2[3:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] update_tag = _tag_T_3[6:0]; // @[tage.scala:62:{50,64}] wire [6:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [6:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [6:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [6:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26] wire _wen_T = io_update_mask_0_0 \| io_update_mask_1_0; // @[tage.scala:24:7, :121:60] wire _wen_T_1 = _wen_T \| io_update_mask_2_0; // @[tage.scala:24:7, :121:60] wire _wen_T_2 = _wen_T_1 \| io_update_mask_3_0; // @[tage.scala:24:7, :121:60] wire _wen_T_3 = doing_reset \| _wen_T_2; // @[tage.scala:72:28, :121:{34,60}] wire wen = _wen_T_3; // @[tage.scala:121:{21,34}] reg REG; // @[tage.scala:123:16] assign s2_req_rtage_0_ctr = _tage_table_4_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_tag = _tage_table_4_R0_data[9:3]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_valid = _tage_table_4_R0_data[10]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_ctr = _tage_table_4_R0_data[13:11]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_tag = _tage_table_4_R0_data[20:14]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_valid = _tage_table_4_R0_data[21]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_ctr = _tage_table_4_R0_data[24:22]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_tag = _tage_table_4_R0_data[31:25]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_valid = _tage_table_4_R0_data[32]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_ctr = _tage_table_4_R0_data[35:33]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_tag = _tage_table_4_R0_data[42:36]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_valid = _tage_table_4_R0_data[43]; // @[tage.scala:90:27, :98:26, :126:49] wire [6:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19] wire [7:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}] wire [7:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}] wire [7:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}] wire [7:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}] assign wdata_0 = doing_reset ? 11'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}] assign wdata_1 = doing_reset ? 11'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}] assign wdata_2 = doing_reset ? 11'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}] assign wdata_3 = doing_reset ? 11'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}] wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70] wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70] wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70] wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}] wire _GEN_0 = doing_reset \| doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43] wire _update_u_wen_T; // @[tage.scala:136:43] assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43] wire _wdata_T_4; // @[tage.scala:145:33] assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33] wire _update_u_wen_T_1 = update_u_mask_0 \| update_u_mask_1; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_2 = _update_u_wen_T_1 \| update_u_mask_2; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_3 = _update_u_wen_T_2 \| update_u_mask_3; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_4 = _update_u_wen_T_3 \| update_u_mask_4; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_5 = _update_u_wen_T_4 \| update_u_mask_5; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_6 = _update_u_wen_T_5 \| update_u_mask_6; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_7 = _update_u_wen_T_6 \| update_u_mask_7; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_8 = _update_u_wen_T \| _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}] wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}] wire [7:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47] wire [7:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}] wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110] wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110] wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110] wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}] wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}] wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}] wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}] wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}] wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}] wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}] wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}] assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}] assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}] assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}] assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}] assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}] assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}] assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}] assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}] wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106] wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106] wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106] wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}] wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}] reg [6:0] wrbypass_tags_0; // @[tage.scala:154:29] reg [6:0] wrbypass_tags_1; // @[tage.scala:154:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:155:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:155:29] reg [2:0] wrbypass_0_0; // @[tage.scala:156:29] reg [2:0] wrbypass_0_1; // @[tage.scala:156:29] reg [2:0] wrbypass_0_2; // @[tage.scala:156:29] reg [2:0] wrbypass_0_3; // @[tage.scala:156:29] reg [2:0] wrbypass_1_0; // @[tage.scala:156:29] reg [2:0] wrbypass_1_1; // @[tage.scala:156:29] reg [2:0] wrbypass_1_2; // @[tage.scala:156:29] reg [2:0] wrbypass_1_3; // @[tage.scala:156:29] reg wrbypass_enq_idx; // @[tage.scala:157:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37] wire wrbypass_hit = wrbypass_hits_0 \| wrbypass_hits_1; // @[tage.scala:159:33, :164:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}] wire _T_31 = _wen_T \| io_update_mask_2_0 \| io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_31 \| wrbypass_hit \| wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] wire _GEN_15 = ~_T_31 \| wrbypass_hit \| ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_31 \| wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39] end else // @[tage.scala:157:33, :180:38, :181:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29] REG <= wen; // @[tage.scala:121:21, :123:16] if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29] if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29] if (~_T_31 \| _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] end else begin // @[tage.scala:156:29, :180:38, :181:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end always @(posedge) tage_u_4 tage_u_4 ( // @[tage.scala:89:27] .R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_u_4_R0_data), .W0_addr (widx_1[6:0]), // @[tage.scala:144:19, :147:13] .W0_en (update_u_wen), // @[tage.scala:136:30] .W0_clk (clock), .W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20] .W0_mask (wmask_1) // @[tage.scala:146:20] ); // @[tage.scala:89:27] tage_table_4 tage_table_4 ( // @[tage.scala:90:27] .R0_addr (_rdata_WIRE), // @[tage.scala:122:99] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_table_4_R0_data), .W0_addr (widx), // @[tage.scala:129:19] .W0_en (wen), // @[tage.scala:121:21] .W0_clk (clock), .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20] .W0_mask (wmask) // @[tage.scala:131:20] ); // @[tage.scala:90:27] assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_54 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_108 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_54 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = and(io.in.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail invalidate route_buffer.io.enq.bits.flow.egress_node_id invalidate route_buffer.io.enq.bits.flow.egress_node invalidate route_buffer.io.enq.bits.flow.ingress_node_id invalidate route_buffer.io.enq.bits.flow.ingress_node invalidate route_buffer.io.enq.bits.flow.vnet_id connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0h8)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_6 = and(io.in.ready, io.in.valid) node _T_7 = and(_T_6, io.in.bits.head) node _T_8 = and(_T_7, at_dest) when _T_8 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<5>(0h17), io.in.bits.egress_id) when _T_9 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<5>(0h18), io.in.bits.egress_id) when _T_10 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(UInt<5>(0h19), io.in.bits.egress_id) when _T_11 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_12 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_13 = and(route_q.io.enq.valid, _T_12) node _T_14 = eq(_T_13, UInt<1>(0h0)) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_14, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_109 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_54 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_18 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_19 = and(vcalloc_q.io.enq.valid, _T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_20, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _c_T = cat(c_hi, c_lo) node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_hi_2 = cat(c_hi_hi_1, io.out_credit_available.`0`[2]) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_channel_oh_0 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 4, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1 connect io.in.ready, UInt<1>(0h0) connect io.router_req.valid, UInt<1>(0h0) invalidate io.router_req.bits.flow.egress_node_id invalidate io.router_req.bits.flow.egress_node invalidate io.router_req.bits.flow.ingress_node_id invalidate io.router_req.bits.flow.ingress_node invalidate io.router_req.bits.flow.vnet_id invalidate io.router_req.bits.src_virt_id connect io.vcalloc_req.valid, UInt<1>(0h0) invalidate io.vcalloc_req.bits.vc_sel.`0`[0] invalidate io.vcalloc_req.bits.vc_sel.`0`[1] invalidate io.vcalloc_req.bits.vc_sel.`0`[2] invalidate io.vcalloc_req.bits.vc_sel.`0`[3] invalidate io.vcalloc_req.bits.vc_sel.`0`[4] invalidate io.vcalloc_req.bits.vc_sel.`1`[0] invalidate io.vcalloc_req.bits.vc_sel.`2`[0] invalidate io.vcalloc_req.bits.vc_sel.`3`[0] invalidate io.vcalloc_req.bits.in_vc invalidate io.vcalloc_req.bits.flow.egress_node_id invalidate io.vcalloc_req.bits.flow.egress_node invalidate io.vcalloc_req.bits.flow.ingress_node_id invalidate io.vcalloc_req.bits.flow.ingress_node invalidate io.vcalloc_req.bits.flow.vnet_id connect io.salloc_req[0].valid, UInt<1>(0h0) invalidate io.salloc_req[0].bits.tail invalidate io.salloc_req[0].bits.vc_sel.`0`[0] invalidate io.salloc_req[0].bits.vc_sel.`0`[1] invalidate io.salloc_req[0].bits.vc_sel.`0`[2] invalidate io.salloc_req[0].bits.vc_sel.`0`[3] invalidate io.salloc_req[0].bits.vc_sel.`0`[4] invalidate io.salloc_req[0].bits.vc_sel.`1`[0] invalidate io.salloc_req[0].bits.vc_sel.`2`[0] invalidate io.salloc_req[0].bits.vc_sel.`3`[0] connect io.out[0].valid, UInt<1>(0h0) invalidate io.out[0].bits.out_virt_channel invalidate io.out[0].bits.flit.virt_channel_id invalidate io.out[0].bits.flit.flow.egress_node_id invalidate io.out[0].bits.flit.flow.egress_node invalidate io.out[0].bits.flit.flow.ingress_node_id invalidate io.out[0].bits.flit.flow.ingress_node invalidate io.out[0].bits.flit.flow.vnet_id invalidate io.out[0].bits.flit.payload invalidate io.out[0].bits.flit.tail invalidate io.out[0].bits.flit.head	module IngressUnit_54( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset // @[IngressUnit.scala:11:7] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_221 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_221( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_102 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_190 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_102( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_190 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_43 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_299 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_43( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_299 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_12 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_130 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_131 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_132 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_12( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_130 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_131 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_132 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_17 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[8] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 node _source_ok_T_28 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[2]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[3]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[4]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[5]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[6]) node source_ok = or(_source_ok_T_33, _source_ok_WIRE[7]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = and(_T_11, _T_24) node _T_89 = and(_T_88, _T_37) node _T_90 = and(_T_89, _T_50) node _T_91 = and(_T_90, _T_63) node _T_92 = and(_T_91, _T_71) node _T_93 = and(_T_92, _T_79) node _T_94 = and(_T_93, _T_87) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_94, UInt<1>(0h1), "") : assert_1 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_103 = shr(io.in.a.bits.source, 2) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = leq(UInt<1>(0h0), uncommonBits_4) node _T_106 = and(_T_104, _T_105) node _T_107 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_108 = and(_T_106, _T_107) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_109 = shr(io.in.a.bits.source, 2) node _T_110 = eq(_T_109, UInt<1>(0h1)) node _T_111 = leq(UInt<1>(0h0), uncommonBits_5) node _T_112 = and(_T_110, _T_111) node _T_113 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_114 = and(_T_112, _T_113) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_115 = shr(io.in.a.bits.source, 2) node _T_116 = eq(_T_115, UInt<2>(0h2)) node _T_117 = leq(UInt<1>(0h0), uncommonBits_6) node _T_118 = and(_T_116, _T_117) node _T_119 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_120 = and(_T_118, _T_119) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<2>(0h3)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_7) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_129 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_130 = or(_T_102, _T_108) node _T_131 = or(_T_130, _T_114) node _T_132 = or(_T_131, _T_120) node _T_133 = or(_T_132, _T_126) node _T_134 = or(_T_133, _T_127) node _T_135 = or(_T_134, _T_128) node _T_136 = or(_T_135, _T_129) node _T_137 = and(_T_101, _T_136) node _T_138 = or(UInt<1>(0h0), _T_137) node _T_139 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_140 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<14>(0h2000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<17>(0h10000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_156 = cvt(_T_155) node _T_157 = and(_T_156, asSInt(UInt<18>(0h2f000))) node _T_158 = asSInt(_T_157) node _T_159 = eq(_T_158, asSInt(UInt<1>(0h0))) node _T_160 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_161 = cvt(_T_160) node _T_162 = and(_T_161, asSInt(UInt<17>(0h10000))) node _T_163 = asSInt(_T_162) node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_166 = cvt(_T_165) node _T_167 = and(_T_166, asSInt(UInt<27>(0h4000000))) node _T_168 = asSInt(_T_167) node _T_169 = eq(_T_168, asSInt(UInt<1>(0h0))) node _T_170 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<13>(0h1000))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_176 = cvt(_T_175) node _T_177 = and(_T_176, asSInt(UInt<15>(0h4000))) node _T_178 = asSInt(_T_177) node _T_179 = eq(_T_178, asSInt(UInt<1>(0h0))) node _T_180 = or(_T_144, _T_149) node _T_181 = or(_T_180, _T_154) node _T_182 = or(_T_181, _T_159) node _T_183 = or(_T_182, _T_164) node _T_184 = or(_T_183, _T_169) node _T_185 = or(_T_184, _T_174) node _T_186 = or(_T_185, _T_179) node _T_187 = and(_T_139, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_138, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_189, UInt<1>(0h1), "") : assert_2 node _T_193 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_194 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_195 = and(_T_193, _T_194) node _T_196 = or(UInt<1>(0h0), _T_195) node _T_197 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_198 = cvt(_T_197) node _T_199 = and(_T_198, asSInt(UInt<14>(0h2000))) node _T_200 = asSInt(_T_199) node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0))) node _T_202 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<13>(0h1000))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_208 = cvt(_T_207) node _T_209 = and(_T_208, asSInt(UInt<17>(0h10000))) node _T_210 = asSInt(_T_209) node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0))) node _T_212 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_213 = cvt(_T_212) node _T_214 = and(_T_213, asSInt(UInt<18>(0h2f000))) node _T_215 = asSInt(_T_214) node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0))) node _T_217 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_218 = cvt(_T_217) node _T_219 = and(_T_218, asSInt(UInt<17>(0h10000))) node _T_220 = asSInt(_T_219) node _T_221 = eq(_T_220, asSInt(UInt<1>(0h0))) node _T_222 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_223 = cvt(_T_222) node _T_224 = and(_T_223, asSInt(UInt<27>(0h4000000))) node _T_225 = asSInt(_T_224) node _T_226 = eq(_T_225, asSInt(UInt<1>(0h0))) node _T_227 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_233 = cvt(_T_232) node _T_234 = and(_T_233, asSInt(UInt<15>(0h4000))) node _T_235 = asSInt(_T_234) node _T_236 = eq(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = or(_T_201, _T_206) node _T_238 = or(_T_237, _T_211) node _T_239 = or(_T_238, _T_216) node _T_240 = or(_T_239, _T_221) node _T_241 = or(_T_240, _T_226) node _T_242 = or(_T_241, _T_231) node _T_243 = or(_T_242, _T_236) node _T_244 = and(_T_196, _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = and(UInt<1>(0h0), _T_245) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_246, UInt<1>(0h1), "") : assert_3 node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(source_ok, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_253 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_253, UInt<1>(0h1), "") : assert_5 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(is_aligned, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_260 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_260, UInt<1>(0h1), "") : assert_7 node _T_264 = not(io.in.a.bits.mask) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_T_265, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_265, UInt<1>(0h1), "") : assert_8 node _T_269 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_269, UInt<1>(0h1), "") : assert_9 node _T_273 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h0)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_8) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<1>(0h1)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_9) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h2)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_10) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_296 = shr(io.in.a.bits.source, 2) node _T_297 = eq(_T_296, UInt<2>(0h3)) node _T_298 = leq(UInt<1>(0h0), uncommonBits_11) node _T_299 = and(_T_297, _T_298) node _T_300 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_301 = and(_T_299, _T_300) node _T_302 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_303 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_304 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_305 = or(_T_277, _T_283) node _T_306 = or(_T_305, _T_289) node _T_307 = or(_T_306, _T_295) node _T_308 = or(_T_307, _T_301) node _T_309 = or(_T_308, _T_302) node _T_310 = or(_T_309, _T_303) node _T_311 = or(_T_310, _T_304) node _T_312 = and(_T_276, _T_311) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_315 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<14>(0h2000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<13>(0h1000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<17>(0h10000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<18>(0h2f000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<17>(0h10000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<27>(0h4000000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<15>(0h4000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = or(_T_319, _T_324) node _T_356 = or(_T_355, _T_329) node _T_357 = or(_T_356, _T_334) node _T_358 = or(_T_357, _T_339) node _T_359 = or(_T_358, _T_344) node _T_360 = or(_T_359, _T_349) node _T_361 = or(_T_360, _T_354) node _T_362 = and(_T_314, _T_361) node _T_363 = or(UInt<1>(0h0), _T_362) node _T_364 = and(_T_313, _T_363) node _T_365 = asUInt(reset) node _T_366 = eq(_T_365, UInt<1>(0h0)) when _T_366 : node _T_367 = eq(_T_364, UInt<1>(0h0)) when _T_367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_364, UInt<1>(0h1), "") : assert_10 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<14>(0h2000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<13>(0h1000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<18>(0h2f000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<15>(0h4000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = or(_T_376, _T_381) node _T_413 = or(_T_412, _T_386) node _T_414 = or(_T_413, _T_391) node _T_415 = or(_T_414, _T_396) node _T_416 = or(_T_415, _T_401) node _T_417 = or(_T_416, _T_406) node _T_418 = or(_T_417, _T_411) node _T_419 = and(_T_371, _T_418) node _T_420 = or(UInt<1>(0h0), _T_419) node _T_421 = and(UInt<1>(0h0), _T_420) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_421, UInt<1>(0h1), "") : assert_11 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(source_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_428 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_428, UInt<1>(0h1), "") : assert_13 node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(is_aligned, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_435 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_435, UInt<1>(0h1), "") : assert_15 node _T_439 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_439, UInt<1>(0h1), "") : assert_16 node _T_443 = not(io.in.a.bits.mask) node _T_444 = eq(_T_443, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_444, UInt<1>(0h1), "") : assert_17 node _T_448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_448, UInt<1>(0h1), "") : assert_18 node _T_452 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_452 : node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_457 = shr(io.in.a.bits.source, 2) node _T_458 = eq(_T_457, UInt<1>(0h0)) node _T_459 = leq(UInt<1>(0h0), uncommonBits_12) node _T_460 = and(_T_458, _T_459) node _T_461 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_462 = and(_T_460, _T_461) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_463 = shr(io.in.a.bits.source, 2) node _T_464 = eq(_T_463, UInt<1>(0h1)) node _T_465 = leq(UInt<1>(0h0), uncommonBits_13) node _T_466 = and(_T_464, _T_465) node _T_467 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_468 = and(_T_466, _T_467) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_469 = shr(io.in.a.bits.source, 2) node _T_470 = eq(_T_469, UInt<2>(0h2)) node _T_471 = leq(UInt<1>(0h0), uncommonBits_14) node _T_472 = and(_T_470, _T_471) node _T_473 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_474 = and(_T_472, _T_473) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_475 = shr(io.in.a.bits.source, 2) node _T_476 = eq(_T_475, UInt<2>(0h3)) node _T_477 = leq(UInt<1>(0h0), uncommonBits_15) node _T_478 = and(_T_476, _T_477) node _T_479 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_484 = or(_T_456, _T_462) node _T_485 = or(_T_484, _T_468) node _T_486 = or(_T_485, _T_474) node _T_487 = or(_T_486, _T_480) node _T_488 = or(_T_487, _T_481) node _T_489 = or(_T_488, _T_482) node _T_490 = or(_T_489, _T_483) node _T_491 = and(_T_455, _T_490) node _T_492 = or(UInt<1>(0h0), _T_491) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_492, UInt<1>(0h1), "") : assert_19 node _T_496 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_497 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_498 = and(_T_496, _T_497) node _T_499 = or(UInt<1>(0h0), _T_498) node _T_500 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<13>(0h1000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = and(_T_499, _T_504) node _T_506 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_507 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_508 = and(_T_506, _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_511 = cvt(_T_510) node _T_512 = and(_T_511, asSInt(UInt<14>(0h2000))) node _T_513 = asSInt(_T_512) node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0))) node _T_515 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_516 = cvt(_T_515) node _T_517 = and(_T_516, asSInt(UInt<17>(0h10000))) node _T_518 = asSInt(_T_517) node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0))) node _T_520 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<18>(0h2f000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_526 = cvt(_T_525) node _T_527 = and(_T_526, asSInt(UInt<17>(0h10000))) node _T_528 = asSInt(_T_527) node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0))) node _T_530 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_531 = cvt(_T_530) node _T_532 = and(_T_531, asSInt(UInt<27>(0h4000000))) node _T_533 = asSInt(_T_532) node _T_534 = eq(_T_533, asSInt(UInt<1>(0h0))) node _T_535 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_536 = cvt(_T_535) node _T_537 = and(_T_536, asSInt(UInt<13>(0h1000))) node _T_538 = asSInt(_T_537) node _T_539 = eq(_T_538, asSInt(UInt<1>(0h0))) node _T_540 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_541 = cvt(_T_540) node _T_542 = and(_T_541, asSInt(UInt<15>(0h4000))) node _T_543 = asSInt(_T_542) node _T_544 = eq(_T_543, asSInt(UInt<1>(0h0))) node _T_545 = or(_T_514, _T_519) node _T_546 = or(_T_545, _T_524) node _T_547 = or(_T_546, _T_529) node _T_548 = or(_T_547, _T_534) node _T_549 = or(_T_548, _T_539) node _T_550 = or(_T_549, _T_544) node _T_551 = and(_T_509, _T_550) node _T_552 = or(UInt<1>(0h0), _T_505) node _T_553 = or(_T_552, _T_551) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_553, UInt<1>(0h1), "") : assert_20 node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(source_ok, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(is_aligned, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_563 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_T_563, UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_563, UInt<1>(0h1), "") : assert_23 node _T_567 = eq(io.in.a.bits.mask, mask) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_567, UInt<1>(0h1), "") : assert_24 node _T_571 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_572 = asUInt(reset) node _T_573 = eq(_T_572, UInt<1>(0h0)) when _T_573 : node _T_574 = eq(_T_571, UInt<1>(0h0)) when _T_574 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_571, UInt<1>(0h1), "") : assert_25 node _T_575 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_575 : node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_580 = shr(io.in.a.bits.source, 2) node _T_581 = eq(_T_580, UInt<1>(0h0)) node _T_582 = leq(UInt<1>(0h0), uncommonBits_16) node _T_583 = and(_T_581, _T_582) node _T_584 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_585 = and(_T_583, _T_584) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_586 = shr(io.in.a.bits.source, 2) node _T_587 = eq(_T_586, UInt<1>(0h1)) node _T_588 = leq(UInt<1>(0h0), uncommonBits_17) node _T_589 = and(_T_587, _T_588) node _T_590 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_591 = and(_T_589, _T_590) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_592 = shr(io.in.a.bits.source, 2) node _T_593 = eq(_T_592, UInt<2>(0h2)) node _T_594 = leq(UInt<1>(0h0), uncommonBits_18) node _T_595 = and(_T_593, _T_594) node _T_596 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_597 = and(_T_595, _T_596) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_598 = shr(io.in.a.bits.source, 2) node _T_599 = eq(_T_598, UInt<2>(0h3)) node _T_600 = leq(UInt<1>(0h0), uncommonBits_19) node _T_601 = and(_T_599, _T_600) node _T_602 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_603 = and(_T_601, _T_602) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_606 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_607 = or(_T_579, _T_585) node _T_608 = or(_T_607, _T_591) node _T_609 = or(_T_608, _T_597) node _T_610 = or(_T_609, _T_603) node _T_611 = or(_T_610, _T_604) node _T_612 = or(_T_611, _T_605) node _T_613 = or(_T_612, _T_606) node _T_614 = and(_T_578, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_617 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_618 = and(_T_616, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = and(_T_619, _T_624) node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_628 = and(_T_626, _T_627) node _T_629 = or(UInt<1>(0h0), _T_628) node _T_630 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<14>(0h2000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<27>(0h4000000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<13>(0h1000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<15>(0h4000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = or(_T_634, _T_639) node _T_661 = or(_T_660, _T_644) node _T_662 = or(_T_661, _T_649) node _T_663 = or(_T_662, _T_654) node _T_664 = or(_T_663, _T_659) node _T_665 = and(_T_629, _T_664) node _T_666 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_667 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h10000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = and(_T_666, _T_671) node _T_673 = or(UInt<1>(0h0), _T_625) node _T_674 = or(_T_673, _T_665) node _T_675 = or(_T_674, _T_672) node _T_676 = and(_T_615, _T_675) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_676, UInt<1>(0h1), "") : assert_26 node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(source_ok, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(is_aligned, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_686 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_686, UInt<1>(0h1), "") : assert_29 node _T_690 = eq(io.in.a.bits.mask, mask) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_690, UInt<1>(0h1), "") : assert_30 node _T_694 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_694 : node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_697 = and(_T_695, _T_696) node _T_698 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_699 = shr(io.in.a.bits.source, 2) node _T_700 = eq(_T_699, UInt<1>(0h0)) node _T_701 = leq(UInt<1>(0h0), uncommonBits_20) node _T_702 = and(_T_700, _T_701) node _T_703 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_704 = and(_T_702, _T_703) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_705 = shr(io.in.a.bits.source, 2) node _T_706 = eq(_T_705, UInt<1>(0h1)) node _T_707 = leq(UInt<1>(0h0), uncommonBits_21) node _T_708 = and(_T_706, _T_707) node _T_709 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_710 = and(_T_708, _T_709) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_711 = shr(io.in.a.bits.source, 2) node _T_712 = eq(_T_711, UInt<2>(0h2)) node _T_713 = leq(UInt<1>(0h0), uncommonBits_22) node _T_714 = and(_T_712, _T_713) node _T_715 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_716 = and(_T_714, _T_715) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_717 = shr(io.in.a.bits.source, 2) node _T_718 = eq(_T_717, UInt<2>(0h3)) node _T_719 = leq(UInt<1>(0h0), uncommonBits_23) node _T_720 = and(_T_718, _T_719) node _T_721 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_722 = and(_T_720, _T_721) node _T_723 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_724 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_725 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_726 = or(_T_698, _T_704) node _T_727 = or(_T_726, _T_710) node _T_728 = or(_T_727, _T_716) node _T_729 = or(_T_728, _T_722) node _T_730 = or(_T_729, _T_723) node _T_731 = or(_T_730, _T_724) node _T_732 = or(_T_731, _T_725) node _T_733 = and(_T_697, _T_732) node _T_734 = or(UInt<1>(0h0), _T_733) node _T_735 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_736 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_737 = and(_T_735, _T_736) node _T_738 = or(UInt<1>(0h0), _T_737) node _T_739 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_740 = cvt(_T_739) node _T_741 = and(_T_740, asSInt(UInt<13>(0h1000))) node _T_742 = asSInt(_T_741) node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) node _T_744 = and(_T_738, _T_743) node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<14>(0h2000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<18>(0h2f000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<17>(0h10000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<27>(0h4000000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<13>(0h1000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_775 = cvt(_T_774) node _T_776 = and(_T_775, asSInt(UInt<15>(0h4000))) node _T_777 = asSInt(_T_776) node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0))) node _T_779 = or(_T_753, _T_758) node _T_780 = or(_T_779, _T_763) node _T_781 = or(_T_780, _T_768) node _T_782 = or(_T_781, _T_773) node _T_783 = or(_T_782, _T_778) node _T_784 = and(_T_748, _T_783) node _T_785 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_786 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<17>(0h10000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = and(_T_785, _T_790) node _T_792 = or(UInt<1>(0h0), _T_744) node _T_793 = or(_T_792, _T_784) node _T_794 = or(_T_793, _T_791) node _T_795 = and(_T_734, _T_794) node _T_796 = asUInt(reset) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(_T_795, UInt<1>(0h0)) when _T_798 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_795, UInt<1>(0h1), "") : assert_31 node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(source_ok, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(is_aligned, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_805 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_805, UInt<1>(0h1), "") : assert_34 node _T_809 = not(mask) node _T_810 = and(io.in.a.bits.mask, _T_809) node _T_811 = eq(_T_810, UInt<1>(0h0)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_811, UInt<1>(0h1), "") : assert_35 node _T_815 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_815 : node _T_816 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_817 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_818 = and(_T_816, _T_817) node _T_819 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<1>(0h0)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_24) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<1>(0h1)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_25) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_832 = shr(io.in.a.bits.source, 2) node _T_833 = eq(_T_832, UInt<2>(0h2)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_26) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_837 = and(_T_835, _T_836) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_838 = shr(io.in.a.bits.source, 2) node _T_839 = eq(_T_838, UInt<2>(0h3)) node _T_840 = leq(UInt<1>(0h0), uncommonBits_27) node _T_841 = and(_T_839, _T_840) node _T_842 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_846 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_847 = or(_T_819, _T_825) node _T_848 = or(_T_847, _T_831) node _T_849 = or(_T_848, _T_837) node _T_850 = or(_T_849, _T_843) node _T_851 = or(_T_850, _T_844) node _T_852 = or(_T_851, _T_845) node _T_853 = or(_T_852, _T_846) node _T_854 = and(_T_818, _T_853) node _T_855 = or(UInt<1>(0h0), _T_854) node _T_856 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_857 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _T_859 = or(UInt<1>(0h0), _T_858) node _T_860 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_861 = cvt(_T_860) node _T_862 = and(_T_861, asSInt(UInt<15>(0h5000))) node _T_863 = asSInt(_T_862) node _T_864 = eq(_T_863, asSInt(UInt<1>(0h0))) node _T_865 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_866 = cvt(_T_865) node _T_867 = and(_T_866, asSInt(UInt<13>(0h1000))) node _T_868 = asSInt(_T_867) node _T_869 = eq(_T_868, asSInt(UInt<1>(0h0))) node _T_870 = or(_T_864, _T_869) node _T_871 = and(_T_859, _T_870) node _T_872 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_873 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<13>(0h1000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_879 = cvt(_T_878) node _T_880 = and(_T_879, asSInt(UInt<17>(0h10000))) node _T_881 = asSInt(_T_880) node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0))) node _T_883 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<18>(0h2f000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_889 = cvt(_T_888) node _T_890 = and(_T_889, asSInt(UInt<17>(0h10000))) node _T_891 = asSInt(_T_890) node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0))) node _T_893 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_894 = cvt(_T_893) node _T_895 = and(_T_894, asSInt(UInt<27>(0h4000000))) node _T_896 = asSInt(_T_895) node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0))) node _T_898 = or(_T_877, _T_882) node _T_899 = or(_T_898, _T_887) node _T_900 = or(_T_899, _T_892) node _T_901 = or(_T_900, _T_897) node _T_902 = and(_T_872, _T_901) node _T_903 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_904 = or(UInt<1>(0h0), _T_903) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<15>(0h4000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = and(_T_904, _T_909) node _T_911 = or(UInt<1>(0h0), _T_871) node _T_912 = or(_T_911, _T_902) node _T_913 = or(_T_912, _T_910) node _T_914 = and(_T_855, _T_913) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_914, UInt<1>(0h1), "") : assert_36 node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(source_ok, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(is_aligned, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_924 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_924, UInt<1>(0h1), "") : assert_39 node _T_928 = eq(io.in.a.bits.mask, mask) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_928, UInt<1>(0h1), "") : assert_40 node _T_932 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_932 : node _T_933 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_934 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_935 = and(_T_933, _T_934) node _T_936 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_937 = shr(io.in.a.bits.source, 2) node _T_938 = eq(_T_937, UInt<1>(0h0)) node _T_939 = leq(UInt<1>(0h0), uncommonBits_28) node _T_940 = and(_T_938, _T_939) node _T_941 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_942 = and(_T_940, _T_941) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_943 = shr(io.in.a.bits.source, 2) node _T_944 = eq(_T_943, UInt<1>(0h1)) node _T_945 = leq(UInt<1>(0h0), uncommonBits_29) node _T_946 = and(_T_944, _T_945) node _T_947 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_948 = and(_T_946, _T_947) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_949 = shr(io.in.a.bits.source, 2) node _T_950 = eq(_T_949, UInt<2>(0h2)) node _T_951 = leq(UInt<1>(0h0), uncommonBits_30) node _T_952 = and(_T_950, _T_951) node _T_953 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_954 = and(_T_952, _T_953) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_955 = shr(io.in.a.bits.source, 2) node _T_956 = eq(_T_955, UInt<2>(0h3)) node _T_957 = leq(UInt<1>(0h0), uncommonBits_31) node _T_958 = and(_T_956, _T_957) node _T_959 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_960 = and(_T_958, _T_959) node _T_961 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_962 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_963 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_964 = or(_T_936, _T_942) node _T_965 = or(_T_964, _T_948) node _T_966 = or(_T_965, _T_954) node _T_967 = or(_T_966, _T_960) node _T_968 = or(_T_967, _T_961) node _T_969 = or(_T_968, _T_962) node _T_970 = or(_T_969, _T_963) node _T_971 = and(_T_935, _T_970) node _T_972 = or(UInt<1>(0h0), _T_971) node _T_973 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_974 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_975 = and(_T_973, _T_974) node _T_976 = or(UInt<1>(0h0), _T_975) node _T_977 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<15>(0h5000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = or(_T_981, _T_986) node _T_988 = and(_T_976, _T_987) node _T_989 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_990 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_991 = cvt(_T_990) node _T_992 = and(_T_991, asSInt(UInt<13>(0h1000))) node _T_993 = asSInt(_T_992) node _T_994 = eq(_T_993, asSInt(UInt<1>(0h0))) node _T_995 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_996 = cvt(_T_995) node _T_997 = and(_T_996, asSInt(UInt<17>(0h10000))) node _T_998 = asSInt(_T_997) node _T_999 = eq(_T_998, asSInt(UInt<1>(0h0))) node _T_1000 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<18>(0h2f000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<17>(0h10000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1011 = cvt(_T_1010) node _T_1012 = and(_T_1011, asSInt(UInt<27>(0h4000000))) node _T_1013 = asSInt(_T_1012) node _T_1014 = eq(_T_1013, asSInt(UInt<1>(0h0))) node _T_1015 = or(_T_994, _T_999) node _T_1016 = or(_T_1015, _T_1004) node _T_1017 = or(_T_1016, _T_1009) node _T_1018 = or(_T_1017, _T_1014) node _T_1019 = and(_T_989, _T_1018) node _T_1020 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_1021 = or(UInt<1>(0h0), _T_1020) node _T_1022 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1023 = cvt(_T_1022) node _T_1024 = and(_T_1023, asSInt(UInt<15>(0h4000))) node _T_1025 = asSInt(_T_1024) node _T_1026 = eq(_T_1025, asSInt(UInt<1>(0h0))) node _T_1027 = and(_T_1021, _T_1026) node _T_1028 = or(UInt<1>(0h0), _T_988) node _T_1029 = or(_T_1028, _T_1019) node _T_1030 = or(_T_1029, _T_1027) node _T_1031 = and(_T_972, _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_41 node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(source_ok, UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(is_aligned, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1041 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_44 node _T_1045 = eq(io.in.a.bits.mask, mask) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_45 node _T_1049 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1049 : node _T_1050 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1051 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1052 = and(_T_1050, _T_1051) node _T_1053 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1054 = shr(io.in.a.bits.source, 2) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) node _T_1056 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1059 = and(_T_1057, _T_1058) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1060 = shr(io.in.a.bits.source, 2) node _T_1061 = eq(_T_1060, UInt<1>(0h1)) node _T_1062 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1065 = and(_T_1063, _T_1064) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1066 = shr(io.in.a.bits.source, 2) node _T_1067 = eq(_T_1066, UInt<2>(0h2)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1071 = and(_T_1069, _T_1070) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1072 = shr(io.in.a.bits.source, 2) node _T_1073 = eq(_T_1072, UInt<2>(0h3)) node _T_1074 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1075 = and(_T_1073, _T_1074) node _T_1076 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1079 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1081 = or(_T_1053, _T_1059) node _T_1082 = or(_T_1081, _T_1065) node _T_1083 = or(_T_1082, _T_1071) node _T_1084 = or(_T_1083, _T_1077) node _T_1085 = or(_T_1084, _T_1078) node _T_1086 = or(_T_1085, _T_1079) node _T_1087 = or(_T_1086, _T_1080) node _T_1088 = and(_T_1052, _T_1087) node _T_1089 = or(UInt<1>(0h0), _T_1088) node _T_1090 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1091 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = or(UInt<1>(0h0), _T_1092) node _T_1094 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1095 = cvt(_T_1094) node _T_1096 = and(_T_1095, asSInt(UInt<13>(0h1000))) node _T_1097 = asSInt(_T_1096) node _T_1098 = eq(_T_1097, asSInt(UInt<1>(0h0))) node _T_1099 = and(_T_1093, _T_1098) node _T_1100 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1101 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1102 = cvt(_T_1101) node _T_1103 = and(_T_1102, asSInt(UInt<14>(0h2000))) node _T_1104 = asSInt(_T_1103) node _T_1105 = eq(_T_1104, asSInt(UInt<1>(0h0))) node _T_1106 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1107 = cvt(_T_1106) node _T_1108 = and(_T_1107, asSInt(UInt<17>(0h10000))) node _T_1109 = asSInt(_T_1108) node _T_1110 = eq(_T_1109, asSInt(UInt<1>(0h0))) node _T_1111 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1112 = cvt(_T_1111) node _T_1113 = and(_T_1112, asSInt(UInt<18>(0h2f000))) node _T_1114 = asSInt(_T_1113) node _T_1115 = eq(_T_1114, asSInt(UInt<1>(0h0))) node _T_1116 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1117 = cvt(_T_1116) node _T_1118 = and(_T_1117, asSInt(UInt<17>(0h10000))) node _T_1119 = asSInt(_T_1118) node _T_1120 = eq(_T_1119, asSInt(UInt<1>(0h0))) node _T_1121 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<27>(0h4000000))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1127 = cvt(_T_1126) node _T_1128 = and(_T_1127, asSInt(UInt<13>(0h1000))) node _T_1129 = asSInt(_T_1128) node _T_1130 = eq(_T_1129, asSInt(UInt<1>(0h0))) node _T_1131 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1132 = cvt(_T_1131) node _T_1133 = and(_T_1132, asSInt(UInt<15>(0h4000))) node _T_1134 = asSInt(_T_1133) node _T_1135 = eq(_T_1134, asSInt(UInt<1>(0h0))) node _T_1136 = or(_T_1105, _T_1110) node _T_1137 = or(_T_1136, _T_1115) node _T_1138 = or(_T_1137, _T_1120) node _T_1139 = or(_T_1138, _T_1125) node _T_1140 = or(_T_1139, _T_1130) node _T_1141 = or(_T_1140, _T_1135) node _T_1142 = and(_T_1100, _T_1141) node _T_1143 = or(UInt<1>(0h0), _T_1099) node _T_1144 = or(_T_1143, _T_1142) node _T_1145 = and(_T_1089, _T_1144) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_46 node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(source_ok, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(is_aligned, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1155 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_49 node _T_1159 = eq(io.in.a.bits.mask, mask) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_50 node _T_1163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1167 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_52 node _source_ok_T_34 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h0)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<1>(0h1)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h2)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_53 = shr(io.in.d.bits.source, 2) node _source_ok_T_54 = eq(_source_ok_T_53, UInt<2>(0h3)) node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57) node _source_ok_T_59 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[8] connect _source_ok_WIRE_1[0], _source_ok_T_34 connect _source_ok_WIRE_1[1], _source_ok_T_40 connect _source_ok_WIRE_1[2], _source_ok_T_46 connect _source_ok_WIRE_1[3], _source_ok_T_52 connect _source_ok_WIRE_1[4], _source_ok_T_58 connect _source_ok_WIRE_1[5], _source_ok_T_59 connect _source_ok_WIRE_1[6], _source_ok_T_60 connect _source_ok_WIRE_1[7], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE_1[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE_1[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[6]) node source_ok_1 = or(_source_ok_T_67, _source_ok_WIRE_1[7]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1171 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1171 : node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(source_ok_1, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1175 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_54 node _T_1179 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(_T_1179, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1179, UInt<1>(0h1), "") : assert_55 node _T_1183 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_56 node _T_1187 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_57 node _T_1191 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1191 : node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(source_ok_1, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(sink_ok, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1198 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_60 node _T_1202 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_61 node _T_1206 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(_T_1206, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1206, UInt<1>(0h1), "") : assert_62 node _T_1210 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1211 = asUInt(reset) node _T_1212 = eq(_T_1211, UInt<1>(0h0)) when _T_1212 : node _T_1213 = eq(_T_1210, UInt<1>(0h0)) when _T_1213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1210, UInt<1>(0h1), "") : assert_63 node _T_1214 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1215 = or(UInt<1>(0h1), _T_1214) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_64 node _T_1219 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1219 : node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(source_ok_1, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(sink_ok, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1226 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(_T_1226, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1226, UInt<1>(0h1), "") : assert_67 node _T_1230 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1231 = asUInt(reset) node _T_1232 = eq(_T_1231, UInt<1>(0h0)) when _T_1232 : node _T_1233 = eq(_T_1230, UInt<1>(0h0)) when _T_1233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1230, UInt<1>(0h1), "") : assert_68 node _T_1234 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1235 = asUInt(reset) node _T_1236 = eq(_T_1235, UInt<1>(0h0)) when _T_1236 : node _T_1237 = eq(_T_1234, UInt<1>(0h0)) when _T_1237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1234, UInt<1>(0h1), "") : assert_69 node _T_1238 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1239 = or(_T_1238, io.in.d.bits.corrupt) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_70 node _T_1243 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1244 = or(UInt<1>(0h1), _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_71 node _T_1248 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1248 : node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(source_ok_1, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1252 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_73 node _T_1256 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_74 node _T_1260 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1261 = or(UInt<1>(0h1), _T_1260) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_75 node _T_1265 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1265 : node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(source_ok_1, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1269 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_77 node _T_1273 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1274 = or(_T_1273, io.in.d.bits.corrupt) node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(_T_1274, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1274, UInt<1>(0h1), "") : assert_78 node _T_1278 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1279 = or(UInt<1>(0h1), _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_79 node _T_1283 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1283 : node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(source_ok_1, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1287 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_81 node _T_1291 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_82 node _T_1295 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1296 = or(UInt<1>(0h1), _T_1295) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1300 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1304 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1308 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1312 = eq(a_first, UInt<1>(0h0)) node _T_1313 = and(io.in.a.valid, _T_1312) when _T_1313 : node _T_1314 = eq(io.in.a.bits.opcode, opcode) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_87 node _T_1318 = eq(io.in.a.bits.param, param) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_88 node _T_1322 = eq(io.in.a.bits.size, size) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_89 node _T_1326 = eq(io.in.a.bits.source, source) node _T_1327 = asUInt(reset) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) when _T_1328 : node _T_1329 = eq(_T_1326, UInt<1>(0h0)) when _T_1329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1326, UInt<1>(0h1), "") : assert_90 node _T_1330 = eq(io.in.a.bits.address, address) node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(_T_1330, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1330, UInt<1>(0h1), "") : assert_91 node _T_1334 = and(io.in.a.ready, io.in.a.valid) node _T_1335 = and(_T_1334, a_first) when _T_1335 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1336 = eq(d_first, UInt<1>(0h0)) node _T_1337 = and(io.in.d.valid, _T_1336) when _T_1337 : node _T_1338 = eq(io.in.d.bits.opcode, opcode_1) node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(_T_1338, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1338, UInt<1>(0h1), "") : assert_92 node _T_1342 = eq(io.in.d.bits.param, param_1) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_93 node _T_1346 = eq(io.in.d.bits.size, size_1) node _T_1347 = asUInt(reset) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) when _T_1348 : node _T_1349 = eq(_T_1346, UInt<1>(0h0)) when _T_1349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1346, UInt<1>(0h1), "") : assert_94 node _T_1350 = eq(io.in.d.bits.source, source_1) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_95 node _T_1354 = eq(io.in.d.bits.sink, sink) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_96 node _T_1358 = eq(io.in.d.bits.denied, denied) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_97 node _T_1362 = and(io.in.d.ready, io.in.d.valid) node _T_1363 = and(_T_1362, d_first) when _T_1363 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1364 = and(io.in.a.valid, a_first_1) node _T_1365 = and(_T_1364, UInt<1>(0h1)) when _T_1365 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1366 = and(io.in.a.ready, io.in.a.valid) node _T_1367 = and(_T_1366, a_first_1) node _T_1368 = and(_T_1367, UInt<1>(0h1)) when _T_1368 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1369 = dshr(inflight, io.in.a.bits.source) node _T_1370 = bits(_T_1369, 0, 0) node _T_1371 = eq(_T_1370, UInt<1>(0h0)) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1375 = and(io.in.d.valid, d_first_1) node _T_1376 = and(_T_1375, UInt<1>(0h1)) node _T_1377 = eq(d_release_ack, UInt<1>(0h0)) node _T_1378 = and(_T_1376, _T_1377) when _T_1378 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1379 = and(io.in.d.ready, io.in.d.valid) node _T_1380 = and(_T_1379, d_first_1) node _T_1381 = and(_T_1380, UInt<1>(0h1)) node _T_1382 = eq(d_release_ack, UInt<1>(0h0)) node _T_1383 = and(_T_1381, _T_1382) when _T_1383 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1384 = and(io.in.d.valid, d_first_1) node _T_1385 = and(_T_1384, UInt<1>(0h1)) node _T_1386 = eq(d_release_ack, UInt<1>(0h0)) node _T_1387 = and(_T_1385, _T_1386) when _T_1387 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1388 = dshr(inflight, io.in.d.bits.source) node _T_1389 = bits(_T_1388, 0, 0) node _T_1390 = or(_T_1389, same_cycle_resp) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1394 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1395 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1396 = or(_T_1394, _T_1395) node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(_T_1396, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1396, UInt<1>(0h1), "") : assert_100 node _T_1400 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_101 else : node _T_1404 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1405 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1406 = or(_T_1404, _T_1405) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_102 node _T_1410 = eq(io.in.d.bits.size, a_size_lookup) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_103 node _T_1414 = and(io.in.d.valid, d_first_1) node _T_1415 = and(_T_1414, a_first_1) node _T_1416 = and(_T_1415, io.in.a.valid) node _T_1417 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1418 = and(_T_1416, _T_1417) node _T_1419 = eq(d_release_ack, UInt<1>(0h0)) node _T_1420 = and(_T_1418, _T_1419) when _T_1420 : node _T_1421 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1422 = or(_T_1421, io.in.a.ready) node _T_1423 = asUInt(reset) node _T_1424 = eq(_T_1423, UInt<1>(0h0)) when _T_1424 : node _T_1425 = eq(_T_1422, UInt<1>(0h0)) when _T_1425 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1422, UInt<1>(0h1), "") : assert_104 node _T_1426 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1427 = orr(a_set_wo_ready) node _T_1428 = eq(_T_1427, UInt<1>(0h0)) node _T_1429 = or(_T_1426, _T_1428) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_34 node _T_1433 = orr(inflight) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) node _T_1435 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1436 = or(_T_1434, _T_1435) node _T_1437 = lt(watchdog, plusarg_reader.out) node _T_1438 = or(_T_1436, _T_1437) node _T_1439 = asUInt(reset) node _T_1440 = eq(_T_1439, UInt<1>(0h0)) when _T_1440 : node _T_1441 = eq(_T_1438, UInt<1>(0h0)) when _T_1441 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1438, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1442 = and(io.in.a.ready, io.in.a.valid) node _T_1443 = and(io.in.d.ready, io.in.d.valid) node _T_1444 = or(_T_1442, _T_1443) when _T_1444 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1445 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1446 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1447 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1448 = and(_T_1446, _T_1447) node _T_1449 = and(_T_1445, _T_1448) when _T_1449 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1450 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1451 = and(_T_1450, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1452 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1453 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1454 = and(_T_1452, _T_1453) node _T_1455 = and(_T_1451, _T_1454) when _T_1455 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1456 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1457 = bits(_T_1456, 0, 0) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(_T_1458, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1458, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1462 = and(io.in.d.valid, d_first_2) node _T_1463 = and(_T_1462, UInt<1>(0h1)) node _T_1464 = and(_T_1463, d_release_ack_1) when _T_1464 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1465 = and(io.in.d.ready, io.in.d.valid) node _T_1466 = and(_T_1465, d_first_2) node _T_1467 = and(_T_1466, UInt<1>(0h1)) node _T_1468 = and(_T_1467, d_release_ack_1) when _T_1468 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1469 = and(io.in.d.valid, d_first_2) node _T_1470 = and(_T_1469, UInt<1>(0h1)) node _T_1471 = and(_T_1470, d_release_ack_1) when _T_1471 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1472 = dshr(inflight_1, io.in.d.bits.source) node _T_1473 = bits(_T_1472, 0, 0) node _T_1474 = or(_T_1473, same_cycle_resp_1) node _T_1475 = asUInt(reset) node _T_1476 = eq(_T_1475, UInt<1>(0h0)) when _T_1476 : node _T_1477 = eq(_T_1474, UInt<1>(0h0)) when _T_1477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1474, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1478 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(_T_1478, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1478, UInt<1>(0h1), "") : assert_109 else : node _T_1482 = eq(io.in.d.bits.size, c_size_lookup) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_110 node _T_1486 = and(io.in.d.valid, d_first_2) node _T_1487 = and(_T_1486, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1488 = and(_T_1487, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1489 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1490 = and(_T_1488, _T_1489) node _T_1491 = and(_T_1490, d_release_ack_1) node _T_1492 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1493 = and(_T_1491, _T_1492) when _T_1493 : node _T_1494 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1495 = or(_T_1494, _WIRE_23.ready) node _T_1496 = asUInt(reset) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) when _T_1497 : node _T_1498 = eq(_T_1495, UInt<1>(0h0)) when _T_1498 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1495, UInt<1>(0h1), "") : assert_111 node _T_1499 = orr(c_set_wo_ready) when _T_1499 : node _T_1500 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1501 = asUInt(reset) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) when _T_1502 : node _T_1503 = eq(_T_1500, UInt<1>(0h0)) when _T_1503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1500, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_35 node _T_1504 = orr(inflight_1) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) node _T_1506 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1507 = or(_T_1505, _T_1506) node _T_1508 = lt(watchdog_1, plusarg_reader_1.out) node _T_1509 = or(_T_1507, _T_1508) node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(_T_1509, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1509, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1513 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1514 = and(io.in.d.ready, io.in.d.valid) node _T_1515 = or(_T_1513, _T_1514) when _T_1515 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_17( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_1442 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1442; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1442; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1515 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1515; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1515; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1515; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1368 = _T_1442 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1368 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1368 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1368 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1368 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1368 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1414 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1414 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1383 = _T_1515 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1383 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1383 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1383 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1486 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1486 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1468 = _T_1515 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1468 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1468 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1468 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_39 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_EntryData_39( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_47 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_95 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_47( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_95 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_30 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_30( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_49 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_49( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_307 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_307( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module PE_363 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_107 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_363( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_107 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_137 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_393 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_137( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_393 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_31 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_31( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n0x0_8 : output auto : { } wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset	module IntSyncSyncCrossingSink_n0x0_8(); // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_15 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_30 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_15 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0hc), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0he), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h7) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0hc), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0hb), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0hc), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0hc), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h7)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) node _T_16 = eq(UInt<4>(0h8), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(route_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_31 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_15 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_24 = and(vcalloc_q.io.enq.valid, _T_23) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_25, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node c_lo = cat(c_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _c_T = cat(c_hi, c_lo) node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node c_lo_1 = cat(c_lo_hi_1, io.out_credit_available.`0`[0]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_1 = cat(c_hi_hi_1, io.out_credit_available.`0`[3]) node _c_T_2 = cat(c_hi_1, c_lo_1) node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_channel_oh_0 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 5, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_10 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_15( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hC; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 4'h9 : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 4'hA : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'hB : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hC : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h7; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h7; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_fbus_from_debug_sb : input clock : Clock input reset : Reset output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} inst widget of TLWidthWidget1 connect widget.clock, clock connect widget.reset, reset wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlOut.d.bits.corrupt invalidate tlOut.d.bits.data invalidate tlOut.d.bits.denied invalidate tlOut.d.bits.sink invalidate tlOut.d.bits.source invalidate tlOut.d.bits.size invalidate tlOut.d.bits.param invalidate tlOut.d.bits.opcode invalidate tlOut.d.valid invalidate tlOut.d.ready invalidate tlOut.a.bits.corrupt invalidate tlOut.a.bits.data invalidate tlOut.a.bits.mask invalidate tlOut.a.bits.address invalidate tlOut.a.bits.source invalidate tlOut.a.bits.size invalidate tlOut.a.bits.param invalidate tlOut.a.bits.opcode invalidate tlOut.a.valid invalidate tlOut.a.ready wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlIn.d.bits.corrupt invalidate tlIn.d.bits.data invalidate tlIn.d.bits.denied invalidate tlIn.d.bits.sink invalidate tlIn.d.bits.source invalidate tlIn.d.bits.size invalidate tlIn.d.bits.param invalidate tlIn.d.bits.opcode invalidate tlIn.d.valid invalidate tlIn.d.ready invalidate tlIn.a.bits.corrupt invalidate tlIn.a.bits.data invalidate tlIn.a.bits.mask invalidate tlIn.a.bits.address invalidate tlIn.a.bits.source invalidate tlIn.a.bits.size invalidate tlIn.a.bits.param invalidate tlIn.a.bits.opcode invalidate tlIn.a.valid invalidate tlIn.a.ready connect tlOut, tlIn connect widget.auto.anon_out.d, tlIn.d connect tlIn.a.bits, widget.auto.anon_out.a.bits connect tlIn.a.valid, widget.auto.anon_out.a.valid connect widget.auto.anon_out.a.ready, tlIn.a.ready connect auto.tl_out, tlOut connect widget.auto.anon_in, auto.widget_anon_in extmodule plusarg_reader_41 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_42 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLInterconnectCoupler_fbus_from_debug_sb( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [31:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_widget_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_widget_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [7:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); TLWidthWidget1 widget ( // @[WidthWidget.scala:230:28] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_widget_anon_in_a_ready), .auto_anon_in_a_valid (auto_widget_anon_in_a_valid), .auto_anon_in_a_bits_opcode (auto_widget_anon_in_a_bits_opcode), .auto_anon_in_a_bits_size (auto_widget_anon_in_a_bits_size), .auto_anon_in_a_bits_address (auto_widget_anon_in_a_bits_address), .auto_anon_in_a_bits_data (auto_widget_anon_in_a_bits_data), .auto_anon_in_d_ready (auto_widget_anon_in_d_ready), .auto_anon_in_d_valid (auto_widget_anon_in_d_valid), .auto_anon_in_d_bits_opcode (auto_widget_anon_in_d_bits_opcode), .auto_anon_in_d_bits_param (auto_widget_anon_in_d_bits_param), .auto_anon_in_d_bits_size (auto_widget_anon_in_d_bits_size), .auto_anon_in_d_bits_sink (auto_widget_anon_in_d_bits_sink), .auto_anon_in_d_bits_denied (auto_widget_anon_in_d_bits_denied), .auto_anon_in_d_bits_data (auto_widget_anon_in_d_bits_data), .auto_anon_in_d_bits_corrupt (auto_widget_anon_in_d_bits_corrupt), .auto_anon_out_a_ready (auto_tl_out_a_ready), .auto_anon_out_a_valid (auto_tl_out_a_valid), .auto_anon_out_a_bits_opcode (auto_tl_out_a_bits_opcode), .auto_anon_out_a_bits_size (auto_tl_out_a_bits_size), .auto_anon_out_a_bits_address (auto_tl_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_tl_out_a_bits_mask), .auto_anon_out_a_bits_data (auto_tl_out_a_bits_data), .auto_anon_out_d_ready (auto_tl_out_d_ready), .auto_anon_out_d_valid (auto_tl_out_d_valid), .auto_anon_out_d_bits_opcode (auto_tl_out_d_bits_opcode), .auto_anon_out_d_bits_param (auto_tl_out_d_bits_param), .auto_anon_out_d_bits_size (auto_tl_out_d_bits_size), .auto_anon_out_d_bits_sink (auto_tl_out_d_bits_sink), .auto_anon_out_d_bits_denied (auto_tl_out_d_bits_denied), .auto_anon_out_d_bits_data (auto_tl_out_d_bits_data), .auto_anon_out_d_bits_corrupt (auto_tl_out_d_bits_corrupt) ); // @[WidthWidget.scala:230:28] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_266 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_283 connect io_out_sink_extend.clock, clock connect io_out_sink_extend.reset, reset connect io_out_sink_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_extend.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_266( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_283 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AXI4UserYanker_2 : input clock : Clock input reset : Reset output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<8>}, extra_id : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<8>}, extra_id : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<8>}, extra_id : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<8>}, extra_id : UInt<1>}, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<8>}, extra_id : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<8>}, extra_id : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<8>}, extra_id : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { tl_state : { size : UInt<4>, source : UInt<8>}, extra_id : UInt<1>}, last : UInt<1>}}} invalidate nodeIn.r.bits.last invalidate nodeIn.r.bits.echo.extra_id invalidate nodeIn.r.bits.echo.tl_state.source invalidate nodeIn.r.bits.echo.tl_state.size invalidate nodeIn.r.bits.resp invalidate nodeIn.r.bits.data invalidate nodeIn.r.bits.id invalidate nodeIn.r.valid invalidate nodeIn.r.ready invalidate nodeIn.ar.bits.echo.extra_id invalidate nodeIn.ar.bits.echo.tl_state.source invalidate nodeIn.ar.bits.echo.tl_state.size invalidate nodeIn.ar.bits.qos invalidate nodeIn.ar.bits.prot invalidate nodeIn.ar.bits.cache invalidate nodeIn.ar.bits.lock invalidate nodeIn.ar.bits.burst invalidate nodeIn.ar.bits.size invalidate nodeIn.ar.bits.len invalidate nodeIn.ar.bits.addr invalidate nodeIn.ar.bits.id invalidate nodeIn.ar.valid invalidate nodeIn.ar.ready invalidate nodeIn.b.bits.echo.extra_id invalidate nodeIn.b.bits.echo.tl_state.source invalidate nodeIn.b.bits.echo.tl_state.size invalidate nodeIn.b.bits.resp invalidate nodeIn.b.bits.id invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.w.bits.last invalidate nodeIn.w.bits.strb invalidate nodeIn.w.bits.data invalidate nodeIn.w.valid invalidate nodeIn.w.ready invalidate nodeIn.aw.bits.echo.extra_id invalidate nodeIn.aw.bits.echo.tl_state.source invalidate nodeIn.aw.bits.echo.tl_state.size invalidate nodeIn.aw.bits.qos invalidate nodeIn.aw.bits.prot invalidate nodeIn.aw.bits.cache invalidate nodeIn.aw.bits.lock invalidate nodeIn.aw.bits.burst invalidate nodeIn.aw.bits.size invalidate nodeIn.aw.bits.len invalidate nodeIn.aw.bits.addr invalidate nodeIn.aw.bits.id invalidate nodeIn.aw.valid invalidate nodeIn.aw.ready wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<7>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate nodeOut.r.bits.last invalidate nodeOut.r.bits.resp invalidate nodeOut.r.bits.data invalidate nodeOut.r.bits.id invalidate nodeOut.r.valid invalidate nodeOut.r.ready invalidate nodeOut.ar.bits.qos invalidate nodeOut.ar.bits.prot invalidate nodeOut.ar.bits.cache invalidate nodeOut.ar.bits.lock invalidate nodeOut.ar.bits.burst invalidate nodeOut.ar.bits.size invalidate nodeOut.ar.bits.len invalidate nodeOut.ar.bits.addr invalidate nodeOut.ar.bits.id invalidate nodeOut.ar.valid invalidate nodeOut.ar.ready invalidate nodeOut.b.bits.resp invalidate nodeOut.b.bits.id invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.w.bits.last invalidate nodeOut.w.bits.strb invalidate nodeOut.w.bits.data invalidate nodeOut.w.valid invalidate nodeOut.w.ready invalidate nodeOut.aw.bits.qos invalidate nodeOut.aw.bits.prot invalidate nodeOut.aw.bits.cache invalidate nodeOut.aw.bits.lock invalidate nodeOut.aw.bits.burst invalidate nodeOut.aw.bits.size invalidate nodeOut.aw.bits.len invalidate nodeOut.aw.bits.addr invalidate nodeOut.aw.bits.id invalidate nodeOut.aw.valid invalidate nodeOut.aw.ready connect auto.out, nodeOut connect nodeIn, auto.in inst Queue2_BundleMap of Queue2_BundleMap_464 connect Queue2_BundleMap.clock, clock connect Queue2_BundleMap.reset, reset inst Queue2_BundleMap_1 of Queue2_BundleMap_465 connect Queue2_BundleMap_1.clock, clock connect Queue2_BundleMap_1.reset, reset inst Queue2_BundleMap_2 of Queue2_BundleMap_466 connect Queue2_BundleMap_2.clock, clock connect Queue2_BundleMap_2.reset, reset inst Queue2_BundleMap_3 of Queue2_BundleMap_467 connect Queue2_BundleMap_3.clock, clock connect Queue2_BundleMap_3.reset, reset inst Queue2_BundleMap_4 of Queue2_BundleMap_468 connect Queue2_BundleMap_4.clock, clock connect Queue2_BundleMap_4.reset, reset inst Queue2_BundleMap_5 of Queue2_BundleMap_469 connect Queue2_BundleMap_5.clock, clock connect Queue2_BundleMap_5.reset, reset inst Queue2_BundleMap_6 of Queue2_BundleMap_470 connect Queue2_BundleMap_6.clock, clock connect Queue2_BundleMap_6.reset, reset inst Queue2_BundleMap_7 of Queue2_BundleMap_471 connect Queue2_BundleMap_7.clock, clock connect Queue2_BundleMap_7.reset, reset inst Queue2_BundleMap_8 of Queue2_BundleMap_472 connect Queue2_BundleMap_8.clock, clock connect Queue2_BundleMap_8.reset, reset inst Queue2_BundleMap_9 of Queue2_BundleMap_473 connect Queue2_BundleMap_9.clock, clock connect Queue2_BundleMap_9.reset, reset inst Queue2_BundleMap_10 of Queue2_BundleMap_474 connect Queue2_BundleMap_10.clock, clock connect Queue2_BundleMap_10.reset, reset inst Queue2_BundleMap_11 of Queue2_BundleMap_475 connect Queue2_BundleMap_11.clock, clock connect Queue2_BundleMap_11.reset, reset inst Queue2_BundleMap_12 of Queue2_BundleMap_476 connect Queue2_BundleMap_12.clock, clock connect Queue2_BundleMap_12.reset, reset inst Queue2_BundleMap_13 of Queue2_BundleMap_477 connect Queue2_BundleMap_13.clock, clock connect Queue2_BundleMap_13.reset, reset inst Queue2_BundleMap_14 of Queue2_BundleMap_478 connect Queue2_BundleMap_14.clock, clock connect Queue2_BundleMap_14.reset, reset inst Queue2_BundleMap_15 of Queue2_BundleMap_479 connect Queue2_BundleMap_15.clock, clock connect Queue2_BundleMap_15.reset, reset inst Queue2_BundleMap_16 of Queue2_BundleMap_480 connect Queue2_BundleMap_16.clock, clock connect Queue2_BundleMap_16.reset, reset inst Queue2_BundleMap_17 of Queue2_BundleMap_481 connect Queue2_BundleMap_17.clock, clock connect Queue2_BundleMap_17.reset, reset inst Queue2_BundleMap_18 of Queue2_BundleMap_482 connect Queue2_BundleMap_18.clock, clock connect Queue2_BundleMap_18.reset, reset inst Queue2_BundleMap_19 of Queue2_BundleMap_483 connect Queue2_BundleMap_19.clock, clock connect Queue2_BundleMap_19.reset, reset inst Queue2_BundleMap_20 of Queue2_BundleMap_484 connect Queue2_BundleMap_20.clock, clock connect Queue2_BundleMap_20.reset, reset inst Queue2_BundleMap_21 of Queue2_BundleMap_485 connect Queue2_BundleMap_21.clock, clock connect Queue2_BundleMap_21.reset, reset inst Queue2_BundleMap_22 of Queue2_BundleMap_486 connect Queue2_BundleMap_22.clock, clock connect Queue2_BundleMap_22.reset, reset inst Queue2_BundleMap_23 of Queue2_BundleMap_487 connect Queue2_BundleMap_23.clock, clock connect Queue2_BundleMap_23.reset, reset inst Queue2_BundleMap_24 of Queue2_BundleMap_488 connect Queue2_BundleMap_24.clock, clock connect Queue2_BundleMap_24.reset, reset inst Queue2_BundleMap_25 of Queue2_BundleMap_489 connect Queue2_BundleMap_25.clock, clock connect Queue2_BundleMap_25.reset, reset inst Queue2_BundleMap_26 of Queue2_BundleMap_490 connect Queue2_BundleMap_26.clock, clock connect Queue2_BundleMap_26.reset, reset inst Queue2_BundleMap_27 of Queue2_BundleMap_491 connect Queue2_BundleMap_27.clock, clock connect Queue2_BundleMap_27.reset, reset inst Queue2_BundleMap_28 of Queue2_BundleMap_492 connect Queue2_BundleMap_28.clock, clock connect Queue2_BundleMap_28.reset, reset inst Queue2_BundleMap_29 of Queue2_BundleMap_493 connect Queue2_BundleMap_29.clock, clock connect Queue2_BundleMap_29.reset, reset inst Queue2_BundleMap_30 of Queue2_BundleMap_494 connect Queue2_BundleMap_30.clock, clock connect Queue2_BundleMap_30.reset, reset inst Queue2_BundleMap_31 of Queue2_BundleMap_495 connect Queue2_BundleMap_31.clock, clock connect Queue2_BundleMap_31.reset, reset inst Queue2_BundleMap_32 of Queue2_BundleMap_496 connect Queue2_BundleMap_32.clock, clock connect Queue2_BundleMap_32.reset, reset inst Queue2_BundleMap_33 of Queue2_BundleMap_497 connect Queue2_BundleMap_33.clock, clock connect Queue2_BundleMap_33.reset, reset inst Queue2_BundleMap_34 of Queue2_BundleMap_498 connect Queue2_BundleMap_34.clock, clock connect Queue2_BundleMap_34.reset, reset inst Queue2_BundleMap_35 of Queue2_BundleMap_499 connect Queue2_BundleMap_35.clock, clock connect Queue2_BundleMap_35.reset, reset inst Queue2_BundleMap_36 of Queue2_BundleMap_500 connect Queue2_BundleMap_36.clock, clock connect Queue2_BundleMap_36.reset, reset inst Queue2_BundleMap_37 of Queue2_BundleMap_501 connect Queue2_BundleMap_37.clock, clock connect Queue2_BundleMap_37.reset, reset inst Queue2_BundleMap_38 of Queue2_BundleMap_502 connect Queue2_BundleMap_38.clock, clock connect Queue2_BundleMap_38.reset, reset inst Queue2_BundleMap_39 of Queue2_BundleMap_503 connect Queue2_BundleMap_39.clock, clock connect Queue2_BundleMap_39.reset, reset inst Queue2_BundleMap_40 of Queue2_BundleMap_504 connect Queue2_BundleMap_40.clock, clock connect Queue2_BundleMap_40.reset, reset inst Queue2_BundleMap_41 of Queue2_BundleMap_505 connect Queue2_BundleMap_41.clock, clock connect Queue2_BundleMap_41.reset, reset inst Queue2_BundleMap_42 of Queue2_BundleMap_506 connect Queue2_BundleMap_42.clock, clock connect Queue2_BundleMap_42.reset, reset inst Queue2_BundleMap_43 of Queue2_BundleMap_507 connect Queue2_BundleMap_43.clock, clock connect Queue2_BundleMap_43.reset, reset inst Queue2_BundleMap_44 of Queue2_BundleMap_508 connect Queue2_BundleMap_44.clock, clock connect Queue2_BundleMap_44.reset, reset inst Queue2_BundleMap_45 of Queue2_BundleMap_509 connect Queue2_BundleMap_45.clock, clock connect Queue2_BundleMap_45.reset, reset inst Queue2_BundleMap_46 of Queue2_BundleMap_510 connect Queue2_BundleMap_46.clock, clock connect Queue2_BundleMap_46.reset, reset inst Queue2_BundleMap_47 of Queue2_BundleMap_511 connect Queue2_BundleMap_47.clock, clock connect Queue2_BundleMap_47.reset, reset inst Queue2_BundleMap_48 of Queue2_BundleMap_512 connect Queue2_BundleMap_48.clock, clock connect Queue2_BundleMap_48.reset, reset inst Queue2_BundleMap_49 of Queue2_BundleMap_513 connect Queue2_BundleMap_49.clock, clock connect Queue2_BundleMap_49.reset, reset inst Queue2_BundleMap_50 of Queue2_BundleMap_514 connect Queue2_BundleMap_50.clock, clock connect Queue2_BundleMap_50.reset, reset inst Queue2_BundleMap_51 of Queue2_BundleMap_515 connect Queue2_BundleMap_51.clock, clock connect Queue2_BundleMap_51.reset, reset inst Queue2_BundleMap_52 of Queue2_BundleMap_516 connect Queue2_BundleMap_52.clock, clock connect Queue2_BundleMap_52.reset, reset inst Queue2_BundleMap_53 of Queue2_BundleMap_517 connect Queue2_BundleMap_53.clock, clock connect Queue2_BundleMap_53.reset, reset inst Queue2_BundleMap_54 of Queue2_BundleMap_518 connect Queue2_BundleMap_54.clock, clock connect Queue2_BundleMap_54.reset, reset inst Queue2_BundleMap_55 of Queue2_BundleMap_519 connect Queue2_BundleMap_55.clock, clock connect Queue2_BundleMap_55.reset, reset inst Queue2_BundleMap_56 of Queue2_BundleMap_520 connect Queue2_BundleMap_56.clock, clock connect Queue2_BundleMap_56.reset, reset inst Queue2_BundleMap_57 of Queue2_BundleMap_521 connect Queue2_BundleMap_57.clock, clock connect Queue2_BundleMap_57.reset, reset inst Queue2_BundleMap_58 of Queue2_BundleMap_522 connect Queue2_BundleMap_58.clock, clock connect Queue2_BundleMap_58.reset, reset inst Queue2_BundleMap_59 of Queue2_BundleMap_523 connect Queue2_BundleMap_59.clock, clock connect Queue2_BundleMap_59.reset, reset inst Queue2_BundleMap_60 of Queue2_BundleMap_524 connect Queue2_BundleMap_60.clock, clock connect Queue2_BundleMap_60.reset, reset inst Queue2_BundleMap_61 of Queue2_BundleMap_525 connect Queue2_BundleMap_61.clock, clock connect Queue2_BundleMap_61.reset, reset inst Queue2_BundleMap_62 of Queue2_BundleMap_526 connect Queue2_BundleMap_62.clock, clock connect Queue2_BundleMap_62.reset, reset inst Queue2_BundleMap_63 of Queue2_BundleMap_527 connect Queue2_BundleMap_63.clock, clock connect Queue2_BundleMap_63.reset, reset inst Queue2_BundleMap_64 of Queue2_BundleMap_528 connect Queue2_BundleMap_64.clock, clock connect Queue2_BundleMap_64.reset, reset inst Queue2_BundleMap_65 of Queue2_BundleMap_529 connect Queue2_BundleMap_65.clock, clock connect Queue2_BundleMap_65.reset, reset inst Queue2_BundleMap_66 of Queue2_BundleMap_530 connect Queue2_BundleMap_66.clock, clock connect Queue2_BundleMap_66.reset, reset inst Queue2_BundleMap_67 of Queue2_BundleMap_531 connect Queue2_BundleMap_67.clock, clock connect Queue2_BundleMap_67.reset, reset inst Queue2_BundleMap_68 of Queue2_BundleMap_532 connect Queue2_BundleMap_68.clock, clock connect Queue2_BundleMap_68.reset, reset inst Queue2_BundleMap_69 of Queue2_BundleMap_533 connect Queue2_BundleMap_69.clock, clock connect Queue2_BundleMap_69.reset, reset inst Queue2_BundleMap_70 of Queue2_BundleMap_534 connect Queue2_BundleMap_70.clock, clock connect Queue2_BundleMap_70.reset, reset inst Queue2_BundleMap_71 of Queue2_BundleMap_535 connect Queue2_BundleMap_71.clock, clock connect Queue2_BundleMap_71.reset, reset inst Queue2_BundleMap_72 of Queue2_BundleMap_536 connect Queue2_BundleMap_72.clock, clock connect Queue2_BundleMap_72.reset, reset inst Queue2_BundleMap_73 of Queue2_BundleMap_537 connect Queue2_BundleMap_73.clock, clock connect Queue2_BundleMap_73.reset, reset inst Queue2_BundleMap_74 of Queue2_BundleMap_538 connect Queue2_BundleMap_74.clock, clock connect Queue2_BundleMap_74.reset, reset inst Queue2_BundleMap_75 of Queue2_BundleMap_539 connect Queue2_BundleMap_75.clock, clock connect Queue2_BundleMap_75.reset, reset inst Queue2_BundleMap_76 of Queue2_BundleMap_540 connect Queue2_BundleMap_76.clock, clock connect Queue2_BundleMap_76.reset, reset inst Queue2_BundleMap_77 of Queue2_BundleMap_541 connect Queue2_BundleMap_77.clock, clock connect Queue2_BundleMap_77.reset, reset inst Queue2_BundleMap_78 of Queue2_BundleMap_542 connect Queue2_BundleMap_78.clock, clock connect Queue2_BundleMap_78.reset, reset inst Queue2_BundleMap_79 of Queue2_BundleMap_543 connect Queue2_BundleMap_79.clock, clock connect Queue2_BundleMap_79.reset, reset inst Queue2_BundleMap_80 of Queue2_BundleMap_544 connect Queue2_BundleMap_80.clock, clock connect Queue2_BundleMap_80.reset, reset inst Queue2_BundleMap_81 of Queue2_BundleMap_545 connect Queue2_BundleMap_81.clock, clock connect Queue2_BundleMap_81.reset, reset inst Queue2_BundleMap_82 of Queue2_BundleMap_546 connect Queue2_BundleMap_82.clock, clock connect Queue2_BundleMap_82.reset, reset inst Queue2_BundleMap_83 of Queue2_BundleMap_547 connect Queue2_BundleMap_83.clock, clock connect Queue2_BundleMap_83.reset, reset inst Queue2_BundleMap_84 of Queue2_BundleMap_548 connect Queue2_BundleMap_84.clock, clock connect Queue2_BundleMap_84.reset, reset inst Queue2_BundleMap_85 of Queue2_BundleMap_549 connect Queue2_BundleMap_85.clock, clock connect Queue2_BundleMap_85.reset, reset inst Queue2_BundleMap_86 of Queue2_BundleMap_550 connect Queue2_BundleMap_86.clock, clock connect Queue2_BundleMap_86.reset, reset inst Queue2_BundleMap_87 of Queue2_BundleMap_551 connect Queue2_BundleMap_87.clock, clock connect Queue2_BundleMap_87.reset, reset inst Queue2_BundleMap_88 of Queue2_BundleMap_552 connect Queue2_BundleMap_88.clock, clock connect Queue2_BundleMap_88.reset, reset inst Queue2_BundleMap_89 of Queue2_BundleMap_553 connect Queue2_BundleMap_89.clock, clock connect Queue2_BundleMap_89.reset, reset inst Queue2_BundleMap_90 of Queue2_BundleMap_554 connect Queue2_BundleMap_90.clock, clock connect Queue2_BundleMap_90.reset, reset inst Queue2_BundleMap_91 of Queue2_BundleMap_555 connect Queue2_BundleMap_91.clock, clock connect Queue2_BundleMap_91.reset, reset inst Queue2_BundleMap_92 of Queue2_BundleMap_556 connect Queue2_BundleMap_92.clock, clock connect Queue2_BundleMap_92.reset, reset inst Queue2_BundleMap_93 of Queue2_BundleMap_557 connect Queue2_BundleMap_93.clock, clock connect Queue2_BundleMap_93.reset, reset inst Queue2_BundleMap_94 of Queue2_BundleMap_558 connect Queue2_BundleMap_94.clock, clock connect Queue2_BundleMap_94.reset, reset inst Queue2_BundleMap_95 of Queue2_BundleMap_559 connect Queue2_BundleMap_95.clock, clock connect Queue2_BundleMap_95.reset, reset inst Queue2_BundleMap_96 of Queue2_BundleMap_560 connect Queue2_BundleMap_96.clock, clock connect Queue2_BundleMap_96.reset, reset inst Queue2_BundleMap_97 of Queue2_BundleMap_561 connect Queue2_BundleMap_97.clock, clock connect Queue2_BundleMap_97.reset, reset inst Queue2_BundleMap_98 of Queue2_BundleMap_562 connect Queue2_BundleMap_98.clock, clock connect Queue2_BundleMap_98.reset, reset inst Queue2_BundleMap_99 of Queue2_BundleMap_563 connect Queue2_BundleMap_99.clock, clock connect Queue2_BundleMap_99.reset, reset inst Queue2_BundleMap_100 of Queue2_BundleMap_564 connect Queue2_BundleMap_100.clock, clock connect Queue2_BundleMap_100.reset, reset inst Queue2_BundleMap_101 of Queue2_BundleMap_565 connect Queue2_BundleMap_101.clock, clock connect Queue2_BundleMap_101.reset, reset inst Queue2_BundleMap_102 of Queue2_BundleMap_566 connect Queue2_BundleMap_102.clock, clock connect Queue2_BundleMap_102.reset, reset inst Queue2_BundleMap_103 of Queue2_BundleMap_567 connect Queue2_BundleMap_103.clock, clock connect Queue2_BundleMap_103.reset, reset inst Queue2_BundleMap_104 of Queue2_BundleMap_568 connect Queue2_BundleMap_104.clock, clock connect Queue2_BundleMap_104.reset, reset inst Queue2_BundleMap_105 of Queue2_BundleMap_569 connect Queue2_BundleMap_105.clock, clock connect Queue2_BundleMap_105.reset, reset inst Queue2_BundleMap_106 of Queue2_BundleMap_570 connect Queue2_BundleMap_106.clock, clock connect Queue2_BundleMap_106.reset, reset inst Queue2_BundleMap_107 of Queue2_BundleMap_571 connect Queue2_BundleMap_107.clock, clock connect Queue2_BundleMap_107.reset, reset inst Queue2_BundleMap_108 of Queue2_BundleMap_572 connect Queue2_BundleMap_108.clock, clock connect Queue2_BundleMap_108.reset, reset inst Queue2_BundleMap_109 of Queue2_BundleMap_573 connect Queue2_BundleMap_109.clock, clock connect Queue2_BundleMap_109.reset, reset inst Queue2_BundleMap_110 of Queue2_BundleMap_574 connect Queue2_BundleMap_110.clock, clock connect Queue2_BundleMap_110.reset, reset inst Queue2_BundleMap_111 of Queue2_BundleMap_575 connect Queue2_BundleMap_111.clock, clock connect Queue2_BundleMap_111.reset, reset inst Queue2_BundleMap_112 of Queue2_BundleMap_576 connect Queue2_BundleMap_112.clock, clock connect Queue2_BundleMap_112.reset, reset inst Queue2_BundleMap_113 of Queue2_BundleMap_577 connect Queue2_BundleMap_113.clock, clock connect Queue2_BundleMap_113.reset, reset inst Queue2_BundleMap_114 of Queue2_BundleMap_578 connect Queue2_BundleMap_114.clock, clock connect Queue2_BundleMap_114.reset, reset inst Queue2_BundleMap_115 of Queue2_BundleMap_579 connect Queue2_BundleMap_115.clock, clock connect Queue2_BundleMap_115.reset, reset inst Queue1_BundleMap of Queue1_BundleMap_48 connect Queue1_BundleMap.clock, clock connect Queue1_BundleMap.reset, reset inst Queue1_BundleMap_1 of Queue1_BundleMap_49 connect Queue1_BundleMap_1.clock, clock connect Queue1_BundleMap_1.reset, reset inst Queue1_BundleMap_2 of Queue1_BundleMap_50 connect Queue1_BundleMap_2.clock, clock connect Queue1_BundleMap_2.reset, reset inst Queue1_BundleMap_3 of Queue1_BundleMap_51 connect Queue1_BundleMap_3.clock, clock connect Queue1_BundleMap_3.reset, reset inst Queue1_BundleMap_4 of Queue1_BundleMap_52 connect Queue1_BundleMap_4.clock, clock connect Queue1_BundleMap_4.reset, reset inst Queue1_BundleMap_5 of Queue1_BundleMap_53 connect Queue1_BundleMap_5.clock, clock connect Queue1_BundleMap_5.reset, reset inst Queue1_BundleMap_6 of Queue1_BundleMap_54 connect Queue1_BundleMap_6.clock, clock connect Queue1_BundleMap_6.reset, reset inst Queue1_BundleMap_7 of Queue1_BundleMap_55 connect Queue1_BundleMap_7.clock, clock connect Queue1_BundleMap_7.reset, reset inst Queue1_BundleMap_8 of Queue1_BundleMap_56 connect Queue1_BundleMap_8.clock, clock connect Queue1_BundleMap_8.reset, reset inst Queue1_BundleMap_9 of Queue1_BundleMap_57 connect Queue1_BundleMap_9.clock, clock connect Queue1_BundleMap_9.reset, reset inst Queue1_BundleMap_10 of Queue1_BundleMap_58 connect Queue1_BundleMap_10.clock, clock connect Queue1_BundleMap_10.reset, reset inst Queue1_BundleMap_11 of Queue1_BundleMap_59 connect Queue1_BundleMap_11.clock, clock connect Queue1_BundleMap_11.reset, reset inst Queue2_BundleMap_116 of Queue2_BundleMap_580 connect Queue2_BundleMap_116.clock, clock connect Queue2_BundleMap_116.reset, reset inst Queue2_BundleMap_117 of Queue2_BundleMap_581 connect Queue2_BundleMap_117.clock, clock connect Queue2_BundleMap_117.reset, reset inst Queue2_BundleMap_118 of Queue2_BundleMap_582 connect Queue2_BundleMap_118.clock, clock connect Queue2_BundleMap_118.reset, reset inst Queue2_BundleMap_119 of Queue2_BundleMap_583 connect Queue2_BundleMap_119.clock, clock connect Queue2_BundleMap_119.reset, reset inst Queue2_BundleMap_120 of Queue2_BundleMap_584 connect Queue2_BundleMap_120.clock, clock connect Queue2_BundleMap_120.reset, reset inst Queue2_BundleMap_121 of Queue2_BundleMap_585 connect Queue2_BundleMap_121.clock, clock connect Queue2_BundleMap_121.reset, reset inst Queue2_BundleMap_122 of Queue2_BundleMap_586 connect Queue2_BundleMap_122.clock, clock connect Queue2_BundleMap_122.reset, reset inst Queue2_BundleMap_123 of Queue2_BundleMap_587 connect Queue2_BundleMap_123.clock, clock connect Queue2_BundleMap_123.reset, reset inst Queue2_BundleMap_124 of Queue2_BundleMap_588 connect Queue2_BundleMap_124.clock, clock connect Queue2_BundleMap_124.reset, reset inst Queue2_BundleMap_125 of Queue2_BundleMap_589 connect Queue2_BundleMap_125.clock, clock connect Queue2_BundleMap_125.reset, reset inst Queue2_BundleMap_126 of Queue2_BundleMap_590 connect Queue2_BundleMap_126.clock, clock connect Queue2_BundleMap_126.reset, reset inst Queue2_BundleMap_127 of Queue2_BundleMap_591 connect Queue2_BundleMap_127.clock, clock connect Queue2_BundleMap_127.reset, reset inst Queue2_BundleMap_128 of Queue2_BundleMap_592 connect Queue2_BundleMap_128.clock, clock connect Queue2_BundleMap_128.reset, reset inst Queue2_BundleMap_129 of Queue2_BundleMap_593 connect Queue2_BundleMap_129.clock, clock connect Queue2_BundleMap_129.reset, reset inst Queue2_BundleMap_130 of Queue2_BundleMap_594 connect Queue2_BundleMap_130.clock, clock connect Queue2_BundleMap_130.reset, reset inst Queue2_BundleMap_131 of Queue2_BundleMap_595 connect Queue2_BundleMap_131.clock, clock connect Queue2_BundleMap_131.reset, reset inst Queue2_BundleMap_132 of Queue2_BundleMap_596 connect Queue2_BundleMap_132.clock, clock connect Queue2_BundleMap_132.reset, reset inst Queue2_BundleMap_133 of Queue2_BundleMap_597 connect Queue2_BundleMap_133.clock, clock connect Queue2_BundleMap_133.reset, reset inst Queue2_BundleMap_134 of Queue2_BundleMap_598 connect Queue2_BundleMap_134.clock, clock connect Queue2_BundleMap_134.reset, reset inst Queue2_BundleMap_135 of Queue2_BundleMap_599 connect Queue2_BundleMap_135.clock, clock connect Queue2_BundleMap_135.reset, reset inst Queue2_BundleMap_136 of Queue2_BundleMap_600 connect Queue2_BundleMap_136.clock, clock connect Queue2_BundleMap_136.reset, reset inst Queue2_BundleMap_137 of Queue2_BundleMap_601 connect Queue2_BundleMap_137.clock, clock connect Queue2_BundleMap_137.reset, reset inst Queue2_BundleMap_138 of Queue2_BundleMap_602 connect Queue2_BundleMap_138.clock, clock connect Queue2_BundleMap_138.reset, reset inst Queue2_BundleMap_139 of Queue2_BundleMap_603 connect Queue2_BundleMap_139.clock, clock connect Queue2_BundleMap_139.reset, reset inst Queue2_BundleMap_140 of Queue2_BundleMap_604 connect Queue2_BundleMap_140.clock, clock connect Queue2_BundleMap_140.reset, reset inst Queue2_BundleMap_141 of Queue2_BundleMap_605 connect Queue2_BundleMap_141.clock, clock connect Queue2_BundleMap_141.reset, reset inst Queue2_BundleMap_142 of Queue2_BundleMap_606 connect Queue2_BundleMap_142.clock, clock connect Queue2_BundleMap_142.reset, reset inst Queue2_BundleMap_143 of Queue2_BundleMap_607 connect Queue2_BundleMap_143.clock, clock connect Queue2_BundleMap_143.reset, reset inst Queue2_BundleMap_144 of Queue2_BundleMap_608 connect Queue2_BundleMap_144.clock, clock connect Queue2_BundleMap_144.reset, reset inst Queue2_BundleMap_145 of Queue2_BundleMap_609 connect Queue2_BundleMap_145.clock, clock connect Queue2_BundleMap_145.reset, reset inst Queue2_BundleMap_146 of Queue2_BundleMap_610 connect Queue2_BundleMap_146.clock, clock connect Queue2_BundleMap_146.reset, reset inst Queue2_BundleMap_147 of Queue2_BundleMap_611 connect Queue2_BundleMap_147.clock, clock connect Queue2_BundleMap_147.reset, reset inst Queue2_BundleMap_148 of Queue2_BundleMap_612 connect Queue2_BundleMap_148.clock, clock connect Queue2_BundleMap_148.reset, reset inst Queue2_BundleMap_149 of Queue2_BundleMap_613 connect Queue2_BundleMap_149.clock, clock connect Queue2_BundleMap_149.reset, reset inst Queue2_BundleMap_150 of Queue2_BundleMap_614 connect Queue2_BundleMap_150.clock, clock connect Queue2_BundleMap_150.reset, reset inst Queue2_BundleMap_151 of Queue2_BundleMap_615 connect Queue2_BundleMap_151.clock, clock connect Queue2_BundleMap_151.reset, reset inst Queue2_BundleMap_152 of Queue2_BundleMap_616 connect Queue2_BundleMap_152.clock, clock connect Queue2_BundleMap_152.reset, reset inst Queue2_BundleMap_153 of Queue2_BundleMap_617 connect Queue2_BundleMap_153.clock, clock connect Queue2_BundleMap_153.reset, reset inst Queue2_BundleMap_154 of Queue2_BundleMap_618 connect Queue2_BundleMap_154.clock, clock connect Queue2_BundleMap_154.reset, reset inst Queue2_BundleMap_155 of Queue2_BundleMap_619 connect Queue2_BundleMap_155.clock, clock connect Queue2_BundleMap_155.reset, reset inst Queue2_BundleMap_156 of Queue2_BundleMap_620 connect Queue2_BundleMap_156.clock, clock connect Queue2_BundleMap_156.reset, reset inst Queue2_BundleMap_157 of Queue2_BundleMap_621 connect Queue2_BundleMap_157.clock, clock connect Queue2_BundleMap_157.reset, reset inst Queue2_BundleMap_158 of Queue2_BundleMap_622 connect Queue2_BundleMap_158.clock, clock connect Queue2_BundleMap_158.reset, reset inst Queue2_BundleMap_159 of Queue2_BundleMap_623 connect Queue2_BundleMap_159.clock, clock connect Queue2_BundleMap_159.reset, reset inst Queue2_BundleMap_160 of Queue2_BundleMap_624 connect Queue2_BundleMap_160.clock, clock connect Queue2_BundleMap_160.reset, reset inst Queue2_BundleMap_161 of Queue2_BundleMap_625 connect Queue2_BundleMap_161.clock, clock connect Queue2_BundleMap_161.reset, reset inst Queue2_BundleMap_162 of Queue2_BundleMap_626 connect Queue2_BundleMap_162.clock, clock connect Queue2_BundleMap_162.reset, reset inst Queue2_BundleMap_163 of Queue2_BundleMap_627 connect Queue2_BundleMap_163.clock, clock connect Queue2_BundleMap_163.reset, reset inst Queue2_BundleMap_164 of Queue2_BundleMap_628 connect Queue2_BundleMap_164.clock, clock connect Queue2_BundleMap_164.reset, reset inst Queue2_BundleMap_165 of Queue2_BundleMap_629 connect Queue2_BundleMap_165.clock, clock connect Queue2_BundleMap_165.reset, reset inst Queue2_BundleMap_166 of Queue2_BundleMap_630 connect Queue2_BundleMap_166.clock, clock connect Queue2_BundleMap_166.reset, reset inst Queue2_BundleMap_167 of Queue2_BundleMap_631 connect Queue2_BundleMap_167.clock, clock connect Queue2_BundleMap_167.reset, reset inst Queue2_BundleMap_168 of Queue2_BundleMap_632 connect Queue2_BundleMap_168.clock, clock connect Queue2_BundleMap_168.reset, reset inst Queue2_BundleMap_169 of Queue2_BundleMap_633 connect Queue2_BundleMap_169.clock, clock connect Queue2_BundleMap_169.reset, reset inst Queue2_BundleMap_170 of Queue2_BundleMap_634 connect Queue2_BundleMap_170.clock, clock connect Queue2_BundleMap_170.reset, reset inst Queue2_BundleMap_171 of Queue2_BundleMap_635 connect Queue2_BundleMap_171.clock, clock connect Queue2_BundleMap_171.reset, reset inst Queue2_BundleMap_172 of Queue2_BundleMap_636 connect Queue2_BundleMap_172.clock, clock connect Queue2_BundleMap_172.reset, reset inst Queue2_BundleMap_173 of Queue2_BundleMap_637 connect Queue2_BundleMap_173.clock, clock connect Queue2_BundleMap_173.reset, reset inst Queue2_BundleMap_174 of Queue2_BundleMap_638 connect Queue2_BundleMap_174.clock, clock connect Queue2_BundleMap_174.reset, reset inst Queue2_BundleMap_175 of Queue2_BundleMap_639 connect Queue2_BundleMap_175.clock, clock connect Queue2_BundleMap_175.reset, reset inst Queue2_BundleMap_176 of Queue2_BundleMap_640 connect Queue2_BundleMap_176.clock, clock connect Queue2_BundleMap_176.reset, reset inst Queue2_BundleMap_177 of Queue2_BundleMap_641 connect Queue2_BundleMap_177.clock, clock connect Queue2_BundleMap_177.reset, reset inst Queue2_BundleMap_178 of Queue2_BundleMap_642 connect Queue2_BundleMap_178.clock, clock connect Queue2_BundleMap_178.reset, reset inst Queue2_BundleMap_179 of Queue2_BundleMap_643 connect Queue2_BundleMap_179.clock, clock connect Queue2_BundleMap_179.reset, reset inst Queue2_BundleMap_180 of Queue2_BundleMap_644 connect Queue2_BundleMap_180.clock, clock connect Queue2_BundleMap_180.reset, reset inst Queue2_BundleMap_181 of Queue2_BundleMap_645 connect Queue2_BundleMap_181.clock, clock connect Queue2_BundleMap_181.reset, reset inst Queue2_BundleMap_182 of Queue2_BundleMap_646 connect Queue2_BundleMap_182.clock, clock connect Queue2_BundleMap_182.reset, reset inst Queue2_BundleMap_183 of Queue2_BundleMap_647 connect Queue2_BundleMap_183.clock, clock connect Queue2_BundleMap_183.reset, reset inst Queue2_BundleMap_184 of Queue2_BundleMap_648 connect Queue2_BundleMap_184.clock, clock connect Queue2_BundleMap_184.reset, reset inst Queue2_BundleMap_185 of Queue2_BundleMap_649 connect Queue2_BundleMap_185.clock, clock connect Queue2_BundleMap_185.reset, reset inst Queue2_BundleMap_186 of Queue2_BundleMap_650 connect Queue2_BundleMap_186.clock, clock connect Queue2_BundleMap_186.reset, reset inst Queue2_BundleMap_187 of Queue2_BundleMap_651 connect Queue2_BundleMap_187.clock, clock connect Queue2_BundleMap_187.reset, reset inst Queue2_BundleMap_188 of Queue2_BundleMap_652 connect Queue2_BundleMap_188.clock, clock connect Queue2_BundleMap_188.reset, reset inst Queue2_BundleMap_189 of Queue2_BundleMap_653 connect Queue2_BundleMap_189.clock, clock connect Queue2_BundleMap_189.reset, reset inst Queue2_BundleMap_190 of Queue2_BundleMap_654 connect Queue2_BundleMap_190.clock, clock connect Queue2_BundleMap_190.reset, reset inst Queue2_BundleMap_191 of Queue2_BundleMap_655 connect Queue2_BundleMap_191.clock, clock connect Queue2_BundleMap_191.reset, reset inst Queue2_BundleMap_192 of Queue2_BundleMap_656 connect Queue2_BundleMap_192.clock, clock connect Queue2_BundleMap_192.reset, reset inst Queue2_BundleMap_193 of Queue2_BundleMap_657 connect Queue2_BundleMap_193.clock, clock connect Queue2_BundleMap_193.reset, reset inst Queue2_BundleMap_194 of Queue2_BundleMap_658 connect Queue2_BundleMap_194.clock, clock connect Queue2_BundleMap_194.reset, reset inst Queue2_BundleMap_195 of Queue2_BundleMap_659 connect Queue2_BundleMap_195.clock, clock connect Queue2_BundleMap_195.reset, reset inst Queue2_BundleMap_196 of Queue2_BundleMap_660 connect Queue2_BundleMap_196.clock, clock connect Queue2_BundleMap_196.reset, reset inst Queue2_BundleMap_197 of Queue2_BundleMap_661 connect Queue2_BundleMap_197.clock, clock connect Queue2_BundleMap_197.reset, reset inst Queue2_BundleMap_198 of Queue2_BundleMap_662 connect Queue2_BundleMap_198.clock, clock connect Queue2_BundleMap_198.reset, reset inst Queue2_BundleMap_199 of Queue2_BundleMap_663 connect Queue2_BundleMap_199.clock, clock connect Queue2_BundleMap_199.reset, reset inst Queue2_BundleMap_200 of Queue2_BundleMap_664 connect Queue2_BundleMap_200.clock, clock connect Queue2_BundleMap_200.reset, reset inst Queue2_BundleMap_201 of Queue2_BundleMap_665 connect Queue2_BundleMap_201.clock, clock connect Queue2_BundleMap_201.reset, reset inst Queue2_BundleMap_202 of Queue2_BundleMap_666 connect Queue2_BundleMap_202.clock, clock connect Queue2_BundleMap_202.reset, reset inst Queue2_BundleMap_203 of Queue2_BundleMap_667 connect Queue2_BundleMap_203.clock, clock connect Queue2_BundleMap_203.reset, reset inst Queue2_BundleMap_204 of Queue2_BundleMap_668 connect Queue2_BundleMap_204.clock, clock connect Queue2_BundleMap_204.reset, reset inst Queue2_BundleMap_205 of Queue2_BundleMap_669 connect Queue2_BundleMap_205.clock, clock connect Queue2_BundleMap_205.reset, reset inst Queue2_BundleMap_206 of Queue2_BundleMap_670 connect Queue2_BundleMap_206.clock, clock connect Queue2_BundleMap_206.reset, reset inst Queue2_BundleMap_207 of Queue2_BundleMap_671 connect Queue2_BundleMap_207.clock, clock connect Queue2_BundleMap_207.reset, reset inst Queue2_BundleMap_208 of Queue2_BundleMap_672 connect Queue2_BundleMap_208.clock, clock connect Queue2_BundleMap_208.reset, reset inst Queue2_BundleMap_209 of Queue2_BundleMap_673 connect Queue2_BundleMap_209.clock, clock connect Queue2_BundleMap_209.reset, reset inst Queue2_BundleMap_210 of Queue2_BundleMap_674 connect Queue2_BundleMap_210.clock, clock connect Queue2_BundleMap_210.reset, reset inst Queue2_BundleMap_211 of Queue2_BundleMap_675 connect Queue2_BundleMap_211.clock, clock connect Queue2_BundleMap_211.reset, reset inst Queue2_BundleMap_212 of Queue2_BundleMap_676 connect Queue2_BundleMap_212.clock, clock connect Queue2_BundleMap_212.reset, reset inst Queue2_BundleMap_213 of Queue2_BundleMap_677 connect Queue2_BundleMap_213.clock, clock connect Queue2_BundleMap_213.reset, reset inst Queue2_BundleMap_214 of Queue2_BundleMap_678 connect Queue2_BundleMap_214.clock, clock connect Queue2_BundleMap_214.reset, reset inst Queue2_BundleMap_215 of Queue2_BundleMap_679 connect Queue2_BundleMap_215.clock, clock connect Queue2_BundleMap_215.reset, reset inst Queue2_BundleMap_216 of Queue2_BundleMap_680 connect Queue2_BundleMap_216.clock, clock connect Queue2_BundleMap_216.reset, reset inst Queue2_BundleMap_217 of Queue2_BundleMap_681 connect Queue2_BundleMap_217.clock, clock connect Queue2_BundleMap_217.reset, reset inst Queue2_BundleMap_218 of Queue2_BundleMap_682 connect Queue2_BundleMap_218.clock, clock connect Queue2_BundleMap_218.reset, reset inst Queue2_BundleMap_219 of Queue2_BundleMap_683 connect Queue2_BundleMap_219.clock, clock connect Queue2_BundleMap_219.reset, reset inst Queue2_BundleMap_220 of Queue2_BundleMap_684 connect Queue2_BundleMap_220.clock, clock connect Queue2_BundleMap_220.reset, reset inst Queue2_BundleMap_221 of Queue2_BundleMap_685 connect Queue2_BundleMap_221.clock, clock connect Queue2_BundleMap_221.reset, reset inst Queue2_BundleMap_222 of Queue2_BundleMap_686 connect Queue2_BundleMap_222.clock, clock connect Queue2_BundleMap_222.reset, reset inst Queue2_BundleMap_223 of Queue2_BundleMap_687 connect Queue2_BundleMap_223.clock, clock connect Queue2_BundleMap_223.reset, reset inst Queue2_BundleMap_224 of Queue2_BundleMap_688 connect Queue2_BundleMap_224.clock, clock connect Queue2_BundleMap_224.reset, reset inst Queue2_BundleMap_225 of Queue2_BundleMap_689 connect Queue2_BundleMap_225.clock, clock connect Queue2_BundleMap_225.reset, reset inst Queue2_BundleMap_226 of Queue2_BundleMap_690 connect Queue2_BundleMap_226.clock, clock connect Queue2_BundleMap_226.reset, reset inst Queue2_BundleMap_227 of Queue2_BundleMap_691 connect Queue2_BundleMap_227.clock, clock connect Queue2_BundleMap_227.reset, reset inst Queue2_BundleMap_228 of Queue2_BundleMap_692 connect Queue2_BundleMap_228.clock, clock connect Queue2_BundleMap_228.reset, reset inst Queue2_BundleMap_229 of Queue2_BundleMap_693 connect Queue2_BundleMap_229.clock, clock connect Queue2_BundleMap_229.reset, reset inst Queue2_BundleMap_230 of Queue2_BundleMap_694 connect Queue2_BundleMap_230.clock, clock connect Queue2_BundleMap_230.reset, reset inst Queue2_BundleMap_231 of Queue2_BundleMap_695 connect Queue2_BundleMap_231.clock, clock connect Queue2_BundleMap_231.reset, reset inst Queue1_BundleMap_12 of Queue1_BundleMap_60 connect Queue1_BundleMap_12.clock, clock connect Queue1_BundleMap_12.reset, reset inst Queue1_BundleMap_13 of Queue1_BundleMap_61 connect Queue1_BundleMap_13.clock, clock connect Queue1_BundleMap_13.reset, reset inst Queue1_BundleMap_14 of Queue1_BundleMap_62 connect Queue1_BundleMap_14.clock, clock connect Queue1_BundleMap_14.reset, reset inst Queue1_BundleMap_15 of Queue1_BundleMap_63 connect Queue1_BundleMap_15.clock, clock connect Queue1_BundleMap_15.reset, reset inst Queue1_BundleMap_16 of Queue1_BundleMap_64 connect Queue1_BundleMap_16.clock, clock connect Queue1_BundleMap_16.reset, reset inst Queue1_BundleMap_17 of Queue1_BundleMap_65 connect Queue1_BundleMap_17.clock, clock connect Queue1_BundleMap_17.reset, reset inst Queue1_BundleMap_18 of Queue1_BundleMap_66 connect Queue1_BundleMap_18.clock, clock connect Queue1_BundleMap_18.reset, reset inst Queue1_BundleMap_19 of Queue1_BundleMap_67 connect Queue1_BundleMap_19.clock, clock connect Queue1_BundleMap_19.reset, reset inst Queue1_BundleMap_20 of Queue1_BundleMap_68 connect Queue1_BundleMap_20.clock, clock connect Queue1_BundleMap_20.reset, reset inst Queue1_BundleMap_21 of Queue1_BundleMap_69 connect Queue1_BundleMap_21.clock, clock connect Queue1_BundleMap_21.reset, reset inst Queue1_BundleMap_22 of Queue1_BundleMap_70 connect Queue1_BundleMap_22.clock, clock connect Queue1_BundleMap_22.reset, reset inst Queue1_BundleMap_23 of Queue1_BundleMap_71 connect Queue1_BundleMap_23.clock, clock connect Queue1_BundleMap_23.reset, reset wire _ar_ready_WIRE : UInt<1>[128] connect _ar_ready_WIRE[0], Queue2_BundleMap.io.enq.ready connect _ar_ready_WIRE[1], Queue2_BundleMap_1.io.enq.ready connect _ar_ready_WIRE[2], Queue2_BundleMap_2.io.enq.ready connect _ar_ready_WIRE[3], Queue2_BundleMap_3.io.enq.ready connect _ar_ready_WIRE[4], Queue2_BundleMap_4.io.enq.ready connect _ar_ready_WIRE[5], Queue2_BundleMap_5.io.enq.ready connect _ar_ready_WIRE[6], Queue2_BundleMap_6.io.enq.ready connect _ar_ready_WIRE[7], Queue2_BundleMap_7.io.enq.ready connect _ar_ready_WIRE[8], Queue2_BundleMap_8.io.enq.ready connect _ar_ready_WIRE[9], Queue2_BundleMap_9.io.enq.ready connect _ar_ready_WIRE[10], Queue2_BundleMap_10.io.enq.ready connect _ar_ready_WIRE[11], Queue2_BundleMap_11.io.enq.ready connect _ar_ready_WIRE[12], Queue2_BundleMap_12.io.enq.ready connect _ar_ready_WIRE[13], Queue2_BundleMap_13.io.enq.ready connect _ar_ready_WIRE[14], Queue2_BundleMap_14.io.enq.ready connect _ar_ready_WIRE[15], Queue2_BundleMap_15.io.enq.ready connect _ar_ready_WIRE[16], Queue2_BundleMap_16.io.enq.ready connect _ar_ready_WIRE[17], Queue2_BundleMap_17.io.enq.ready connect _ar_ready_WIRE[18], Queue2_BundleMap_18.io.enq.ready connect _ar_ready_WIRE[19], Queue2_BundleMap_19.io.enq.ready connect _ar_ready_WIRE[20], Queue2_BundleMap_20.io.enq.ready connect _ar_ready_WIRE[21], Queue2_BundleMap_21.io.enq.ready connect _ar_ready_WIRE[22], Queue2_BundleMap_22.io.enq.ready connect _ar_ready_WIRE[23], Queue2_BundleMap_23.io.enq.ready connect _ar_ready_WIRE[24], Queue2_BundleMap_24.io.enq.ready connect _ar_ready_WIRE[25], Queue2_BundleMap_25.io.enq.ready connect _ar_ready_WIRE[26], Queue2_BundleMap_26.io.enq.ready connect _ar_ready_WIRE[27], Queue2_BundleMap_27.io.enq.ready connect _ar_ready_WIRE[28], Queue2_BundleMap_28.io.enq.ready connect _ar_ready_WIRE[29], Queue2_BundleMap_29.io.enq.ready connect _ar_ready_WIRE[30], Queue2_BundleMap_30.io.enq.ready connect _ar_ready_WIRE[31], Queue2_BundleMap_31.io.enq.ready connect _ar_ready_WIRE[32], Queue2_BundleMap_32.io.enq.ready connect _ar_ready_WIRE[33], Queue2_BundleMap_33.io.enq.ready connect _ar_ready_WIRE[34], Queue2_BundleMap_34.io.enq.ready connect _ar_ready_WIRE[35], Queue2_BundleMap_35.io.enq.ready connect _ar_ready_WIRE[36], Queue2_BundleMap_36.io.enq.ready connect _ar_ready_WIRE[37], Queue2_BundleMap_37.io.enq.ready connect _ar_ready_WIRE[38], Queue2_BundleMap_38.io.enq.ready connect _ar_ready_WIRE[39], Queue2_BundleMap_39.io.enq.ready connect _ar_ready_WIRE[40], Queue2_BundleMap_40.io.enq.ready connect _ar_ready_WIRE[41], Queue2_BundleMap_41.io.enq.ready connect _ar_ready_WIRE[42], Queue2_BundleMap_42.io.enq.ready connect _ar_ready_WIRE[43], Queue2_BundleMap_43.io.enq.ready connect _ar_ready_WIRE[44], Queue2_BundleMap_44.io.enq.ready connect _ar_ready_WIRE[45], Queue2_BundleMap_45.io.enq.ready connect _ar_ready_WIRE[46], Queue2_BundleMap_46.io.enq.ready connect _ar_ready_WIRE[47], Queue2_BundleMap_47.io.enq.ready connect _ar_ready_WIRE[48], Queue2_BundleMap_48.io.enq.ready connect _ar_ready_WIRE[49], Queue2_BundleMap_49.io.enq.ready connect _ar_ready_WIRE[50], Queue2_BundleMap_50.io.enq.ready connect _ar_ready_WIRE[51], Queue2_BundleMap_51.io.enq.ready connect _ar_ready_WIRE[52], Queue2_BundleMap_52.io.enq.ready connect _ar_ready_WIRE[53], Queue2_BundleMap_53.io.enq.ready connect _ar_ready_WIRE[54], Queue2_BundleMap_54.io.enq.ready connect _ar_ready_WIRE[55], Queue2_BundleMap_55.io.enq.ready connect _ar_ready_WIRE[56], Queue2_BundleMap_56.io.enq.ready connect _ar_ready_WIRE[57], Queue2_BundleMap_57.io.enq.ready connect _ar_ready_WIRE[58], Queue2_BundleMap_58.io.enq.ready connect _ar_ready_WIRE[59], Queue2_BundleMap_59.io.enq.ready connect _ar_ready_WIRE[60], Queue2_BundleMap_60.io.enq.ready connect _ar_ready_WIRE[61], Queue2_BundleMap_61.io.enq.ready connect _ar_ready_WIRE[62], Queue2_BundleMap_62.io.enq.ready connect _ar_ready_WIRE[63], Queue2_BundleMap_63.io.enq.ready connect _ar_ready_WIRE[64], Queue2_BundleMap_64.io.enq.ready connect _ar_ready_WIRE[65], Queue2_BundleMap_65.io.enq.ready connect _ar_ready_WIRE[66], Queue2_BundleMap_66.io.enq.ready connect _ar_ready_WIRE[67], Queue2_BundleMap_67.io.enq.ready connect _ar_ready_WIRE[68], Queue2_BundleMap_68.io.enq.ready connect _ar_ready_WIRE[69], Queue2_BundleMap_69.io.enq.ready connect _ar_ready_WIRE[70], Queue2_BundleMap_70.io.enq.ready connect _ar_ready_WIRE[71], Queue2_BundleMap_71.io.enq.ready connect _ar_ready_WIRE[72], Queue2_BundleMap_72.io.enq.ready connect _ar_ready_WIRE[73], Queue2_BundleMap_73.io.enq.ready connect _ar_ready_WIRE[74], Queue2_BundleMap_74.io.enq.ready connect _ar_ready_WIRE[75], Queue2_BundleMap_75.io.enq.ready connect _ar_ready_WIRE[76], Queue2_BundleMap_76.io.enq.ready connect _ar_ready_WIRE[77], Queue2_BundleMap_77.io.enq.ready connect _ar_ready_WIRE[78], Queue2_BundleMap_78.io.enq.ready connect _ar_ready_WIRE[79], Queue2_BundleMap_79.io.enq.ready connect _ar_ready_WIRE[80], Queue2_BundleMap_80.io.enq.ready connect _ar_ready_WIRE[81], Queue2_BundleMap_81.io.enq.ready connect _ar_ready_WIRE[82], Queue2_BundleMap_82.io.enq.ready connect _ar_ready_WIRE[83], Queue2_BundleMap_83.io.enq.ready connect _ar_ready_WIRE[84], Queue2_BundleMap_84.io.enq.ready connect _ar_ready_WIRE[85], Queue2_BundleMap_85.io.enq.ready connect _ar_ready_WIRE[86], Queue2_BundleMap_86.io.enq.ready connect _ar_ready_WIRE[87], Queue2_BundleMap_87.io.enq.ready connect _ar_ready_WIRE[88], Queue2_BundleMap_88.io.enq.ready connect _ar_ready_WIRE[89], Queue2_BundleMap_89.io.enq.ready connect _ar_ready_WIRE[90], Queue2_BundleMap_90.io.enq.ready connect _ar_ready_WIRE[91], Queue2_BundleMap_91.io.enq.ready connect _ar_ready_WIRE[92], Queue2_BundleMap_92.io.enq.ready connect _ar_ready_WIRE[93], Queue2_BundleMap_93.io.enq.ready connect _ar_ready_WIRE[94], Queue2_BundleMap_94.io.enq.ready connect _ar_ready_WIRE[95], Queue2_BundleMap_95.io.enq.ready connect _ar_ready_WIRE[96], Queue2_BundleMap_96.io.enq.ready connect _ar_ready_WIRE[97], Queue2_BundleMap_97.io.enq.ready connect _ar_ready_WIRE[98], Queue2_BundleMap_98.io.enq.ready connect _ar_ready_WIRE[99], Queue2_BundleMap_99.io.enq.ready connect _ar_ready_WIRE[100], Queue2_BundleMap_100.io.enq.ready connect _ar_ready_WIRE[101], Queue2_BundleMap_101.io.enq.ready connect _ar_ready_WIRE[102], Queue2_BundleMap_102.io.enq.ready connect _ar_ready_WIRE[103], Queue2_BundleMap_103.io.enq.ready connect _ar_ready_WIRE[104], Queue2_BundleMap_104.io.enq.ready connect _ar_ready_WIRE[105], Queue2_BundleMap_105.io.enq.ready connect _ar_ready_WIRE[106], Queue2_BundleMap_106.io.enq.ready connect _ar_ready_WIRE[107], Queue2_BundleMap_107.io.enq.ready connect _ar_ready_WIRE[108], Queue2_BundleMap_108.io.enq.ready connect _ar_ready_WIRE[109], Queue2_BundleMap_109.io.enq.ready connect _ar_ready_WIRE[110], Queue2_BundleMap_110.io.enq.ready connect _ar_ready_WIRE[111], Queue2_BundleMap_111.io.enq.ready connect _ar_ready_WIRE[112], Queue2_BundleMap_112.io.enq.ready connect _ar_ready_WIRE[113], Queue2_BundleMap_113.io.enq.ready connect _ar_ready_WIRE[114], Queue2_BundleMap_114.io.enq.ready connect _ar_ready_WIRE[115], Queue2_BundleMap_115.io.enq.ready connect _ar_ready_WIRE[116], Queue1_BundleMap.io.enq.ready connect _ar_ready_WIRE[117], Queue1_BundleMap_1.io.enq.ready connect _ar_ready_WIRE[118], Queue1_BundleMap_2.io.enq.ready connect _ar_ready_WIRE[119], Queue1_BundleMap_3.io.enq.ready connect _ar_ready_WIRE[120], Queue1_BundleMap_4.io.enq.ready connect _ar_ready_WIRE[121], Queue1_BundleMap_5.io.enq.ready connect _ar_ready_WIRE[122], Queue1_BundleMap_6.io.enq.ready connect _ar_ready_WIRE[123], Queue1_BundleMap_7.io.enq.ready connect _ar_ready_WIRE[124], Queue1_BundleMap_8.io.enq.ready connect _ar_ready_WIRE[125], Queue1_BundleMap_9.io.enq.ready connect _ar_ready_WIRE[126], Queue1_BundleMap_10.io.enq.ready connect _ar_ready_WIRE[127], Queue1_BundleMap_11.io.enq.ready node _nodeIn_ar_ready_T = and(nodeOut.ar.ready, _ar_ready_WIRE[nodeIn.ar.bits.id]) connect nodeIn.ar.ready, _nodeIn_ar_ready_T node _nodeOut_ar_valid_T = and(nodeIn.ar.valid, _ar_ready_WIRE[nodeIn.ar.bits.id]) connect nodeOut.ar.valid, _nodeOut_ar_valid_T connect nodeOut.ar.bits.qos, nodeIn.ar.bits.qos connect nodeOut.ar.bits.prot, nodeIn.ar.bits.prot connect nodeOut.ar.bits.cache, nodeIn.ar.bits.cache connect nodeOut.ar.bits.lock, nodeIn.ar.bits.lock connect nodeOut.ar.bits.burst, nodeIn.ar.bits.burst connect nodeOut.ar.bits.size, nodeIn.ar.bits.size connect nodeOut.ar.bits.len, nodeIn.ar.bits.len connect nodeOut.ar.bits.addr, nodeIn.ar.bits.addr connect nodeOut.ar.bits.id, nodeIn.ar.bits.id wire _r_valid_WIRE : UInt<1>[128] connect _r_valid_WIRE[0], Queue2_BundleMap.io.deq.valid connect _r_valid_WIRE[1], Queue2_BundleMap_1.io.deq.valid connect _r_valid_WIRE[2], Queue2_BundleMap_2.io.deq.valid connect _r_valid_WIRE[3], Queue2_BundleMap_3.io.deq.valid connect _r_valid_WIRE[4], Queue2_BundleMap_4.io.deq.valid connect _r_valid_WIRE[5], Queue2_BundleMap_5.io.deq.valid connect _r_valid_WIRE[6], Queue2_BundleMap_6.io.deq.valid connect _r_valid_WIRE[7], Queue2_BundleMap_7.io.deq.valid connect _r_valid_WIRE[8], Queue2_BundleMap_8.io.deq.valid connect _r_valid_WIRE[9], Queue2_BundleMap_9.io.deq.valid connect _r_valid_WIRE[10], Queue2_BundleMap_10.io.deq.valid connect _r_valid_WIRE[11], Queue2_BundleMap_11.io.deq.valid connect _r_valid_WIRE[12], Queue2_BundleMap_12.io.deq.valid connect _r_valid_WIRE[13], Queue2_BundleMap_13.io.deq.valid connect _r_valid_WIRE[14], Queue2_BundleMap_14.io.deq.valid connect _r_valid_WIRE[15], Queue2_BundleMap_15.io.deq.valid connect _r_valid_WIRE[16], Queue2_BundleMap_16.io.deq.valid connect _r_valid_WIRE[17], Queue2_BundleMap_17.io.deq.valid connect _r_valid_WIRE[18], Queue2_BundleMap_18.io.deq.valid connect _r_valid_WIRE[19], Queue2_BundleMap_19.io.deq.valid connect _r_valid_WIRE[20], Queue2_BundleMap_20.io.deq.valid connect _r_valid_WIRE[21], Queue2_BundleMap_21.io.deq.valid connect _r_valid_WIRE[22], Queue2_BundleMap_22.io.deq.valid connect _r_valid_WIRE[23], Queue2_BundleMap_23.io.deq.valid connect _r_valid_WIRE[24], Queue2_BundleMap_24.io.deq.valid connect _r_valid_WIRE[25], Queue2_BundleMap_25.io.deq.valid connect _r_valid_WIRE[26], Queue2_BundleMap_26.io.deq.valid connect _r_valid_WIRE[27], Queue2_BundleMap_27.io.deq.valid connect _r_valid_WIRE[28], Queue2_BundleMap_28.io.deq.valid connect _r_valid_WIRE[29], Queue2_BundleMap_29.io.deq.valid connect _r_valid_WIRE[30], Queue2_BundleMap_30.io.deq.valid connect _r_valid_WIRE[31], Queue2_BundleMap_31.io.deq.valid connect _r_valid_WIRE[32], Queue2_BundleMap_32.io.deq.valid connect _r_valid_WIRE[33], Queue2_BundleMap_33.io.deq.valid connect _r_valid_WIRE[34], Queue2_BundleMap_34.io.deq.valid connect _r_valid_WIRE[35], Queue2_BundleMap_35.io.deq.valid connect _r_valid_WIRE[36], Queue2_BundleMap_36.io.deq.valid connect _r_valid_WIRE[37], Queue2_BundleMap_37.io.deq.valid connect _r_valid_WIRE[38], Queue2_BundleMap_38.io.deq.valid connect _r_valid_WIRE[39], Queue2_BundleMap_39.io.deq.valid connect _r_valid_WIRE[40], Queue2_BundleMap_40.io.deq.valid connect _r_valid_WIRE[41], Queue2_BundleMap_41.io.deq.valid connect _r_valid_WIRE[42], Queue2_BundleMap_42.io.deq.valid connect _r_valid_WIRE[43], Queue2_BundleMap_43.io.deq.valid connect _r_valid_WIRE[44], Queue2_BundleMap_44.io.deq.valid connect _r_valid_WIRE[45], Queue2_BundleMap_45.io.deq.valid connect _r_valid_WIRE[46], Queue2_BundleMap_46.io.deq.valid connect _r_valid_WIRE[47], Queue2_BundleMap_47.io.deq.valid connect _r_valid_WIRE[48], Queue2_BundleMap_48.io.deq.valid connect _r_valid_WIRE[49], Queue2_BundleMap_49.io.deq.valid connect _r_valid_WIRE[50], Queue2_BundleMap_50.io.deq.valid connect _r_valid_WIRE[51], Queue2_BundleMap_51.io.deq.valid connect _r_valid_WIRE[52], Queue2_BundleMap_52.io.deq.valid connect _r_valid_WIRE[53], Queue2_BundleMap_53.io.deq.valid connect _r_valid_WIRE[54], Queue2_BundleMap_54.io.deq.valid connect _r_valid_WIRE[55], Queue2_BundleMap_55.io.deq.valid connect _r_valid_WIRE[56], Queue2_BundleMap_56.io.deq.valid connect _r_valid_WIRE[57], Queue2_BundleMap_57.io.deq.valid connect _r_valid_WIRE[58], Queue2_BundleMap_58.io.deq.valid connect _r_valid_WIRE[59], Queue2_BundleMap_59.io.deq.valid connect _r_valid_WIRE[60], Queue2_BundleMap_60.io.deq.valid connect _r_valid_WIRE[61], Queue2_BundleMap_61.io.deq.valid connect _r_valid_WIRE[62], Queue2_BundleMap_62.io.deq.valid connect _r_valid_WIRE[63], Queue2_BundleMap_63.io.deq.valid connect _r_valid_WIRE[64], Queue2_BundleMap_64.io.deq.valid connect _r_valid_WIRE[65], Queue2_BundleMap_65.io.deq.valid connect _r_valid_WIRE[66], Queue2_BundleMap_66.io.deq.valid connect _r_valid_WIRE[67], Queue2_BundleMap_67.io.deq.valid connect _r_valid_WIRE[68], Queue2_BundleMap_68.io.deq.valid connect _r_valid_WIRE[69], Queue2_BundleMap_69.io.deq.valid connect _r_valid_WIRE[70], Queue2_BundleMap_70.io.deq.valid connect _r_valid_WIRE[71], Queue2_BundleMap_71.io.deq.valid connect _r_valid_WIRE[72], Queue2_BundleMap_72.io.deq.valid connect _r_valid_WIRE[73], Queue2_BundleMap_73.io.deq.valid connect _r_valid_WIRE[74], Queue2_BundleMap_74.io.deq.valid connect _r_valid_WIRE[75], Queue2_BundleMap_75.io.deq.valid connect _r_valid_WIRE[76], Queue2_BundleMap_76.io.deq.valid connect _r_valid_WIRE[77], Queue2_BundleMap_77.io.deq.valid connect _r_valid_WIRE[78], Queue2_BundleMap_78.io.deq.valid connect _r_valid_WIRE[79], Queue2_BundleMap_79.io.deq.valid connect _r_valid_WIRE[80], Queue2_BundleMap_80.io.deq.valid connect _r_valid_WIRE[81], Queue2_BundleMap_81.io.deq.valid connect _r_valid_WIRE[82], Queue2_BundleMap_82.io.deq.valid connect _r_valid_WIRE[83], Queue2_BundleMap_83.io.deq.valid connect _r_valid_WIRE[84], Queue2_BundleMap_84.io.deq.valid connect _r_valid_WIRE[85], Queue2_BundleMap_85.io.deq.valid connect _r_valid_WIRE[86], Queue2_BundleMap_86.io.deq.valid connect _r_valid_WIRE[87], Queue2_BundleMap_87.io.deq.valid connect _r_valid_WIRE[88], Queue2_BundleMap_88.io.deq.valid connect _r_valid_WIRE[89], Queue2_BundleMap_89.io.deq.valid connect _r_valid_WIRE[90], Queue2_BundleMap_90.io.deq.valid connect _r_valid_WIRE[91], Queue2_BundleMap_91.io.deq.valid connect _r_valid_WIRE[92], Queue2_BundleMap_92.io.deq.valid connect _r_valid_WIRE[93], Queue2_BundleMap_93.io.deq.valid connect _r_valid_WIRE[94], Queue2_BundleMap_94.io.deq.valid connect _r_valid_WIRE[95], Queue2_BundleMap_95.io.deq.valid connect _r_valid_WIRE[96], Queue2_BundleMap_96.io.deq.valid connect _r_valid_WIRE[97], Queue2_BundleMap_97.io.deq.valid connect _r_valid_WIRE[98], Queue2_BundleMap_98.io.deq.valid connect _r_valid_WIRE[99], Queue2_BundleMap_99.io.deq.valid connect _r_valid_WIRE[100], Queue2_BundleMap_100.io.deq.valid connect _r_valid_WIRE[101], Queue2_BundleMap_101.io.deq.valid connect _r_valid_WIRE[102], Queue2_BundleMap_102.io.deq.valid connect _r_valid_WIRE[103], Queue2_BundleMap_103.io.deq.valid connect _r_valid_WIRE[104], Queue2_BundleMap_104.io.deq.valid connect _r_valid_WIRE[105], Queue2_BundleMap_105.io.deq.valid connect _r_valid_WIRE[106], Queue2_BundleMap_106.io.deq.valid connect _r_valid_WIRE[107], Queue2_BundleMap_107.io.deq.valid connect _r_valid_WIRE[108], Queue2_BundleMap_108.io.deq.valid connect _r_valid_WIRE[109], Queue2_BundleMap_109.io.deq.valid connect _r_valid_WIRE[110], Queue2_BundleMap_110.io.deq.valid connect _r_valid_WIRE[111], Queue2_BundleMap_111.io.deq.valid connect _r_valid_WIRE[112], Queue2_BundleMap_112.io.deq.valid connect _r_valid_WIRE[113], Queue2_BundleMap_113.io.deq.valid connect _r_valid_WIRE[114], Queue2_BundleMap_114.io.deq.valid connect _r_valid_WIRE[115], Queue2_BundleMap_115.io.deq.valid connect _r_valid_WIRE[116], Queue1_BundleMap.io.deq.valid connect _r_valid_WIRE[117], Queue1_BundleMap_1.io.deq.valid connect _r_valid_WIRE[118], Queue1_BundleMap_2.io.deq.valid connect _r_valid_WIRE[119], Queue1_BundleMap_3.io.deq.valid connect _r_valid_WIRE[120], Queue1_BundleMap_4.io.deq.valid connect _r_valid_WIRE[121], Queue1_BundleMap_5.io.deq.valid connect _r_valid_WIRE[122], Queue1_BundleMap_6.io.deq.valid connect _r_valid_WIRE[123], Queue1_BundleMap_7.io.deq.valid connect _r_valid_WIRE[124], Queue1_BundleMap_8.io.deq.valid connect _r_valid_WIRE[125], Queue1_BundleMap_9.io.deq.valid connect _r_valid_WIRE[126], Queue1_BundleMap_10.io.deq.valid connect _r_valid_WIRE[127], Queue1_BundleMap_11.io.deq.valid wire _r_bits_WIRE : { tl_state : { size : UInt<4>, source : UInt<8>}, extra_id : UInt<1>}[128] connect _r_bits_WIRE[0], Queue2_BundleMap.io.deq.bits connect _r_bits_WIRE[1], Queue2_BundleMap_1.io.deq.bits connect _r_bits_WIRE[2], Queue2_BundleMap_2.io.deq.bits connect _r_bits_WIRE[3], Queue2_BundleMap_3.io.deq.bits connect _r_bits_WIRE[4], Queue2_BundleMap_4.io.deq.bits connect _r_bits_WIRE[5], Queue2_BundleMap_5.io.deq.bits connect _r_bits_WIRE[6], Queue2_BundleMap_6.io.deq.bits connect _r_bits_WIRE[7], Queue2_BundleMap_7.io.deq.bits connect _r_bits_WIRE[8], Queue2_BundleMap_8.io.deq.bits connect _r_bits_WIRE[9], Queue2_BundleMap_9.io.deq.bits connect _r_bits_WIRE[10], Queue2_BundleMap_10.io.deq.bits connect _r_bits_WIRE[11], Queue2_BundleMap_11.io.deq.bits connect _r_bits_WIRE[12], Queue2_BundleMap_12.io.deq.bits connect _r_bits_WIRE[13], Queue2_BundleMap_13.io.deq.bits connect _r_bits_WIRE[14], Queue2_BundleMap_14.io.deq.bits connect _r_bits_WIRE[15], Queue2_BundleMap_15.io.deq.bits connect _r_bits_WIRE[16], Queue2_BundleMap_16.io.deq.bits connect _r_bits_WIRE[17], Queue2_BundleMap_17.io.deq.bits connect _r_bits_WIRE[18], Queue2_BundleMap_18.io.deq.bits connect _r_bits_WIRE[19], Queue2_BundleMap_19.io.deq.bits connect _r_bits_WIRE[20], Queue2_BundleMap_20.io.deq.bits connect _r_bits_WIRE[21], Queue2_BundleMap_21.io.deq.bits connect _r_bits_WIRE[22], Queue2_BundleMap_22.io.deq.bits connect _r_bits_WIRE[23], Queue2_BundleMap_23.io.deq.bits connect _r_bits_WIRE[24], Queue2_BundleMap_24.io.deq.bits connect _r_bits_WIRE[25], Queue2_BundleMap_25.io.deq.bits connect _r_bits_WIRE[26], Queue2_BundleMap_26.io.deq.bits connect _r_bits_WIRE[27], Queue2_BundleMap_27.io.deq.bits connect _r_bits_WIRE[28], Queue2_BundleMap_28.io.deq.bits connect _r_bits_WIRE[29], Queue2_BundleMap_29.io.deq.bits connect _r_bits_WIRE[30], Queue2_BundleMap_30.io.deq.bits connect _r_bits_WIRE[31], Queue2_BundleMap_31.io.deq.bits connect _r_bits_WIRE[32], Queue2_BundleMap_32.io.deq.bits connect _r_bits_WIRE[33], Queue2_BundleMap_33.io.deq.bits connect _r_bits_WIRE[34], Queue2_BundleMap_34.io.deq.bits connect _r_bits_WIRE[35], Queue2_BundleMap_35.io.deq.bits connect _r_bits_WIRE[36], Queue2_BundleMap_36.io.deq.bits connect _r_bits_WIRE[37], Queue2_BundleMap_37.io.deq.bits connect _r_bits_WIRE[38], Queue2_BundleMap_38.io.deq.bits connect _r_bits_WIRE[39], Queue2_BundleMap_39.io.deq.bits connect _r_bits_WIRE[40], Queue2_BundleMap_40.io.deq.bits connect _r_bits_WIRE[41], Queue2_BundleMap_41.io.deq.bits connect _r_bits_WIRE[42], Queue2_BundleMap_42.io.deq.bits connect _r_bits_WIRE[43], Queue2_BundleMap_43.io.deq.bits connect _r_bits_WIRE[44], Queue2_BundleMap_44.io.deq.bits connect _r_bits_WIRE[45], Queue2_BundleMap_45.io.deq.bits connect _r_bits_WIRE[46], Queue2_BundleMap_46.io.deq.bits connect _r_bits_WIRE[47], Queue2_BundleMap_47.io.deq.bits connect _r_bits_WIRE[48], Queue2_BundleMap_48.io.deq.bits connect _r_bits_WIRE[49], Queue2_BundleMap_49.io.deq.bits connect _r_bits_WIRE[50], Queue2_BundleMap_50.io.deq.bits connect _r_bits_WIRE[51], Queue2_BundleMap_51.io.deq.bits connect _r_bits_WIRE[52], Queue2_BundleMap_52.io.deq.bits connect _r_bits_WIRE[53], Queue2_BundleMap_53.io.deq.bits connect _r_bits_WIRE[54], Queue2_BundleMap_54.io.deq.bits connect _r_bits_WIRE[55], Queue2_BundleMap_55.io.deq.bits connect _r_bits_WIRE[56], Queue2_BundleMap_56.io.deq.bits connect _r_bits_WIRE[57], Queue2_BundleMap_57.io.deq.bits connect _r_bits_WIRE[58], Queue2_BundleMap_58.io.deq.bits connect _r_bits_WIRE[59], Queue2_BundleMap_59.io.deq.bits connect _r_bits_WIRE[60], Queue2_BundleMap_60.io.deq.bits connect _r_bits_WIRE[61], Queue2_BundleMap_61.io.deq.bits connect _r_bits_WIRE[62], Queue2_BundleMap_62.io.deq.bits connect _r_bits_WIRE[63], Queue2_BundleMap_63.io.deq.bits connect _r_bits_WIRE[64], Queue2_BundleMap_64.io.deq.bits connect _r_bits_WIRE[65], Queue2_BundleMap_65.io.deq.bits connect _r_bits_WIRE[66], Queue2_BundleMap_66.io.deq.bits connect _r_bits_WIRE[67], Queue2_BundleMap_67.io.deq.bits connect _r_bits_WIRE[68], Queue2_BundleMap_68.io.deq.bits connect _r_bits_WIRE[69], Queue2_BundleMap_69.io.deq.bits connect _r_bits_WIRE[70], Queue2_BundleMap_70.io.deq.bits connect _r_bits_WIRE[71], Queue2_BundleMap_71.io.deq.bits connect _r_bits_WIRE[72], Queue2_BundleMap_72.io.deq.bits connect _r_bits_WIRE[73], Queue2_BundleMap_73.io.deq.bits connect _r_bits_WIRE[74], Queue2_BundleMap_74.io.deq.bits connect _r_bits_WIRE[75], Queue2_BundleMap_75.io.deq.bits connect _r_bits_WIRE[76], Queue2_BundleMap_76.io.deq.bits connect _r_bits_WIRE[77], Queue2_BundleMap_77.io.deq.bits connect _r_bits_WIRE[78], Queue2_BundleMap_78.io.deq.bits connect _r_bits_WIRE[79], Queue2_BundleMap_79.io.deq.bits connect _r_bits_WIRE[80], Queue2_BundleMap_80.io.deq.bits connect _r_bits_WIRE[81], Queue2_BundleMap_81.io.deq.bits connect _r_bits_WIRE[82], Queue2_BundleMap_82.io.deq.bits connect _r_bits_WIRE[83], Queue2_BundleMap_83.io.deq.bits connect _r_bits_WIRE[84], Queue2_BundleMap_84.io.deq.bits connect _r_bits_WIRE[85], Queue2_BundleMap_85.io.deq.bits connect _r_bits_WIRE[86], Queue2_BundleMap_86.io.deq.bits connect _r_bits_WIRE[87], Queue2_BundleMap_87.io.deq.bits connect _r_bits_WIRE[88], Queue2_BundleMap_88.io.deq.bits connect _r_bits_WIRE[89], Queue2_BundleMap_89.io.deq.bits connect _r_bits_WIRE[90], Queue2_BundleMap_90.io.deq.bits connect _r_bits_WIRE[91], Queue2_BundleMap_91.io.deq.bits connect _r_bits_WIRE[92], Queue2_BundleMap_92.io.deq.bits connect _r_bits_WIRE[93], Queue2_BundleMap_93.io.deq.bits connect _r_bits_WIRE[94], Queue2_BundleMap_94.io.deq.bits connect _r_bits_WIRE[95], Queue2_BundleMap_95.io.deq.bits connect _r_bits_WIRE[96], Queue2_BundleMap_96.io.deq.bits connect _r_bits_WIRE[97], Queue2_BundleMap_97.io.deq.bits connect _r_bits_WIRE[98], Queue2_BundleMap_98.io.deq.bits connect _r_bits_WIRE[99], Queue2_BundleMap_99.io.deq.bits connect _r_bits_WIRE[100], Queue2_BundleMap_100.io.deq.bits connect _r_bits_WIRE[101], Queue2_BundleMap_101.io.deq.bits connect _r_bits_WIRE[102], Queue2_BundleMap_102.io.deq.bits connect _r_bits_WIRE[103], Queue2_BundleMap_103.io.deq.bits connect _r_bits_WIRE[104], Queue2_BundleMap_104.io.deq.bits connect _r_bits_WIRE[105], Queue2_BundleMap_105.io.deq.bits connect _r_bits_WIRE[106], Queue2_BundleMap_106.io.deq.bits connect _r_bits_WIRE[107], Queue2_BundleMap_107.io.deq.bits connect _r_bits_WIRE[108], Queue2_BundleMap_108.io.deq.bits connect _r_bits_WIRE[109], Queue2_BundleMap_109.io.deq.bits connect _r_bits_WIRE[110], Queue2_BundleMap_110.io.deq.bits connect _r_bits_WIRE[111], Queue2_BundleMap_111.io.deq.bits connect _r_bits_WIRE[112], Queue2_BundleMap_112.io.deq.bits connect _r_bits_WIRE[113], Queue2_BundleMap_113.io.deq.bits connect _r_bits_WIRE[114], Queue2_BundleMap_114.io.deq.bits connect _r_bits_WIRE[115], Queue2_BundleMap_115.io.deq.bits connect _r_bits_WIRE[116], Queue1_BundleMap.io.deq.bits connect _r_bits_WIRE[117], Queue1_BundleMap_1.io.deq.bits connect _r_bits_WIRE[118], Queue1_BundleMap_2.io.deq.bits connect _r_bits_WIRE[119], Queue1_BundleMap_3.io.deq.bits connect _r_bits_WIRE[120], Queue1_BundleMap_4.io.deq.bits connect _r_bits_WIRE[121], Queue1_BundleMap_5.io.deq.bits connect _r_bits_WIRE[122], Queue1_BundleMap_6.io.deq.bits connect _r_bits_WIRE[123], Queue1_BundleMap_7.io.deq.bits connect _r_bits_WIRE[124], Queue1_BundleMap_8.io.deq.bits connect _r_bits_WIRE[125], Queue1_BundleMap_9.io.deq.bits connect _r_bits_WIRE[126], Queue1_BundleMap_10.io.deq.bits connect _r_bits_WIRE[127], Queue1_BundleMap_11.io.deq.bits node _T = eq(nodeOut.r.valid, UInt<1>(0h0)) node _T_1 = or(_T, _r_valid_WIRE[nodeOut.r.bits.id]) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at UserYanker.scala:69 assert (!out.r.valid \|\| r_valid) // Q must be ready faster than the response\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert connect nodeIn.r.bits.last, nodeOut.r.bits.last connect nodeIn.r.bits.resp, nodeOut.r.bits.resp connect nodeIn.r.bits.data, nodeOut.r.bits.data connect nodeIn.r.bits.id, nodeOut.r.bits.id connect nodeIn.r.valid, nodeOut.r.valid connect nodeOut.r.ready, nodeIn.r.ready connect nodeIn.r.bits.echo.extra_id, _r_bits_WIRE[nodeOut.r.bits.id].extra_id connect nodeIn.r.bits.echo.tl_state.source, _r_bits_WIRE[nodeOut.r.bits.id].tl_state.source connect nodeIn.r.bits.echo.tl_state.size, _r_bits_WIRE[nodeOut.r.bits.id].tl_state.size node arsel_shiftAmount = bits(nodeIn.ar.bits.id, 6, 0) node _arsel_T = dshl(UInt<1>(0h1), arsel_shiftAmount) node _arsel_T_1 = bits(_arsel_T, 127, 0) node arsel_0 = bits(_arsel_T_1, 0, 0) node arsel_1 = bits(_arsel_T_1, 1, 1) node arsel_2 = bits(_arsel_T_1, 2, 2) node arsel_3 = bits(_arsel_T_1, 3, 3) node arsel_4 = bits(_arsel_T_1, 4, 4) node arsel_5 = bits(_arsel_T_1, 5, 5) node arsel_6 = bits(_arsel_T_1, 6, 6) node arsel_7 = bits(_arsel_T_1, 7, 7) node arsel_8 = bits(_arsel_T_1, 8, 8) node arsel_9 = bits(_arsel_T_1, 9, 9) node arsel_10 = bits(_arsel_T_1, 10, 10) node arsel_11 = bits(_arsel_T_1, 11, 11) node arsel_12 = bits(_arsel_T_1, 12, 12) node arsel_13 = bits(_arsel_T_1, 13, 13) node arsel_14 = bits(_arsel_T_1, 14, 14) node arsel_15 = bits(_arsel_T_1, 15, 15) node arsel_16 = bits(_arsel_T_1, 16, 16) node arsel_17 = bits(_arsel_T_1, 17, 17) node arsel_18 = bits(_arsel_T_1, 18, 18) node arsel_19 = bits(_arsel_T_1, 19, 19) node arsel_20 = bits(_arsel_T_1, 20, 20) node arsel_21 = bits(_arsel_T_1, 21, 21) node arsel_22 = bits(_arsel_T_1, 22, 22) node arsel_23 = bits(_arsel_T_1, 23, 23) node arsel_24 = bits(_arsel_T_1, 24, 24) node arsel_25 = bits(_arsel_T_1, 25, 25) node arsel_26 = bits(_arsel_T_1, 26, 26) node arsel_27 = bits(_arsel_T_1, 27, 27) node arsel_28 = bits(_arsel_T_1, 28, 28) node arsel_29 = bits(_arsel_T_1, 29, 29) node arsel_30 = bits(_arsel_T_1, 30, 30) node arsel_31 = bits(_arsel_T_1, 31, 31) node arsel_32 = bits(_arsel_T_1, 32, 32) node arsel_33 = bits(_arsel_T_1, 33, 33) node arsel_34 = bits(_arsel_T_1, 34, 34) node arsel_35 = bits(_arsel_T_1, 35, 35) node arsel_36 = bits(_arsel_T_1, 36, 36) node arsel_37 = bits(_arsel_T_1, 37, 37) node arsel_38 = bits(_arsel_T_1, 38, 38) node arsel_39 = bits(_arsel_T_1, 39, 39) node arsel_40 = bits(_arsel_T_1, 40, 40) node arsel_41 = bits(_arsel_T_1, 41, 41) node arsel_42 = bits(_arsel_T_1, 42, 42) node arsel_43 = bits(_arsel_T_1, 43, 43) node arsel_44 = bits(_arsel_T_1, 44, 44) node arsel_45 = bits(_arsel_T_1, 45, 45) node arsel_46 = bits(_arsel_T_1, 46, 46) node arsel_47 = bits(_arsel_T_1, 47, 47) node arsel_48 = bits(_arsel_T_1, 48, 48) node arsel_49 = bits(_arsel_T_1, 49, 49) node arsel_50 = bits(_arsel_T_1, 50, 50) node arsel_51 = bits(_arsel_T_1, 51, 51) node arsel_52 = bits(_arsel_T_1, 52, 52) node arsel_53 = bits(_arsel_T_1, 53, 53) node arsel_54 = bits(_arsel_T_1, 54, 54) node arsel_55 = bits(_arsel_T_1, 55, 55) node arsel_56 = bits(_arsel_T_1, 56, 56) node arsel_57 = bits(_arsel_T_1, 57, 57) node arsel_58 = bits(_arsel_T_1, 58, 58) node arsel_59 = bits(_arsel_T_1, 59, 59) node arsel_60 = bits(_arsel_T_1, 60, 60) node arsel_61 = bits(_arsel_T_1, 61, 61) node arsel_62 = bits(_arsel_T_1, 62, 62) node arsel_63 = bits(_arsel_T_1, 63, 63) node arsel_64 = bits(_arsel_T_1, 64, 64) node arsel_65 = bits(_arsel_T_1, 65, 65) node arsel_66 = bits(_arsel_T_1, 66, 66) node arsel_67 = bits(_arsel_T_1, 67, 67) node arsel_68 = bits(_arsel_T_1, 68, 68) node arsel_69 = bits(_arsel_T_1, 69, 69) node arsel_70 = bits(_arsel_T_1, 70, 70) node arsel_71 = bits(_arsel_T_1, 71, 71) node arsel_72 = bits(_arsel_T_1, 72, 72) node arsel_73 = bits(_arsel_T_1, 73, 73) node arsel_74 = bits(_arsel_T_1, 74, 74) node arsel_75 = bits(_arsel_T_1, 75, 75) node arsel_76 = bits(_arsel_T_1, 76, 76) node arsel_77 = bits(_arsel_T_1, 77, 77) node arsel_78 = bits(_arsel_T_1, 78, 78) node arsel_79 = bits(_arsel_T_1, 79, 79) node arsel_80 = bits(_arsel_T_1, 80, 80) node arsel_81 = bits(_arsel_T_1, 81, 81) node arsel_82 = bits(_arsel_T_1, 82, 82) node arsel_83 = bits(_arsel_T_1, 83, 83) node arsel_84 = bits(_arsel_T_1, 84, 84) node arsel_85 = bits(_arsel_T_1, 85, 85) node arsel_86 = bits(_arsel_T_1, 86, 86) node arsel_87 = bits(_arsel_T_1, 87, 87) node arsel_88 = bits(_arsel_T_1, 88, 88) node arsel_89 = bits(_arsel_T_1, 89, 89) node arsel_90 = bits(_arsel_T_1, 90, 90) node arsel_91 = bits(_arsel_T_1, 91, 91) node arsel_92 = bits(_arsel_T_1, 92, 92) node arsel_93 = bits(_arsel_T_1, 93, 93) node arsel_94 = bits(_arsel_T_1, 94, 94) node arsel_95 = bits(_arsel_T_1, 95, 95) node arsel_96 = bits(_arsel_T_1, 96, 96) node arsel_97 = bits(_arsel_T_1, 97, 97) node arsel_98 = bits(_arsel_T_1, 98, 98) node arsel_99 = bits(_arsel_T_1, 99, 99) node arsel_100 = bits(_arsel_T_1, 100, 100) node arsel_101 = bits(_arsel_T_1, 101, 101) node arsel_102 = bits(_arsel_T_1, 102, 102) node arsel_103 = bits(_arsel_T_1, 103, 103) node arsel_104 = bits(_arsel_T_1, 104, 104) node arsel_105 = bits(_arsel_T_1, 105, 105) node arsel_106 = bits(_arsel_T_1, 106, 106) node arsel_107 = bits(_arsel_T_1, 107, 107) node arsel_108 = bits(_arsel_T_1, 108, 108) node arsel_109 = bits(_arsel_T_1, 109, 109) node arsel_110 = bits(_arsel_T_1, 110, 110) node arsel_111 = bits(_arsel_T_1, 111, 111) node arsel_112 = bits(_arsel_T_1, 112, 112) node arsel_113 = bits(_arsel_T_1, 113, 113) node arsel_114 = bits(_arsel_T_1, 114, 114) node arsel_115 = bits(_arsel_T_1, 115, 115) node arsel_116 = bits(_arsel_T_1, 116, 116) node arsel_117 = bits(_arsel_T_1, 117, 117) node arsel_118 = bits(_arsel_T_1, 118, 118) node arsel_119 = bits(_arsel_T_1, 119, 119) node arsel_120 = bits(_arsel_T_1, 120, 120) node arsel_121 = bits(_arsel_T_1, 121, 121) node arsel_122 = bits(_arsel_T_1, 122, 122) node arsel_123 = bits(_arsel_T_1, 123, 123) node arsel_124 = bits(_arsel_T_1, 124, 124) node arsel_125 = bits(_arsel_T_1, 125, 125) node arsel_126 = bits(_arsel_T_1, 126, 126) node arsel_127 = bits(_arsel_T_1, 127, 127) node rsel_shiftAmount = bits(nodeOut.r.bits.id, 6, 0) node _rsel_T = dshl(UInt<1>(0h1), rsel_shiftAmount) node _rsel_T_1 = bits(_rsel_T, 127, 0) node rsel_0 = bits(_rsel_T_1, 0, 0) node rsel_1 = bits(_rsel_T_1, 1, 1) node rsel_2 = bits(_rsel_T_1, 2, 2) node rsel_3 = bits(_rsel_T_1, 3, 3) node rsel_4 = bits(_rsel_T_1, 4, 4) node rsel_5 = bits(_rsel_T_1, 5, 5) node rsel_6 = bits(_rsel_T_1, 6, 6) node rsel_7 = bits(_rsel_T_1, 7, 7) node rsel_8 = bits(_rsel_T_1, 8, 8) node rsel_9 = bits(_rsel_T_1, 9, 9) node rsel_10 = bits(_rsel_T_1, 10, 10) node rsel_11 = bits(_rsel_T_1, 11, 11) node rsel_12 = bits(_rsel_T_1, 12, 12) node rsel_13 = bits(_rsel_T_1, 13, 13) node rsel_14 = bits(_rsel_T_1, 14, 14) node rsel_15 = bits(_rsel_T_1, 15, 15) node rsel_16 = bits(_rsel_T_1, 16, 16) node rsel_17 = bits(_rsel_T_1, 17, 17) node rsel_18 = bits(_rsel_T_1, 18, 18) node rsel_19 = bits(_rsel_T_1, 19, 19) node rsel_20 = bits(_rsel_T_1, 20, 20) node rsel_21 = bits(_rsel_T_1, 21, 21) node rsel_22 = bits(_rsel_T_1, 22, 22) node rsel_23 = bits(_rsel_T_1, 23, 23) node rsel_24 = bits(_rsel_T_1, 24, 24) node rsel_25 = bits(_rsel_T_1, 25, 25) node rsel_26 = bits(_rsel_T_1, 26, 26) node rsel_27 = bits(_rsel_T_1, 27, 27) node rsel_28 = bits(_rsel_T_1, 28, 28) node rsel_29 = bits(_rsel_T_1, 29, 29) node rsel_30 = bits(_rsel_T_1, 30, 30) node rsel_31 = bits(_rsel_T_1, 31, 31) node rsel_32 = bits(_rsel_T_1, 32, 32) node rsel_33 = bits(_rsel_T_1, 33, 33) node rsel_34 = bits(_rsel_T_1, 34, 34) node rsel_35 = bits(_rsel_T_1, 35, 35) node rsel_36 = bits(_rsel_T_1, 36, 36) node rsel_37 = bits(_rsel_T_1, 37, 37) node rsel_38 = bits(_rsel_T_1, 38, 38) node rsel_39 = bits(_rsel_T_1, 39, 39) node rsel_40 = bits(_rsel_T_1, 40, 40) node rsel_41 = bits(_rsel_T_1, 41, 41) node rsel_42 = bits(_rsel_T_1, 42, 42) node rsel_43 = bits(_rsel_T_1, 43, 43) node rsel_44 = bits(_rsel_T_1, 44, 44) node rsel_45 = bits(_rsel_T_1, 45, 45) node rsel_46 = bits(_rsel_T_1, 46, 46) node rsel_47 = bits(_rsel_T_1, 47, 47) node rsel_48 = bits(_rsel_T_1, 48, 48) node rsel_49 = bits(_rsel_T_1, 49, 49) node rsel_50 = bits(_rsel_T_1, 50, 50) node rsel_51 = bits(_rsel_T_1, 51, 51) node rsel_52 = bits(_rsel_T_1, 52, 52) node rsel_53 = bits(_rsel_T_1, 53, 53) node rsel_54 = bits(_rsel_T_1, 54, 54) node rsel_55 = bits(_rsel_T_1, 55, 55) node rsel_56 = bits(_rsel_T_1, 56, 56) node rsel_57 = bits(_rsel_T_1, 57, 57) node rsel_58 = bits(_rsel_T_1, 58, 58) node rsel_59 = bits(_rsel_T_1, 59, 59) node rsel_60 = bits(_rsel_T_1, 60, 60) node rsel_61 = bits(_rsel_T_1, 61, 61) node rsel_62 = bits(_rsel_T_1, 62, 62) node rsel_63 = bits(_rsel_T_1, 63, 63) node rsel_64 = bits(_rsel_T_1, 64, 64) node rsel_65 = bits(_rsel_T_1, 65, 65) node rsel_66 = bits(_rsel_T_1, 66, 66) node rsel_67 = bits(_rsel_T_1, 67, 67) node rsel_68 = bits(_rsel_T_1, 68, 68) node rsel_69 = bits(_rsel_T_1, 69, 69) node rsel_70 = bits(_rsel_T_1, 70, 70) node rsel_71 = bits(_rsel_T_1, 71, 71) node rsel_72 = bits(_rsel_T_1, 72, 72) node rsel_73 = bits(_rsel_T_1, 73, 73) node rsel_74 = bits(_rsel_T_1, 74, 74) node rsel_75 = bits(_rsel_T_1, 75, 75) node rsel_76 = bits(_rsel_T_1, 76, 76) node rsel_77 = bits(_rsel_T_1, 77, 77) node rsel_78 = bits(_rsel_T_1, 78, 78) node rsel_79 = bits(_rsel_T_1, 79, 79) node rsel_80 = bits(_rsel_T_1, 80, 80) node rsel_81 = bits(_rsel_T_1, 81, 81) node rsel_82 = bits(_rsel_T_1, 82, 82) node rsel_83 = bits(_rsel_T_1, 83, 83) node rsel_84 = bits(_rsel_T_1, 84, 84) node rsel_85 = bits(_rsel_T_1, 85, 85) node rsel_86 = bits(_rsel_T_1, 86, 86) node rsel_87 = bits(_rsel_T_1, 87, 87) node rsel_88 = bits(_rsel_T_1, 88, 88) node rsel_89 = bits(_rsel_T_1, 89, 89) node rsel_90 = bits(_rsel_T_1, 90, 90) node rsel_91 = bits(_rsel_T_1, 91, 91) node rsel_92 = bits(_rsel_T_1, 92, 92) node rsel_93 = bits(_rsel_T_1, 93, 93) node rsel_94 = bits(_rsel_T_1, 94, 94) node rsel_95 = bits(_rsel_T_1, 95, 95) node rsel_96 = bits(_rsel_T_1, 96, 96) node rsel_97 = bits(_rsel_T_1, 97, 97) node rsel_98 = bits(_rsel_T_1, 98, 98) node rsel_99 = bits(_rsel_T_1, 99, 99) node rsel_100 = bits(_rsel_T_1, 100, 100) node rsel_101 = bits(_rsel_T_1, 101, 101) node rsel_102 = bits(_rsel_T_1, 102, 102) node rsel_103 = bits(_rsel_T_1, 103, 103) node rsel_104 = bits(_rsel_T_1, 104, 104) node rsel_105 = bits(_rsel_T_1, 105, 105) node rsel_106 = bits(_rsel_T_1, 106, 106) node rsel_107 = bits(_rsel_T_1, 107, 107) node rsel_108 = bits(_rsel_T_1, 108, 108) node rsel_109 = bits(_rsel_T_1, 109, 109) node rsel_110 = bits(_rsel_T_1, 110, 110) node rsel_111 = bits(_rsel_T_1, 111, 111) node rsel_112 = bits(_rsel_T_1, 112, 112) node rsel_113 = bits(_rsel_T_1, 113, 113) node rsel_114 = bits(_rsel_T_1, 114, 114) node rsel_115 = bits(_rsel_T_1, 115, 115) node rsel_116 = bits(_rsel_T_1, 116, 116) node rsel_117 = bits(_rsel_T_1, 117, 117) node rsel_118 = bits(_rsel_T_1, 118, 118) node rsel_119 = bits(_rsel_T_1, 119, 119) node rsel_120 = bits(_rsel_T_1, 120, 120) node rsel_121 = bits(_rsel_T_1, 121, 121) node rsel_122 = bits(_rsel_T_1, 122, 122) node rsel_123 = bits(_rsel_T_1, 123, 123) node rsel_124 = bits(_rsel_T_1, 124, 124) node rsel_125 = bits(_rsel_T_1, 125, 125) node rsel_126 = bits(_rsel_T_1, 126, 126) node rsel_127 = bits(_rsel_T_1, 127, 127) node _T_5 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_6 = and(_T_5, rsel_0) node _T_7 = and(_T_6, nodeOut.r.bits.last) connect Queue2_BundleMap.io.deq.ready, _T_7 invalidate Queue2_BundleMap.io.deq.valid invalidate Queue2_BundleMap.io.deq.bits.extra_id invalidate Queue2_BundleMap.io.deq.bits.tl_state.source invalidate Queue2_BundleMap.io.deq.bits.tl_state.size node _T_8 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_9 = and(_T_8, arsel_0) connect Queue2_BundleMap.io.enq.valid, _T_9 invalidate Queue2_BundleMap.io.enq.ready connect Queue2_BundleMap.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap.io.count node _T_10 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_11 = and(_T_10, rsel_1) node _T_12 = and(_T_11, nodeOut.r.bits.last) connect Queue2_BundleMap_1.io.deq.ready, _T_12 invalidate Queue2_BundleMap_1.io.deq.valid invalidate Queue2_BundleMap_1.io.deq.bits.extra_id invalidate Queue2_BundleMap_1.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_1.io.deq.bits.tl_state.size node _T_13 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_14 = and(_T_13, arsel_1) connect Queue2_BundleMap_1.io.enq.valid, _T_14 invalidate Queue2_BundleMap_1.io.enq.ready connect Queue2_BundleMap_1.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_1.io.count node _T_15 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_16 = and(_T_15, rsel_2) node _T_17 = and(_T_16, nodeOut.r.bits.last) connect Queue2_BundleMap_2.io.deq.ready, _T_17 invalidate Queue2_BundleMap_2.io.deq.valid invalidate Queue2_BundleMap_2.io.deq.bits.extra_id invalidate Queue2_BundleMap_2.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_2.io.deq.bits.tl_state.size node _T_18 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_19 = and(_T_18, arsel_2) connect Queue2_BundleMap_2.io.enq.valid, _T_19 invalidate Queue2_BundleMap_2.io.enq.ready connect Queue2_BundleMap_2.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_2.io.count node _T_20 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_21 = and(_T_20, rsel_3) node _T_22 = and(_T_21, nodeOut.r.bits.last) connect Queue2_BundleMap_3.io.deq.ready, _T_22 invalidate Queue2_BundleMap_3.io.deq.valid invalidate Queue2_BundleMap_3.io.deq.bits.extra_id invalidate Queue2_BundleMap_3.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_3.io.deq.bits.tl_state.size node _T_23 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_24 = and(_T_23, arsel_3) connect Queue2_BundleMap_3.io.enq.valid, _T_24 invalidate Queue2_BundleMap_3.io.enq.ready connect Queue2_BundleMap_3.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_3.io.count node _T_25 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_26 = and(_T_25, rsel_4) node _T_27 = and(_T_26, nodeOut.r.bits.last) connect Queue2_BundleMap_4.io.deq.ready, _T_27 invalidate Queue2_BundleMap_4.io.deq.valid invalidate Queue2_BundleMap_4.io.deq.bits.extra_id invalidate Queue2_BundleMap_4.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_4.io.deq.bits.tl_state.size node _T_28 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_29 = and(_T_28, arsel_4) connect Queue2_BundleMap_4.io.enq.valid, _T_29 invalidate Queue2_BundleMap_4.io.enq.ready connect Queue2_BundleMap_4.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_4.io.count node _T_30 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_31 = and(_T_30, rsel_5) node _T_32 = and(_T_31, nodeOut.r.bits.last) connect Queue2_BundleMap_5.io.deq.ready, _T_32 invalidate Queue2_BundleMap_5.io.deq.valid invalidate Queue2_BundleMap_5.io.deq.bits.extra_id invalidate Queue2_BundleMap_5.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_5.io.deq.bits.tl_state.size node _T_33 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_34 = and(_T_33, arsel_5) connect Queue2_BundleMap_5.io.enq.valid, _T_34 invalidate Queue2_BundleMap_5.io.enq.ready connect Queue2_BundleMap_5.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_5.io.count node _T_35 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_36 = and(_T_35, rsel_6) node _T_37 = and(_T_36, nodeOut.r.bits.last) connect Queue2_BundleMap_6.io.deq.ready, _T_37 invalidate Queue2_BundleMap_6.io.deq.valid invalidate Queue2_BundleMap_6.io.deq.bits.extra_id invalidate Queue2_BundleMap_6.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_6.io.deq.bits.tl_state.size node _T_38 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_39 = and(_T_38, arsel_6) connect Queue2_BundleMap_6.io.enq.valid, _T_39 invalidate Queue2_BundleMap_6.io.enq.ready connect Queue2_BundleMap_6.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_6.io.count node _T_40 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_41 = and(_T_40, rsel_7) node _T_42 = and(_T_41, nodeOut.r.bits.last) connect Queue2_BundleMap_7.io.deq.ready, _T_42 invalidate Queue2_BundleMap_7.io.deq.valid invalidate Queue2_BundleMap_7.io.deq.bits.extra_id invalidate Queue2_BundleMap_7.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_7.io.deq.bits.tl_state.size node _T_43 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_44 = and(_T_43, arsel_7) connect Queue2_BundleMap_7.io.enq.valid, _T_44 invalidate Queue2_BundleMap_7.io.enq.ready connect Queue2_BundleMap_7.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_7.io.count node _T_45 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_46 = and(_T_45, rsel_8) node _T_47 = and(_T_46, nodeOut.r.bits.last) connect Queue2_BundleMap_8.io.deq.ready, _T_47 invalidate Queue2_BundleMap_8.io.deq.valid invalidate Queue2_BundleMap_8.io.deq.bits.extra_id invalidate Queue2_BundleMap_8.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_8.io.deq.bits.tl_state.size node _T_48 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_49 = and(_T_48, arsel_8) connect Queue2_BundleMap_8.io.enq.valid, _T_49 invalidate Queue2_BundleMap_8.io.enq.ready connect Queue2_BundleMap_8.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_8.io.count node _T_50 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_51 = and(_T_50, rsel_9) node _T_52 = and(_T_51, nodeOut.r.bits.last) connect Queue2_BundleMap_9.io.deq.ready, _T_52 invalidate Queue2_BundleMap_9.io.deq.valid invalidate Queue2_BundleMap_9.io.deq.bits.extra_id invalidate Queue2_BundleMap_9.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_9.io.deq.bits.tl_state.size node _T_53 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_54 = and(_T_53, arsel_9) connect Queue2_BundleMap_9.io.enq.valid, _T_54 invalidate Queue2_BundleMap_9.io.enq.ready connect Queue2_BundleMap_9.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_9.io.count node _T_55 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_56 = and(_T_55, rsel_10) node _T_57 = and(_T_56, nodeOut.r.bits.last) connect Queue2_BundleMap_10.io.deq.ready, _T_57 invalidate Queue2_BundleMap_10.io.deq.valid invalidate Queue2_BundleMap_10.io.deq.bits.extra_id invalidate Queue2_BundleMap_10.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_10.io.deq.bits.tl_state.size node _T_58 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_59 = and(_T_58, arsel_10) connect Queue2_BundleMap_10.io.enq.valid, _T_59 invalidate Queue2_BundleMap_10.io.enq.ready connect Queue2_BundleMap_10.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_10.io.count node _T_60 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_61 = and(_T_60, rsel_11) node _T_62 = and(_T_61, nodeOut.r.bits.last) connect Queue2_BundleMap_11.io.deq.ready, _T_62 invalidate Queue2_BundleMap_11.io.deq.valid invalidate Queue2_BundleMap_11.io.deq.bits.extra_id invalidate Queue2_BundleMap_11.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_11.io.deq.bits.tl_state.size node _T_63 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_64 = and(_T_63, arsel_11) connect Queue2_BundleMap_11.io.enq.valid, _T_64 invalidate Queue2_BundleMap_11.io.enq.ready connect Queue2_BundleMap_11.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_11.io.count node _T_65 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_66 = and(_T_65, rsel_12) node _T_67 = and(_T_66, nodeOut.r.bits.last) connect Queue2_BundleMap_12.io.deq.ready, _T_67 invalidate Queue2_BundleMap_12.io.deq.valid invalidate Queue2_BundleMap_12.io.deq.bits.extra_id invalidate Queue2_BundleMap_12.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_12.io.deq.bits.tl_state.size node _T_68 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_69 = and(_T_68, arsel_12) connect Queue2_BundleMap_12.io.enq.valid, _T_69 invalidate Queue2_BundleMap_12.io.enq.ready connect Queue2_BundleMap_12.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_12.io.count node _T_70 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_71 = and(_T_70, rsel_13) node _T_72 = and(_T_71, nodeOut.r.bits.last) connect Queue2_BundleMap_13.io.deq.ready, _T_72 invalidate Queue2_BundleMap_13.io.deq.valid invalidate Queue2_BundleMap_13.io.deq.bits.extra_id invalidate Queue2_BundleMap_13.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_13.io.deq.bits.tl_state.size node _T_73 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_74 = and(_T_73, arsel_13) connect Queue2_BundleMap_13.io.enq.valid, _T_74 invalidate Queue2_BundleMap_13.io.enq.ready connect Queue2_BundleMap_13.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_13.io.count node _T_75 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_76 = and(_T_75, rsel_14) node _T_77 = and(_T_76, nodeOut.r.bits.last) connect Queue2_BundleMap_14.io.deq.ready, _T_77 invalidate Queue2_BundleMap_14.io.deq.valid invalidate Queue2_BundleMap_14.io.deq.bits.extra_id invalidate Queue2_BundleMap_14.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_14.io.deq.bits.tl_state.size node _T_78 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_79 = and(_T_78, arsel_14) connect Queue2_BundleMap_14.io.enq.valid, _T_79 invalidate Queue2_BundleMap_14.io.enq.ready connect Queue2_BundleMap_14.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_14.io.count node _T_80 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_81 = and(_T_80, rsel_15) node _T_82 = and(_T_81, nodeOut.r.bits.last) connect Queue2_BundleMap_15.io.deq.ready, _T_82 invalidate Queue2_BundleMap_15.io.deq.valid invalidate Queue2_BundleMap_15.io.deq.bits.extra_id invalidate Queue2_BundleMap_15.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_15.io.deq.bits.tl_state.size node _T_83 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_84 = and(_T_83, arsel_15) connect Queue2_BundleMap_15.io.enq.valid, _T_84 invalidate Queue2_BundleMap_15.io.enq.ready connect Queue2_BundleMap_15.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_15.io.count node _T_85 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_86 = and(_T_85, rsel_16) node _T_87 = and(_T_86, nodeOut.r.bits.last) connect Queue2_BundleMap_16.io.deq.ready, _T_87 invalidate Queue2_BundleMap_16.io.deq.valid invalidate Queue2_BundleMap_16.io.deq.bits.extra_id invalidate Queue2_BundleMap_16.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_16.io.deq.bits.tl_state.size node _T_88 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_89 = and(_T_88, arsel_16) connect Queue2_BundleMap_16.io.enq.valid, _T_89 invalidate Queue2_BundleMap_16.io.enq.ready connect Queue2_BundleMap_16.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_16.io.count node _T_90 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_91 = and(_T_90, rsel_17) node _T_92 = and(_T_91, nodeOut.r.bits.last) connect Queue2_BundleMap_17.io.deq.ready, _T_92 invalidate Queue2_BundleMap_17.io.deq.valid invalidate Queue2_BundleMap_17.io.deq.bits.extra_id invalidate Queue2_BundleMap_17.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_17.io.deq.bits.tl_state.size node _T_93 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_94 = and(_T_93, arsel_17) connect Queue2_BundleMap_17.io.enq.valid, _T_94 invalidate Queue2_BundleMap_17.io.enq.ready connect Queue2_BundleMap_17.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_17.io.count node _T_95 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_96 = and(_T_95, rsel_18) node _T_97 = and(_T_96, nodeOut.r.bits.last) connect Queue2_BundleMap_18.io.deq.ready, _T_97 invalidate Queue2_BundleMap_18.io.deq.valid invalidate Queue2_BundleMap_18.io.deq.bits.extra_id invalidate Queue2_BundleMap_18.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_18.io.deq.bits.tl_state.size node _T_98 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_99 = and(_T_98, arsel_18) connect Queue2_BundleMap_18.io.enq.valid, _T_99 invalidate Queue2_BundleMap_18.io.enq.ready connect Queue2_BundleMap_18.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_18.io.count node _T_100 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_101 = and(_T_100, rsel_19) node _T_102 = and(_T_101, nodeOut.r.bits.last) connect Queue2_BundleMap_19.io.deq.ready, _T_102 invalidate Queue2_BundleMap_19.io.deq.valid invalidate Queue2_BundleMap_19.io.deq.bits.extra_id invalidate Queue2_BundleMap_19.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_19.io.deq.bits.tl_state.size node _T_103 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_104 = and(_T_103, arsel_19) connect Queue2_BundleMap_19.io.enq.valid, _T_104 invalidate Queue2_BundleMap_19.io.enq.ready connect Queue2_BundleMap_19.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_19.io.count node _T_105 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_106 = and(_T_105, rsel_20) node _T_107 = and(_T_106, nodeOut.r.bits.last) connect Queue2_BundleMap_20.io.deq.ready, _T_107 invalidate Queue2_BundleMap_20.io.deq.valid invalidate Queue2_BundleMap_20.io.deq.bits.extra_id invalidate Queue2_BundleMap_20.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_20.io.deq.bits.tl_state.size node _T_108 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_109 = and(_T_108, arsel_20) connect Queue2_BundleMap_20.io.enq.valid, _T_109 invalidate Queue2_BundleMap_20.io.enq.ready connect Queue2_BundleMap_20.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_20.io.count node _T_110 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_111 = and(_T_110, rsel_21) node _T_112 = and(_T_111, nodeOut.r.bits.last) connect Queue2_BundleMap_21.io.deq.ready, _T_112 invalidate Queue2_BundleMap_21.io.deq.valid invalidate Queue2_BundleMap_21.io.deq.bits.extra_id invalidate Queue2_BundleMap_21.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_21.io.deq.bits.tl_state.size node _T_113 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_114 = and(_T_113, arsel_21) connect Queue2_BundleMap_21.io.enq.valid, _T_114 invalidate Queue2_BundleMap_21.io.enq.ready connect Queue2_BundleMap_21.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_21.io.count node _T_115 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_116 = and(_T_115, rsel_22) node _T_117 = and(_T_116, nodeOut.r.bits.last) connect Queue2_BundleMap_22.io.deq.ready, _T_117 invalidate Queue2_BundleMap_22.io.deq.valid invalidate Queue2_BundleMap_22.io.deq.bits.extra_id invalidate Queue2_BundleMap_22.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_22.io.deq.bits.tl_state.size node _T_118 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_119 = and(_T_118, arsel_22) connect Queue2_BundleMap_22.io.enq.valid, _T_119 invalidate Queue2_BundleMap_22.io.enq.ready connect Queue2_BundleMap_22.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_22.io.count node _T_120 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_121 = and(_T_120, rsel_23) node _T_122 = and(_T_121, nodeOut.r.bits.last) connect Queue2_BundleMap_23.io.deq.ready, _T_122 invalidate Queue2_BundleMap_23.io.deq.valid invalidate Queue2_BundleMap_23.io.deq.bits.extra_id invalidate Queue2_BundleMap_23.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_23.io.deq.bits.tl_state.size node _T_123 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_124 = and(_T_123, arsel_23) connect Queue2_BundleMap_23.io.enq.valid, _T_124 invalidate Queue2_BundleMap_23.io.enq.ready connect Queue2_BundleMap_23.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_23.io.count node _T_125 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_126 = and(_T_125, rsel_24) node _T_127 = and(_T_126, nodeOut.r.bits.last) connect Queue2_BundleMap_24.io.deq.ready, _T_127 invalidate Queue2_BundleMap_24.io.deq.valid invalidate Queue2_BundleMap_24.io.deq.bits.extra_id invalidate Queue2_BundleMap_24.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_24.io.deq.bits.tl_state.size node _T_128 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_129 = and(_T_128, arsel_24) connect Queue2_BundleMap_24.io.enq.valid, _T_129 invalidate Queue2_BundleMap_24.io.enq.ready connect Queue2_BundleMap_24.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_24.io.count node _T_130 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_131 = and(_T_130, rsel_25) node _T_132 = and(_T_131, nodeOut.r.bits.last) connect Queue2_BundleMap_25.io.deq.ready, _T_132 invalidate Queue2_BundleMap_25.io.deq.valid invalidate Queue2_BundleMap_25.io.deq.bits.extra_id invalidate Queue2_BundleMap_25.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_25.io.deq.bits.tl_state.size node _T_133 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_134 = and(_T_133, arsel_25) connect Queue2_BundleMap_25.io.enq.valid, _T_134 invalidate Queue2_BundleMap_25.io.enq.ready connect Queue2_BundleMap_25.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_25.io.count node _T_135 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_136 = and(_T_135, rsel_26) node _T_137 = and(_T_136, nodeOut.r.bits.last) connect Queue2_BundleMap_26.io.deq.ready, _T_137 invalidate Queue2_BundleMap_26.io.deq.valid invalidate Queue2_BundleMap_26.io.deq.bits.extra_id invalidate Queue2_BundleMap_26.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_26.io.deq.bits.tl_state.size node _T_138 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_139 = and(_T_138, arsel_26) connect Queue2_BundleMap_26.io.enq.valid, _T_139 invalidate Queue2_BundleMap_26.io.enq.ready connect Queue2_BundleMap_26.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_26.io.count node _T_140 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_141 = and(_T_140, rsel_27) node _T_142 = and(_T_141, nodeOut.r.bits.last) connect Queue2_BundleMap_27.io.deq.ready, _T_142 invalidate Queue2_BundleMap_27.io.deq.valid invalidate Queue2_BundleMap_27.io.deq.bits.extra_id invalidate Queue2_BundleMap_27.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_27.io.deq.bits.tl_state.size node _T_143 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_144 = and(_T_143, arsel_27) connect Queue2_BundleMap_27.io.enq.valid, _T_144 invalidate Queue2_BundleMap_27.io.enq.ready connect Queue2_BundleMap_27.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_27.io.count node _T_145 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_146 = and(_T_145, rsel_28) node _T_147 = and(_T_146, nodeOut.r.bits.last) connect Queue2_BundleMap_28.io.deq.ready, _T_147 invalidate Queue2_BundleMap_28.io.deq.valid invalidate Queue2_BundleMap_28.io.deq.bits.extra_id invalidate Queue2_BundleMap_28.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_28.io.deq.bits.tl_state.size node _T_148 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_149 = and(_T_148, arsel_28) connect Queue2_BundleMap_28.io.enq.valid, _T_149 invalidate Queue2_BundleMap_28.io.enq.ready connect Queue2_BundleMap_28.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_28.io.count node _T_150 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_151 = and(_T_150, rsel_29) node _T_152 = and(_T_151, nodeOut.r.bits.last) connect Queue2_BundleMap_29.io.deq.ready, _T_152 invalidate Queue2_BundleMap_29.io.deq.valid invalidate Queue2_BundleMap_29.io.deq.bits.extra_id invalidate Queue2_BundleMap_29.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_29.io.deq.bits.tl_state.size node _T_153 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_154 = and(_T_153, arsel_29) connect Queue2_BundleMap_29.io.enq.valid, _T_154 invalidate Queue2_BundleMap_29.io.enq.ready connect Queue2_BundleMap_29.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_29.io.count node _T_155 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_156 = and(_T_155, rsel_30) node _T_157 = and(_T_156, nodeOut.r.bits.last) connect Queue2_BundleMap_30.io.deq.ready, _T_157 invalidate Queue2_BundleMap_30.io.deq.valid invalidate Queue2_BundleMap_30.io.deq.bits.extra_id invalidate Queue2_BundleMap_30.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_30.io.deq.bits.tl_state.size node _T_158 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_159 = and(_T_158, arsel_30) connect Queue2_BundleMap_30.io.enq.valid, _T_159 invalidate Queue2_BundleMap_30.io.enq.ready connect Queue2_BundleMap_30.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_30.io.count node _T_160 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_161 = and(_T_160, rsel_31) node _T_162 = and(_T_161, nodeOut.r.bits.last) connect Queue2_BundleMap_31.io.deq.ready, _T_162 invalidate Queue2_BundleMap_31.io.deq.valid invalidate Queue2_BundleMap_31.io.deq.bits.extra_id invalidate Queue2_BundleMap_31.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_31.io.deq.bits.tl_state.size node _T_163 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_164 = and(_T_163, arsel_31) connect Queue2_BundleMap_31.io.enq.valid, _T_164 invalidate Queue2_BundleMap_31.io.enq.ready connect Queue2_BundleMap_31.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_31.io.count node _T_165 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_166 = and(_T_165, rsel_32) node _T_167 = and(_T_166, nodeOut.r.bits.last) connect Queue2_BundleMap_32.io.deq.ready, _T_167 invalidate Queue2_BundleMap_32.io.deq.valid invalidate Queue2_BundleMap_32.io.deq.bits.extra_id invalidate Queue2_BundleMap_32.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_32.io.deq.bits.tl_state.size node _T_168 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_169 = and(_T_168, arsel_32) connect Queue2_BundleMap_32.io.enq.valid, _T_169 invalidate Queue2_BundleMap_32.io.enq.ready connect Queue2_BundleMap_32.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_32.io.count node _T_170 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_171 = and(_T_170, rsel_33) node _T_172 = and(_T_171, nodeOut.r.bits.last) connect Queue2_BundleMap_33.io.deq.ready, _T_172 invalidate Queue2_BundleMap_33.io.deq.valid invalidate Queue2_BundleMap_33.io.deq.bits.extra_id invalidate Queue2_BundleMap_33.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_33.io.deq.bits.tl_state.size node _T_173 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_174 = and(_T_173, arsel_33) connect Queue2_BundleMap_33.io.enq.valid, _T_174 invalidate Queue2_BundleMap_33.io.enq.ready connect Queue2_BundleMap_33.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_33.io.count node _T_175 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_176 = and(_T_175, rsel_34) node _T_177 = and(_T_176, nodeOut.r.bits.last) connect Queue2_BundleMap_34.io.deq.ready, _T_177 invalidate Queue2_BundleMap_34.io.deq.valid invalidate Queue2_BundleMap_34.io.deq.bits.extra_id invalidate Queue2_BundleMap_34.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_34.io.deq.bits.tl_state.size node _T_178 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_179 = and(_T_178, arsel_34) connect Queue2_BundleMap_34.io.enq.valid, _T_179 invalidate Queue2_BundleMap_34.io.enq.ready connect Queue2_BundleMap_34.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_34.io.count node _T_180 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_181 = and(_T_180, rsel_35) node _T_182 = and(_T_181, nodeOut.r.bits.last) connect Queue2_BundleMap_35.io.deq.ready, _T_182 invalidate Queue2_BundleMap_35.io.deq.valid invalidate Queue2_BundleMap_35.io.deq.bits.extra_id invalidate Queue2_BundleMap_35.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_35.io.deq.bits.tl_state.size node _T_183 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_184 = and(_T_183, arsel_35) connect Queue2_BundleMap_35.io.enq.valid, _T_184 invalidate Queue2_BundleMap_35.io.enq.ready connect Queue2_BundleMap_35.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_35.io.count node _T_185 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_186 = and(_T_185, rsel_36) node _T_187 = and(_T_186, nodeOut.r.bits.last) connect Queue2_BundleMap_36.io.deq.ready, _T_187 invalidate Queue2_BundleMap_36.io.deq.valid invalidate Queue2_BundleMap_36.io.deq.bits.extra_id invalidate Queue2_BundleMap_36.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_36.io.deq.bits.tl_state.size node _T_188 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_189 = and(_T_188, arsel_36) connect Queue2_BundleMap_36.io.enq.valid, _T_189 invalidate Queue2_BundleMap_36.io.enq.ready connect Queue2_BundleMap_36.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_36.io.count node _T_190 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_191 = and(_T_190, rsel_37) node _T_192 = and(_T_191, nodeOut.r.bits.last) connect Queue2_BundleMap_37.io.deq.ready, _T_192 invalidate Queue2_BundleMap_37.io.deq.valid invalidate Queue2_BundleMap_37.io.deq.bits.extra_id invalidate Queue2_BundleMap_37.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_37.io.deq.bits.tl_state.size node _T_193 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_194 = and(_T_193, arsel_37) connect Queue2_BundleMap_37.io.enq.valid, _T_194 invalidate Queue2_BundleMap_37.io.enq.ready connect Queue2_BundleMap_37.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_37.io.count node _T_195 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_196 = and(_T_195, rsel_38) node _T_197 = and(_T_196, nodeOut.r.bits.last) connect Queue2_BundleMap_38.io.deq.ready, _T_197 invalidate Queue2_BundleMap_38.io.deq.valid invalidate Queue2_BundleMap_38.io.deq.bits.extra_id invalidate Queue2_BundleMap_38.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_38.io.deq.bits.tl_state.size node _T_198 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_199 = and(_T_198, arsel_38) connect Queue2_BundleMap_38.io.enq.valid, _T_199 invalidate Queue2_BundleMap_38.io.enq.ready connect Queue2_BundleMap_38.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_38.io.count node _T_200 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_201 = and(_T_200, rsel_39) node _T_202 = and(_T_201, nodeOut.r.bits.last) connect Queue2_BundleMap_39.io.deq.ready, _T_202 invalidate Queue2_BundleMap_39.io.deq.valid invalidate Queue2_BundleMap_39.io.deq.bits.extra_id invalidate Queue2_BundleMap_39.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_39.io.deq.bits.tl_state.size node _T_203 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_204 = and(_T_203, arsel_39) connect Queue2_BundleMap_39.io.enq.valid, _T_204 invalidate Queue2_BundleMap_39.io.enq.ready connect Queue2_BundleMap_39.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_39.io.count node _T_205 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_206 = and(_T_205, rsel_40) node _T_207 = and(_T_206, nodeOut.r.bits.last) connect Queue2_BundleMap_40.io.deq.ready, _T_207 invalidate Queue2_BundleMap_40.io.deq.valid invalidate Queue2_BundleMap_40.io.deq.bits.extra_id invalidate Queue2_BundleMap_40.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_40.io.deq.bits.tl_state.size node _T_208 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_209 = and(_T_208, arsel_40) connect Queue2_BundleMap_40.io.enq.valid, _T_209 invalidate Queue2_BundleMap_40.io.enq.ready connect Queue2_BundleMap_40.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_40.io.count node _T_210 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_211 = and(_T_210, rsel_41) node _T_212 = and(_T_211, nodeOut.r.bits.last) connect Queue2_BundleMap_41.io.deq.ready, _T_212 invalidate Queue2_BundleMap_41.io.deq.valid invalidate Queue2_BundleMap_41.io.deq.bits.extra_id invalidate Queue2_BundleMap_41.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_41.io.deq.bits.tl_state.size node _T_213 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_214 = and(_T_213, arsel_41) connect Queue2_BundleMap_41.io.enq.valid, _T_214 invalidate Queue2_BundleMap_41.io.enq.ready connect Queue2_BundleMap_41.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_41.io.count node _T_215 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_216 = and(_T_215, rsel_42) node _T_217 = and(_T_216, nodeOut.r.bits.last) connect Queue2_BundleMap_42.io.deq.ready, _T_217 invalidate Queue2_BundleMap_42.io.deq.valid invalidate Queue2_BundleMap_42.io.deq.bits.extra_id invalidate Queue2_BundleMap_42.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_42.io.deq.bits.tl_state.size node _T_218 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_219 = and(_T_218, arsel_42) connect Queue2_BundleMap_42.io.enq.valid, _T_219 invalidate Queue2_BundleMap_42.io.enq.ready connect Queue2_BundleMap_42.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_42.io.count node _T_220 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_221 = and(_T_220, rsel_43) node _T_222 = and(_T_221, nodeOut.r.bits.last) connect Queue2_BundleMap_43.io.deq.ready, _T_222 invalidate Queue2_BundleMap_43.io.deq.valid invalidate Queue2_BundleMap_43.io.deq.bits.extra_id invalidate Queue2_BundleMap_43.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_43.io.deq.bits.tl_state.size node _T_223 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_224 = and(_T_223, arsel_43) connect Queue2_BundleMap_43.io.enq.valid, _T_224 invalidate Queue2_BundleMap_43.io.enq.ready connect Queue2_BundleMap_43.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_43.io.count node _T_225 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_226 = and(_T_225, rsel_44) node _T_227 = and(_T_226, nodeOut.r.bits.last) connect Queue2_BundleMap_44.io.deq.ready, _T_227 invalidate Queue2_BundleMap_44.io.deq.valid invalidate Queue2_BundleMap_44.io.deq.bits.extra_id invalidate Queue2_BundleMap_44.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_44.io.deq.bits.tl_state.size node _T_228 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_229 = and(_T_228, arsel_44) connect Queue2_BundleMap_44.io.enq.valid, _T_229 invalidate Queue2_BundleMap_44.io.enq.ready connect Queue2_BundleMap_44.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_44.io.count node _T_230 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_231 = and(_T_230, rsel_45) node _T_232 = and(_T_231, nodeOut.r.bits.last) connect Queue2_BundleMap_45.io.deq.ready, _T_232 invalidate Queue2_BundleMap_45.io.deq.valid invalidate Queue2_BundleMap_45.io.deq.bits.extra_id invalidate Queue2_BundleMap_45.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_45.io.deq.bits.tl_state.size node _T_233 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_234 = and(_T_233, arsel_45) connect Queue2_BundleMap_45.io.enq.valid, _T_234 invalidate Queue2_BundleMap_45.io.enq.ready connect Queue2_BundleMap_45.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_45.io.count node _T_235 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_236 = and(_T_235, rsel_46) node _T_237 = and(_T_236, nodeOut.r.bits.last) connect Queue2_BundleMap_46.io.deq.ready, _T_237 invalidate Queue2_BundleMap_46.io.deq.valid invalidate Queue2_BundleMap_46.io.deq.bits.extra_id invalidate Queue2_BundleMap_46.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_46.io.deq.bits.tl_state.size node _T_238 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_239 = and(_T_238, arsel_46) connect Queue2_BundleMap_46.io.enq.valid, _T_239 invalidate Queue2_BundleMap_46.io.enq.ready connect Queue2_BundleMap_46.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_46.io.count node _T_240 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_241 = and(_T_240, rsel_47) node _T_242 = and(_T_241, nodeOut.r.bits.last) connect Queue2_BundleMap_47.io.deq.ready, _T_242 invalidate Queue2_BundleMap_47.io.deq.valid invalidate Queue2_BundleMap_47.io.deq.bits.extra_id invalidate Queue2_BundleMap_47.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_47.io.deq.bits.tl_state.size node _T_243 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_244 = and(_T_243, arsel_47) connect Queue2_BundleMap_47.io.enq.valid, _T_244 invalidate Queue2_BundleMap_47.io.enq.ready connect Queue2_BundleMap_47.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_47.io.count node _T_245 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_246 = and(_T_245, rsel_48) node _T_247 = and(_T_246, nodeOut.r.bits.last) connect Queue2_BundleMap_48.io.deq.ready, _T_247 invalidate Queue2_BundleMap_48.io.deq.valid invalidate Queue2_BundleMap_48.io.deq.bits.extra_id invalidate Queue2_BundleMap_48.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_48.io.deq.bits.tl_state.size node _T_248 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_249 = and(_T_248, arsel_48) connect Queue2_BundleMap_48.io.enq.valid, _T_249 invalidate Queue2_BundleMap_48.io.enq.ready connect Queue2_BundleMap_48.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_48.io.count node _T_250 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_251 = and(_T_250, rsel_49) node _T_252 = and(_T_251, nodeOut.r.bits.last) connect Queue2_BundleMap_49.io.deq.ready, _T_252 invalidate Queue2_BundleMap_49.io.deq.valid invalidate Queue2_BundleMap_49.io.deq.bits.extra_id invalidate Queue2_BundleMap_49.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_49.io.deq.bits.tl_state.size node _T_253 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_254 = and(_T_253, arsel_49) connect Queue2_BundleMap_49.io.enq.valid, _T_254 invalidate Queue2_BundleMap_49.io.enq.ready connect Queue2_BundleMap_49.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_49.io.count node _T_255 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_256 = and(_T_255, rsel_50) node _T_257 = and(_T_256, nodeOut.r.bits.last) connect Queue2_BundleMap_50.io.deq.ready, _T_257 invalidate Queue2_BundleMap_50.io.deq.valid invalidate Queue2_BundleMap_50.io.deq.bits.extra_id invalidate Queue2_BundleMap_50.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_50.io.deq.bits.tl_state.size node _T_258 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_259 = and(_T_258, arsel_50) connect Queue2_BundleMap_50.io.enq.valid, _T_259 invalidate Queue2_BundleMap_50.io.enq.ready connect Queue2_BundleMap_50.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_50.io.count node _T_260 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_261 = and(_T_260, rsel_51) node _T_262 = and(_T_261, nodeOut.r.bits.last) connect Queue2_BundleMap_51.io.deq.ready, _T_262 invalidate Queue2_BundleMap_51.io.deq.valid invalidate Queue2_BundleMap_51.io.deq.bits.extra_id invalidate Queue2_BundleMap_51.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_51.io.deq.bits.tl_state.size node _T_263 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_264 = and(_T_263, arsel_51) connect Queue2_BundleMap_51.io.enq.valid, _T_264 invalidate Queue2_BundleMap_51.io.enq.ready connect Queue2_BundleMap_51.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_51.io.count node _T_265 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_266 = and(_T_265, rsel_52) node _T_267 = and(_T_266, nodeOut.r.bits.last) connect Queue2_BundleMap_52.io.deq.ready, _T_267 invalidate Queue2_BundleMap_52.io.deq.valid invalidate Queue2_BundleMap_52.io.deq.bits.extra_id invalidate Queue2_BundleMap_52.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_52.io.deq.bits.tl_state.size node _T_268 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_269 = and(_T_268, arsel_52) connect Queue2_BundleMap_52.io.enq.valid, _T_269 invalidate Queue2_BundleMap_52.io.enq.ready connect Queue2_BundleMap_52.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_52.io.count node _T_270 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_271 = and(_T_270, rsel_53) node _T_272 = and(_T_271, nodeOut.r.bits.last) connect Queue2_BundleMap_53.io.deq.ready, _T_272 invalidate Queue2_BundleMap_53.io.deq.valid invalidate Queue2_BundleMap_53.io.deq.bits.extra_id invalidate Queue2_BundleMap_53.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_53.io.deq.bits.tl_state.size node _T_273 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_274 = and(_T_273, arsel_53) connect Queue2_BundleMap_53.io.enq.valid, _T_274 invalidate Queue2_BundleMap_53.io.enq.ready connect Queue2_BundleMap_53.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_53.io.count node _T_275 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_276 = and(_T_275, rsel_54) node _T_277 = and(_T_276, nodeOut.r.bits.last) connect Queue2_BundleMap_54.io.deq.ready, _T_277 invalidate Queue2_BundleMap_54.io.deq.valid invalidate Queue2_BundleMap_54.io.deq.bits.extra_id invalidate Queue2_BundleMap_54.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_54.io.deq.bits.tl_state.size node _T_278 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_279 = and(_T_278, arsel_54) connect Queue2_BundleMap_54.io.enq.valid, _T_279 invalidate Queue2_BundleMap_54.io.enq.ready connect Queue2_BundleMap_54.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_54.io.count node _T_280 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_281 = and(_T_280, rsel_55) node _T_282 = and(_T_281, nodeOut.r.bits.last) connect Queue2_BundleMap_55.io.deq.ready, _T_282 invalidate Queue2_BundleMap_55.io.deq.valid invalidate Queue2_BundleMap_55.io.deq.bits.extra_id invalidate Queue2_BundleMap_55.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_55.io.deq.bits.tl_state.size node _T_283 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_284 = and(_T_283, arsel_55) connect Queue2_BundleMap_55.io.enq.valid, _T_284 invalidate Queue2_BundleMap_55.io.enq.ready connect Queue2_BundleMap_55.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_55.io.count node _T_285 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_286 = and(_T_285, rsel_56) node _T_287 = and(_T_286, nodeOut.r.bits.last) connect Queue2_BundleMap_56.io.deq.ready, _T_287 invalidate Queue2_BundleMap_56.io.deq.valid invalidate Queue2_BundleMap_56.io.deq.bits.extra_id invalidate Queue2_BundleMap_56.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_56.io.deq.bits.tl_state.size node _T_288 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_289 = and(_T_288, arsel_56) connect Queue2_BundleMap_56.io.enq.valid, _T_289 invalidate Queue2_BundleMap_56.io.enq.ready connect Queue2_BundleMap_56.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_56.io.count node _T_290 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_291 = and(_T_290, rsel_57) node _T_292 = and(_T_291, nodeOut.r.bits.last) connect Queue2_BundleMap_57.io.deq.ready, _T_292 invalidate Queue2_BundleMap_57.io.deq.valid invalidate Queue2_BundleMap_57.io.deq.bits.extra_id invalidate Queue2_BundleMap_57.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_57.io.deq.bits.tl_state.size node _T_293 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_294 = and(_T_293, arsel_57) connect Queue2_BundleMap_57.io.enq.valid, _T_294 invalidate Queue2_BundleMap_57.io.enq.ready connect Queue2_BundleMap_57.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_57.io.count node _T_295 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_296 = and(_T_295, rsel_58) node _T_297 = and(_T_296, nodeOut.r.bits.last) connect Queue2_BundleMap_58.io.deq.ready, _T_297 invalidate Queue2_BundleMap_58.io.deq.valid invalidate Queue2_BundleMap_58.io.deq.bits.extra_id invalidate Queue2_BundleMap_58.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_58.io.deq.bits.tl_state.size node _T_298 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_299 = and(_T_298, arsel_58) connect Queue2_BundleMap_58.io.enq.valid, _T_299 invalidate Queue2_BundleMap_58.io.enq.ready connect Queue2_BundleMap_58.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_58.io.count node _T_300 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_301 = and(_T_300, rsel_59) node _T_302 = and(_T_301, nodeOut.r.bits.last) connect Queue2_BundleMap_59.io.deq.ready, _T_302 invalidate Queue2_BundleMap_59.io.deq.valid invalidate Queue2_BundleMap_59.io.deq.bits.extra_id invalidate Queue2_BundleMap_59.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_59.io.deq.bits.tl_state.size node _T_303 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_304 = and(_T_303, arsel_59) connect Queue2_BundleMap_59.io.enq.valid, _T_304 invalidate Queue2_BundleMap_59.io.enq.ready connect Queue2_BundleMap_59.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_59.io.count node _T_305 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_306 = and(_T_305, rsel_60) node _T_307 = and(_T_306, nodeOut.r.bits.last) connect Queue2_BundleMap_60.io.deq.ready, _T_307 invalidate Queue2_BundleMap_60.io.deq.valid invalidate Queue2_BundleMap_60.io.deq.bits.extra_id invalidate Queue2_BundleMap_60.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_60.io.deq.bits.tl_state.size node _T_308 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_309 = and(_T_308, arsel_60) connect Queue2_BundleMap_60.io.enq.valid, _T_309 invalidate Queue2_BundleMap_60.io.enq.ready connect Queue2_BundleMap_60.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_60.io.count node _T_310 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_311 = and(_T_310, rsel_61) node _T_312 = and(_T_311, nodeOut.r.bits.last) connect Queue2_BundleMap_61.io.deq.ready, _T_312 invalidate Queue2_BundleMap_61.io.deq.valid invalidate Queue2_BundleMap_61.io.deq.bits.extra_id invalidate Queue2_BundleMap_61.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_61.io.deq.bits.tl_state.size node _T_313 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_314 = and(_T_313, arsel_61) connect Queue2_BundleMap_61.io.enq.valid, _T_314 invalidate Queue2_BundleMap_61.io.enq.ready connect Queue2_BundleMap_61.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_61.io.count node _T_315 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_316 = and(_T_315, rsel_62) node _T_317 = and(_T_316, nodeOut.r.bits.last) connect Queue2_BundleMap_62.io.deq.ready, _T_317 invalidate Queue2_BundleMap_62.io.deq.valid invalidate Queue2_BundleMap_62.io.deq.bits.extra_id invalidate Queue2_BundleMap_62.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_62.io.deq.bits.tl_state.size node _T_318 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_319 = and(_T_318, arsel_62) connect Queue2_BundleMap_62.io.enq.valid, _T_319 invalidate Queue2_BundleMap_62.io.enq.ready connect Queue2_BundleMap_62.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_62.io.count node _T_320 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_321 = and(_T_320, rsel_63) node _T_322 = and(_T_321, nodeOut.r.bits.last) connect Queue2_BundleMap_63.io.deq.ready, _T_322 invalidate Queue2_BundleMap_63.io.deq.valid invalidate Queue2_BundleMap_63.io.deq.bits.extra_id invalidate Queue2_BundleMap_63.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_63.io.deq.bits.tl_state.size node _T_323 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_324 = and(_T_323, arsel_63) connect Queue2_BundleMap_63.io.enq.valid, _T_324 invalidate Queue2_BundleMap_63.io.enq.ready connect Queue2_BundleMap_63.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_63.io.count node _T_325 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_326 = and(_T_325, rsel_64) node _T_327 = and(_T_326, nodeOut.r.bits.last) connect Queue2_BundleMap_64.io.deq.ready, _T_327 invalidate Queue2_BundleMap_64.io.deq.valid invalidate Queue2_BundleMap_64.io.deq.bits.extra_id invalidate Queue2_BundleMap_64.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_64.io.deq.bits.tl_state.size node _T_328 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_329 = and(_T_328, arsel_64) connect Queue2_BundleMap_64.io.enq.valid, _T_329 invalidate Queue2_BundleMap_64.io.enq.ready connect Queue2_BundleMap_64.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_64.io.count node _T_330 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_331 = and(_T_330, rsel_65) node _T_332 = and(_T_331, nodeOut.r.bits.last) connect Queue2_BundleMap_65.io.deq.ready, _T_332 invalidate Queue2_BundleMap_65.io.deq.valid invalidate Queue2_BundleMap_65.io.deq.bits.extra_id invalidate Queue2_BundleMap_65.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_65.io.deq.bits.tl_state.size node _T_333 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_334 = and(_T_333, arsel_65) connect Queue2_BundleMap_65.io.enq.valid, _T_334 invalidate Queue2_BundleMap_65.io.enq.ready connect Queue2_BundleMap_65.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_65.io.count node _T_335 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_336 = and(_T_335, rsel_66) node _T_337 = and(_T_336, nodeOut.r.bits.last) connect Queue2_BundleMap_66.io.deq.ready, _T_337 invalidate Queue2_BundleMap_66.io.deq.valid invalidate Queue2_BundleMap_66.io.deq.bits.extra_id invalidate Queue2_BundleMap_66.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_66.io.deq.bits.tl_state.size node _T_338 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_339 = and(_T_338, arsel_66) connect Queue2_BundleMap_66.io.enq.valid, _T_339 invalidate Queue2_BundleMap_66.io.enq.ready connect Queue2_BundleMap_66.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_66.io.count node _T_340 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_341 = and(_T_340, rsel_67) node _T_342 = and(_T_341, nodeOut.r.bits.last) connect Queue2_BundleMap_67.io.deq.ready, _T_342 invalidate Queue2_BundleMap_67.io.deq.valid invalidate Queue2_BundleMap_67.io.deq.bits.extra_id invalidate Queue2_BundleMap_67.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_67.io.deq.bits.tl_state.size node _T_343 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_344 = and(_T_343, arsel_67) connect Queue2_BundleMap_67.io.enq.valid, _T_344 invalidate Queue2_BundleMap_67.io.enq.ready connect Queue2_BundleMap_67.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_67.io.count node _T_345 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_346 = and(_T_345, rsel_68) node _T_347 = and(_T_346, nodeOut.r.bits.last) connect Queue2_BundleMap_68.io.deq.ready, _T_347 invalidate Queue2_BundleMap_68.io.deq.valid invalidate Queue2_BundleMap_68.io.deq.bits.extra_id invalidate Queue2_BundleMap_68.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_68.io.deq.bits.tl_state.size node _T_348 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_349 = and(_T_348, arsel_68) connect Queue2_BundleMap_68.io.enq.valid, _T_349 invalidate Queue2_BundleMap_68.io.enq.ready connect Queue2_BundleMap_68.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_68.io.count node _T_350 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_351 = and(_T_350, rsel_69) node _T_352 = and(_T_351, nodeOut.r.bits.last) connect Queue2_BundleMap_69.io.deq.ready, _T_352 invalidate Queue2_BundleMap_69.io.deq.valid invalidate Queue2_BundleMap_69.io.deq.bits.extra_id invalidate Queue2_BundleMap_69.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_69.io.deq.bits.tl_state.size node _T_353 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_354 = and(_T_353, arsel_69) connect Queue2_BundleMap_69.io.enq.valid, _T_354 invalidate Queue2_BundleMap_69.io.enq.ready connect Queue2_BundleMap_69.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_69.io.count node _T_355 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_356 = and(_T_355, rsel_70) node _T_357 = and(_T_356, nodeOut.r.bits.last) connect Queue2_BundleMap_70.io.deq.ready, _T_357 invalidate Queue2_BundleMap_70.io.deq.valid invalidate Queue2_BundleMap_70.io.deq.bits.extra_id invalidate Queue2_BundleMap_70.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_70.io.deq.bits.tl_state.size node _T_358 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_359 = and(_T_358, arsel_70) connect Queue2_BundleMap_70.io.enq.valid, _T_359 invalidate Queue2_BundleMap_70.io.enq.ready connect Queue2_BundleMap_70.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_70.io.count node _T_360 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_361 = and(_T_360, rsel_71) node _T_362 = and(_T_361, nodeOut.r.bits.last) connect Queue2_BundleMap_71.io.deq.ready, _T_362 invalidate Queue2_BundleMap_71.io.deq.valid invalidate Queue2_BundleMap_71.io.deq.bits.extra_id invalidate Queue2_BundleMap_71.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_71.io.deq.bits.tl_state.size node _T_363 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_364 = and(_T_363, arsel_71) connect Queue2_BundleMap_71.io.enq.valid, _T_364 invalidate Queue2_BundleMap_71.io.enq.ready connect Queue2_BundleMap_71.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_71.io.count node _T_365 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_366 = and(_T_365, rsel_72) node _T_367 = and(_T_366, nodeOut.r.bits.last) connect Queue2_BundleMap_72.io.deq.ready, _T_367 invalidate Queue2_BundleMap_72.io.deq.valid invalidate Queue2_BundleMap_72.io.deq.bits.extra_id invalidate Queue2_BundleMap_72.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_72.io.deq.bits.tl_state.size node _T_368 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_369 = and(_T_368, arsel_72) connect Queue2_BundleMap_72.io.enq.valid, _T_369 invalidate Queue2_BundleMap_72.io.enq.ready connect Queue2_BundleMap_72.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_72.io.count node _T_370 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_371 = and(_T_370, rsel_73) node _T_372 = and(_T_371, nodeOut.r.bits.last) connect Queue2_BundleMap_73.io.deq.ready, _T_372 invalidate Queue2_BundleMap_73.io.deq.valid invalidate Queue2_BundleMap_73.io.deq.bits.extra_id invalidate Queue2_BundleMap_73.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_73.io.deq.bits.tl_state.size node _T_373 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_374 = and(_T_373, arsel_73) connect Queue2_BundleMap_73.io.enq.valid, _T_374 invalidate Queue2_BundleMap_73.io.enq.ready connect Queue2_BundleMap_73.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_73.io.count node _T_375 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_376 = and(_T_375, rsel_74) node _T_377 = and(_T_376, nodeOut.r.bits.last) connect Queue2_BundleMap_74.io.deq.ready, _T_377 invalidate Queue2_BundleMap_74.io.deq.valid invalidate Queue2_BundleMap_74.io.deq.bits.extra_id invalidate Queue2_BundleMap_74.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_74.io.deq.bits.tl_state.size node _T_378 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_379 = and(_T_378, arsel_74) connect Queue2_BundleMap_74.io.enq.valid, _T_379 invalidate Queue2_BundleMap_74.io.enq.ready connect Queue2_BundleMap_74.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_74.io.count node _T_380 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_381 = and(_T_380, rsel_75) node _T_382 = and(_T_381, nodeOut.r.bits.last) connect Queue2_BundleMap_75.io.deq.ready, _T_382 invalidate Queue2_BundleMap_75.io.deq.valid invalidate Queue2_BundleMap_75.io.deq.bits.extra_id invalidate Queue2_BundleMap_75.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_75.io.deq.bits.tl_state.size node _T_383 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_384 = and(_T_383, arsel_75) connect Queue2_BundleMap_75.io.enq.valid, _T_384 invalidate Queue2_BundleMap_75.io.enq.ready connect Queue2_BundleMap_75.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_75.io.count node _T_385 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_386 = and(_T_385, rsel_76) node _T_387 = and(_T_386, nodeOut.r.bits.last) connect Queue2_BundleMap_76.io.deq.ready, _T_387 invalidate Queue2_BundleMap_76.io.deq.valid invalidate Queue2_BundleMap_76.io.deq.bits.extra_id invalidate Queue2_BundleMap_76.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_76.io.deq.bits.tl_state.size node _T_388 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_389 = and(_T_388, arsel_76) connect Queue2_BundleMap_76.io.enq.valid, _T_389 invalidate Queue2_BundleMap_76.io.enq.ready connect Queue2_BundleMap_76.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_76.io.count node _T_390 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_391 = and(_T_390, rsel_77) node _T_392 = and(_T_391, nodeOut.r.bits.last) connect Queue2_BundleMap_77.io.deq.ready, _T_392 invalidate Queue2_BundleMap_77.io.deq.valid invalidate Queue2_BundleMap_77.io.deq.bits.extra_id invalidate Queue2_BundleMap_77.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_77.io.deq.bits.tl_state.size node _T_393 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_394 = and(_T_393, arsel_77) connect Queue2_BundleMap_77.io.enq.valid, _T_394 invalidate Queue2_BundleMap_77.io.enq.ready connect Queue2_BundleMap_77.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_77.io.count node _T_395 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_396 = and(_T_395, rsel_78) node _T_397 = and(_T_396, nodeOut.r.bits.last) connect Queue2_BundleMap_78.io.deq.ready, _T_397 invalidate Queue2_BundleMap_78.io.deq.valid invalidate Queue2_BundleMap_78.io.deq.bits.extra_id invalidate Queue2_BundleMap_78.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_78.io.deq.bits.tl_state.size node _T_398 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_399 = and(_T_398, arsel_78) connect Queue2_BundleMap_78.io.enq.valid, _T_399 invalidate Queue2_BundleMap_78.io.enq.ready connect Queue2_BundleMap_78.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_78.io.count node _T_400 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_401 = and(_T_400, rsel_79) node _T_402 = and(_T_401, nodeOut.r.bits.last) connect Queue2_BundleMap_79.io.deq.ready, _T_402 invalidate Queue2_BundleMap_79.io.deq.valid invalidate Queue2_BundleMap_79.io.deq.bits.extra_id invalidate Queue2_BundleMap_79.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_79.io.deq.bits.tl_state.size node _T_403 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_404 = and(_T_403, arsel_79) connect Queue2_BundleMap_79.io.enq.valid, _T_404 invalidate Queue2_BundleMap_79.io.enq.ready connect Queue2_BundleMap_79.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_79.io.count node _T_405 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_406 = and(_T_405, rsel_80) node _T_407 = and(_T_406, nodeOut.r.bits.last) connect Queue2_BundleMap_80.io.deq.ready, _T_407 invalidate Queue2_BundleMap_80.io.deq.valid invalidate Queue2_BundleMap_80.io.deq.bits.extra_id invalidate Queue2_BundleMap_80.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_80.io.deq.bits.tl_state.size node _T_408 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_409 = and(_T_408, arsel_80) connect Queue2_BundleMap_80.io.enq.valid, _T_409 invalidate Queue2_BundleMap_80.io.enq.ready connect Queue2_BundleMap_80.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_80.io.count node _T_410 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_411 = and(_T_410, rsel_81) node _T_412 = and(_T_411, nodeOut.r.bits.last) connect Queue2_BundleMap_81.io.deq.ready, _T_412 invalidate Queue2_BundleMap_81.io.deq.valid invalidate Queue2_BundleMap_81.io.deq.bits.extra_id invalidate Queue2_BundleMap_81.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_81.io.deq.bits.tl_state.size node _T_413 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_414 = and(_T_413, arsel_81) connect Queue2_BundleMap_81.io.enq.valid, _T_414 invalidate Queue2_BundleMap_81.io.enq.ready connect Queue2_BundleMap_81.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_81.io.count node _T_415 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_416 = and(_T_415, rsel_82) node _T_417 = and(_T_416, nodeOut.r.bits.last) connect Queue2_BundleMap_82.io.deq.ready, _T_417 invalidate Queue2_BundleMap_82.io.deq.valid invalidate Queue2_BundleMap_82.io.deq.bits.extra_id invalidate Queue2_BundleMap_82.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_82.io.deq.bits.tl_state.size node _T_418 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_419 = and(_T_418, arsel_82) connect Queue2_BundleMap_82.io.enq.valid, _T_419 invalidate Queue2_BundleMap_82.io.enq.ready connect Queue2_BundleMap_82.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_82.io.count node _T_420 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_421 = and(_T_420, rsel_83) node _T_422 = and(_T_421, nodeOut.r.bits.last) connect Queue2_BundleMap_83.io.deq.ready, _T_422 invalidate Queue2_BundleMap_83.io.deq.valid invalidate Queue2_BundleMap_83.io.deq.bits.extra_id invalidate Queue2_BundleMap_83.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_83.io.deq.bits.tl_state.size node _T_423 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_424 = and(_T_423, arsel_83) connect Queue2_BundleMap_83.io.enq.valid, _T_424 invalidate Queue2_BundleMap_83.io.enq.ready connect Queue2_BundleMap_83.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_83.io.count node _T_425 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_426 = and(_T_425, rsel_84) node _T_427 = and(_T_426, nodeOut.r.bits.last) connect Queue2_BundleMap_84.io.deq.ready, _T_427 invalidate Queue2_BundleMap_84.io.deq.valid invalidate Queue2_BundleMap_84.io.deq.bits.extra_id invalidate Queue2_BundleMap_84.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_84.io.deq.bits.tl_state.size node _T_428 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_429 = and(_T_428, arsel_84) connect Queue2_BundleMap_84.io.enq.valid, _T_429 invalidate Queue2_BundleMap_84.io.enq.ready connect Queue2_BundleMap_84.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_84.io.count node _T_430 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_431 = and(_T_430, rsel_85) node _T_432 = and(_T_431, nodeOut.r.bits.last) connect Queue2_BundleMap_85.io.deq.ready, _T_432 invalidate Queue2_BundleMap_85.io.deq.valid invalidate Queue2_BundleMap_85.io.deq.bits.extra_id invalidate Queue2_BundleMap_85.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_85.io.deq.bits.tl_state.size node _T_433 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_434 = and(_T_433, arsel_85) connect Queue2_BundleMap_85.io.enq.valid, _T_434 invalidate Queue2_BundleMap_85.io.enq.ready connect Queue2_BundleMap_85.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_85.io.count node _T_435 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_436 = and(_T_435, rsel_86) node _T_437 = and(_T_436, nodeOut.r.bits.last) connect Queue2_BundleMap_86.io.deq.ready, _T_437 invalidate Queue2_BundleMap_86.io.deq.valid invalidate Queue2_BundleMap_86.io.deq.bits.extra_id invalidate Queue2_BundleMap_86.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_86.io.deq.bits.tl_state.size node _T_438 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_439 = and(_T_438, arsel_86) connect Queue2_BundleMap_86.io.enq.valid, _T_439 invalidate Queue2_BundleMap_86.io.enq.ready connect Queue2_BundleMap_86.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_86.io.count node _T_440 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_441 = and(_T_440, rsel_87) node _T_442 = and(_T_441, nodeOut.r.bits.last) connect Queue2_BundleMap_87.io.deq.ready, _T_442 invalidate Queue2_BundleMap_87.io.deq.valid invalidate Queue2_BundleMap_87.io.deq.bits.extra_id invalidate Queue2_BundleMap_87.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_87.io.deq.bits.tl_state.size node _T_443 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_444 = and(_T_443, arsel_87) connect Queue2_BundleMap_87.io.enq.valid, _T_444 invalidate Queue2_BundleMap_87.io.enq.ready connect Queue2_BundleMap_87.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_87.io.count node _T_445 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_446 = and(_T_445, rsel_88) node _T_447 = and(_T_446, nodeOut.r.bits.last) connect Queue2_BundleMap_88.io.deq.ready, _T_447 invalidate Queue2_BundleMap_88.io.deq.valid invalidate Queue2_BundleMap_88.io.deq.bits.extra_id invalidate Queue2_BundleMap_88.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_88.io.deq.bits.tl_state.size node _T_448 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_449 = and(_T_448, arsel_88) connect Queue2_BundleMap_88.io.enq.valid, _T_449 invalidate Queue2_BundleMap_88.io.enq.ready connect Queue2_BundleMap_88.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_88.io.count node _T_450 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_451 = and(_T_450, rsel_89) node _T_452 = and(_T_451, nodeOut.r.bits.last) connect Queue2_BundleMap_89.io.deq.ready, _T_452 invalidate Queue2_BundleMap_89.io.deq.valid invalidate Queue2_BundleMap_89.io.deq.bits.extra_id invalidate Queue2_BundleMap_89.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_89.io.deq.bits.tl_state.size node _T_453 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_454 = and(_T_453, arsel_89) connect Queue2_BundleMap_89.io.enq.valid, _T_454 invalidate Queue2_BundleMap_89.io.enq.ready connect Queue2_BundleMap_89.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_89.io.count node _T_455 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_456 = and(_T_455, rsel_90) node _T_457 = and(_T_456, nodeOut.r.bits.last) connect Queue2_BundleMap_90.io.deq.ready, _T_457 invalidate Queue2_BundleMap_90.io.deq.valid invalidate Queue2_BundleMap_90.io.deq.bits.extra_id invalidate Queue2_BundleMap_90.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_90.io.deq.bits.tl_state.size node _T_458 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_459 = and(_T_458, arsel_90) connect Queue2_BundleMap_90.io.enq.valid, _T_459 invalidate Queue2_BundleMap_90.io.enq.ready connect Queue2_BundleMap_90.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_90.io.count node _T_460 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_461 = and(_T_460, rsel_91) node _T_462 = and(_T_461, nodeOut.r.bits.last) connect Queue2_BundleMap_91.io.deq.ready, _T_462 invalidate Queue2_BundleMap_91.io.deq.valid invalidate Queue2_BundleMap_91.io.deq.bits.extra_id invalidate Queue2_BundleMap_91.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_91.io.deq.bits.tl_state.size node _T_463 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_464 = and(_T_463, arsel_91) connect Queue2_BundleMap_91.io.enq.valid, _T_464 invalidate Queue2_BundleMap_91.io.enq.ready connect Queue2_BundleMap_91.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_91.io.count node _T_465 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_466 = and(_T_465, rsel_92) node _T_467 = and(_T_466, nodeOut.r.bits.last) connect Queue2_BundleMap_92.io.deq.ready, _T_467 invalidate Queue2_BundleMap_92.io.deq.valid invalidate Queue2_BundleMap_92.io.deq.bits.extra_id invalidate Queue2_BundleMap_92.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_92.io.deq.bits.tl_state.size node _T_468 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_469 = and(_T_468, arsel_92) connect Queue2_BundleMap_92.io.enq.valid, _T_469 invalidate Queue2_BundleMap_92.io.enq.ready connect Queue2_BundleMap_92.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_92.io.count node _T_470 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_471 = and(_T_470, rsel_93) node _T_472 = and(_T_471, nodeOut.r.bits.last) connect Queue2_BundleMap_93.io.deq.ready, _T_472 invalidate Queue2_BundleMap_93.io.deq.valid invalidate Queue2_BundleMap_93.io.deq.bits.extra_id invalidate Queue2_BundleMap_93.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_93.io.deq.bits.tl_state.size node _T_473 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_474 = and(_T_473, arsel_93) connect Queue2_BundleMap_93.io.enq.valid, _T_474 invalidate Queue2_BundleMap_93.io.enq.ready connect Queue2_BundleMap_93.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_93.io.count node _T_475 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_476 = and(_T_475, rsel_94) node _T_477 = and(_T_476, nodeOut.r.bits.last) connect Queue2_BundleMap_94.io.deq.ready, _T_477 invalidate Queue2_BundleMap_94.io.deq.valid invalidate Queue2_BundleMap_94.io.deq.bits.extra_id invalidate Queue2_BundleMap_94.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_94.io.deq.bits.tl_state.size node _T_478 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_479 = and(_T_478, arsel_94) connect Queue2_BundleMap_94.io.enq.valid, _T_479 invalidate Queue2_BundleMap_94.io.enq.ready connect Queue2_BundleMap_94.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_94.io.count node _T_480 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_481 = and(_T_480, rsel_95) node _T_482 = and(_T_481, nodeOut.r.bits.last) connect Queue2_BundleMap_95.io.deq.ready, _T_482 invalidate Queue2_BundleMap_95.io.deq.valid invalidate Queue2_BundleMap_95.io.deq.bits.extra_id invalidate Queue2_BundleMap_95.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_95.io.deq.bits.tl_state.size node _T_483 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_484 = and(_T_483, arsel_95) connect Queue2_BundleMap_95.io.enq.valid, _T_484 invalidate Queue2_BundleMap_95.io.enq.ready connect Queue2_BundleMap_95.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_95.io.count node _T_485 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_486 = and(_T_485, rsel_96) node _T_487 = and(_T_486, nodeOut.r.bits.last) connect Queue2_BundleMap_96.io.deq.ready, _T_487 invalidate Queue2_BundleMap_96.io.deq.valid invalidate Queue2_BundleMap_96.io.deq.bits.extra_id invalidate Queue2_BundleMap_96.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_96.io.deq.bits.tl_state.size node _T_488 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_489 = and(_T_488, arsel_96) connect Queue2_BundleMap_96.io.enq.valid, _T_489 invalidate Queue2_BundleMap_96.io.enq.ready connect Queue2_BundleMap_96.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_96.io.count node _T_490 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_491 = and(_T_490, rsel_97) node _T_492 = and(_T_491, nodeOut.r.bits.last) connect Queue2_BundleMap_97.io.deq.ready, _T_492 invalidate Queue2_BundleMap_97.io.deq.valid invalidate Queue2_BundleMap_97.io.deq.bits.extra_id invalidate Queue2_BundleMap_97.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_97.io.deq.bits.tl_state.size node _T_493 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_494 = and(_T_493, arsel_97) connect Queue2_BundleMap_97.io.enq.valid, _T_494 invalidate Queue2_BundleMap_97.io.enq.ready connect Queue2_BundleMap_97.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_97.io.count node _T_495 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_496 = and(_T_495, rsel_98) node _T_497 = and(_T_496, nodeOut.r.bits.last) connect Queue2_BundleMap_98.io.deq.ready, _T_497 invalidate Queue2_BundleMap_98.io.deq.valid invalidate Queue2_BundleMap_98.io.deq.bits.extra_id invalidate Queue2_BundleMap_98.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_98.io.deq.bits.tl_state.size node _T_498 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_499 = and(_T_498, arsel_98) connect Queue2_BundleMap_98.io.enq.valid, _T_499 invalidate Queue2_BundleMap_98.io.enq.ready connect Queue2_BundleMap_98.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_98.io.count node _T_500 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_501 = and(_T_500, rsel_99) node _T_502 = and(_T_501, nodeOut.r.bits.last) connect Queue2_BundleMap_99.io.deq.ready, _T_502 invalidate Queue2_BundleMap_99.io.deq.valid invalidate Queue2_BundleMap_99.io.deq.bits.extra_id invalidate Queue2_BundleMap_99.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_99.io.deq.bits.tl_state.size node _T_503 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_504 = and(_T_503, arsel_99) connect Queue2_BundleMap_99.io.enq.valid, _T_504 invalidate Queue2_BundleMap_99.io.enq.ready connect Queue2_BundleMap_99.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_99.io.count node _T_505 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_506 = and(_T_505, rsel_100) node _T_507 = and(_T_506, nodeOut.r.bits.last) connect Queue2_BundleMap_100.io.deq.ready, _T_507 invalidate Queue2_BundleMap_100.io.deq.valid invalidate Queue2_BundleMap_100.io.deq.bits.extra_id invalidate Queue2_BundleMap_100.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_100.io.deq.bits.tl_state.size node _T_508 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_509 = and(_T_508, arsel_100) connect Queue2_BundleMap_100.io.enq.valid, _T_509 invalidate Queue2_BundleMap_100.io.enq.ready connect Queue2_BundleMap_100.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_100.io.count node _T_510 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_511 = and(_T_510, rsel_101) node _T_512 = and(_T_511, nodeOut.r.bits.last) connect Queue2_BundleMap_101.io.deq.ready, _T_512 invalidate Queue2_BundleMap_101.io.deq.valid invalidate Queue2_BundleMap_101.io.deq.bits.extra_id invalidate Queue2_BundleMap_101.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_101.io.deq.bits.tl_state.size node _T_513 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_514 = and(_T_513, arsel_101) connect Queue2_BundleMap_101.io.enq.valid, _T_514 invalidate Queue2_BundleMap_101.io.enq.ready connect Queue2_BundleMap_101.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_101.io.count node _T_515 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_516 = and(_T_515, rsel_102) node _T_517 = and(_T_516, nodeOut.r.bits.last) connect Queue2_BundleMap_102.io.deq.ready, _T_517 invalidate Queue2_BundleMap_102.io.deq.valid invalidate Queue2_BundleMap_102.io.deq.bits.extra_id invalidate Queue2_BundleMap_102.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_102.io.deq.bits.tl_state.size node _T_518 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_519 = and(_T_518, arsel_102) connect Queue2_BundleMap_102.io.enq.valid, _T_519 invalidate Queue2_BundleMap_102.io.enq.ready connect Queue2_BundleMap_102.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_102.io.count node _T_520 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_521 = and(_T_520, rsel_103) node _T_522 = and(_T_521, nodeOut.r.bits.last) connect Queue2_BundleMap_103.io.deq.ready, _T_522 invalidate Queue2_BundleMap_103.io.deq.valid invalidate Queue2_BundleMap_103.io.deq.bits.extra_id invalidate Queue2_BundleMap_103.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_103.io.deq.bits.tl_state.size node _T_523 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_524 = and(_T_523, arsel_103) connect Queue2_BundleMap_103.io.enq.valid, _T_524 invalidate Queue2_BundleMap_103.io.enq.ready connect Queue2_BundleMap_103.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_103.io.count node _T_525 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_526 = and(_T_525, rsel_104) node _T_527 = and(_T_526, nodeOut.r.bits.last) connect Queue2_BundleMap_104.io.deq.ready, _T_527 invalidate Queue2_BundleMap_104.io.deq.valid invalidate Queue2_BundleMap_104.io.deq.bits.extra_id invalidate Queue2_BundleMap_104.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_104.io.deq.bits.tl_state.size node _T_528 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_529 = and(_T_528, arsel_104) connect Queue2_BundleMap_104.io.enq.valid, _T_529 invalidate Queue2_BundleMap_104.io.enq.ready connect Queue2_BundleMap_104.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_104.io.count node _T_530 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_531 = and(_T_530, rsel_105) node _T_532 = and(_T_531, nodeOut.r.bits.last) connect Queue2_BundleMap_105.io.deq.ready, _T_532 invalidate Queue2_BundleMap_105.io.deq.valid invalidate Queue2_BundleMap_105.io.deq.bits.extra_id invalidate Queue2_BundleMap_105.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_105.io.deq.bits.tl_state.size node _T_533 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_534 = and(_T_533, arsel_105) connect Queue2_BundleMap_105.io.enq.valid, _T_534 invalidate Queue2_BundleMap_105.io.enq.ready connect Queue2_BundleMap_105.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_105.io.count node _T_535 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_536 = and(_T_535, rsel_106) node _T_537 = and(_T_536, nodeOut.r.bits.last) connect Queue2_BundleMap_106.io.deq.ready, _T_537 invalidate Queue2_BundleMap_106.io.deq.valid invalidate Queue2_BundleMap_106.io.deq.bits.extra_id invalidate Queue2_BundleMap_106.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_106.io.deq.bits.tl_state.size node _T_538 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_539 = and(_T_538, arsel_106) connect Queue2_BundleMap_106.io.enq.valid, _T_539 invalidate Queue2_BundleMap_106.io.enq.ready connect Queue2_BundleMap_106.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_106.io.count node _T_540 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_541 = and(_T_540, rsel_107) node _T_542 = and(_T_541, nodeOut.r.bits.last) connect Queue2_BundleMap_107.io.deq.ready, _T_542 invalidate Queue2_BundleMap_107.io.deq.valid invalidate Queue2_BundleMap_107.io.deq.bits.extra_id invalidate Queue2_BundleMap_107.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_107.io.deq.bits.tl_state.size node _T_543 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_544 = and(_T_543, arsel_107) connect Queue2_BundleMap_107.io.enq.valid, _T_544 invalidate Queue2_BundleMap_107.io.enq.ready connect Queue2_BundleMap_107.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_107.io.count node _T_545 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_546 = and(_T_545, rsel_108) node _T_547 = and(_T_546, nodeOut.r.bits.last) connect Queue2_BundleMap_108.io.deq.ready, _T_547 invalidate Queue2_BundleMap_108.io.deq.valid invalidate Queue2_BundleMap_108.io.deq.bits.extra_id invalidate Queue2_BundleMap_108.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_108.io.deq.bits.tl_state.size node _T_548 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_549 = and(_T_548, arsel_108) connect Queue2_BundleMap_108.io.enq.valid, _T_549 invalidate Queue2_BundleMap_108.io.enq.ready connect Queue2_BundleMap_108.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_108.io.count node _T_550 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_551 = and(_T_550, rsel_109) node _T_552 = and(_T_551, nodeOut.r.bits.last) connect Queue2_BundleMap_109.io.deq.ready, _T_552 invalidate Queue2_BundleMap_109.io.deq.valid invalidate Queue2_BundleMap_109.io.deq.bits.extra_id invalidate Queue2_BundleMap_109.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_109.io.deq.bits.tl_state.size node _T_553 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_554 = and(_T_553, arsel_109) connect Queue2_BundleMap_109.io.enq.valid, _T_554 invalidate Queue2_BundleMap_109.io.enq.ready connect Queue2_BundleMap_109.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_109.io.count node _T_555 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_556 = and(_T_555, rsel_110) node _T_557 = and(_T_556, nodeOut.r.bits.last) connect Queue2_BundleMap_110.io.deq.ready, _T_557 invalidate Queue2_BundleMap_110.io.deq.valid invalidate Queue2_BundleMap_110.io.deq.bits.extra_id invalidate Queue2_BundleMap_110.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_110.io.deq.bits.tl_state.size node _T_558 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_559 = and(_T_558, arsel_110) connect Queue2_BundleMap_110.io.enq.valid, _T_559 invalidate Queue2_BundleMap_110.io.enq.ready connect Queue2_BundleMap_110.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_110.io.count node _T_560 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_561 = and(_T_560, rsel_111) node _T_562 = and(_T_561, nodeOut.r.bits.last) connect Queue2_BundleMap_111.io.deq.ready, _T_562 invalidate Queue2_BundleMap_111.io.deq.valid invalidate Queue2_BundleMap_111.io.deq.bits.extra_id invalidate Queue2_BundleMap_111.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_111.io.deq.bits.tl_state.size node _T_563 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_564 = and(_T_563, arsel_111) connect Queue2_BundleMap_111.io.enq.valid, _T_564 invalidate Queue2_BundleMap_111.io.enq.ready connect Queue2_BundleMap_111.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_111.io.count node _T_565 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_566 = and(_T_565, rsel_112) node _T_567 = and(_T_566, nodeOut.r.bits.last) connect Queue2_BundleMap_112.io.deq.ready, _T_567 invalidate Queue2_BundleMap_112.io.deq.valid invalidate Queue2_BundleMap_112.io.deq.bits.extra_id invalidate Queue2_BundleMap_112.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_112.io.deq.bits.tl_state.size node _T_568 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_569 = and(_T_568, arsel_112) connect Queue2_BundleMap_112.io.enq.valid, _T_569 invalidate Queue2_BundleMap_112.io.enq.ready connect Queue2_BundleMap_112.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_112.io.count node _T_570 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_571 = and(_T_570, rsel_113) node _T_572 = and(_T_571, nodeOut.r.bits.last) connect Queue2_BundleMap_113.io.deq.ready, _T_572 invalidate Queue2_BundleMap_113.io.deq.valid invalidate Queue2_BundleMap_113.io.deq.bits.extra_id invalidate Queue2_BundleMap_113.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_113.io.deq.bits.tl_state.size node _T_573 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_574 = and(_T_573, arsel_113) connect Queue2_BundleMap_113.io.enq.valid, _T_574 invalidate Queue2_BundleMap_113.io.enq.ready connect Queue2_BundleMap_113.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_113.io.count node _T_575 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_576 = and(_T_575, rsel_114) node _T_577 = and(_T_576, nodeOut.r.bits.last) connect Queue2_BundleMap_114.io.deq.ready, _T_577 invalidate Queue2_BundleMap_114.io.deq.valid invalidate Queue2_BundleMap_114.io.deq.bits.extra_id invalidate Queue2_BundleMap_114.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_114.io.deq.bits.tl_state.size node _T_578 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_579 = and(_T_578, arsel_114) connect Queue2_BundleMap_114.io.enq.valid, _T_579 invalidate Queue2_BundleMap_114.io.enq.ready connect Queue2_BundleMap_114.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_114.io.count node _T_580 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_581 = and(_T_580, rsel_115) node _T_582 = and(_T_581, nodeOut.r.bits.last) connect Queue2_BundleMap_115.io.deq.ready, _T_582 invalidate Queue2_BundleMap_115.io.deq.valid invalidate Queue2_BundleMap_115.io.deq.bits.extra_id invalidate Queue2_BundleMap_115.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_115.io.deq.bits.tl_state.size node _T_583 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_584 = and(_T_583, arsel_115) connect Queue2_BundleMap_115.io.enq.valid, _T_584 invalidate Queue2_BundleMap_115.io.enq.ready connect Queue2_BundleMap_115.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue2_BundleMap_115.io.count node _T_585 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_586 = and(_T_585, rsel_116) node _T_587 = and(_T_586, nodeOut.r.bits.last) connect Queue1_BundleMap.io.deq.ready, _T_587 invalidate Queue1_BundleMap.io.deq.valid invalidate Queue1_BundleMap.io.deq.bits.extra_id invalidate Queue1_BundleMap.io.deq.bits.tl_state.source invalidate Queue1_BundleMap.io.deq.bits.tl_state.size node _T_588 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_589 = and(_T_588, arsel_116) connect Queue1_BundleMap.io.enq.valid, _T_589 invalidate Queue1_BundleMap.io.enq.ready connect Queue1_BundleMap.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap.io.count node _T_590 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_591 = and(_T_590, rsel_117) node _T_592 = and(_T_591, nodeOut.r.bits.last) connect Queue1_BundleMap_1.io.deq.ready, _T_592 invalidate Queue1_BundleMap_1.io.deq.valid invalidate Queue1_BundleMap_1.io.deq.bits.extra_id invalidate Queue1_BundleMap_1.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_1.io.deq.bits.tl_state.size node _T_593 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_594 = and(_T_593, arsel_117) connect Queue1_BundleMap_1.io.enq.valid, _T_594 invalidate Queue1_BundleMap_1.io.enq.ready connect Queue1_BundleMap_1.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_1.io.count node _T_595 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_596 = and(_T_595, rsel_118) node _T_597 = and(_T_596, nodeOut.r.bits.last) connect Queue1_BundleMap_2.io.deq.ready, _T_597 invalidate Queue1_BundleMap_2.io.deq.valid invalidate Queue1_BundleMap_2.io.deq.bits.extra_id invalidate Queue1_BundleMap_2.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_2.io.deq.bits.tl_state.size node _T_598 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_599 = and(_T_598, arsel_118) connect Queue1_BundleMap_2.io.enq.valid, _T_599 invalidate Queue1_BundleMap_2.io.enq.ready connect Queue1_BundleMap_2.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_2.io.count node _T_600 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_601 = and(_T_600, rsel_119) node _T_602 = and(_T_601, nodeOut.r.bits.last) connect Queue1_BundleMap_3.io.deq.ready, _T_602 invalidate Queue1_BundleMap_3.io.deq.valid invalidate Queue1_BundleMap_3.io.deq.bits.extra_id invalidate Queue1_BundleMap_3.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_3.io.deq.bits.tl_state.size node _T_603 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_604 = and(_T_603, arsel_119) connect Queue1_BundleMap_3.io.enq.valid, _T_604 invalidate Queue1_BundleMap_3.io.enq.ready connect Queue1_BundleMap_3.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_3.io.count node _T_605 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_606 = and(_T_605, rsel_120) node _T_607 = and(_T_606, nodeOut.r.bits.last) connect Queue1_BundleMap_4.io.deq.ready, _T_607 invalidate Queue1_BundleMap_4.io.deq.valid invalidate Queue1_BundleMap_4.io.deq.bits.extra_id invalidate Queue1_BundleMap_4.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_4.io.deq.bits.tl_state.size node _T_608 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_609 = and(_T_608, arsel_120) connect Queue1_BundleMap_4.io.enq.valid, _T_609 invalidate Queue1_BundleMap_4.io.enq.ready connect Queue1_BundleMap_4.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_4.io.count node _T_610 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_611 = and(_T_610, rsel_121) node _T_612 = and(_T_611, nodeOut.r.bits.last) connect Queue1_BundleMap_5.io.deq.ready, _T_612 invalidate Queue1_BundleMap_5.io.deq.valid invalidate Queue1_BundleMap_5.io.deq.bits.extra_id invalidate Queue1_BundleMap_5.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_5.io.deq.bits.tl_state.size node _T_613 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_614 = and(_T_613, arsel_121) connect Queue1_BundleMap_5.io.enq.valid, _T_614 invalidate Queue1_BundleMap_5.io.enq.ready connect Queue1_BundleMap_5.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_5.io.count node _T_615 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_616 = and(_T_615, rsel_122) node _T_617 = and(_T_616, nodeOut.r.bits.last) connect Queue1_BundleMap_6.io.deq.ready, _T_617 invalidate Queue1_BundleMap_6.io.deq.valid invalidate Queue1_BundleMap_6.io.deq.bits.extra_id invalidate Queue1_BundleMap_6.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_6.io.deq.bits.tl_state.size node _T_618 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_619 = and(_T_618, arsel_122) connect Queue1_BundleMap_6.io.enq.valid, _T_619 invalidate Queue1_BundleMap_6.io.enq.ready connect Queue1_BundleMap_6.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_6.io.count node _T_620 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_621 = and(_T_620, rsel_123) node _T_622 = and(_T_621, nodeOut.r.bits.last) connect Queue1_BundleMap_7.io.deq.ready, _T_622 invalidate Queue1_BundleMap_7.io.deq.valid invalidate Queue1_BundleMap_7.io.deq.bits.extra_id invalidate Queue1_BundleMap_7.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_7.io.deq.bits.tl_state.size node _T_623 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_624 = and(_T_623, arsel_123) connect Queue1_BundleMap_7.io.enq.valid, _T_624 invalidate Queue1_BundleMap_7.io.enq.ready connect Queue1_BundleMap_7.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_7.io.count node _T_625 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_626 = and(_T_625, rsel_124) node _T_627 = and(_T_626, nodeOut.r.bits.last) connect Queue1_BundleMap_8.io.deq.ready, _T_627 invalidate Queue1_BundleMap_8.io.deq.valid invalidate Queue1_BundleMap_8.io.deq.bits.extra_id invalidate Queue1_BundleMap_8.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_8.io.deq.bits.tl_state.size node _T_628 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_629 = and(_T_628, arsel_124) connect Queue1_BundleMap_8.io.enq.valid, _T_629 invalidate Queue1_BundleMap_8.io.enq.ready connect Queue1_BundleMap_8.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_8.io.count node _T_630 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_631 = and(_T_630, rsel_125) node _T_632 = and(_T_631, nodeOut.r.bits.last) connect Queue1_BundleMap_9.io.deq.ready, _T_632 invalidate Queue1_BundleMap_9.io.deq.valid invalidate Queue1_BundleMap_9.io.deq.bits.extra_id invalidate Queue1_BundleMap_9.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_9.io.deq.bits.tl_state.size node _T_633 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_634 = and(_T_633, arsel_125) connect Queue1_BundleMap_9.io.enq.valid, _T_634 invalidate Queue1_BundleMap_9.io.enq.ready connect Queue1_BundleMap_9.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_9.io.count node _T_635 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_636 = and(_T_635, rsel_126) node _T_637 = and(_T_636, nodeOut.r.bits.last) connect Queue1_BundleMap_10.io.deq.ready, _T_637 invalidate Queue1_BundleMap_10.io.deq.valid invalidate Queue1_BundleMap_10.io.deq.bits.extra_id invalidate Queue1_BundleMap_10.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_10.io.deq.bits.tl_state.size node _T_638 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_639 = and(_T_638, arsel_126) connect Queue1_BundleMap_10.io.enq.valid, _T_639 invalidate Queue1_BundleMap_10.io.enq.ready connect Queue1_BundleMap_10.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_10.io.count node _T_640 = and(nodeOut.r.valid, nodeIn.r.ready) node _T_641 = and(_T_640, rsel_127) node _T_642 = and(_T_641, nodeOut.r.bits.last) connect Queue1_BundleMap_11.io.deq.ready, _T_642 invalidate Queue1_BundleMap_11.io.deq.valid invalidate Queue1_BundleMap_11.io.deq.bits.extra_id invalidate Queue1_BundleMap_11.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_11.io.deq.bits.tl_state.size node _T_643 = and(nodeIn.ar.valid, nodeOut.ar.ready) node _T_644 = and(_T_643, arsel_127) connect Queue1_BundleMap_11.io.enq.valid, _T_644 invalidate Queue1_BundleMap_11.io.enq.ready connect Queue1_BundleMap_11.io.enq.bits, nodeIn.ar.bits.echo invalidate Queue1_BundleMap_11.io.count wire _aw_ready_WIRE : UInt<1>[128] connect _aw_ready_WIRE[0], Queue2_BundleMap_116.io.enq.ready connect _aw_ready_WIRE[1], Queue2_BundleMap_117.io.enq.ready connect _aw_ready_WIRE[2], Queue2_BundleMap_118.io.enq.ready connect _aw_ready_WIRE[3], Queue2_BundleMap_119.io.enq.ready connect _aw_ready_WIRE[4], Queue2_BundleMap_120.io.enq.ready connect _aw_ready_WIRE[5], Queue2_BundleMap_121.io.enq.ready connect _aw_ready_WIRE[6], Queue2_BundleMap_122.io.enq.ready connect _aw_ready_WIRE[7], Queue2_BundleMap_123.io.enq.ready connect _aw_ready_WIRE[8], Queue2_BundleMap_124.io.enq.ready connect _aw_ready_WIRE[9], Queue2_BundleMap_125.io.enq.ready connect _aw_ready_WIRE[10], Queue2_BundleMap_126.io.enq.ready connect _aw_ready_WIRE[11], Queue2_BundleMap_127.io.enq.ready connect _aw_ready_WIRE[12], Queue2_BundleMap_128.io.enq.ready connect _aw_ready_WIRE[13], Queue2_BundleMap_129.io.enq.ready connect _aw_ready_WIRE[14], Queue2_BundleMap_130.io.enq.ready connect _aw_ready_WIRE[15], Queue2_BundleMap_131.io.enq.ready connect _aw_ready_WIRE[16], Queue2_BundleMap_132.io.enq.ready connect _aw_ready_WIRE[17], Queue2_BundleMap_133.io.enq.ready connect _aw_ready_WIRE[18], Queue2_BundleMap_134.io.enq.ready connect _aw_ready_WIRE[19], Queue2_BundleMap_135.io.enq.ready connect _aw_ready_WIRE[20], Queue2_BundleMap_136.io.enq.ready connect _aw_ready_WIRE[21], Queue2_BundleMap_137.io.enq.ready connect _aw_ready_WIRE[22], Queue2_BundleMap_138.io.enq.ready connect _aw_ready_WIRE[23], Queue2_BundleMap_139.io.enq.ready connect _aw_ready_WIRE[24], Queue2_BundleMap_140.io.enq.ready connect _aw_ready_WIRE[25], Queue2_BundleMap_141.io.enq.ready connect _aw_ready_WIRE[26], Queue2_BundleMap_142.io.enq.ready connect _aw_ready_WIRE[27], Queue2_BundleMap_143.io.enq.ready connect _aw_ready_WIRE[28], Queue2_BundleMap_144.io.enq.ready connect _aw_ready_WIRE[29], Queue2_BundleMap_145.io.enq.ready connect _aw_ready_WIRE[30], Queue2_BundleMap_146.io.enq.ready connect _aw_ready_WIRE[31], Queue2_BundleMap_147.io.enq.ready connect _aw_ready_WIRE[32], Queue2_BundleMap_148.io.enq.ready connect _aw_ready_WIRE[33], Queue2_BundleMap_149.io.enq.ready connect _aw_ready_WIRE[34], Queue2_BundleMap_150.io.enq.ready connect _aw_ready_WIRE[35], Queue2_BundleMap_151.io.enq.ready connect _aw_ready_WIRE[36], Queue2_BundleMap_152.io.enq.ready connect _aw_ready_WIRE[37], Queue2_BundleMap_153.io.enq.ready connect _aw_ready_WIRE[38], Queue2_BundleMap_154.io.enq.ready connect _aw_ready_WIRE[39], Queue2_BundleMap_155.io.enq.ready connect _aw_ready_WIRE[40], Queue2_BundleMap_156.io.enq.ready connect _aw_ready_WIRE[41], Queue2_BundleMap_157.io.enq.ready connect _aw_ready_WIRE[42], Queue2_BundleMap_158.io.enq.ready connect _aw_ready_WIRE[43], Queue2_BundleMap_159.io.enq.ready connect _aw_ready_WIRE[44], Queue2_BundleMap_160.io.enq.ready connect _aw_ready_WIRE[45], Queue2_BundleMap_161.io.enq.ready connect _aw_ready_WIRE[46], Queue2_BundleMap_162.io.enq.ready connect _aw_ready_WIRE[47], Queue2_BundleMap_163.io.enq.ready connect _aw_ready_WIRE[48], Queue2_BundleMap_164.io.enq.ready connect _aw_ready_WIRE[49], Queue2_BundleMap_165.io.enq.ready connect _aw_ready_WIRE[50], Queue2_BundleMap_166.io.enq.ready connect _aw_ready_WIRE[51], Queue2_BundleMap_167.io.enq.ready connect _aw_ready_WIRE[52], Queue2_BundleMap_168.io.enq.ready connect _aw_ready_WIRE[53], Queue2_BundleMap_169.io.enq.ready connect _aw_ready_WIRE[54], Queue2_BundleMap_170.io.enq.ready connect _aw_ready_WIRE[55], Queue2_BundleMap_171.io.enq.ready connect _aw_ready_WIRE[56], Queue2_BundleMap_172.io.enq.ready connect _aw_ready_WIRE[57], Queue2_BundleMap_173.io.enq.ready connect _aw_ready_WIRE[58], Queue2_BundleMap_174.io.enq.ready connect _aw_ready_WIRE[59], Queue2_BundleMap_175.io.enq.ready connect _aw_ready_WIRE[60], Queue2_BundleMap_176.io.enq.ready connect _aw_ready_WIRE[61], Queue2_BundleMap_177.io.enq.ready connect _aw_ready_WIRE[62], Queue2_BundleMap_178.io.enq.ready connect _aw_ready_WIRE[63], Queue2_BundleMap_179.io.enq.ready connect _aw_ready_WIRE[64], Queue2_BundleMap_180.io.enq.ready connect _aw_ready_WIRE[65], Queue2_BundleMap_181.io.enq.ready connect _aw_ready_WIRE[66], Queue2_BundleMap_182.io.enq.ready connect _aw_ready_WIRE[67], Queue2_BundleMap_183.io.enq.ready connect _aw_ready_WIRE[68], Queue2_BundleMap_184.io.enq.ready connect _aw_ready_WIRE[69], Queue2_BundleMap_185.io.enq.ready connect _aw_ready_WIRE[70], Queue2_BundleMap_186.io.enq.ready connect _aw_ready_WIRE[71], Queue2_BundleMap_187.io.enq.ready connect _aw_ready_WIRE[72], Queue2_BundleMap_188.io.enq.ready connect _aw_ready_WIRE[73], Queue2_BundleMap_189.io.enq.ready connect _aw_ready_WIRE[74], Queue2_BundleMap_190.io.enq.ready connect _aw_ready_WIRE[75], Queue2_BundleMap_191.io.enq.ready connect _aw_ready_WIRE[76], Queue2_BundleMap_192.io.enq.ready connect _aw_ready_WIRE[77], Queue2_BundleMap_193.io.enq.ready connect _aw_ready_WIRE[78], Queue2_BundleMap_194.io.enq.ready connect _aw_ready_WIRE[79], Queue2_BundleMap_195.io.enq.ready connect _aw_ready_WIRE[80], Queue2_BundleMap_196.io.enq.ready connect _aw_ready_WIRE[81], Queue2_BundleMap_197.io.enq.ready connect _aw_ready_WIRE[82], Queue2_BundleMap_198.io.enq.ready connect _aw_ready_WIRE[83], Queue2_BundleMap_199.io.enq.ready connect _aw_ready_WIRE[84], Queue2_BundleMap_200.io.enq.ready connect _aw_ready_WIRE[85], Queue2_BundleMap_201.io.enq.ready connect _aw_ready_WIRE[86], Queue2_BundleMap_202.io.enq.ready connect _aw_ready_WIRE[87], Queue2_BundleMap_203.io.enq.ready connect _aw_ready_WIRE[88], Queue2_BundleMap_204.io.enq.ready connect _aw_ready_WIRE[89], Queue2_BundleMap_205.io.enq.ready connect _aw_ready_WIRE[90], Queue2_BundleMap_206.io.enq.ready connect _aw_ready_WIRE[91], Queue2_BundleMap_207.io.enq.ready connect _aw_ready_WIRE[92], Queue2_BundleMap_208.io.enq.ready connect _aw_ready_WIRE[93], Queue2_BundleMap_209.io.enq.ready connect _aw_ready_WIRE[94], Queue2_BundleMap_210.io.enq.ready connect _aw_ready_WIRE[95], Queue2_BundleMap_211.io.enq.ready connect _aw_ready_WIRE[96], Queue2_BundleMap_212.io.enq.ready connect _aw_ready_WIRE[97], Queue2_BundleMap_213.io.enq.ready connect _aw_ready_WIRE[98], Queue2_BundleMap_214.io.enq.ready connect _aw_ready_WIRE[99], Queue2_BundleMap_215.io.enq.ready connect _aw_ready_WIRE[100], Queue2_BundleMap_216.io.enq.ready connect _aw_ready_WIRE[101], Queue2_BundleMap_217.io.enq.ready connect _aw_ready_WIRE[102], Queue2_BundleMap_218.io.enq.ready connect _aw_ready_WIRE[103], Queue2_BundleMap_219.io.enq.ready connect _aw_ready_WIRE[104], Queue2_BundleMap_220.io.enq.ready connect _aw_ready_WIRE[105], Queue2_BundleMap_221.io.enq.ready connect _aw_ready_WIRE[106], Queue2_BundleMap_222.io.enq.ready connect _aw_ready_WIRE[107], Queue2_BundleMap_223.io.enq.ready connect _aw_ready_WIRE[108], Queue2_BundleMap_224.io.enq.ready connect _aw_ready_WIRE[109], Queue2_BundleMap_225.io.enq.ready connect _aw_ready_WIRE[110], Queue2_BundleMap_226.io.enq.ready connect _aw_ready_WIRE[111], Queue2_BundleMap_227.io.enq.ready connect _aw_ready_WIRE[112], Queue2_BundleMap_228.io.enq.ready connect _aw_ready_WIRE[113], Queue2_BundleMap_229.io.enq.ready connect _aw_ready_WIRE[114], Queue2_BundleMap_230.io.enq.ready connect _aw_ready_WIRE[115], Queue2_BundleMap_231.io.enq.ready connect _aw_ready_WIRE[116], Queue1_BundleMap_12.io.enq.ready connect _aw_ready_WIRE[117], Queue1_BundleMap_13.io.enq.ready connect _aw_ready_WIRE[118], Queue1_BundleMap_14.io.enq.ready connect _aw_ready_WIRE[119], Queue1_BundleMap_15.io.enq.ready connect _aw_ready_WIRE[120], Queue1_BundleMap_16.io.enq.ready connect _aw_ready_WIRE[121], Queue1_BundleMap_17.io.enq.ready connect _aw_ready_WIRE[122], Queue1_BundleMap_18.io.enq.ready connect _aw_ready_WIRE[123], Queue1_BundleMap_19.io.enq.ready connect _aw_ready_WIRE[124], Queue1_BundleMap_20.io.enq.ready connect _aw_ready_WIRE[125], Queue1_BundleMap_21.io.enq.ready connect _aw_ready_WIRE[126], Queue1_BundleMap_22.io.enq.ready connect _aw_ready_WIRE[127], Queue1_BundleMap_23.io.enq.ready node _nodeIn_aw_ready_T = and(nodeOut.aw.ready, _aw_ready_WIRE[nodeIn.aw.bits.id]) connect nodeIn.aw.ready, _nodeIn_aw_ready_T node _nodeOut_aw_valid_T = and(nodeIn.aw.valid, _aw_ready_WIRE[nodeIn.aw.bits.id]) connect nodeOut.aw.valid, _nodeOut_aw_valid_T connect nodeOut.aw.bits.qos, nodeIn.aw.bits.qos connect nodeOut.aw.bits.prot, nodeIn.aw.bits.prot connect nodeOut.aw.bits.cache, nodeIn.aw.bits.cache connect nodeOut.aw.bits.lock, nodeIn.aw.bits.lock connect nodeOut.aw.bits.burst, nodeIn.aw.bits.burst connect nodeOut.aw.bits.size, nodeIn.aw.bits.size connect nodeOut.aw.bits.len, nodeIn.aw.bits.len connect nodeOut.aw.bits.addr, nodeIn.aw.bits.addr connect nodeOut.aw.bits.id, nodeIn.aw.bits.id wire _b_valid_WIRE : UInt<1>[128] connect _b_valid_WIRE[0], Queue2_BundleMap_116.io.deq.valid connect _b_valid_WIRE[1], Queue2_BundleMap_117.io.deq.valid connect _b_valid_WIRE[2], Queue2_BundleMap_118.io.deq.valid connect _b_valid_WIRE[3], Queue2_BundleMap_119.io.deq.valid connect _b_valid_WIRE[4], Queue2_BundleMap_120.io.deq.valid connect _b_valid_WIRE[5], Queue2_BundleMap_121.io.deq.valid connect _b_valid_WIRE[6], Queue2_BundleMap_122.io.deq.valid connect _b_valid_WIRE[7], Queue2_BundleMap_123.io.deq.valid connect _b_valid_WIRE[8], Queue2_BundleMap_124.io.deq.valid connect _b_valid_WIRE[9], Queue2_BundleMap_125.io.deq.valid connect _b_valid_WIRE[10], Queue2_BundleMap_126.io.deq.valid connect _b_valid_WIRE[11], Queue2_BundleMap_127.io.deq.valid connect _b_valid_WIRE[12], Queue2_BundleMap_128.io.deq.valid connect _b_valid_WIRE[13], Queue2_BundleMap_129.io.deq.valid connect _b_valid_WIRE[14], Queue2_BundleMap_130.io.deq.valid connect _b_valid_WIRE[15], Queue2_BundleMap_131.io.deq.valid connect _b_valid_WIRE[16], Queue2_BundleMap_132.io.deq.valid connect _b_valid_WIRE[17], Queue2_BundleMap_133.io.deq.valid connect _b_valid_WIRE[18], Queue2_BundleMap_134.io.deq.valid connect _b_valid_WIRE[19], Queue2_BundleMap_135.io.deq.valid connect _b_valid_WIRE[20], Queue2_BundleMap_136.io.deq.valid connect _b_valid_WIRE[21], Queue2_BundleMap_137.io.deq.valid connect _b_valid_WIRE[22], Queue2_BundleMap_138.io.deq.valid connect _b_valid_WIRE[23], Queue2_BundleMap_139.io.deq.valid connect _b_valid_WIRE[24], Queue2_BundleMap_140.io.deq.valid connect _b_valid_WIRE[25], Queue2_BundleMap_141.io.deq.valid connect _b_valid_WIRE[26], Queue2_BundleMap_142.io.deq.valid connect _b_valid_WIRE[27], Queue2_BundleMap_143.io.deq.valid connect _b_valid_WIRE[28], Queue2_BundleMap_144.io.deq.valid connect _b_valid_WIRE[29], Queue2_BundleMap_145.io.deq.valid connect _b_valid_WIRE[30], Queue2_BundleMap_146.io.deq.valid connect _b_valid_WIRE[31], Queue2_BundleMap_147.io.deq.valid connect _b_valid_WIRE[32], Queue2_BundleMap_148.io.deq.valid connect _b_valid_WIRE[33], Queue2_BundleMap_149.io.deq.valid connect _b_valid_WIRE[34], Queue2_BundleMap_150.io.deq.valid connect _b_valid_WIRE[35], Queue2_BundleMap_151.io.deq.valid connect _b_valid_WIRE[36], Queue2_BundleMap_152.io.deq.valid connect _b_valid_WIRE[37], Queue2_BundleMap_153.io.deq.valid connect _b_valid_WIRE[38], Queue2_BundleMap_154.io.deq.valid connect _b_valid_WIRE[39], Queue2_BundleMap_155.io.deq.valid connect _b_valid_WIRE[40], Queue2_BundleMap_156.io.deq.valid connect _b_valid_WIRE[41], Queue2_BundleMap_157.io.deq.valid connect _b_valid_WIRE[42], Queue2_BundleMap_158.io.deq.valid connect _b_valid_WIRE[43], Queue2_BundleMap_159.io.deq.valid connect _b_valid_WIRE[44], Queue2_BundleMap_160.io.deq.valid connect _b_valid_WIRE[45], Queue2_BundleMap_161.io.deq.valid connect _b_valid_WIRE[46], Queue2_BundleMap_162.io.deq.valid connect _b_valid_WIRE[47], Queue2_BundleMap_163.io.deq.valid connect _b_valid_WIRE[48], Queue2_BundleMap_164.io.deq.valid connect _b_valid_WIRE[49], Queue2_BundleMap_165.io.deq.valid connect _b_valid_WIRE[50], Queue2_BundleMap_166.io.deq.valid connect _b_valid_WIRE[51], Queue2_BundleMap_167.io.deq.valid connect _b_valid_WIRE[52], Queue2_BundleMap_168.io.deq.valid connect _b_valid_WIRE[53], Queue2_BundleMap_169.io.deq.valid connect _b_valid_WIRE[54], Queue2_BundleMap_170.io.deq.valid connect _b_valid_WIRE[55], Queue2_BundleMap_171.io.deq.valid connect _b_valid_WIRE[56], Queue2_BundleMap_172.io.deq.valid connect _b_valid_WIRE[57], Queue2_BundleMap_173.io.deq.valid connect _b_valid_WIRE[58], Queue2_BundleMap_174.io.deq.valid connect _b_valid_WIRE[59], Queue2_BundleMap_175.io.deq.valid connect _b_valid_WIRE[60], Queue2_BundleMap_176.io.deq.valid connect _b_valid_WIRE[61], Queue2_BundleMap_177.io.deq.valid connect _b_valid_WIRE[62], Queue2_BundleMap_178.io.deq.valid connect _b_valid_WIRE[63], Queue2_BundleMap_179.io.deq.valid connect _b_valid_WIRE[64], Queue2_BundleMap_180.io.deq.valid connect _b_valid_WIRE[65], Queue2_BundleMap_181.io.deq.valid connect _b_valid_WIRE[66], Queue2_BundleMap_182.io.deq.valid connect _b_valid_WIRE[67], Queue2_BundleMap_183.io.deq.valid connect _b_valid_WIRE[68], Queue2_BundleMap_184.io.deq.valid connect _b_valid_WIRE[69], Queue2_BundleMap_185.io.deq.valid connect _b_valid_WIRE[70], Queue2_BundleMap_186.io.deq.valid connect _b_valid_WIRE[71], Queue2_BundleMap_187.io.deq.valid connect _b_valid_WIRE[72], Queue2_BundleMap_188.io.deq.valid connect _b_valid_WIRE[73], Queue2_BundleMap_189.io.deq.valid connect _b_valid_WIRE[74], Queue2_BundleMap_190.io.deq.valid connect _b_valid_WIRE[75], Queue2_BundleMap_191.io.deq.valid connect _b_valid_WIRE[76], Queue2_BundleMap_192.io.deq.valid connect _b_valid_WIRE[77], Queue2_BundleMap_193.io.deq.valid connect _b_valid_WIRE[78], Queue2_BundleMap_194.io.deq.valid connect _b_valid_WIRE[79], Queue2_BundleMap_195.io.deq.valid connect _b_valid_WIRE[80], Queue2_BundleMap_196.io.deq.valid connect _b_valid_WIRE[81], Queue2_BundleMap_197.io.deq.valid connect _b_valid_WIRE[82], Queue2_BundleMap_198.io.deq.valid connect _b_valid_WIRE[83], Queue2_BundleMap_199.io.deq.valid connect _b_valid_WIRE[84], Queue2_BundleMap_200.io.deq.valid connect _b_valid_WIRE[85], Queue2_BundleMap_201.io.deq.valid connect _b_valid_WIRE[86], Queue2_BundleMap_202.io.deq.valid connect _b_valid_WIRE[87], Queue2_BundleMap_203.io.deq.valid connect _b_valid_WIRE[88], Queue2_BundleMap_204.io.deq.valid connect _b_valid_WIRE[89], Queue2_BundleMap_205.io.deq.valid connect _b_valid_WIRE[90], Queue2_BundleMap_206.io.deq.valid connect _b_valid_WIRE[91], Queue2_BundleMap_207.io.deq.valid connect _b_valid_WIRE[92], Queue2_BundleMap_208.io.deq.valid connect _b_valid_WIRE[93], Queue2_BundleMap_209.io.deq.valid connect _b_valid_WIRE[94], Queue2_BundleMap_210.io.deq.valid connect _b_valid_WIRE[95], Queue2_BundleMap_211.io.deq.valid connect _b_valid_WIRE[96], Queue2_BundleMap_212.io.deq.valid connect _b_valid_WIRE[97], Queue2_BundleMap_213.io.deq.valid connect _b_valid_WIRE[98], Queue2_BundleMap_214.io.deq.valid connect _b_valid_WIRE[99], Queue2_BundleMap_215.io.deq.valid connect _b_valid_WIRE[100], Queue2_BundleMap_216.io.deq.valid connect _b_valid_WIRE[101], Queue2_BundleMap_217.io.deq.valid connect _b_valid_WIRE[102], Queue2_BundleMap_218.io.deq.valid connect _b_valid_WIRE[103], Queue2_BundleMap_219.io.deq.valid connect _b_valid_WIRE[104], Queue2_BundleMap_220.io.deq.valid connect _b_valid_WIRE[105], Queue2_BundleMap_221.io.deq.valid connect _b_valid_WIRE[106], Queue2_BundleMap_222.io.deq.valid connect _b_valid_WIRE[107], Queue2_BundleMap_223.io.deq.valid connect _b_valid_WIRE[108], Queue2_BundleMap_224.io.deq.valid connect _b_valid_WIRE[109], Queue2_BundleMap_225.io.deq.valid connect _b_valid_WIRE[110], Queue2_BundleMap_226.io.deq.valid connect _b_valid_WIRE[111], Queue2_BundleMap_227.io.deq.valid connect _b_valid_WIRE[112], Queue2_BundleMap_228.io.deq.valid connect _b_valid_WIRE[113], Queue2_BundleMap_229.io.deq.valid connect _b_valid_WIRE[114], Queue2_BundleMap_230.io.deq.valid connect _b_valid_WIRE[115], Queue2_BundleMap_231.io.deq.valid connect _b_valid_WIRE[116], Queue1_BundleMap_12.io.deq.valid connect _b_valid_WIRE[117], Queue1_BundleMap_13.io.deq.valid connect _b_valid_WIRE[118], Queue1_BundleMap_14.io.deq.valid connect _b_valid_WIRE[119], Queue1_BundleMap_15.io.deq.valid connect _b_valid_WIRE[120], Queue1_BundleMap_16.io.deq.valid connect _b_valid_WIRE[121], Queue1_BundleMap_17.io.deq.valid connect _b_valid_WIRE[122], Queue1_BundleMap_18.io.deq.valid connect _b_valid_WIRE[123], Queue1_BundleMap_19.io.deq.valid connect _b_valid_WIRE[124], Queue1_BundleMap_20.io.deq.valid connect _b_valid_WIRE[125], Queue1_BundleMap_21.io.deq.valid connect _b_valid_WIRE[126], Queue1_BundleMap_22.io.deq.valid connect _b_valid_WIRE[127], Queue1_BundleMap_23.io.deq.valid wire _b_bits_WIRE : { tl_state : { size : UInt<4>, source : UInt<8>}, extra_id : UInt<1>}[128] connect _b_bits_WIRE[0], Queue2_BundleMap_116.io.deq.bits connect _b_bits_WIRE[1], Queue2_BundleMap_117.io.deq.bits connect _b_bits_WIRE[2], Queue2_BundleMap_118.io.deq.bits connect _b_bits_WIRE[3], Queue2_BundleMap_119.io.deq.bits connect _b_bits_WIRE[4], Queue2_BundleMap_120.io.deq.bits connect _b_bits_WIRE[5], Queue2_BundleMap_121.io.deq.bits connect _b_bits_WIRE[6], Queue2_BundleMap_122.io.deq.bits connect _b_bits_WIRE[7], Queue2_BundleMap_123.io.deq.bits connect _b_bits_WIRE[8], Queue2_BundleMap_124.io.deq.bits connect _b_bits_WIRE[9], Queue2_BundleMap_125.io.deq.bits connect _b_bits_WIRE[10], Queue2_BundleMap_126.io.deq.bits connect _b_bits_WIRE[11], Queue2_BundleMap_127.io.deq.bits connect _b_bits_WIRE[12], Queue2_BundleMap_128.io.deq.bits connect _b_bits_WIRE[13], Queue2_BundleMap_129.io.deq.bits connect _b_bits_WIRE[14], Queue2_BundleMap_130.io.deq.bits connect _b_bits_WIRE[15], Queue2_BundleMap_131.io.deq.bits connect _b_bits_WIRE[16], Queue2_BundleMap_132.io.deq.bits connect _b_bits_WIRE[17], Queue2_BundleMap_133.io.deq.bits connect _b_bits_WIRE[18], Queue2_BundleMap_134.io.deq.bits connect _b_bits_WIRE[19], Queue2_BundleMap_135.io.deq.bits connect _b_bits_WIRE[20], Queue2_BundleMap_136.io.deq.bits connect _b_bits_WIRE[21], Queue2_BundleMap_137.io.deq.bits connect _b_bits_WIRE[22], Queue2_BundleMap_138.io.deq.bits connect _b_bits_WIRE[23], Queue2_BundleMap_139.io.deq.bits connect _b_bits_WIRE[24], Queue2_BundleMap_140.io.deq.bits connect _b_bits_WIRE[25], Queue2_BundleMap_141.io.deq.bits connect _b_bits_WIRE[26], Queue2_BundleMap_142.io.deq.bits connect _b_bits_WIRE[27], Queue2_BundleMap_143.io.deq.bits connect _b_bits_WIRE[28], Queue2_BundleMap_144.io.deq.bits connect _b_bits_WIRE[29], Queue2_BundleMap_145.io.deq.bits connect _b_bits_WIRE[30], Queue2_BundleMap_146.io.deq.bits connect _b_bits_WIRE[31], Queue2_BundleMap_147.io.deq.bits connect _b_bits_WIRE[32], Queue2_BundleMap_148.io.deq.bits connect _b_bits_WIRE[33], Queue2_BundleMap_149.io.deq.bits connect _b_bits_WIRE[34], Queue2_BundleMap_150.io.deq.bits connect _b_bits_WIRE[35], Queue2_BundleMap_151.io.deq.bits connect _b_bits_WIRE[36], Queue2_BundleMap_152.io.deq.bits connect _b_bits_WIRE[37], Queue2_BundleMap_153.io.deq.bits connect _b_bits_WIRE[38], Queue2_BundleMap_154.io.deq.bits connect _b_bits_WIRE[39], Queue2_BundleMap_155.io.deq.bits connect _b_bits_WIRE[40], Queue2_BundleMap_156.io.deq.bits connect _b_bits_WIRE[41], Queue2_BundleMap_157.io.deq.bits connect _b_bits_WIRE[42], Queue2_BundleMap_158.io.deq.bits connect _b_bits_WIRE[43], Queue2_BundleMap_159.io.deq.bits connect _b_bits_WIRE[44], Queue2_BundleMap_160.io.deq.bits connect _b_bits_WIRE[45], Queue2_BundleMap_161.io.deq.bits connect _b_bits_WIRE[46], Queue2_BundleMap_162.io.deq.bits connect _b_bits_WIRE[47], Queue2_BundleMap_163.io.deq.bits connect _b_bits_WIRE[48], Queue2_BundleMap_164.io.deq.bits connect _b_bits_WIRE[49], Queue2_BundleMap_165.io.deq.bits connect _b_bits_WIRE[50], Queue2_BundleMap_166.io.deq.bits connect _b_bits_WIRE[51], Queue2_BundleMap_167.io.deq.bits connect _b_bits_WIRE[52], Queue2_BundleMap_168.io.deq.bits connect _b_bits_WIRE[53], Queue2_BundleMap_169.io.deq.bits connect _b_bits_WIRE[54], Queue2_BundleMap_170.io.deq.bits connect _b_bits_WIRE[55], Queue2_BundleMap_171.io.deq.bits connect _b_bits_WIRE[56], Queue2_BundleMap_172.io.deq.bits connect _b_bits_WIRE[57], Queue2_BundleMap_173.io.deq.bits connect _b_bits_WIRE[58], Queue2_BundleMap_174.io.deq.bits connect _b_bits_WIRE[59], Queue2_BundleMap_175.io.deq.bits connect _b_bits_WIRE[60], Queue2_BundleMap_176.io.deq.bits connect _b_bits_WIRE[61], Queue2_BundleMap_177.io.deq.bits connect _b_bits_WIRE[62], Queue2_BundleMap_178.io.deq.bits connect _b_bits_WIRE[63], Queue2_BundleMap_179.io.deq.bits connect _b_bits_WIRE[64], Queue2_BundleMap_180.io.deq.bits connect _b_bits_WIRE[65], Queue2_BundleMap_181.io.deq.bits connect _b_bits_WIRE[66], Queue2_BundleMap_182.io.deq.bits connect _b_bits_WIRE[67], Queue2_BundleMap_183.io.deq.bits connect _b_bits_WIRE[68], Queue2_BundleMap_184.io.deq.bits connect _b_bits_WIRE[69], Queue2_BundleMap_185.io.deq.bits connect _b_bits_WIRE[70], Queue2_BundleMap_186.io.deq.bits connect _b_bits_WIRE[71], Queue2_BundleMap_187.io.deq.bits connect _b_bits_WIRE[72], Queue2_BundleMap_188.io.deq.bits connect _b_bits_WIRE[73], Queue2_BundleMap_189.io.deq.bits connect _b_bits_WIRE[74], Queue2_BundleMap_190.io.deq.bits connect _b_bits_WIRE[75], Queue2_BundleMap_191.io.deq.bits connect _b_bits_WIRE[76], Queue2_BundleMap_192.io.deq.bits connect _b_bits_WIRE[77], Queue2_BundleMap_193.io.deq.bits connect _b_bits_WIRE[78], Queue2_BundleMap_194.io.deq.bits connect _b_bits_WIRE[79], Queue2_BundleMap_195.io.deq.bits connect _b_bits_WIRE[80], Queue2_BundleMap_196.io.deq.bits connect _b_bits_WIRE[81], Queue2_BundleMap_197.io.deq.bits connect _b_bits_WIRE[82], Queue2_BundleMap_198.io.deq.bits connect _b_bits_WIRE[83], Queue2_BundleMap_199.io.deq.bits connect _b_bits_WIRE[84], Queue2_BundleMap_200.io.deq.bits connect _b_bits_WIRE[85], Queue2_BundleMap_201.io.deq.bits connect _b_bits_WIRE[86], Queue2_BundleMap_202.io.deq.bits connect _b_bits_WIRE[87], Queue2_BundleMap_203.io.deq.bits connect _b_bits_WIRE[88], Queue2_BundleMap_204.io.deq.bits connect _b_bits_WIRE[89], Queue2_BundleMap_205.io.deq.bits connect _b_bits_WIRE[90], Queue2_BundleMap_206.io.deq.bits connect _b_bits_WIRE[91], Queue2_BundleMap_207.io.deq.bits connect _b_bits_WIRE[92], Queue2_BundleMap_208.io.deq.bits connect _b_bits_WIRE[93], Queue2_BundleMap_209.io.deq.bits connect _b_bits_WIRE[94], Queue2_BundleMap_210.io.deq.bits connect _b_bits_WIRE[95], Queue2_BundleMap_211.io.deq.bits connect _b_bits_WIRE[96], Queue2_BundleMap_212.io.deq.bits connect _b_bits_WIRE[97], Queue2_BundleMap_213.io.deq.bits connect _b_bits_WIRE[98], Queue2_BundleMap_214.io.deq.bits connect _b_bits_WIRE[99], Queue2_BundleMap_215.io.deq.bits connect _b_bits_WIRE[100], Queue2_BundleMap_216.io.deq.bits connect _b_bits_WIRE[101], Queue2_BundleMap_217.io.deq.bits connect _b_bits_WIRE[102], Queue2_BundleMap_218.io.deq.bits connect _b_bits_WIRE[103], Queue2_BundleMap_219.io.deq.bits connect _b_bits_WIRE[104], Queue2_BundleMap_220.io.deq.bits connect _b_bits_WIRE[105], Queue2_BundleMap_221.io.deq.bits connect _b_bits_WIRE[106], Queue2_BundleMap_222.io.deq.bits connect _b_bits_WIRE[107], Queue2_BundleMap_223.io.deq.bits connect _b_bits_WIRE[108], Queue2_BundleMap_224.io.deq.bits connect _b_bits_WIRE[109], Queue2_BundleMap_225.io.deq.bits connect _b_bits_WIRE[110], Queue2_BundleMap_226.io.deq.bits connect _b_bits_WIRE[111], Queue2_BundleMap_227.io.deq.bits connect _b_bits_WIRE[112], Queue2_BundleMap_228.io.deq.bits connect _b_bits_WIRE[113], Queue2_BundleMap_229.io.deq.bits connect _b_bits_WIRE[114], Queue2_BundleMap_230.io.deq.bits connect _b_bits_WIRE[115], Queue2_BundleMap_231.io.deq.bits connect _b_bits_WIRE[116], Queue1_BundleMap_12.io.deq.bits connect _b_bits_WIRE[117], Queue1_BundleMap_13.io.deq.bits connect _b_bits_WIRE[118], Queue1_BundleMap_14.io.deq.bits connect _b_bits_WIRE[119], Queue1_BundleMap_15.io.deq.bits connect _b_bits_WIRE[120], Queue1_BundleMap_16.io.deq.bits connect _b_bits_WIRE[121], Queue1_BundleMap_17.io.deq.bits connect _b_bits_WIRE[122], Queue1_BundleMap_18.io.deq.bits connect _b_bits_WIRE[123], Queue1_BundleMap_19.io.deq.bits connect _b_bits_WIRE[124], Queue1_BundleMap_20.io.deq.bits connect _b_bits_WIRE[125], Queue1_BundleMap_21.io.deq.bits connect _b_bits_WIRE[126], Queue1_BundleMap_22.io.deq.bits connect _b_bits_WIRE[127], Queue1_BundleMap_23.io.deq.bits node _T_645 = eq(nodeOut.b.valid, UInt<1>(0h0)) node _T_646 = or(_T_645, _b_valid_WIRE[nodeOut.b.bits.id]) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed\n at UserYanker.scala:98 assert (!out.b.valid \|\| b_valid) // Q must be ready faster than the response\n") : printf_1 assert(clock, _T_646, UInt<1>(0h1), "") : assert_1 connect nodeIn.b.bits.resp, nodeOut.b.bits.resp connect nodeIn.b.bits.id, nodeOut.b.bits.id connect nodeIn.b.valid, nodeOut.b.valid connect nodeOut.b.ready, nodeIn.b.ready connect nodeIn.b.bits.echo, _b_bits_WIRE[nodeOut.b.bits.id] node awsel_shiftAmount = bits(nodeIn.aw.bits.id, 6, 0) node _awsel_T = dshl(UInt<1>(0h1), awsel_shiftAmount) node _awsel_T_1 = bits(_awsel_T, 127, 0) node awsel_0 = bits(_awsel_T_1, 0, 0) node awsel_1 = bits(_awsel_T_1, 1, 1) node awsel_2 = bits(_awsel_T_1, 2, 2) node awsel_3 = bits(_awsel_T_1, 3, 3) node awsel_4 = bits(_awsel_T_1, 4, 4) node awsel_5 = bits(_awsel_T_1, 5, 5) node awsel_6 = bits(_awsel_T_1, 6, 6) node awsel_7 = bits(_awsel_T_1, 7, 7) node awsel_8 = bits(_awsel_T_1, 8, 8) node awsel_9 = bits(_awsel_T_1, 9, 9) node awsel_10 = bits(_awsel_T_1, 10, 10) node awsel_11 = bits(_awsel_T_1, 11, 11) node awsel_12 = bits(_awsel_T_1, 12, 12) node awsel_13 = bits(_awsel_T_1, 13, 13) node awsel_14 = bits(_awsel_T_1, 14, 14) node awsel_15 = bits(_awsel_T_1, 15, 15) node awsel_16 = bits(_awsel_T_1, 16, 16) node awsel_17 = bits(_awsel_T_1, 17, 17) node awsel_18 = bits(_awsel_T_1, 18, 18) node awsel_19 = bits(_awsel_T_1, 19, 19) node awsel_20 = bits(_awsel_T_1, 20, 20) node awsel_21 = bits(_awsel_T_1, 21, 21) node awsel_22 = bits(_awsel_T_1, 22, 22) node awsel_23 = bits(_awsel_T_1, 23, 23) node awsel_24 = bits(_awsel_T_1, 24, 24) node awsel_25 = bits(_awsel_T_1, 25, 25) node awsel_26 = bits(_awsel_T_1, 26, 26) node awsel_27 = bits(_awsel_T_1, 27, 27) node awsel_28 = bits(_awsel_T_1, 28, 28) node awsel_29 = bits(_awsel_T_1, 29, 29) node awsel_30 = bits(_awsel_T_1, 30, 30) node awsel_31 = bits(_awsel_T_1, 31, 31) node awsel_32 = bits(_awsel_T_1, 32, 32) node awsel_33 = bits(_awsel_T_1, 33, 33) node awsel_34 = bits(_awsel_T_1, 34, 34) node awsel_35 = bits(_awsel_T_1, 35, 35) node awsel_36 = bits(_awsel_T_1, 36, 36) node awsel_37 = bits(_awsel_T_1, 37, 37) node awsel_38 = bits(_awsel_T_1, 38, 38) node awsel_39 = bits(_awsel_T_1, 39, 39) node awsel_40 = bits(_awsel_T_1, 40, 40) node awsel_41 = bits(_awsel_T_1, 41, 41) node awsel_42 = bits(_awsel_T_1, 42, 42) node awsel_43 = bits(_awsel_T_1, 43, 43) node awsel_44 = bits(_awsel_T_1, 44, 44) node awsel_45 = bits(_awsel_T_1, 45, 45) node awsel_46 = bits(_awsel_T_1, 46, 46) node awsel_47 = bits(_awsel_T_1, 47, 47) node awsel_48 = bits(_awsel_T_1, 48, 48) node awsel_49 = bits(_awsel_T_1, 49, 49) node awsel_50 = bits(_awsel_T_1, 50, 50) node awsel_51 = bits(_awsel_T_1, 51, 51) node awsel_52 = bits(_awsel_T_1, 52, 52) node awsel_53 = bits(_awsel_T_1, 53, 53) node awsel_54 = bits(_awsel_T_1, 54, 54) node awsel_55 = bits(_awsel_T_1, 55, 55) node awsel_56 = bits(_awsel_T_1, 56, 56) node awsel_57 = bits(_awsel_T_1, 57, 57) node awsel_58 = bits(_awsel_T_1, 58, 58) node awsel_59 = bits(_awsel_T_1, 59, 59) node awsel_60 = bits(_awsel_T_1, 60, 60) node awsel_61 = bits(_awsel_T_1, 61, 61) node awsel_62 = bits(_awsel_T_1, 62, 62) node awsel_63 = bits(_awsel_T_1, 63, 63) node awsel_64 = bits(_awsel_T_1, 64, 64) node awsel_65 = bits(_awsel_T_1, 65, 65) node awsel_66 = bits(_awsel_T_1, 66, 66) node awsel_67 = bits(_awsel_T_1, 67, 67) node awsel_68 = bits(_awsel_T_1, 68, 68) node awsel_69 = bits(_awsel_T_1, 69, 69) node awsel_70 = bits(_awsel_T_1, 70, 70) node awsel_71 = bits(_awsel_T_1, 71, 71) node awsel_72 = bits(_awsel_T_1, 72, 72) node awsel_73 = bits(_awsel_T_1, 73, 73) node awsel_74 = bits(_awsel_T_1, 74, 74) node awsel_75 = bits(_awsel_T_1, 75, 75) node awsel_76 = bits(_awsel_T_1, 76, 76) node awsel_77 = bits(_awsel_T_1, 77, 77) node awsel_78 = bits(_awsel_T_1, 78, 78) node awsel_79 = bits(_awsel_T_1, 79, 79) node awsel_80 = bits(_awsel_T_1, 80, 80) node awsel_81 = bits(_awsel_T_1, 81, 81) node awsel_82 = bits(_awsel_T_1, 82, 82) node awsel_83 = bits(_awsel_T_1, 83, 83) node awsel_84 = bits(_awsel_T_1, 84, 84) node awsel_85 = bits(_awsel_T_1, 85, 85) node awsel_86 = bits(_awsel_T_1, 86, 86) node awsel_87 = bits(_awsel_T_1, 87, 87) node awsel_88 = bits(_awsel_T_1, 88, 88) node awsel_89 = bits(_awsel_T_1, 89, 89) node awsel_90 = bits(_awsel_T_1, 90, 90) node awsel_91 = bits(_awsel_T_1, 91, 91) node awsel_92 = bits(_awsel_T_1, 92, 92) node awsel_93 = bits(_awsel_T_1, 93, 93) node awsel_94 = bits(_awsel_T_1, 94, 94) node awsel_95 = bits(_awsel_T_1, 95, 95) node awsel_96 = bits(_awsel_T_1, 96, 96) node awsel_97 = bits(_awsel_T_1, 97, 97) node awsel_98 = bits(_awsel_T_1, 98, 98) node awsel_99 = bits(_awsel_T_1, 99, 99) node awsel_100 = bits(_awsel_T_1, 100, 100) node awsel_101 = bits(_awsel_T_1, 101, 101) node awsel_102 = bits(_awsel_T_1, 102, 102) node awsel_103 = bits(_awsel_T_1, 103, 103) node awsel_104 = bits(_awsel_T_1, 104, 104) node awsel_105 = bits(_awsel_T_1, 105, 105) node awsel_106 = bits(_awsel_T_1, 106, 106) node awsel_107 = bits(_awsel_T_1, 107, 107) node awsel_108 = bits(_awsel_T_1, 108, 108) node awsel_109 = bits(_awsel_T_1, 109, 109) node awsel_110 = bits(_awsel_T_1, 110, 110) node awsel_111 = bits(_awsel_T_1, 111, 111) node awsel_112 = bits(_awsel_T_1, 112, 112) node awsel_113 = bits(_awsel_T_1, 113, 113) node awsel_114 = bits(_awsel_T_1, 114, 114) node awsel_115 = bits(_awsel_T_1, 115, 115) node awsel_116 = bits(_awsel_T_1, 116, 116) node awsel_117 = bits(_awsel_T_1, 117, 117) node awsel_118 = bits(_awsel_T_1, 118, 118) node awsel_119 = bits(_awsel_T_1, 119, 119) node awsel_120 = bits(_awsel_T_1, 120, 120) node awsel_121 = bits(_awsel_T_1, 121, 121) node awsel_122 = bits(_awsel_T_1, 122, 122) node awsel_123 = bits(_awsel_T_1, 123, 123) node awsel_124 = bits(_awsel_T_1, 124, 124) node awsel_125 = bits(_awsel_T_1, 125, 125) node awsel_126 = bits(_awsel_T_1, 126, 126) node awsel_127 = bits(_awsel_T_1, 127, 127) node bsel_shiftAmount = bits(nodeOut.b.bits.id, 6, 0) node _bsel_T = dshl(UInt<1>(0h1), bsel_shiftAmount) node _bsel_T_1 = bits(_bsel_T, 127, 0) node bsel_0 = bits(_bsel_T_1, 0, 0) node bsel_1 = bits(_bsel_T_1, 1, 1) node bsel_2 = bits(_bsel_T_1, 2, 2) node bsel_3 = bits(_bsel_T_1, 3, 3) node bsel_4 = bits(_bsel_T_1, 4, 4) node bsel_5 = bits(_bsel_T_1, 5, 5) node bsel_6 = bits(_bsel_T_1, 6, 6) node bsel_7 = bits(_bsel_T_1, 7, 7) node bsel_8 = bits(_bsel_T_1, 8, 8) node bsel_9 = bits(_bsel_T_1, 9, 9) node bsel_10 = bits(_bsel_T_1, 10, 10) node bsel_11 = bits(_bsel_T_1, 11, 11) node bsel_12 = bits(_bsel_T_1, 12, 12) node bsel_13 = bits(_bsel_T_1, 13, 13) node bsel_14 = bits(_bsel_T_1, 14, 14) node bsel_15 = bits(_bsel_T_1, 15, 15) node bsel_16 = bits(_bsel_T_1, 16, 16) node bsel_17 = bits(_bsel_T_1, 17, 17) node bsel_18 = bits(_bsel_T_1, 18, 18) node bsel_19 = bits(_bsel_T_1, 19, 19) node bsel_20 = bits(_bsel_T_1, 20, 20) node bsel_21 = bits(_bsel_T_1, 21, 21) node bsel_22 = bits(_bsel_T_1, 22, 22) node bsel_23 = bits(_bsel_T_1, 23, 23) node bsel_24 = bits(_bsel_T_1, 24, 24) node bsel_25 = bits(_bsel_T_1, 25, 25) node bsel_26 = bits(_bsel_T_1, 26, 26) node bsel_27 = bits(_bsel_T_1, 27, 27) node bsel_28 = bits(_bsel_T_1, 28, 28) node bsel_29 = bits(_bsel_T_1, 29, 29) node bsel_30 = bits(_bsel_T_1, 30, 30) node bsel_31 = bits(_bsel_T_1, 31, 31) node bsel_32 = bits(_bsel_T_1, 32, 32) node bsel_33 = bits(_bsel_T_1, 33, 33) node bsel_34 = bits(_bsel_T_1, 34, 34) node bsel_35 = bits(_bsel_T_1, 35, 35) node bsel_36 = bits(_bsel_T_1, 36, 36) node bsel_37 = bits(_bsel_T_1, 37, 37) node bsel_38 = bits(_bsel_T_1, 38, 38) node bsel_39 = bits(_bsel_T_1, 39, 39) node bsel_40 = bits(_bsel_T_1, 40, 40) node bsel_41 = bits(_bsel_T_1, 41, 41) node bsel_42 = bits(_bsel_T_1, 42, 42) node bsel_43 = bits(_bsel_T_1, 43, 43) node bsel_44 = bits(_bsel_T_1, 44, 44) node bsel_45 = bits(_bsel_T_1, 45, 45) node bsel_46 = bits(_bsel_T_1, 46, 46) node bsel_47 = bits(_bsel_T_1, 47, 47) node bsel_48 = bits(_bsel_T_1, 48, 48) node bsel_49 = bits(_bsel_T_1, 49, 49) node bsel_50 = bits(_bsel_T_1, 50, 50) node bsel_51 = bits(_bsel_T_1, 51, 51) node bsel_52 = bits(_bsel_T_1, 52, 52) node bsel_53 = bits(_bsel_T_1, 53, 53) node bsel_54 = bits(_bsel_T_1, 54, 54) node bsel_55 = bits(_bsel_T_1, 55, 55) node bsel_56 = bits(_bsel_T_1, 56, 56) node bsel_57 = bits(_bsel_T_1, 57, 57) node bsel_58 = bits(_bsel_T_1, 58, 58) node bsel_59 = bits(_bsel_T_1, 59, 59) node bsel_60 = bits(_bsel_T_1, 60, 60) node bsel_61 = bits(_bsel_T_1, 61, 61) node bsel_62 = bits(_bsel_T_1, 62, 62) node bsel_63 = bits(_bsel_T_1, 63, 63) node bsel_64 = bits(_bsel_T_1, 64, 64) node bsel_65 = bits(_bsel_T_1, 65, 65) node bsel_66 = bits(_bsel_T_1, 66, 66) node bsel_67 = bits(_bsel_T_1, 67, 67) node bsel_68 = bits(_bsel_T_1, 68, 68) node bsel_69 = bits(_bsel_T_1, 69, 69) node bsel_70 = bits(_bsel_T_1, 70, 70) node bsel_71 = bits(_bsel_T_1, 71, 71) node bsel_72 = bits(_bsel_T_1, 72, 72) node bsel_73 = bits(_bsel_T_1, 73, 73) node bsel_74 = bits(_bsel_T_1, 74, 74) node bsel_75 = bits(_bsel_T_1, 75, 75) node bsel_76 = bits(_bsel_T_1, 76, 76) node bsel_77 = bits(_bsel_T_1, 77, 77) node bsel_78 = bits(_bsel_T_1, 78, 78) node bsel_79 = bits(_bsel_T_1, 79, 79) node bsel_80 = bits(_bsel_T_1, 80, 80) node bsel_81 = bits(_bsel_T_1, 81, 81) node bsel_82 = bits(_bsel_T_1, 82, 82) node bsel_83 = bits(_bsel_T_1, 83, 83) node bsel_84 = bits(_bsel_T_1, 84, 84) node bsel_85 = bits(_bsel_T_1, 85, 85) node bsel_86 = bits(_bsel_T_1, 86, 86) node bsel_87 = bits(_bsel_T_1, 87, 87) node bsel_88 = bits(_bsel_T_1, 88, 88) node bsel_89 = bits(_bsel_T_1, 89, 89) node bsel_90 = bits(_bsel_T_1, 90, 90) node bsel_91 = bits(_bsel_T_1, 91, 91) node bsel_92 = bits(_bsel_T_1, 92, 92) node bsel_93 = bits(_bsel_T_1, 93, 93) node bsel_94 = bits(_bsel_T_1, 94, 94) node bsel_95 = bits(_bsel_T_1, 95, 95) node bsel_96 = bits(_bsel_T_1, 96, 96) node bsel_97 = bits(_bsel_T_1, 97, 97) node bsel_98 = bits(_bsel_T_1, 98, 98) node bsel_99 = bits(_bsel_T_1, 99, 99) node bsel_100 = bits(_bsel_T_1, 100, 100) node bsel_101 = bits(_bsel_T_1, 101, 101) node bsel_102 = bits(_bsel_T_1, 102, 102) node bsel_103 = bits(_bsel_T_1, 103, 103) node bsel_104 = bits(_bsel_T_1, 104, 104) node bsel_105 = bits(_bsel_T_1, 105, 105) node bsel_106 = bits(_bsel_T_1, 106, 106) node bsel_107 = bits(_bsel_T_1, 107, 107) node bsel_108 = bits(_bsel_T_1, 108, 108) node bsel_109 = bits(_bsel_T_1, 109, 109) node bsel_110 = bits(_bsel_T_1, 110, 110) node bsel_111 = bits(_bsel_T_1, 111, 111) node bsel_112 = bits(_bsel_T_1, 112, 112) node bsel_113 = bits(_bsel_T_1, 113, 113) node bsel_114 = bits(_bsel_T_1, 114, 114) node bsel_115 = bits(_bsel_T_1, 115, 115) node bsel_116 = bits(_bsel_T_1, 116, 116) node bsel_117 = bits(_bsel_T_1, 117, 117) node bsel_118 = bits(_bsel_T_1, 118, 118) node bsel_119 = bits(_bsel_T_1, 119, 119) node bsel_120 = bits(_bsel_T_1, 120, 120) node bsel_121 = bits(_bsel_T_1, 121, 121) node bsel_122 = bits(_bsel_T_1, 122, 122) node bsel_123 = bits(_bsel_T_1, 123, 123) node bsel_124 = bits(_bsel_T_1, 124, 124) node bsel_125 = bits(_bsel_T_1, 125, 125) node bsel_126 = bits(_bsel_T_1, 126, 126) node bsel_127 = bits(_bsel_T_1, 127, 127) node _T_650 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_651 = and(_T_650, bsel_0) connect Queue2_BundleMap_116.io.deq.ready, _T_651 invalidate Queue2_BundleMap_116.io.deq.valid invalidate Queue2_BundleMap_116.io.deq.bits.extra_id invalidate Queue2_BundleMap_116.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_116.io.deq.bits.tl_state.size node _T_652 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_653 = and(_T_652, awsel_0) connect Queue2_BundleMap_116.io.enq.valid, _T_653 invalidate Queue2_BundleMap_116.io.enq.ready connect Queue2_BundleMap_116.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_116.io.count node _T_654 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_655 = and(_T_654, bsel_1) connect Queue2_BundleMap_117.io.deq.ready, _T_655 invalidate Queue2_BundleMap_117.io.deq.valid invalidate Queue2_BundleMap_117.io.deq.bits.extra_id invalidate Queue2_BundleMap_117.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_117.io.deq.bits.tl_state.size node _T_656 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_657 = and(_T_656, awsel_1) connect Queue2_BundleMap_117.io.enq.valid, _T_657 invalidate Queue2_BundleMap_117.io.enq.ready connect Queue2_BundleMap_117.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_117.io.count node _T_658 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_659 = and(_T_658, bsel_2) connect Queue2_BundleMap_118.io.deq.ready, _T_659 invalidate Queue2_BundleMap_118.io.deq.valid invalidate Queue2_BundleMap_118.io.deq.bits.extra_id invalidate Queue2_BundleMap_118.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_118.io.deq.bits.tl_state.size node _T_660 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_661 = and(_T_660, awsel_2) connect Queue2_BundleMap_118.io.enq.valid, _T_661 invalidate Queue2_BundleMap_118.io.enq.ready connect Queue2_BundleMap_118.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_118.io.count node _T_662 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_663 = and(_T_662, bsel_3) connect Queue2_BundleMap_119.io.deq.ready, _T_663 invalidate Queue2_BundleMap_119.io.deq.valid invalidate Queue2_BundleMap_119.io.deq.bits.extra_id invalidate Queue2_BundleMap_119.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_119.io.deq.bits.tl_state.size node _T_664 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_665 = and(_T_664, awsel_3) connect Queue2_BundleMap_119.io.enq.valid, _T_665 invalidate Queue2_BundleMap_119.io.enq.ready connect Queue2_BundleMap_119.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_119.io.count node _T_666 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_667 = and(_T_666, bsel_4) connect Queue2_BundleMap_120.io.deq.ready, _T_667 invalidate Queue2_BundleMap_120.io.deq.valid invalidate Queue2_BundleMap_120.io.deq.bits.extra_id invalidate Queue2_BundleMap_120.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_120.io.deq.bits.tl_state.size node _T_668 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_669 = and(_T_668, awsel_4) connect Queue2_BundleMap_120.io.enq.valid, _T_669 invalidate Queue2_BundleMap_120.io.enq.ready connect Queue2_BundleMap_120.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_120.io.count node _T_670 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_671 = and(_T_670, bsel_5) connect Queue2_BundleMap_121.io.deq.ready, _T_671 invalidate Queue2_BundleMap_121.io.deq.valid invalidate Queue2_BundleMap_121.io.deq.bits.extra_id invalidate Queue2_BundleMap_121.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_121.io.deq.bits.tl_state.size node _T_672 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_673 = and(_T_672, awsel_5) connect Queue2_BundleMap_121.io.enq.valid, _T_673 invalidate Queue2_BundleMap_121.io.enq.ready connect Queue2_BundleMap_121.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_121.io.count node _T_674 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_675 = and(_T_674, bsel_6) connect Queue2_BundleMap_122.io.deq.ready, _T_675 invalidate Queue2_BundleMap_122.io.deq.valid invalidate Queue2_BundleMap_122.io.deq.bits.extra_id invalidate Queue2_BundleMap_122.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_122.io.deq.bits.tl_state.size node _T_676 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_677 = and(_T_676, awsel_6) connect Queue2_BundleMap_122.io.enq.valid, _T_677 invalidate Queue2_BundleMap_122.io.enq.ready connect Queue2_BundleMap_122.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_122.io.count node _T_678 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_679 = and(_T_678, bsel_7) connect Queue2_BundleMap_123.io.deq.ready, _T_679 invalidate Queue2_BundleMap_123.io.deq.valid invalidate Queue2_BundleMap_123.io.deq.bits.extra_id invalidate Queue2_BundleMap_123.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_123.io.deq.bits.tl_state.size node _T_680 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_681 = and(_T_680, awsel_7) connect Queue2_BundleMap_123.io.enq.valid, _T_681 invalidate Queue2_BundleMap_123.io.enq.ready connect Queue2_BundleMap_123.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_123.io.count node _T_682 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_683 = and(_T_682, bsel_8) connect Queue2_BundleMap_124.io.deq.ready, _T_683 invalidate Queue2_BundleMap_124.io.deq.valid invalidate Queue2_BundleMap_124.io.deq.bits.extra_id invalidate Queue2_BundleMap_124.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_124.io.deq.bits.tl_state.size node _T_684 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_685 = and(_T_684, awsel_8) connect Queue2_BundleMap_124.io.enq.valid, _T_685 invalidate Queue2_BundleMap_124.io.enq.ready connect Queue2_BundleMap_124.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_124.io.count node _T_686 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_687 = and(_T_686, bsel_9) connect Queue2_BundleMap_125.io.deq.ready, _T_687 invalidate Queue2_BundleMap_125.io.deq.valid invalidate Queue2_BundleMap_125.io.deq.bits.extra_id invalidate Queue2_BundleMap_125.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_125.io.deq.bits.tl_state.size node _T_688 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_689 = and(_T_688, awsel_9) connect Queue2_BundleMap_125.io.enq.valid, _T_689 invalidate Queue2_BundleMap_125.io.enq.ready connect Queue2_BundleMap_125.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_125.io.count node _T_690 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_691 = and(_T_690, bsel_10) connect Queue2_BundleMap_126.io.deq.ready, _T_691 invalidate Queue2_BundleMap_126.io.deq.valid invalidate Queue2_BundleMap_126.io.deq.bits.extra_id invalidate Queue2_BundleMap_126.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_126.io.deq.bits.tl_state.size node _T_692 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_693 = and(_T_692, awsel_10) connect Queue2_BundleMap_126.io.enq.valid, _T_693 invalidate Queue2_BundleMap_126.io.enq.ready connect Queue2_BundleMap_126.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_126.io.count node _T_694 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_695 = and(_T_694, bsel_11) connect Queue2_BundleMap_127.io.deq.ready, _T_695 invalidate Queue2_BundleMap_127.io.deq.valid invalidate Queue2_BundleMap_127.io.deq.bits.extra_id invalidate Queue2_BundleMap_127.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_127.io.deq.bits.tl_state.size node _T_696 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_697 = and(_T_696, awsel_11) connect Queue2_BundleMap_127.io.enq.valid, _T_697 invalidate Queue2_BundleMap_127.io.enq.ready connect Queue2_BundleMap_127.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_127.io.count node _T_698 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_699 = and(_T_698, bsel_12) connect Queue2_BundleMap_128.io.deq.ready, _T_699 invalidate Queue2_BundleMap_128.io.deq.valid invalidate Queue2_BundleMap_128.io.deq.bits.extra_id invalidate Queue2_BundleMap_128.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_128.io.deq.bits.tl_state.size node _T_700 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_701 = and(_T_700, awsel_12) connect Queue2_BundleMap_128.io.enq.valid, _T_701 invalidate Queue2_BundleMap_128.io.enq.ready connect Queue2_BundleMap_128.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_128.io.count node _T_702 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_703 = and(_T_702, bsel_13) connect Queue2_BundleMap_129.io.deq.ready, _T_703 invalidate Queue2_BundleMap_129.io.deq.valid invalidate Queue2_BundleMap_129.io.deq.bits.extra_id invalidate Queue2_BundleMap_129.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_129.io.deq.bits.tl_state.size node _T_704 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_705 = and(_T_704, awsel_13) connect Queue2_BundleMap_129.io.enq.valid, _T_705 invalidate Queue2_BundleMap_129.io.enq.ready connect Queue2_BundleMap_129.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_129.io.count node _T_706 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_707 = and(_T_706, bsel_14) connect Queue2_BundleMap_130.io.deq.ready, _T_707 invalidate Queue2_BundleMap_130.io.deq.valid invalidate Queue2_BundleMap_130.io.deq.bits.extra_id invalidate Queue2_BundleMap_130.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_130.io.deq.bits.tl_state.size node _T_708 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_709 = and(_T_708, awsel_14) connect Queue2_BundleMap_130.io.enq.valid, _T_709 invalidate Queue2_BundleMap_130.io.enq.ready connect Queue2_BundleMap_130.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_130.io.count node _T_710 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_711 = and(_T_710, bsel_15) connect Queue2_BundleMap_131.io.deq.ready, _T_711 invalidate Queue2_BundleMap_131.io.deq.valid invalidate Queue2_BundleMap_131.io.deq.bits.extra_id invalidate Queue2_BundleMap_131.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_131.io.deq.bits.tl_state.size node _T_712 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_713 = and(_T_712, awsel_15) connect Queue2_BundleMap_131.io.enq.valid, _T_713 invalidate Queue2_BundleMap_131.io.enq.ready connect Queue2_BundleMap_131.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_131.io.count node _T_714 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_715 = and(_T_714, bsel_16) connect Queue2_BundleMap_132.io.deq.ready, _T_715 invalidate Queue2_BundleMap_132.io.deq.valid invalidate Queue2_BundleMap_132.io.deq.bits.extra_id invalidate Queue2_BundleMap_132.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_132.io.deq.bits.tl_state.size node _T_716 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_717 = and(_T_716, awsel_16) connect Queue2_BundleMap_132.io.enq.valid, _T_717 invalidate Queue2_BundleMap_132.io.enq.ready connect Queue2_BundleMap_132.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_132.io.count node _T_718 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_719 = and(_T_718, bsel_17) connect Queue2_BundleMap_133.io.deq.ready, _T_719 invalidate Queue2_BundleMap_133.io.deq.valid invalidate Queue2_BundleMap_133.io.deq.bits.extra_id invalidate Queue2_BundleMap_133.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_133.io.deq.bits.tl_state.size node _T_720 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_721 = and(_T_720, awsel_17) connect Queue2_BundleMap_133.io.enq.valid, _T_721 invalidate Queue2_BundleMap_133.io.enq.ready connect Queue2_BundleMap_133.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_133.io.count node _T_722 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_723 = and(_T_722, bsel_18) connect Queue2_BundleMap_134.io.deq.ready, _T_723 invalidate Queue2_BundleMap_134.io.deq.valid invalidate Queue2_BundleMap_134.io.deq.bits.extra_id invalidate Queue2_BundleMap_134.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_134.io.deq.bits.tl_state.size node _T_724 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_725 = and(_T_724, awsel_18) connect Queue2_BundleMap_134.io.enq.valid, _T_725 invalidate Queue2_BundleMap_134.io.enq.ready connect Queue2_BundleMap_134.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_134.io.count node _T_726 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_727 = and(_T_726, bsel_19) connect Queue2_BundleMap_135.io.deq.ready, _T_727 invalidate Queue2_BundleMap_135.io.deq.valid invalidate Queue2_BundleMap_135.io.deq.bits.extra_id invalidate Queue2_BundleMap_135.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_135.io.deq.bits.tl_state.size node _T_728 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_729 = and(_T_728, awsel_19) connect Queue2_BundleMap_135.io.enq.valid, _T_729 invalidate Queue2_BundleMap_135.io.enq.ready connect Queue2_BundleMap_135.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_135.io.count node _T_730 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_731 = and(_T_730, bsel_20) connect Queue2_BundleMap_136.io.deq.ready, _T_731 invalidate Queue2_BundleMap_136.io.deq.valid invalidate Queue2_BundleMap_136.io.deq.bits.extra_id invalidate Queue2_BundleMap_136.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_136.io.deq.bits.tl_state.size node _T_732 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_733 = and(_T_732, awsel_20) connect Queue2_BundleMap_136.io.enq.valid, _T_733 invalidate Queue2_BundleMap_136.io.enq.ready connect Queue2_BundleMap_136.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_136.io.count node _T_734 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_735 = and(_T_734, bsel_21) connect Queue2_BundleMap_137.io.deq.ready, _T_735 invalidate Queue2_BundleMap_137.io.deq.valid invalidate Queue2_BundleMap_137.io.deq.bits.extra_id invalidate Queue2_BundleMap_137.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_137.io.deq.bits.tl_state.size node _T_736 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_737 = and(_T_736, awsel_21) connect Queue2_BundleMap_137.io.enq.valid, _T_737 invalidate Queue2_BundleMap_137.io.enq.ready connect Queue2_BundleMap_137.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_137.io.count node _T_738 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_739 = and(_T_738, bsel_22) connect Queue2_BundleMap_138.io.deq.ready, _T_739 invalidate Queue2_BundleMap_138.io.deq.valid invalidate Queue2_BundleMap_138.io.deq.bits.extra_id invalidate Queue2_BundleMap_138.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_138.io.deq.bits.tl_state.size node _T_740 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_741 = and(_T_740, awsel_22) connect Queue2_BundleMap_138.io.enq.valid, _T_741 invalidate Queue2_BundleMap_138.io.enq.ready connect Queue2_BundleMap_138.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_138.io.count node _T_742 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_743 = and(_T_742, bsel_23) connect Queue2_BundleMap_139.io.deq.ready, _T_743 invalidate Queue2_BundleMap_139.io.deq.valid invalidate Queue2_BundleMap_139.io.deq.bits.extra_id invalidate Queue2_BundleMap_139.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_139.io.deq.bits.tl_state.size node _T_744 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_745 = and(_T_744, awsel_23) connect Queue2_BundleMap_139.io.enq.valid, _T_745 invalidate Queue2_BundleMap_139.io.enq.ready connect Queue2_BundleMap_139.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_139.io.count node _T_746 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_747 = and(_T_746, bsel_24) connect Queue2_BundleMap_140.io.deq.ready, _T_747 invalidate Queue2_BundleMap_140.io.deq.valid invalidate Queue2_BundleMap_140.io.deq.bits.extra_id invalidate Queue2_BundleMap_140.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_140.io.deq.bits.tl_state.size node _T_748 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_749 = and(_T_748, awsel_24) connect Queue2_BundleMap_140.io.enq.valid, _T_749 invalidate Queue2_BundleMap_140.io.enq.ready connect Queue2_BundleMap_140.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_140.io.count node _T_750 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_751 = and(_T_750, bsel_25) connect Queue2_BundleMap_141.io.deq.ready, _T_751 invalidate Queue2_BundleMap_141.io.deq.valid invalidate Queue2_BundleMap_141.io.deq.bits.extra_id invalidate Queue2_BundleMap_141.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_141.io.deq.bits.tl_state.size node _T_752 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_753 = and(_T_752, awsel_25) connect Queue2_BundleMap_141.io.enq.valid, _T_753 invalidate Queue2_BundleMap_141.io.enq.ready connect Queue2_BundleMap_141.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_141.io.count node _T_754 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_755 = and(_T_754, bsel_26) connect Queue2_BundleMap_142.io.deq.ready, _T_755 invalidate Queue2_BundleMap_142.io.deq.valid invalidate Queue2_BundleMap_142.io.deq.bits.extra_id invalidate Queue2_BundleMap_142.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_142.io.deq.bits.tl_state.size node _T_756 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_757 = and(_T_756, awsel_26) connect Queue2_BundleMap_142.io.enq.valid, _T_757 invalidate Queue2_BundleMap_142.io.enq.ready connect Queue2_BundleMap_142.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_142.io.count node _T_758 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_759 = and(_T_758, bsel_27) connect Queue2_BundleMap_143.io.deq.ready, _T_759 invalidate Queue2_BundleMap_143.io.deq.valid invalidate Queue2_BundleMap_143.io.deq.bits.extra_id invalidate Queue2_BundleMap_143.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_143.io.deq.bits.tl_state.size node _T_760 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_761 = and(_T_760, awsel_27) connect Queue2_BundleMap_143.io.enq.valid, _T_761 invalidate Queue2_BundleMap_143.io.enq.ready connect Queue2_BundleMap_143.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_143.io.count node _T_762 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_763 = and(_T_762, bsel_28) connect Queue2_BundleMap_144.io.deq.ready, _T_763 invalidate Queue2_BundleMap_144.io.deq.valid invalidate Queue2_BundleMap_144.io.deq.bits.extra_id invalidate Queue2_BundleMap_144.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_144.io.deq.bits.tl_state.size node _T_764 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_765 = and(_T_764, awsel_28) connect Queue2_BundleMap_144.io.enq.valid, _T_765 invalidate Queue2_BundleMap_144.io.enq.ready connect Queue2_BundleMap_144.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_144.io.count node _T_766 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_767 = and(_T_766, bsel_29) connect Queue2_BundleMap_145.io.deq.ready, _T_767 invalidate Queue2_BundleMap_145.io.deq.valid invalidate Queue2_BundleMap_145.io.deq.bits.extra_id invalidate Queue2_BundleMap_145.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_145.io.deq.bits.tl_state.size node _T_768 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_769 = and(_T_768, awsel_29) connect Queue2_BundleMap_145.io.enq.valid, _T_769 invalidate Queue2_BundleMap_145.io.enq.ready connect Queue2_BundleMap_145.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_145.io.count node _T_770 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_771 = and(_T_770, bsel_30) connect Queue2_BundleMap_146.io.deq.ready, _T_771 invalidate Queue2_BundleMap_146.io.deq.valid invalidate Queue2_BundleMap_146.io.deq.bits.extra_id invalidate Queue2_BundleMap_146.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_146.io.deq.bits.tl_state.size node _T_772 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_773 = and(_T_772, awsel_30) connect Queue2_BundleMap_146.io.enq.valid, _T_773 invalidate Queue2_BundleMap_146.io.enq.ready connect Queue2_BundleMap_146.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_146.io.count node _T_774 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_775 = and(_T_774, bsel_31) connect Queue2_BundleMap_147.io.deq.ready, _T_775 invalidate Queue2_BundleMap_147.io.deq.valid invalidate Queue2_BundleMap_147.io.deq.bits.extra_id invalidate Queue2_BundleMap_147.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_147.io.deq.bits.tl_state.size node _T_776 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_777 = and(_T_776, awsel_31) connect Queue2_BundleMap_147.io.enq.valid, _T_777 invalidate Queue2_BundleMap_147.io.enq.ready connect Queue2_BundleMap_147.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_147.io.count node _T_778 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_779 = and(_T_778, bsel_32) connect Queue2_BundleMap_148.io.deq.ready, _T_779 invalidate Queue2_BundleMap_148.io.deq.valid invalidate Queue2_BundleMap_148.io.deq.bits.extra_id invalidate Queue2_BundleMap_148.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_148.io.deq.bits.tl_state.size node _T_780 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_781 = and(_T_780, awsel_32) connect Queue2_BundleMap_148.io.enq.valid, _T_781 invalidate Queue2_BundleMap_148.io.enq.ready connect Queue2_BundleMap_148.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_148.io.count node _T_782 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_783 = and(_T_782, bsel_33) connect Queue2_BundleMap_149.io.deq.ready, _T_783 invalidate Queue2_BundleMap_149.io.deq.valid invalidate Queue2_BundleMap_149.io.deq.bits.extra_id invalidate Queue2_BundleMap_149.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_149.io.deq.bits.tl_state.size node _T_784 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_785 = and(_T_784, awsel_33) connect Queue2_BundleMap_149.io.enq.valid, _T_785 invalidate Queue2_BundleMap_149.io.enq.ready connect Queue2_BundleMap_149.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_149.io.count node _T_786 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_787 = and(_T_786, bsel_34) connect Queue2_BundleMap_150.io.deq.ready, _T_787 invalidate Queue2_BundleMap_150.io.deq.valid invalidate Queue2_BundleMap_150.io.deq.bits.extra_id invalidate Queue2_BundleMap_150.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_150.io.deq.bits.tl_state.size node _T_788 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_789 = and(_T_788, awsel_34) connect Queue2_BundleMap_150.io.enq.valid, _T_789 invalidate Queue2_BundleMap_150.io.enq.ready connect Queue2_BundleMap_150.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_150.io.count node _T_790 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_791 = and(_T_790, bsel_35) connect Queue2_BundleMap_151.io.deq.ready, _T_791 invalidate Queue2_BundleMap_151.io.deq.valid invalidate Queue2_BundleMap_151.io.deq.bits.extra_id invalidate Queue2_BundleMap_151.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_151.io.deq.bits.tl_state.size node _T_792 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_793 = and(_T_792, awsel_35) connect Queue2_BundleMap_151.io.enq.valid, _T_793 invalidate Queue2_BundleMap_151.io.enq.ready connect Queue2_BundleMap_151.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_151.io.count node _T_794 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_795 = and(_T_794, bsel_36) connect Queue2_BundleMap_152.io.deq.ready, _T_795 invalidate Queue2_BundleMap_152.io.deq.valid invalidate Queue2_BundleMap_152.io.deq.bits.extra_id invalidate Queue2_BundleMap_152.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_152.io.deq.bits.tl_state.size node _T_796 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_797 = and(_T_796, awsel_36) connect Queue2_BundleMap_152.io.enq.valid, _T_797 invalidate Queue2_BundleMap_152.io.enq.ready connect Queue2_BundleMap_152.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_152.io.count node _T_798 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_799 = and(_T_798, bsel_37) connect Queue2_BundleMap_153.io.deq.ready, _T_799 invalidate Queue2_BundleMap_153.io.deq.valid invalidate Queue2_BundleMap_153.io.deq.bits.extra_id invalidate Queue2_BundleMap_153.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_153.io.deq.bits.tl_state.size node _T_800 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_801 = and(_T_800, awsel_37) connect Queue2_BundleMap_153.io.enq.valid, _T_801 invalidate Queue2_BundleMap_153.io.enq.ready connect Queue2_BundleMap_153.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_153.io.count node _T_802 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_803 = and(_T_802, bsel_38) connect Queue2_BundleMap_154.io.deq.ready, _T_803 invalidate Queue2_BundleMap_154.io.deq.valid invalidate Queue2_BundleMap_154.io.deq.bits.extra_id invalidate Queue2_BundleMap_154.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_154.io.deq.bits.tl_state.size node _T_804 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_805 = and(_T_804, awsel_38) connect Queue2_BundleMap_154.io.enq.valid, _T_805 invalidate Queue2_BundleMap_154.io.enq.ready connect Queue2_BundleMap_154.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_154.io.count node _T_806 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_807 = and(_T_806, bsel_39) connect Queue2_BundleMap_155.io.deq.ready, _T_807 invalidate Queue2_BundleMap_155.io.deq.valid invalidate Queue2_BundleMap_155.io.deq.bits.extra_id invalidate Queue2_BundleMap_155.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_155.io.deq.bits.tl_state.size node _T_808 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_809 = and(_T_808, awsel_39) connect Queue2_BundleMap_155.io.enq.valid, _T_809 invalidate Queue2_BundleMap_155.io.enq.ready connect Queue2_BundleMap_155.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_155.io.count node _T_810 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_811 = and(_T_810, bsel_40) connect Queue2_BundleMap_156.io.deq.ready, _T_811 invalidate Queue2_BundleMap_156.io.deq.valid invalidate Queue2_BundleMap_156.io.deq.bits.extra_id invalidate Queue2_BundleMap_156.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_156.io.deq.bits.tl_state.size node _T_812 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_813 = and(_T_812, awsel_40) connect Queue2_BundleMap_156.io.enq.valid, _T_813 invalidate Queue2_BundleMap_156.io.enq.ready connect Queue2_BundleMap_156.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_156.io.count node _T_814 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_815 = and(_T_814, bsel_41) connect Queue2_BundleMap_157.io.deq.ready, _T_815 invalidate Queue2_BundleMap_157.io.deq.valid invalidate Queue2_BundleMap_157.io.deq.bits.extra_id invalidate Queue2_BundleMap_157.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_157.io.deq.bits.tl_state.size node _T_816 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_817 = and(_T_816, awsel_41) connect Queue2_BundleMap_157.io.enq.valid, _T_817 invalidate Queue2_BundleMap_157.io.enq.ready connect Queue2_BundleMap_157.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_157.io.count node _T_818 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_819 = and(_T_818, bsel_42) connect Queue2_BundleMap_158.io.deq.ready, _T_819 invalidate Queue2_BundleMap_158.io.deq.valid invalidate Queue2_BundleMap_158.io.deq.bits.extra_id invalidate Queue2_BundleMap_158.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_158.io.deq.bits.tl_state.size node _T_820 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_821 = and(_T_820, awsel_42) connect Queue2_BundleMap_158.io.enq.valid, _T_821 invalidate Queue2_BundleMap_158.io.enq.ready connect Queue2_BundleMap_158.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_158.io.count node _T_822 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_823 = and(_T_822, bsel_43) connect Queue2_BundleMap_159.io.deq.ready, _T_823 invalidate Queue2_BundleMap_159.io.deq.valid invalidate Queue2_BundleMap_159.io.deq.bits.extra_id invalidate Queue2_BundleMap_159.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_159.io.deq.bits.tl_state.size node _T_824 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_825 = and(_T_824, awsel_43) connect Queue2_BundleMap_159.io.enq.valid, _T_825 invalidate Queue2_BundleMap_159.io.enq.ready connect Queue2_BundleMap_159.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_159.io.count node _T_826 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_827 = and(_T_826, bsel_44) connect Queue2_BundleMap_160.io.deq.ready, _T_827 invalidate Queue2_BundleMap_160.io.deq.valid invalidate Queue2_BundleMap_160.io.deq.bits.extra_id invalidate Queue2_BundleMap_160.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_160.io.deq.bits.tl_state.size node _T_828 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_829 = and(_T_828, awsel_44) connect Queue2_BundleMap_160.io.enq.valid, _T_829 invalidate Queue2_BundleMap_160.io.enq.ready connect Queue2_BundleMap_160.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_160.io.count node _T_830 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_831 = and(_T_830, bsel_45) connect Queue2_BundleMap_161.io.deq.ready, _T_831 invalidate Queue2_BundleMap_161.io.deq.valid invalidate Queue2_BundleMap_161.io.deq.bits.extra_id invalidate Queue2_BundleMap_161.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_161.io.deq.bits.tl_state.size node _T_832 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_833 = and(_T_832, awsel_45) connect Queue2_BundleMap_161.io.enq.valid, _T_833 invalidate Queue2_BundleMap_161.io.enq.ready connect Queue2_BundleMap_161.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_161.io.count node _T_834 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_835 = and(_T_834, bsel_46) connect Queue2_BundleMap_162.io.deq.ready, _T_835 invalidate Queue2_BundleMap_162.io.deq.valid invalidate Queue2_BundleMap_162.io.deq.bits.extra_id invalidate Queue2_BundleMap_162.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_162.io.deq.bits.tl_state.size node _T_836 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_837 = and(_T_836, awsel_46) connect Queue2_BundleMap_162.io.enq.valid, _T_837 invalidate Queue2_BundleMap_162.io.enq.ready connect Queue2_BundleMap_162.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_162.io.count node _T_838 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_839 = and(_T_838, bsel_47) connect Queue2_BundleMap_163.io.deq.ready, _T_839 invalidate Queue2_BundleMap_163.io.deq.valid invalidate Queue2_BundleMap_163.io.deq.bits.extra_id invalidate Queue2_BundleMap_163.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_163.io.deq.bits.tl_state.size node _T_840 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_841 = and(_T_840, awsel_47) connect Queue2_BundleMap_163.io.enq.valid, _T_841 invalidate Queue2_BundleMap_163.io.enq.ready connect Queue2_BundleMap_163.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_163.io.count node _T_842 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_843 = and(_T_842, bsel_48) connect Queue2_BundleMap_164.io.deq.ready, _T_843 invalidate Queue2_BundleMap_164.io.deq.valid invalidate Queue2_BundleMap_164.io.deq.bits.extra_id invalidate Queue2_BundleMap_164.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_164.io.deq.bits.tl_state.size node _T_844 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_845 = and(_T_844, awsel_48) connect Queue2_BundleMap_164.io.enq.valid, _T_845 invalidate Queue2_BundleMap_164.io.enq.ready connect Queue2_BundleMap_164.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_164.io.count node _T_846 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_847 = and(_T_846, bsel_49) connect Queue2_BundleMap_165.io.deq.ready, _T_847 invalidate Queue2_BundleMap_165.io.deq.valid invalidate Queue2_BundleMap_165.io.deq.bits.extra_id invalidate Queue2_BundleMap_165.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_165.io.deq.bits.tl_state.size node _T_848 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_849 = and(_T_848, awsel_49) connect Queue2_BundleMap_165.io.enq.valid, _T_849 invalidate Queue2_BundleMap_165.io.enq.ready connect Queue2_BundleMap_165.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_165.io.count node _T_850 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_851 = and(_T_850, bsel_50) connect Queue2_BundleMap_166.io.deq.ready, _T_851 invalidate Queue2_BundleMap_166.io.deq.valid invalidate Queue2_BundleMap_166.io.deq.bits.extra_id invalidate Queue2_BundleMap_166.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_166.io.deq.bits.tl_state.size node _T_852 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_853 = and(_T_852, awsel_50) connect Queue2_BundleMap_166.io.enq.valid, _T_853 invalidate Queue2_BundleMap_166.io.enq.ready connect Queue2_BundleMap_166.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_166.io.count node _T_854 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_855 = and(_T_854, bsel_51) connect Queue2_BundleMap_167.io.deq.ready, _T_855 invalidate Queue2_BundleMap_167.io.deq.valid invalidate Queue2_BundleMap_167.io.deq.bits.extra_id invalidate Queue2_BundleMap_167.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_167.io.deq.bits.tl_state.size node _T_856 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_857 = and(_T_856, awsel_51) connect Queue2_BundleMap_167.io.enq.valid, _T_857 invalidate Queue2_BundleMap_167.io.enq.ready connect Queue2_BundleMap_167.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_167.io.count node _T_858 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_859 = and(_T_858, bsel_52) connect Queue2_BundleMap_168.io.deq.ready, _T_859 invalidate Queue2_BundleMap_168.io.deq.valid invalidate Queue2_BundleMap_168.io.deq.bits.extra_id invalidate Queue2_BundleMap_168.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_168.io.deq.bits.tl_state.size node _T_860 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_861 = and(_T_860, awsel_52) connect Queue2_BundleMap_168.io.enq.valid, _T_861 invalidate Queue2_BundleMap_168.io.enq.ready connect Queue2_BundleMap_168.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_168.io.count node _T_862 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_863 = and(_T_862, bsel_53) connect Queue2_BundleMap_169.io.deq.ready, _T_863 invalidate Queue2_BundleMap_169.io.deq.valid invalidate Queue2_BundleMap_169.io.deq.bits.extra_id invalidate Queue2_BundleMap_169.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_169.io.deq.bits.tl_state.size node _T_864 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_865 = and(_T_864, awsel_53) connect Queue2_BundleMap_169.io.enq.valid, _T_865 invalidate Queue2_BundleMap_169.io.enq.ready connect Queue2_BundleMap_169.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_169.io.count node _T_866 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_867 = and(_T_866, bsel_54) connect Queue2_BundleMap_170.io.deq.ready, _T_867 invalidate Queue2_BundleMap_170.io.deq.valid invalidate Queue2_BundleMap_170.io.deq.bits.extra_id invalidate Queue2_BundleMap_170.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_170.io.deq.bits.tl_state.size node _T_868 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_869 = and(_T_868, awsel_54) connect Queue2_BundleMap_170.io.enq.valid, _T_869 invalidate Queue2_BundleMap_170.io.enq.ready connect Queue2_BundleMap_170.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_170.io.count node _T_870 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_871 = and(_T_870, bsel_55) connect Queue2_BundleMap_171.io.deq.ready, _T_871 invalidate Queue2_BundleMap_171.io.deq.valid invalidate Queue2_BundleMap_171.io.deq.bits.extra_id invalidate Queue2_BundleMap_171.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_171.io.deq.bits.tl_state.size node _T_872 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_873 = and(_T_872, awsel_55) connect Queue2_BundleMap_171.io.enq.valid, _T_873 invalidate Queue2_BundleMap_171.io.enq.ready connect Queue2_BundleMap_171.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_171.io.count node _T_874 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_875 = and(_T_874, bsel_56) connect Queue2_BundleMap_172.io.deq.ready, _T_875 invalidate Queue2_BundleMap_172.io.deq.valid invalidate Queue2_BundleMap_172.io.deq.bits.extra_id invalidate Queue2_BundleMap_172.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_172.io.deq.bits.tl_state.size node _T_876 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_877 = and(_T_876, awsel_56) connect Queue2_BundleMap_172.io.enq.valid, _T_877 invalidate Queue2_BundleMap_172.io.enq.ready connect Queue2_BundleMap_172.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_172.io.count node _T_878 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_879 = and(_T_878, bsel_57) connect Queue2_BundleMap_173.io.deq.ready, _T_879 invalidate Queue2_BundleMap_173.io.deq.valid invalidate Queue2_BundleMap_173.io.deq.bits.extra_id invalidate Queue2_BundleMap_173.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_173.io.deq.bits.tl_state.size node _T_880 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_881 = and(_T_880, awsel_57) connect Queue2_BundleMap_173.io.enq.valid, _T_881 invalidate Queue2_BundleMap_173.io.enq.ready connect Queue2_BundleMap_173.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_173.io.count node _T_882 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_883 = and(_T_882, bsel_58) connect Queue2_BundleMap_174.io.deq.ready, _T_883 invalidate Queue2_BundleMap_174.io.deq.valid invalidate Queue2_BundleMap_174.io.deq.bits.extra_id invalidate Queue2_BundleMap_174.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_174.io.deq.bits.tl_state.size node _T_884 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_885 = and(_T_884, awsel_58) connect Queue2_BundleMap_174.io.enq.valid, _T_885 invalidate Queue2_BundleMap_174.io.enq.ready connect Queue2_BundleMap_174.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_174.io.count node _T_886 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_887 = and(_T_886, bsel_59) connect Queue2_BundleMap_175.io.deq.ready, _T_887 invalidate Queue2_BundleMap_175.io.deq.valid invalidate Queue2_BundleMap_175.io.deq.bits.extra_id invalidate Queue2_BundleMap_175.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_175.io.deq.bits.tl_state.size node _T_888 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_889 = and(_T_888, awsel_59) connect Queue2_BundleMap_175.io.enq.valid, _T_889 invalidate Queue2_BundleMap_175.io.enq.ready connect Queue2_BundleMap_175.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_175.io.count node _T_890 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_891 = and(_T_890, bsel_60) connect Queue2_BundleMap_176.io.deq.ready, _T_891 invalidate Queue2_BundleMap_176.io.deq.valid invalidate Queue2_BundleMap_176.io.deq.bits.extra_id invalidate Queue2_BundleMap_176.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_176.io.deq.bits.tl_state.size node _T_892 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_893 = and(_T_892, awsel_60) connect Queue2_BundleMap_176.io.enq.valid, _T_893 invalidate Queue2_BundleMap_176.io.enq.ready connect Queue2_BundleMap_176.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_176.io.count node _T_894 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_895 = and(_T_894, bsel_61) connect Queue2_BundleMap_177.io.deq.ready, _T_895 invalidate Queue2_BundleMap_177.io.deq.valid invalidate Queue2_BundleMap_177.io.deq.bits.extra_id invalidate Queue2_BundleMap_177.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_177.io.deq.bits.tl_state.size node _T_896 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_897 = and(_T_896, awsel_61) connect Queue2_BundleMap_177.io.enq.valid, _T_897 invalidate Queue2_BundleMap_177.io.enq.ready connect Queue2_BundleMap_177.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_177.io.count node _T_898 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_899 = and(_T_898, bsel_62) connect Queue2_BundleMap_178.io.deq.ready, _T_899 invalidate Queue2_BundleMap_178.io.deq.valid invalidate Queue2_BundleMap_178.io.deq.bits.extra_id invalidate Queue2_BundleMap_178.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_178.io.deq.bits.tl_state.size node _T_900 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_901 = and(_T_900, awsel_62) connect Queue2_BundleMap_178.io.enq.valid, _T_901 invalidate Queue2_BundleMap_178.io.enq.ready connect Queue2_BundleMap_178.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_178.io.count node _T_902 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_903 = and(_T_902, bsel_63) connect Queue2_BundleMap_179.io.deq.ready, _T_903 invalidate Queue2_BundleMap_179.io.deq.valid invalidate Queue2_BundleMap_179.io.deq.bits.extra_id invalidate Queue2_BundleMap_179.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_179.io.deq.bits.tl_state.size node _T_904 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_905 = and(_T_904, awsel_63) connect Queue2_BundleMap_179.io.enq.valid, _T_905 invalidate Queue2_BundleMap_179.io.enq.ready connect Queue2_BundleMap_179.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_179.io.count node _T_906 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_907 = and(_T_906, bsel_64) connect Queue2_BundleMap_180.io.deq.ready, _T_907 invalidate Queue2_BundleMap_180.io.deq.valid invalidate Queue2_BundleMap_180.io.deq.bits.extra_id invalidate Queue2_BundleMap_180.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_180.io.deq.bits.tl_state.size node _T_908 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_909 = and(_T_908, awsel_64) connect Queue2_BundleMap_180.io.enq.valid, _T_909 invalidate Queue2_BundleMap_180.io.enq.ready connect Queue2_BundleMap_180.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_180.io.count node _T_910 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_911 = and(_T_910, bsel_65) connect Queue2_BundleMap_181.io.deq.ready, _T_911 invalidate Queue2_BundleMap_181.io.deq.valid invalidate Queue2_BundleMap_181.io.deq.bits.extra_id invalidate Queue2_BundleMap_181.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_181.io.deq.bits.tl_state.size node _T_912 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_913 = and(_T_912, awsel_65) connect Queue2_BundleMap_181.io.enq.valid, _T_913 invalidate Queue2_BundleMap_181.io.enq.ready connect Queue2_BundleMap_181.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_181.io.count node _T_914 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_915 = and(_T_914, bsel_66) connect Queue2_BundleMap_182.io.deq.ready, _T_915 invalidate Queue2_BundleMap_182.io.deq.valid invalidate Queue2_BundleMap_182.io.deq.bits.extra_id invalidate Queue2_BundleMap_182.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_182.io.deq.bits.tl_state.size node _T_916 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_917 = and(_T_916, awsel_66) connect Queue2_BundleMap_182.io.enq.valid, _T_917 invalidate Queue2_BundleMap_182.io.enq.ready connect Queue2_BundleMap_182.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_182.io.count node _T_918 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_919 = and(_T_918, bsel_67) connect Queue2_BundleMap_183.io.deq.ready, _T_919 invalidate Queue2_BundleMap_183.io.deq.valid invalidate Queue2_BundleMap_183.io.deq.bits.extra_id invalidate Queue2_BundleMap_183.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_183.io.deq.bits.tl_state.size node _T_920 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_921 = and(_T_920, awsel_67) connect Queue2_BundleMap_183.io.enq.valid, _T_921 invalidate Queue2_BundleMap_183.io.enq.ready connect Queue2_BundleMap_183.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_183.io.count node _T_922 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_923 = and(_T_922, bsel_68) connect Queue2_BundleMap_184.io.deq.ready, _T_923 invalidate Queue2_BundleMap_184.io.deq.valid invalidate Queue2_BundleMap_184.io.deq.bits.extra_id invalidate Queue2_BundleMap_184.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_184.io.deq.bits.tl_state.size node _T_924 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_925 = and(_T_924, awsel_68) connect Queue2_BundleMap_184.io.enq.valid, _T_925 invalidate Queue2_BundleMap_184.io.enq.ready connect Queue2_BundleMap_184.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_184.io.count node _T_926 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_927 = and(_T_926, bsel_69) connect Queue2_BundleMap_185.io.deq.ready, _T_927 invalidate Queue2_BundleMap_185.io.deq.valid invalidate Queue2_BundleMap_185.io.deq.bits.extra_id invalidate Queue2_BundleMap_185.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_185.io.deq.bits.tl_state.size node _T_928 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_929 = and(_T_928, awsel_69) connect Queue2_BundleMap_185.io.enq.valid, _T_929 invalidate Queue2_BundleMap_185.io.enq.ready connect Queue2_BundleMap_185.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_185.io.count node _T_930 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_931 = and(_T_930, bsel_70) connect Queue2_BundleMap_186.io.deq.ready, _T_931 invalidate Queue2_BundleMap_186.io.deq.valid invalidate Queue2_BundleMap_186.io.deq.bits.extra_id invalidate Queue2_BundleMap_186.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_186.io.deq.bits.tl_state.size node _T_932 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_933 = and(_T_932, awsel_70) connect Queue2_BundleMap_186.io.enq.valid, _T_933 invalidate Queue2_BundleMap_186.io.enq.ready connect Queue2_BundleMap_186.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_186.io.count node _T_934 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_935 = and(_T_934, bsel_71) connect Queue2_BundleMap_187.io.deq.ready, _T_935 invalidate Queue2_BundleMap_187.io.deq.valid invalidate Queue2_BundleMap_187.io.deq.bits.extra_id invalidate Queue2_BundleMap_187.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_187.io.deq.bits.tl_state.size node _T_936 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_937 = and(_T_936, awsel_71) connect Queue2_BundleMap_187.io.enq.valid, _T_937 invalidate Queue2_BundleMap_187.io.enq.ready connect Queue2_BundleMap_187.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_187.io.count node _T_938 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_939 = and(_T_938, bsel_72) connect Queue2_BundleMap_188.io.deq.ready, _T_939 invalidate Queue2_BundleMap_188.io.deq.valid invalidate Queue2_BundleMap_188.io.deq.bits.extra_id invalidate Queue2_BundleMap_188.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_188.io.deq.bits.tl_state.size node _T_940 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_941 = and(_T_940, awsel_72) connect Queue2_BundleMap_188.io.enq.valid, _T_941 invalidate Queue2_BundleMap_188.io.enq.ready connect Queue2_BundleMap_188.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_188.io.count node _T_942 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_943 = and(_T_942, bsel_73) connect Queue2_BundleMap_189.io.deq.ready, _T_943 invalidate Queue2_BundleMap_189.io.deq.valid invalidate Queue2_BundleMap_189.io.deq.bits.extra_id invalidate Queue2_BundleMap_189.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_189.io.deq.bits.tl_state.size node _T_944 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_945 = and(_T_944, awsel_73) connect Queue2_BundleMap_189.io.enq.valid, _T_945 invalidate Queue2_BundleMap_189.io.enq.ready connect Queue2_BundleMap_189.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_189.io.count node _T_946 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_947 = and(_T_946, bsel_74) connect Queue2_BundleMap_190.io.deq.ready, _T_947 invalidate Queue2_BundleMap_190.io.deq.valid invalidate Queue2_BundleMap_190.io.deq.bits.extra_id invalidate Queue2_BundleMap_190.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_190.io.deq.bits.tl_state.size node _T_948 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_949 = and(_T_948, awsel_74) connect Queue2_BundleMap_190.io.enq.valid, _T_949 invalidate Queue2_BundleMap_190.io.enq.ready connect Queue2_BundleMap_190.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_190.io.count node _T_950 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_951 = and(_T_950, bsel_75) connect Queue2_BundleMap_191.io.deq.ready, _T_951 invalidate Queue2_BundleMap_191.io.deq.valid invalidate Queue2_BundleMap_191.io.deq.bits.extra_id invalidate Queue2_BundleMap_191.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_191.io.deq.bits.tl_state.size node _T_952 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_953 = and(_T_952, awsel_75) connect Queue2_BundleMap_191.io.enq.valid, _T_953 invalidate Queue2_BundleMap_191.io.enq.ready connect Queue2_BundleMap_191.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_191.io.count node _T_954 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_955 = and(_T_954, bsel_76) connect Queue2_BundleMap_192.io.deq.ready, _T_955 invalidate Queue2_BundleMap_192.io.deq.valid invalidate Queue2_BundleMap_192.io.deq.bits.extra_id invalidate Queue2_BundleMap_192.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_192.io.deq.bits.tl_state.size node _T_956 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_957 = and(_T_956, awsel_76) connect Queue2_BundleMap_192.io.enq.valid, _T_957 invalidate Queue2_BundleMap_192.io.enq.ready connect Queue2_BundleMap_192.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_192.io.count node _T_958 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_959 = and(_T_958, bsel_77) connect Queue2_BundleMap_193.io.deq.ready, _T_959 invalidate Queue2_BundleMap_193.io.deq.valid invalidate Queue2_BundleMap_193.io.deq.bits.extra_id invalidate Queue2_BundleMap_193.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_193.io.deq.bits.tl_state.size node _T_960 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_961 = and(_T_960, awsel_77) connect Queue2_BundleMap_193.io.enq.valid, _T_961 invalidate Queue2_BundleMap_193.io.enq.ready connect Queue2_BundleMap_193.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_193.io.count node _T_962 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_963 = and(_T_962, bsel_78) connect Queue2_BundleMap_194.io.deq.ready, _T_963 invalidate Queue2_BundleMap_194.io.deq.valid invalidate Queue2_BundleMap_194.io.deq.bits.extra_id invalidate Queue2_BundleMap_194.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_194.io.deq.bits.tl_state.size node _T_964 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_965 = and(_T_964, awsel_78) connect Queue2_BundleMap_194.io.enq.valid, _T_965 invalidate Queue2_BundleMap_194.io.enq.ready connect Queue2_BundleMap_194.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_194.io.count node _T_966 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_967 = and(_T_966, bsel_79) connect Queue2_BundleMap_195.io.deq.ready, _T_967 invalidate Queue2_BundleMap_195.io.deq.valid invalidate Queue2_BundleMap_195.io.deq.bits.extra_id invalidate Queue2_BundleMap_195.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_195.io.deq.bits.tl_state.size node _T_968 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_969 = and(_T_968, awsel_79) connect Queue2_BundleMap_195.io.enq.valid, _T_969 invalidate Queue2_BundleMap_195.io.enq.ready connect Queue2_BundleMap_195.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_195.io.count node _T_970 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_971 = and(_T_970, bsel_80) connect Queue2_BundleMap_196.io.deq.ready, _T_971 invalidate Queue2_BundleMap_196.io.deq.valid invalidate Queue2_BundleMap_196.io.deq.bits.extra_id invalidate Queue2_BundleMap_196.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_196.io.deq.bits.tl_state.size node _T_972 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_973 = and(_T_972, awsel_80) connect Queue2_BundleMap_196.io.enq.valid, _T_973 invalidate Queue2_BundleMap_196.io.enq.ready connect Queue2_BundleMap_196.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_196.io.count node _T_974 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_975 = and(_T_974, bsel_81) connect Queue2_BundleMap_197.io.deq.ready, _T_975 invalidate Queue2_BundleMap_197.io.deq.valid invalidate Queue2_BundleMap_197.io.deq.bits.extra_id invalidate Queue2_BundleMap_197.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_197.io.deq.bits.tl_state.size node _T_976 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_977 = and(_T_976, awsel_81) connect Queue2_BundleMap_197.io.enq.valid, _T_977 invalidate Queue2_BundleMap_197.io.enq.ready connect Queue2_BundleMap_197.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_197.io.count node _T_978 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_979 = and(_T_978, bsel_82) connect Queue2_BundleMap_198.io.deq.ready, _T_979 invalidate Queue2_BundleMap_198.io.deq.valid invalidate Queue2_BundleMap_198.io.deq.bits.extra_id invalidate Queue2_BundleMap_198.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_198.io.deq.bits.tl_state.size node _T_980 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_981 = and(_T_980, awsel_82) connect Queue2_BundleMap_198.io.enq.valid, _T_981 invalidate Queue2_BundleMap_198.io.enq.ready connect Queue2_BundleMap_198.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_198.io.count node _T_982 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_983 = and(_T_982, bsel_83) connect Queue2_BundleMap_199.io.deq.ready, _T_983 invalidate Queue2_BundleMap_199.io.deq.valid invalidate Queue2_BundleMap_199.io.deq.bits.extra_id invalidate Queue2_BundleMap_199.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_199.io.deq.bits.tl_state.size node _T_984 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_985 = and(_T_984, awsel_83) connect Queue2_BundleMap_199.io.enq.valid, _T_985 invalidate Queue2_BundleMap_199.io.enq.ready connect Queue2_BundleMap_199.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_199.io.count node _T_986 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_987 = and(_T_986, bsel_84) connect Queue2_BundleMap_200.io.deq.ready, _T_987 invalidate Queue2_BundleMap_200.io.deq.valid invalidate Queue2_BundleMap_200.io.deq.bits.extra_id invalidate Queue2_BundleMap_200.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_200.io.deq.bits.tl_state.size node _T_988 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_989 = and(_T_988, awsel_84) connect Queue2_BundleMap_200.io.enq.valid, _T_989 invalidate Queue2_BundleMap_200.io.enq.ready connect Queue2_BundleMap_200.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_200.io.count node _T_990 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_991 = and(_T_990, bsel_85) connect Queue2_BundleMap_201.io.deq.ready, _T_991 invalidate Queue2_BundleMap_201.io.deq.valid invalidate Queue2_BundleMap_201.io.deq.bits.extra_id invalidate Queue2_BundleMap_201.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_201.io.deq.bits.tl_state.size node _T_992 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_993 = and(_T_992, awsel_85) connect Queue2_BundleMap_201.io.enq.valid, _T_993 invalidate Queue2_BundleMap_201.io.enq.ready connect Queue2_BundleMap_201.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_201.io.count node _T_994 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_995 = and(_T_994, bsel_86) connect Queue2_BundleMap_202.io.deq.ready, _T_995 invalidate Queue2_BundleMap_202.io.deq.valid invalidate Queue2_BundleMap_202.io.deq.bits.extra_id invalidate Queue2_BundleMap_202.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_202.io.deq.bits.tl_state.size node _T_996 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_997 = and(_T_996, awsel_86) connect Queue2_BundleMap_202.io.enq.valid, _T_997 invalidate Queue2_BundleMap_202.io.enq.ready connect Queue2_BundleMap_202.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_202.io.count node _T_998 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_999 = and(_T_998, bsel_87) connect Queue2_BundleMap_203.io.deq.ready, _T_999 invalidate Queue2_BundleMap_203.io.deq.valid invalidate Queue2_BundleMap_203.io.deq.bits.extra_id invalidate Queue2_BundleMap_203.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_203.io.deq.bits.tl_state.size node _T_1000 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1001 = and(_T_1000, awsel_87) connect Queue2_BundleMap_203.io.enq.valid, _T_1001 invalidate Queue2_BundleMap_203.io.enq.ready connect Queue2_BundleMap_203.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_203.io.count node _T_1002 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1003 = and(_T_1002, bsel_88) connect Queue2_BundleMap_204.io.deq.ready, _T_1003 invalidate Queue2_BundleMap_204.io.deq.valid invalidate Queue2_BundleMap_204.io.deq.bits.extra_id invalidate Queue2_BundleMap_204.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_204.io.deq.bits.tl_state.size node _T_1004 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1005 = and(_T_1004, awsel_88) connect Queue2_BundleMap_204.io.enq.valid, _T_1005 invalidate Queue2_BundleMap_204.io.enq.ready connect Queue2_BundleMap_204.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_204.io.count node _T_1006 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1007 = and(_T_1006, bsel_89) connect Queue2_BundleMap_205.io.deq.ready, _T_1007 invalidate Queue2_BundleMap_205.io.deq.valid invalidate Queue2_BundleMap_205.io.deq.bits.extra_id invalidate Queue2_BundleMap_205.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_205.io.deq.bits.tl_state.size node _T_1008 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1009 = and(_T_1008, awsel_89) connect Queue2_BundleMap_205.io.enq.valid, _T_1009 invalidate Queue2_BundleMap_205.io.enq.ready connect Queue2_BundleMap_205.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_205.io.count node _T_1010 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1011 = and(_T_1010, bsel_90) connect Queue2_BundleMap_206.io.deq.ready, _T_1011 invalidate Queue2_BundleMap_206.io.deq.valid invalidate Queue2_BundleMap_206.io.deq.bits.extra_id invalidate Queue2_BundleMap_206.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_206.io.deq.bits.tl_state.size node _T_1012 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1013 = and(_T_1012, awsel_90) connect Queue2_BundleMap_206.io.enq.valid, _T_1013 invalidate Queue2_BundleMap_206.io.enq.ready connect Queue2_BundleMap_206.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_206.io.count node _T_1014 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1015 = and(_T_1014, bsel_91) connect Queue2_BundleMap_207.io.deq.ready, _T_1015 invalidate Queue2_BundleMap_207.io.deq.valid invalidate Queue2_BundleMap_207.io.deq.bits.extra_id invalidate Queue2_BundleMap_207.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_207.io.deq.bits.tl_state.size node _T_1016 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1017 = and(_T_1016, awsel_91) connect Queue2_BundleMap_207.io.enq.valid, _T_1017 invalidate Queue2_BundleMap_207.io.enq.ready connect Queue2_BundleMap_207.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_207.io.count node _T_1018 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1019 = and(_T_1018, bsel_92) connect Queue2_BundleMap_208.io.deq.ready, _T_1019 invalidate Queue2_BundleMap_208.io.deq.valid invalidate Queue2_BundleMap_208.io.deq.bits.extra_id invalidate Queue2_BundleMap_208.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_208.io.deq.bits.tl_state.size node _T_1020 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1021 = and(_T_1020, awsel_92) connect Queue2_BundleMap_208.io.enq.valid, _T_1021 invalidate Queue2_BundleMap_208.io.enq.ready connect Queue2_BundleMap_208.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_208.io.count node _T_1022 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1023 = and(_T_1022, bsel_93) connect Queue2_BundleMap_209.io.deq.ready, _T_1023 invalidate Queue2_BundleMap_209.io.deq.valid invalidate Queue2_BundleMap_209.io.deq.bits.extra_id invalidate Queue2_BundleMap_209.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_209.io.deq.bits.tl_state.size node _T_1024 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1025 = and(_T_1024, awsel_93) connect Queue2_BundleMap_209.io.enq.valid, _T_1025 invalidate Queue2_BundleMap_209.io.enq.ready connect Queue2_BundleMap_209.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_209.io.count node _T_1026 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1027 = and(_T_1026, bsel_94) connect Queue2_BundleMap_210.io.deq.ready, _T_1027 invalidate Queue2_BundleMap_210.io.deq.valid invalidate Queue2_BundleMap_210.io.deq.bits.extra_id invalidate Queue2_BundleMap_210.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_210.io.deq.bits.tl_state.size node _T_1028 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1029 = and(_T_1028, awsel_94) connect Queue2_BundleMap_210.io.enq.valid, _T_1029 invalidate Queue2_BundleMap_210.io.enq.ready connect Queue2_BundleMap_210.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_210.io.count node _T_1030 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1031 = and(_T_1030, bsel_95) connect Queue2_BundleMap_211.io.deq.ready, _T_1031 invalidate Queue2_BundleMap_211.io.deq.valid invalidate Queue2_BundleMap_211.io.deq.bits.extra_id invalidate Queue2_BundleMap_211.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_211.io.deq.bits.tl_state.size node _T_1032 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1033 = and(_T_1032, awsel_95) connect Queue2_BundleMap_211.io.enq.valid, _T_1033 invalidate Queue2_BundleMap_211.io.enq.ready connect Queue2_BundleMap_211.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_211.io.count node _T_1034 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1035 = and(_T_1034, bsel_96) connect Queue2_BundleMap_212.io.deq.ready, _T_1035 invalidate Queue2_BundleMap_212.io.deq.valid invalidate Queue2_BundleMap_212.io.deq.bits.extra_id invalidate Queue2_BundleMap_212.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_212.io.deq.bits.tl_state.size node _T_1036 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1037 = and(_T_1036, awsel_96) connect Queue2_BundleMap_212.io.enq.valid, _T_1037 invalidate Queue2_BundleMap_212.io.enq.ready connect Queue2_BundleMap_212.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_212.io.count node _T_1038 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1039 = and(_T_1038, bsel_97) connect Queue2_BundleMap_213.io.deq.ready, _T_1039 invalidate Queue2_BundleMap_213.io.deq.valid invalidate Queue2_BundleMap_213.io.deq.bits.extra_id invalidate Queue2_BundleMap_213.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_213.io.deq.bits.tl_state.size node _T_1040 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1041 = and(_T_1040, awsel_97) connect Queue2_BundleMap_213.io.enq.valid, _T_1041 invalidate Queue2_BundleMap_213.io.enq.ready connect Queue2_BundleMap_213.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_213.io.count node _T_1042 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1043 = and(_T_1042, bsel_98) connect Queue2_BundleMap_214.io.deq.ready, _T_1043 invalidate Queue2_BundleMap_214.io.deq.valid invalidate Queue2_BundleMap_214.io.deq.bits.extra_id invalidate Queue2_BundleMap_214.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_214.io.deq.bits.tl_state.size node _T_1044 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1045 = and(_T_1044, awsel_98) connect Queue2_BundleMap_214.io.enq.valid, _T_1045 invalidate Queue2_BundleMap_214.io.enq.ready connect Queue2_BundleMap_214.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_214.io.count node _T_1046 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1047 = and(_T_1046, bsel_99) connect Queue2_BundleMap_215.io.deq.ready, _T_1047 invalidate Queue2_BundleMap_215.io.deq.valid invalidate Queue2_BundleMap_215.io.deq.bits.extra_id invalidate Queue2_BundleMap_215.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_215.io.deq.bits.tl_state.size node _T_1048 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1049 = and(_T_1048, awsel_99) connect Queue2_BundleMap_215.io.enq.valid, _T_1049 invalidate Queue2_BundleMap_215.io.enq.ready connect Queue2_BundleMap_215.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_215.io.count node _T_1050 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1051 = and(_T_1050, bsel_100) connect Queue2_BundleMap_216.io.deq.ready, _T_1051 invalidate Queue2_BundleMap_216.io.deq.valid invalidate Queue2_BundleMap_216.io.deq.bits.extra_id invalidate Queue2_BundleMap_216.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_216.io.deq.bits.tl_state.size node _T_1052 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1053 = and(_T_1052, awsel_100) connect Queue2_BundleMap_216.io.enq.valid, _T_1053 invalidate Queue2_BundleMap_216.io.enq.ready connect Queue2_BundleMap_216.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_216.io.count node _T_1054 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1055 = and(_T_1054, bsel_101) connect Queue2_BundleMap_217.io.deq.ready, _T_1055 invalidate Queue2_BundleMap_217.io.deq.valid invalidate Queue2_BundleMap_217.io.deq.bits.extra_id invalidate Queue2_BundleMap_217.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_217.io.deq.bits.tl_state.size node _T_1056 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1057 = and(_T_1056, awsel_101) connect Queue2_BundleMap_217.io.enq.valid, _T_1057 invalidate Queue2_BundleMap_217.io.enq.ready connect Queue2_BundleMap_217.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_217.io.count node _T_1058 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1059 = and(_T_1058, bsel_102) connect Queue2_BundleMap_218.io.deq.ready, _T_1059 invalidate Queue2_BundleMap_218.io.deq.valid invalidate Queue2_BundleMap_218.io.deq.bits.extra_id invalidate Queue2_BundleMap_218.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_218.io.deq.bits.tl_state.size node _T_1060 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1061 = and(_T_1060, awsel_102) connect Queue2_BundleMap_218.io.enq.valid, _T_1061 invalidate Queue2_BundleMap_218.io.enq.ready connect Queue2_BundleMap_218.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_218.io.count node _T_1062 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1063 = and(_T_1062, bsel_103) connect Queue2_BundleMap_219.io.deq.ready, _T_1063 invalidate Queue2_BundleMap_219.io.deq.valid invalidate Queue2_BundleMap_219.io.deq.bits.extra_id invalidate Queue2_BundleMap_219.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_219.io.deq.bits.tl_state.size node _T_1064 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1065 = and(_T_1064, awsel_103) connect Queue2_BundleMap_219.io.enq.valid, _T_1065 invalidate Queue2_BundleMap_219.io.enq.ready connect Queue2_BundleMap_219.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_219.io.count node _T_1066 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1067 = and(_T_1066, bsel_104) connect Queue2_BundleMap_220.io.deq.ready, _T_1067 invalidate Queue2_BundleMap_220.io.deq.valid invalidate Queue2_BundleMap_220.io.deq.bits.extra_id invalidate Queue2_BundleMap_220.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_220.io.deq.bits.tl_state.size node _T_1068 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1069 = and(_T_1068, awsel_104) connect Queue2_BundleMap_220.io.enq.valid, _T_1069 invalidate Queue2_BundleMap_220.io.enq.ready connect Queue2_BundleMap_220.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_220.io.count node _T_1070 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1071 = and(_T_1070, bsel_105) connect Queue2_BundleMap_221.io.deq.ready, _T_1071 invalidate Queue2_BundleMap_221.io.deq.valid invalidate Queue2_BundleMap_221.io.deq.bits.extra_id invalidate Queue2_BundleMap_221.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_221.io.deq.bits.tl_state.size node _T_1072 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1073 = and(_T_1072, awsel_105) connect Queue2_BundleMap_221.io.enq.valid, _T_1073 invalidate Queue2_BundleMap_221.io.enq.ready connect Queue2_BundleMap_221.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_221.io.count node _T_1074 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1075 = and(_T_1074, bsel_106) connect Queue2_BundleMap_222.io.deq.ready, _T_1075 invalidate Queue2_BundleMap_222.io.deq.valid invalidate Queue2_BundleMap_222.io.deq.bits.extra_id invalidate Queue2_BundleMap_222.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_222.io.deq.bits.tl_state.size node _T_1076 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1077 = and(_T_1076, awsel_106) connect Queue2_BundleMap_222.io.enq.valid, _T_1077 invalidate Queue2_BundleMap_222.io.enq.ready connect Queue2_BundleMap_222.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_222.io.count node _T_1078 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1079 = and(_T_1078, bsel_107) connect Queue2_BundleMap_223.io.deq.ready, _T_1079 invalidate Queue2_BundleMap_223.io.deq.valid invalidate Queue2_BundleMap_223.io.deq.bits.extra_id invalidate Queue2_BundleMap_223.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_223.io.deq.bits.tl_state.size node _T_1080 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1081 = and(_T_1080, awsel_107) connect Queue2_BundleMap_223.io.enq.valid, _T_1081 invalidate Queue2_BundleMap_223.io.enq.ready connect Queue2_BundleMap_223.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_223.io.count node _T_1082 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1083 = and(_T_1082, bsel_108) connect Queue2_BundleMap_224.io.deq.ready, _T_1083 invalidate Queue2_BundleMap_224.io.deq.valid invalidate Queue2_BundleMap_224.io.deq.bits.extra_id invalidate Queue2_BundleMap_224.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_224.io.deq.bits.tl_state.size node _T_1084 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1085 = and(_T_1084, awsel_108) connect Queue2_BundleMap_224.io.enq.valid, _T_1085 invalidate Queue2_BundleMap_224.io.enq.ready connect Queue2_BundleMap_224.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_224.io.count node _T_1086 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1087 = and(_T_1086, bsel_109) connect Queue2_BundleMap_225.io.deq.ready, _T_1087 invalidate Queue2_BundleMap_225.io.deq.valid invalidate Queue2_BundleMap_225.io.deq.bits.extra_id invalidate Queue2_BundleMap_225.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_225.io.deq.bits.tl_state.size node _T_1088 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1089 = and(_T_1088, awsel_109) connect Queue2_BundleMap_225.io.enq.valid, _T_1089 invalidate Queue2_BundleMap_225.io.enq.ready connect Queue2_BundleMap_225.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_225.io.count node _T_1090 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1091 = and(_T_1090, bsel_110) connect Queue2_BundleMap_226.io.deq.ready, _T_1091 invalidate Queue2_BundleMap_226.io.deq.valid invalidate Queue2_BundleMap_226.io.deq.bits.extra_id invalidate Queue2_BundleMap_226.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_226.io.deq.bits.tl_state.size node _T_1092 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1093 = and(_T_1092, awsel_110) connect Queue2_BundleMap_226.io.enq.valid, _T_1093 invalidate Queue2_BundleMap_226.io.enq.ready connect Queue2_BundleMap_226.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_226.io.count node _T_1094 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1095 = and(_T_1094, bsel_111) connect Queue2_BundleMap_227.io.deq.ready, _T_1095 invalidate Queue2_BundleMap_227.io.deq.valid invalidate Queue2_BundleMap_227.io.deq.bits.extra_id invalidate Queue2_BundleMap_227.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_227.io.deq.bits.tl_state.size node _T_1096 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1097 = and(_T_1096, awsel_111) connect Queue2_BundleMap_227.io.enq.valid, _T_1097 invalidate Queue2_BundleMap_227.io.enq.ready connect Queue2_BundleMap_227.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_227.io.count node _T_1098 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1099 = and(_T_1098, bsel_112) connect Queue2_BundleMap_228.io.deq.ready, _T_1099 invalidate Queue2_BundleMap_228.io.deq.valid invalidate Queue2_BundleMap_228.io.deq.bits.extra_id invalidate Queue2_BundleMap_228.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_228.io.deq.bits.tl_state.size node _T_1100 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1101 = and(_T_1100, awsel_112) connect Queue2_BundleMap_228.io.enq.valid, _T_1101 invalidate Queue2_BundleMap_228.io.enq.ready connect Queue2_BundleMap_228.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_228.io.count node _T_1102 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1103 = and(_T_1102, bsel_113) connect Queue2_BundleMap_229.io.deq.ready, _T_1103 invalidate Queue2_BundleMap_229.io.deq.valid invalidate Queue2_BundleMap_229.io.deq.bits.extra_id invalidate Queue2_BundleMap_229.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_229.io.deq.bits.tl_state.size node _T_1104 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1105 = and(_T_1104, awsel_113) connect Queue2_BundleMap_229.io.enq.valid, _T_1105 invalidate Queue2_BundleMap_229.io.enq.ready connect Queue2_BundleMap_229.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_229.io.count node _T_1106 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1107 = and(_T_1106, bsel_114) connect Queue2_BundleMap_230.io.deq.ready, _T_1107 invalidate Queue2_BundleMap_230.io.deq.valid invalidate Queue2_BundleMap_230.io.deq.bits.extra_id invalidate Queue2_BundleMap_230.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_230.io.deq.bits.tl_state.size node _T_1108 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1109 = and(_T_1108, awsel_114) connect Queue2_BundleMap_230.io.enq.valid, _T_1109 invalidate Queue2_BundleMap_230.io.enq.ready connect Queue2_BundleMap_230.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_230.io.count node _T_1110 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1111 = and(_T_1110, bsel_115) connect Queue2_BundleMap_231.io.deq.ready, _T_1111 invalidate Queue2_BundleMap_231.io.deq.valid invalidate Queue2_BundleMap_231.io.deq.bits.extra_id invalidate Queue2_BundleMap_231.io.deq.bits.tl_state.source invalidate Queue2_BundleMap_231.io.deq.bits.tl_state.size node _T_1112 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1113 = and(_T_1112, awsel_115) connect Queue2_BundleMap_231.io.enq.valid, _T_1113 invalidate Queue2_BundleMap_231.io.enq.ready connect Queue2_BundleMap_231.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue2_BundleMap_231.io.count node _T_1114 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1115 = and(_T_1114, bsel_116) connect Queue1_BundleMap_12.io.deq.ready, _T_1115 invalidate Queue1_BundleMap_12.io.deq.valid invalidate Queue1_BundleMap_12.io.deq.bits.extra_id invalidate Queue1_BundleMap_12.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_12.io.deq.bits.tl_state.size node _T_1116 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1117 = and(_T_1116, awsel_116) connect Queue1_BundleMap_12.io.enq.valid, _T_1117 invalidate Queue1_BundleMap_12.io.enq.ready connect Queue1_BundleMap_12.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_12.io.count node _T_1118 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1119 = and(_T_1118, bsel_117) connect Queue1_BundleMap_13.io.deq.ready, _T_1119 invalidate Queue1_BundleMap_13.io.deq.valid invalidate Queue1_BundleMap_13.io.deq.bits.extra_id invalidate Queue1_BundleMap_13.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_13.io.deq.bits.tl_state.size node _T_1120 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1121 = and(_T_1120, awsel_117) connect Queue1_BundleMap_13.io.enq.valid, _T_1121 invalidate Queue1_BundleMap_13.io.enq.ready connect Queue1_BundleMap_13.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_13.io.count node _T_1122 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1123 = and(_T_1122, bsel_118) connect Queue1_BundleMap_14.io.deq.ready, _T_1123 invalidate Queue1_BundleMap_14.io.deq.valid invalidate Queue1_BundleMap_14.io.deq.bits.extra_id invalidate Queue1_BundleMap_14.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_14.io.deq.bits.tl_state.size node _T_1124 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1125 = and(_T_1124, awsel_118) connect Queue1_BundleMap_14.io.enq.valid, _T_1125 invalidate Queue1_BundleMap_14.io.enq.ready connect Queue1_BundleMap_14.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_14.io.count node _T_1126 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1127 = and(_T_1126, bsel_119) connect Queue1_BundleMap_15.io.deq.ready, _T_1127 invalidate Queue1_BundleMap_15.io.deq.valid invalidate Queue1_BundleMap_15.io.deq.bits.extra_id invalidate Queue1_BundleMap_15.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_15.io.deq.bits.tl_state.size node _T_1128 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1129 = and(_T_1128, awsel_119) connect Queue1_BundleMap_15.io.enq.valid, _T_1129 invalidate Queue1_BundleMap_15.io.enq.ready connect Queue1_BundleMap_15.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_15.io.count node _T_1130 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1131 = and(_T_1130, bsel_120) connect Queue1_BundleMap_16.io.deq.ready, _T_1131 invalidate Queue1_BundleMap_16.io.deq.valid invalidate Queue1_BundleMap_16.io.deq.bits.extra_id invalidate Queue1_BundleMap_16.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_16.io.deq.bits.tl_state.size node _T_1132 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1133 = and(_T_1132, awsel_120) connect Queue1_BundleMap_16.io.enq.valid, _T_1133 invalidate Queue1_BundleMap_16.io.enq.ready connect Queue1_BundleMap_16.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_16.io.count node _T_1134 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1135 = and(_T_1134, bsel_121) connect Queue1_BundleMap_17.io.deq.ready, _T_1135 invalidate Queue1_BundleMap_17.io.deq.valid invalidate Queue1_BundleMap_17.io.deq.bits.extra_id invalidate Queue1_BundleMap_17.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_17.io.deq.bits.tl_state.size node _T_1136 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1137 = and(_T_1136, awsel_121) connect Queue1_BundleMap_17.io.enq.valid, _T_1137 invalidate Queue1_BundleMap_17.io.enq.ready connect Queue1_BundleMap_17.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_17.io.count node _T_1138 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1139 = and(_T_1138, bsel_122) connect Queue1_BundleMap_18.io.deq.ready, _T_1139 invalidate Queue1_BundleMap_18.io.deq.valid invalidate Queue1_BundleMap_18.io.deq.bits.extra_id invalidate Queue1_BundleMap_18.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_18.io.deq.bits.tl_state.size node _T_1140 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1141 = and(_T_1140, awsel_122) connect Queue1_BundleMap_18.io.enq.valid, _T_1141 invalidate Queue1_BundleMap_18.io.enq.ready connect Queue1_BundleMap_18.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_18.io.count node _T_1142 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1143 = and(_T_1142, bsel_123) connect Queue1_BundleMap_19.io.deq.ready, _T_1143 invalidate Queue1_BundleMap_19.io.deq.valid invalidate Queue1_BundleMap_19.io.deq.bits.extra_id invalidate Queue1_BundleMap_19.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_19.io.deq.bits.tl_state.size node _T_1144 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1145 = and(_T_1144, awsel_123) connect Queue1_BundleMap_19.io.enq.valid, _T_1145 invalidate Queue1_BundleMap_19.io.enq.ready connect Queue1_BundleMap_19.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_19.io.count node _T_1146 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1147 = and(_T_1146, bsel_124) connect Queue1_BundleMap_20.io.deq.ready, _T_1147 invalidate Queue1_BundleMap_20.io.deq.valid invalidate Queue1_BundleMap_20.io.deq.bits.extra_id invalidate Queue1_BundleMap_20.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_20.io.deq.bits.tl_state.size node _T_1148 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1149 = and(_T_1148, awsel_124) connect Queue1_BundleMap_20.io.enq.valid, _T_1149 invalidate Queue1_BundleMap_20.io.enq.ready connect Queue1_BundleMap_20.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_20.io.count node _T_1150 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1151 = and(_T_1150, bsel_125) connect Queue1_BundleMap_21.io.deq.ready, _T_1151 invalidate Queue1_BundleMap_21.io.deq.valid invalidate Queue1_BundleMap_21.io.deq.bits.extra_id invalidate Queue1_BundleMap_21.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_21.io.deq.bits.tl_state.size node _T_1152 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1153 = and(_T_1152, awsel_125) connect Queue1_BundleMap_21.io.enq.valid, _T_1153 invalidate Queue1_BundleMap_21.io.enq.ready connect Queue1_BundleMap_21.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_21.io.count node _T_1154 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1155 = and(_T_1154, bsel_126) connect Queue1_BundleMap_22.io.deq.ready, _T_1155 invalidate Queue1_BundleMap_22.io.deq.valid invalidate Queue1_BundleMap_22.io.deq.bits.extra_id invalidate Queue1_BundleMap_22.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_22.io.deq.bits.tl_state.size node _T_1156 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1157 = and(_T_1156, awsel_126) connect Queue1_BundleMap_22.io.enq.valid, _T_1157 invalidate Queue1_BundleMap_22.io.enq.ready connect Queue1_BundleMap_22.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_22.io.count node _T_1158 = and(nodeOut.b.valid, nodeIn.b.ready) node _T_1159 = and(_T_1158, bsel_127) connect Queue1_BundleMap_23.io.deq.ready, _T_1159 invalidate Queue1_BundleMap_23.io.deq.valid invalidate Queue1_BundleMap_23.io.deq.bits.extra_id invalidate Queue1_BundleMap_23.io.deq.bits.tl_state.source invalidate Queue1_BundleMap_23.io.deq.bits.tl_state.size node _T_1160 = and(nodeIn.aw.valid, nodeOut.aw.ready) node _T_1161 = and(_T_1160, awsel_127) connect Queue1_BundleMap_23.io.enq.valid, _T_1161 invalidate Queue1_BundleMap_23.io.enq.ready connect Queue1_BundleMap_23.io.enq.bits, nodeIn.aw.bits.echo invalidate Queue1_BundleMap_23.io.count connect nodeOut.w, nodeIn.w	module AXI4UserYanker_2( // @[UserYanker.scala:36:9] input clock, // @[UserYanker.scala:36:9] input reset, // @[UserYanker.scala:36:9] output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25] input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_w_ready, // @[LazyModuleImp.scala:107:25] input auto_in_w_valid, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25] input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25] input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_in_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] input auto_in_r_ready, // @[LazyModuleImp.scala:107:25] output auto_in_r_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25] output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[UserYanker.scala:36:9] wire [6:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[UserYanker.scala:36:9] wire [31:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[UserYanker.scala:36:9] wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[UserYanker.scala:36:9] wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[UserYanker.scala:36:9] wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[UserYanker.scala:36:9] wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[UserYanker.scala:36:9] wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[UserYanker.scala:36:9] wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[UserYanker.scala:36:9] wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[UserYanker.scala:36:9] wire [3:0] auto_in_aw_bits_echo_tl_state_size_0 = auto_in_aw_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] wire [7:0] auto_in_aw_bits_echo_tl_state_source_0 = auto_in_aw_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] wire auto_in_aw_bits_echo_extra_id_0 = auto_in_aw_bits_echo_extra_id; // @[UserYanker.scala:36:9] wire auto_in_w_valid_0 = auto_in_w_valid; // @[UserYanker.scala:36:9] wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[UserYanker.scala:36:9] wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[UserYanker.scala:36:9] wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[UserYanker.scala:36:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[UserYanker.scala:36:9] wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[UserYanker.scala:36:9] wire [6:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[UserYanker.scala:36:9] wire [31:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[UserYanker.scala:36:9] wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[UserYanker.scala:36:9] wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[UserYanker.scala:36:9] wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[UserYanker.scala:36:9] wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[UserYanker.scala:36:9] wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[UserYanker.scala:36:9] wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[UserYanker.scala:36:9] wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[UserYanker.scala:36:9] wire [3:0] auto_in_ar_bits_echo_tl_state_size_0 = auto_in_ar_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] wire [7:0] auto_in_ar_bits_echo_tl_state_source_0 = auto_in_ar_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] wire auto_in_ar_bits_echo_extra_id_0 = auto_in_ar_bits_echo_extra_id; // @[UserYanker.scala:36:9] wire auto_in_r_ready_0 = auto_in_r_ready; // @[UserYanker.scala:36:9] wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[UserYanker.scala:36:9] wire auto_out_w_ready_0 = auto_out_w_ready; // @[UserYanker.scala:36:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[UserYanker.scala:36:9] wire [6:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[UserYanker.scala:36:9] wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[UserYanker.scala:36:9] wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[UserYanker.scala:36:9] wire auto_out_r_valid_0 = auto_out_r_valid; // @[UserYanker.scala:36:9] wire [6:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[UserYanker.scala:36:9] wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[UserYanker.scala:36:9] wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[UserYanker.scala:36:9] wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[UserYanker.scala:36:9] wire nodeIn_aw_ready; // @[MixedNode.scala:551:17] wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[UserYanker.scala:36:9] wire [6:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[UserYanker.scala:36:9] wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_aw_bits_echo_tl_state_size = auto_in_aw_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_aw_bits_echo_tl_state_source = auto_in_aw_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire nodeIn_aw_bits_echo_extra_id = auto_in_aw_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire nodeIn_w_ready; // @[MixedNode.scala:551:17] wire nodeIn_w_valid = auto_in_w_valid_0; // @[UserYanker.scala:36:9] wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[UserYanker.scala:36:9] wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[UserYanker.scala:36:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[UserYanker.scala:36:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_echo_extra_id; // @[MixedNode.scala:551:17] wire nodeIn_ar_ready; // @[MixedNode.scala:551:17] wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[UserYanker.scala:36:9] wire [6:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[UserYanker.scala:36:9] wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[UserYanker.scala:36:9] wire [3:0] nodeIn_ar_bits_echo_tl_state_size = auto_in_ar_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [7:0] nodeIn_ar_bits_echo_tl_state_source = auto_in_ar_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire nodeIn_ar_bits_echo_extra_id = auto_in_ar_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire nodeIn_r_ready = auto_in_r_ready_0; // @[UserYanker.scala:36:9] wire nodeIn_r_valid; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_r_bits_echo_tl_state_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_r_bits_echo_tl_state_source; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_echo_extra_id; // @[MixedNode.scala:551:17] wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17] wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[UserYanker.scala:36:9] wire nodeOut_aw_valid; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17] wire nodeOut_w_ready = auto_out_w_ready_0; // @[UserYanker.scala:36:9] wire nodeOut_w_valid; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17] wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[UserYanker.scala:36:9] wire [6:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[UserYanker.scala:36:9] wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[UserYanker.scala:36:9] wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[UserYanker.scala:36:9] wire nodeOut_ar_valid; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17] wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17] wire nodeOut_r_ready; // @[MixedNode.scala:542:17] wire nodeOut_r_valid = auto_out_r_valid_0; // @[UserYanker.scala:36:9] wire [6:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[UserYanker.scala:36:9] wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[UserYanker.scala:36:9] wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[UserYanker.scala:36:9] wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[UserYanker.scala:36:9] wire auto_in_aw_ready_0; // @[UserYanker.scala:36:9] wire auto_in_w_ready_0; // @[UserYanker.scala:36:9] wire [3:0] auto_in_b_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [7:0] auto_in_b_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire auto_in_b_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire [6:0] auto_in_b_bits_id_0; // @[UserYanker.scala:36:9] wire [1:0] auto_in_b_bits_resp_0; // @[UserYanker.scala:36:9] wire auto_in_b_valid_0; // @[UserYanker.scala:36:9] wire auto_in_ar_ready_0; // @[UserYanker.scala:36:9] wire [3:0] auto_in_r_bits_echo_tl_state_size_0; // @[UserYanker.scala:36:9] wire [7:0] auto_in_r_bits_echo_tl_state_source_0; // @[UserYanker.scala:36:9] wire auto_in_r_bits_echo_extra_id_0; // @[UserYanker.scala:36:9] wire [6:0] auto_in_r_bits_id_0; // @[UserYanker.scala:36:9] wire [63:0] auto_in_r_bits_data_0; // @[UserYanker.scala:36:9] wire [1:0] auto_in_r_bits_resp_0; // @[UserYanker.scala:36:9] wire auto_in_r_bits_last_0; // @[UserYanker.scala:36:9] wire auto_in_r_valid_0; // @[UserYanker.scala:36:9] wire [6:0] auto_out_aw_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] auto_out_aw_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] auto_out_aw_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_aw_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] auto_out_aw_bits_burst_0; // @[UserYanker.scala:36:9] wire auto_out_aw_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_aw_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_aw_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_aw_bits_qos_0; // @[UserYanker.scala:36:9] wire auto_out_aw_valid_0; // @[UserYanker.scala:36:9] wire [63:0] auto_out_w_bits_data_0; // @[UserYanker.scala:36:9] wire [7:0] auto_out_w_bits_strb_0; // @[UserYanker.scala:36:9] wire auto_out_w_bits_last_0; // @[UserYanker.scala:36:9] wire auto_out_w_valid_0; // @[UserYanker.scala:36:9] wire auto_out_b_ready_0; // @[UserYanker.scala:36:9] wire [6:0] auto_out_ar_bits_id_0; // @[UserYanker.scala:36:9] wire [31:0] auto_out_ar_bits_addr_0; // @[UserYanker.scala:36:9] wire [7:0] auto_out_ar_bits_len_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_ar_bits_size_0; // @[UserYanker.scala:36:9] wire [1:0] auto_out_ar_bits_burst_0; // @[UserYanker.scala:36:9] wire auto_out_ar_bits_lock_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_ar_bits_cache_0; // @[UserYanker.scala:36:9] wire [2:0] auto_out_ar_bits_prot_0; // @[UserYanker.scala:36:9] wire [3:0] auto_out_ar_bits_qos_0; // @[UserYanker.scala:36:9] wire auto_out_ar_valid_0; // @[UserYanker.scala:36:9] wire auto_out_r_ready_0; // @[UserYanker.scala:36:9] wire _nodeIn_aw_ready_T; // @[UserYanker.scala:89:36] assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[UserYanker.scala:36:9] assign nodeOut_aw_bits_id = nodeIn_aw_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [6:0] awsel_shiftAmount = nodeIn_aw_bits_id; // @[OneHot.scala:64:49] assign nodeOut_aw_bits_addr = nodeIn_aw_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_len = nodeIn_aw_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_size = nodeIn_aw_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_burst = nodeIn_aw_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_lock = nodeIn_aw_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_cache = nodeIn_aw_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_prot = nodeIn_aw_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_aw_bits_qos = nodeIn_aw_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign auto_in_w_ready_0 = nodeIn_w_ready; // @[UserYanker.scala:36:9] assign nodeOut_w_valid = nodeIn_w_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_data = nodeIn_w_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_strb = nodeIn_w_bits_strb; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_w_bits_last = nodeIn_w_bits_last; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_b_ready = nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[UserYanker.scala:36:9] assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[UserYanker.scala:36:9] assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[UserYanker.scala:36:9] assign auto_in_b_bits_echo_tl_state_size_0 = nodeIn_b_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] assign auto_in_b_bits_echo_tl_state_source_0 = nodeIn_b_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] assign auto_in_b_bits_echo_extra_id_0 = nodeIn_b_bits_echo_extra_id; // @[UserYanker.scala:36:9] wire _nodeIn_ar_ready_T; // @[UserYanker.scala:60:36] assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[UserYanker.scala:36:9] assign nodeOut_ar_bits_id = nodeIn_ar_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [6:0] arsel_shiftAmount = nodeIn_ar_bits_id; // @[OneHot.scala:64:49] assign nodeOut_ar_bits_addr = nodeIn_ar_bits_addr; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_len = nodeIn_ar_bits_len; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_size = nodeIn_ar_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_burst = nodeIn_ar_bits_burst; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_lock = nodeIn_ar_bits_lock; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_cache = nodeIn_ar_bits_cache; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_prot = nodeIn_ar_bits_prot; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_ar_bits_qos = nodeIn_ar_bits_qos; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_r_valid_0 = nodeIn_r_valid; // @[UserYanker.scala:36:9] assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[UserYanker.scala:36:9] assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[UserYanker.scala:36:9] assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[UserYanker.scala:36:9] assign auto_in_r_bits_echo_tl_state_size_0 = nodeIn_r_bits_echo_tl_state_size; // @[UserYanker.scala:36:9] assign auto_in_r_bits_echo_tl_state_source_0 = nodeIn_r_bits_echo_tl_state_source; // @[UserYanker.scala:36:9] assign auto_in_r_bits_echo_extra_id_0 = nodeIn_r_bits_echo_extra_id; // @[UserYanker.scala:36:9] assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[UserYanker.scala:36:9] wire _nodeOut_aw_valid_T; // @[UserYanker.scala:90:36] assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[UserYanker.scala:36:9] assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[UserYanker.scala:36:9] assign nodeIn_w_ready = nodeOut_w_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_w_valid_0 = nodeOut_w_valid; // @[UserYanker.scala:36:9] assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[UserYanker.scala:36:9] assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[UserYanker.scala:36:9] assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[UserYanker.scala:36:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[UserYanker.scala:36:9] assign nodeIn_b_valid = nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_b_bits_id = nodeOut_b_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [6:0] bsel_shiftAmount = nodeOut_b_bits_id; // @[OneHot.scala:64:49] assign nodeIn_b_bits_resp = nodeOut_b_bits_resp; // @[MixedNode.scala:542:17, :551:17] wire _nodeOut_ar_valid_T; // @[UserYanker.scala:61:36] assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[UserYanker.scala:36:9] assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[UserYanker.scala:36:9] assign auto_out_r_ready_0 = nodeOut_r_ready; // @[UserYanker.scala:36:9] assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_id = nodeOut_r_bits_id; // @[MixedNode.scala:542:17, :551:17] wire [6:0] rsel_shiftAmount = nodeOut_r_bits_id; // @[OneHot.scala:64:49] assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_r_bits_last = nodeOut_r_bits_last; // @[MixedNode.scala:542:17, :551:17] wire _ar_ready_WIRE_0; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_1; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_2; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_3; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_4; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_5; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_6; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_7; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_8; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_9; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_10; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_11; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_12; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_13; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_14; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_15; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_16; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_17; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_18; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_19; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_20; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_21; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_22; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_23; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_24; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_25; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_26; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_27; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_28; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_29; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_30; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_31; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_32; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_33; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_34; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_35; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_36; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_37; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_38; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_39; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_40; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_41; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_42; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_43; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_44; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_45; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_46; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_47; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_48; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_49; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_50; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_51; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_52; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_53; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_54; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_55; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_56; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_57; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_58; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_59; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_60; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_61; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_62; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_63; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_64; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_65; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_66; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_67; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_68; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_69; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_70; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_71; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_72; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_73; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_74; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_75; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_76; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_77; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_78; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_79; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_80; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_81; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_82; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_83; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_84; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_85; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_86; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_87; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_88; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_89; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_90; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_91; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_92; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_93; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_94; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_95; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_96; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_97; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_98; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_99; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_100; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_101; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_102; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_103; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_104; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_105; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_106; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_107; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_108; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_109; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_110; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_111; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_112; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_113; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_114; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_115; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_116; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_117; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_118; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_119; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_120; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_121; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_122; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_123; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_124; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_125; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_126; // @[UserYanker.scala:59:29] wire _ar_ready_WIRE_127; // @[UserYanker.scala:59:29] wire [127:0] _GEN = {{_ar_ready_WIRE_127}, {_ar_ready_WIRE_126}, {_ar_ready_WIRE_125}, {_ar_ready_WIRE_124}, {_ar_ready_WIRE_123}, {_ar_ready_WIRE_122}, {_ar_ready_WIRE_121}, {_ar_ready_WIRE_120}, {_ar_ready_WIRE_119}, {_ar_ready_WIRE_118}, {_ar_ready_WIRE_117}, {_ar_ready_WIRE_116}, {_ar_ready_WIRE_115}, {_ar_ready_WIRE_114}, {_ar_ready_WIRE_113}, {_ar_ready_WIRE_112}, {_ar_ready_WIRE_111}, {_ar_ready_WIRE_110}, {_ar_ready_WIRE_109}, {_ar_ready_WIRE_108}, {_ar_ready_WIRE_107}, {_ar_ready_WIRE_106}, {_ar_ready_WIRE_105}, {_ar_ready_WIRE_104}, {_ar_ready_WIRE_103}, {_ar_ready_WIRE_102}, {_ar_ready_WIRE_101}, {_ar_ready_WIRE_100}, {_ar_ready_WIRE_99}, {_ar_ready_WIRE_98}, {_ar_ready_WIRE_97}, {_ar_ready_WIRE_96}, {_ar_ready_WIRE_95}, {_ar_ready_WIRE_94}, {_ar_ready_WIRE_93}, {_ar_ready_WIRE_92}, {_ar_ready_WIRE_91}, {_ar_ready_WIRE_90}, {_ar_ready_WIRE_89}, {_ar_ready_WIRE_88}, {_ar_ready_WIRE_87}, {_ar_ready_WIRE_86}, {_ar_ready_WIRE_85}, {_ar_ready_WIRE_84}, {_ar_ready_WIRE_83}, {_ar_ready_WIRE_82}, {_ar_ready_WIRE_81}, {_ar_ready_WIRE_80}, {_ar_ready_WIRE_79}, {_ar_ready_WIRE_78}, {_ar_ready_WIRE_77}, {_ar_ready_WIRE_76}, {_ar_ready_WIRE_75}, {_ar_ready_WIRE_74}, {_ar_ready_WIRE_73}, {_ar_ready_WIRE_72}, {_ar_ready_WIRE_71}, {_ar_ready_WIRE_70}, {_ar_ready_WIRE_69}, {_ar_ready_WIRE_68}, {_ar_ready_WIRE_67}, {_ar_ready_WIRE_66}, {_ar_ready_WIRE_65}, {_ar_ready_WIRE_64}, {_ar_ready_WIRE_63}, {_ar_ready_WIRE_62}, {_ar_ready_WIRE_61}, {_ar_ready_WIRE_60}, {_ar_ready_WIRE_59}, {_ar_ready_WIRE_58}, {_ar_ready_WIRE_57}, {_ar_ready_WIRE_56}, {_ar_ready_WIRE_55}, {_ar_ready_WIRE_54}, {_ar_ready_WIRE_53}, {_ar_ready_WIRE_52}, {_ar_ready_WIRE_51}, {_ar_ready_WIRE_50}, {_ar_ready_WIRE_49}, {_ar_ready_WIRE_48}, {_ar_ready_WIRE_47}, {_ar_ready_WIRE_46}, {_ar_ready_WIRE_45}, {_ar_ready_WIRE_44}, {_ar_ready_WIRE_43}, {_ar_ready_WIRE_42}, {_ar_ready_WIRE_41}, {_ar_ready_WIRE_40}, {_ar_ready_WIRE_39}, {_ar_ready_WIRE_38}, {_ar_ready_WIRE_37}, {_ar_ready_WIRE_36}, {_ar_ready_WIRE_35}, {_ar_ready_WIRE_34}, {_ar_ready_WIRE_33}, {_ar_ready_WIRE_32}, {_ar_ready_WIRE_31}, {_ar_ready_WIRE_30}, {_ar_ready_WIRE_29}, {_ar_ready_WIRE_28}, {_ar_ready_WIRE_27}, {_ar_ready_WIRE_26}, {_ar_ready_WIRE_25}, {_ar_ready_WIRE_24}, {_ar_ready_WIRE_23}, {_ar_ready_WIRE_22}, {_ar_ready_WIRE_21}, {_ar_ready_WIRE_20}, {_ar_ready_WIRE_19}, {_ar_ready_WIRE_18}, {_ar_ready_WIRE_17}, {_ar_ready_WIRE_16}, {_ar_ready_WIRE_15}, {_ar_ready_WIRE_14}, {_ar_ready_WIRE_13}, {_ar_ready_WIRE_12}, {_ar_ready_WIRE_11}, {_ar_ready_WIRE_10}, {_ar_ready_WIRE_9}, {_ar_ready_WIRE_8}, {_ar_ready_WIRE_7}, {_ar_ready_WIRE_6}, {_ar_ready_WIRE_5}, {_ar_ready_WIRE_4}, {_ar_ready_WIRE_3}, {_ar_ready_WIRE_2}, {_ar_ready_WIRE_1}, {_ar_ready_WIRE_0}}; // @[UserYanker.scala:59:29, :60:36] assign _nodeIn_ar_ready_T = nodeOut_ar_ready & _GEN[nodeIn_ar_bits_id]; // @[UserYanker.scala:60:36] assign nodeIn_ar_ready = _nodeIn_ar_ready_T; // @[UserYanker.scala:60:36] assign _nodeOut_ar_valid_T = nodeIn_ar_valid & _GEN[nodeIn_ar_bits_id]; // @[UserYanker.scala:60:36, :61:36] assign nodeOut_ar_valid = _nodeOut_ar_valid_T; // @[UserYanker.scala:61:36] wire [3:0] _r_bits_WIRE_0_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_1_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_2_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_3_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_4_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_5_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_6_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_7_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_8_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_9_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_10_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_11_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_12_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_13_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_14_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_15_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_16_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_17_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_18_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_19_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_20_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_21_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_22_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_23_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_24_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_25_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_26_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_27_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_28_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_29_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_30_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_31_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_32_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_33_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_34_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_35_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_36_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_37_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_38_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_39_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_40_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_41_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_42_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_43_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_44_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_45_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_46_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_47_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_48_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_49_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_50_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_51_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_52_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_53_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_54_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_55_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_56_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_57_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_58_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_59_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_60_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_61_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_62_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_63_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_64_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_65_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_66_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_67_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_68_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_69_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_70_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_71_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_72_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_73_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_74_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_75_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_76_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_77_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_78_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_79_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_80_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_81_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_82_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_83_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_84_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_85_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_86_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_87_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_88_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_89_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_90_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_91_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_92_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_93_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_94_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_95_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_96_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_97_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_98_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_99_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_100_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_101_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_102_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_103_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_104_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_105_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_106_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_107_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_108_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_109_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_110_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_111_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_112_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_113_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_114_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_115_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_116_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_117_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_118_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_119_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_120_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_121_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_122_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_123_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_124_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_125_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_126_tl_state_size; // @[UserYanker.scala:68:27] wire [3:0] _r_bits_WIRE_127_tl_state_size; // @[UserYanker.scala:68:27] wire [127:0][3:0] _GEN_0 = {{_r_bits_WIRE_127_tl_state_size}, {_r_bits_WIRE_126_tl_state_size}, {_r_bits_WIRE_125_tl_state_size}, {_r_bits_WIRE_124_tl_state_size}, {_r_bits_WIRE_123_tl_state_size}, {_r_bits_WIRE_122_tl_state_size}, {_r_bits_WIRE_121_tl_state_size}, {_r_bits_WIRE_120_tl_state_size}, {_r_bits_WIRE_119_tl_state_size}, {_r_bits_WIRE_118_tl_state_size}, {_r_bits_WIRE_117_tl_state_size}, {_r_bits_WIRE_116_tl_state_size}, {_r_bits_WIRE_115_tl_state_size}, {_r_bits_WIRE_114_tl_state_size}, {_r_bits_WIRE_113_tl_state_size}, {_r_bits_WIRE_112_tl_state_size}, {_r_bits_WIRE_111_tl_state_size}, {_r_bits_WIRE_110_tl_state_size}, {_r_bits_WIRE_109_tl_state_size}, {_r_bits_WIRE_108_tl_state_size}, {_r_bits_WIRE_107_tl_state_size}, {_r_bits_WIRE_106_tl_state_size}, {_r_bits_WIRE_105_tl_state_size}, {_r_bits_WIRE_104_tl_state_size}, {_r_bits_WIRE_103_tl_state_size}, {_r_bits_WIRE_102_tl_state_size}, {_r_bits_WIRE_101_tl_state_size}, {_r_bits_WIRE_100_tl_state_size}, {_r_bits_WIRE_99_tl_state_size}, {_r_bits_WIRE_98_tl_state_size}, {_r_bits_WIRE_97_tl_state_size}, {_r_bits_WIRE_96_tl_state_size}, {_r_bits_WIRE_95_tl_state_size}, {_r_bits_WIRE_94_tl_state_size}, {_r_bits_WIRE_93_tl_state_size}, {_r_bits_WIRE_92_tl_state_size}, {_r_bits_WIRE_91_tl_state_size}, {_r_bits_WIRE_90_tl_state_size}, {_r_bits_WIRE_89_tl_state_size}, {_r_bits_WIRE_88_tl_state_size}, {_r_bits_WIRE_87_tl_state_size}, {_r_bits_WIRE_86_tl_state_size}, {_r_bits_WIRE_85_tl_state_size}, {_r_bits_WIRE_84_tl_state_size}, {_r_bits_WIRE_83_tl_state_size}, {_r_bits_WIRE_82_tl_state_size}, {_r_bits_WIRE_81_tl_state_size}, {_r_bits_WIRE_80_tl_state_size}, {_r_bits_WIRE_79_tl_state_size}, {_r_bits_WIRE_78_tl_state_size}, {_r_bits_WIRE_77_tl_state_size}, {_r_bits_WIRE_76_tl_state_size}, {_r_bits_WIRE_75_tl_state_size}, {_r_bits_WIRE_74_tl_state_size}, {_r_bits_WIRE_73_tl_state_size}, {_r_bits_WIRE_72_tl_state_size}, {_r_bits_WIRE_71_tl_state_size}, {_r_bits_WIRE_70_tl_state_size}, {_r_bits_WIRE_69_tl_state_size}, {_r_bits_WIRE_68_tl_state_size}, {_r_bits_WIRE_67_tl_state_size}, {_r_bits_WIRE_66_tl_state_size}, {_r_bits_WIRE_65_tl_state_size}, {_r_bits_WIRE_64_tl_state_size}, {_r_bits_WIRE_63_tl_state_size}, {_r_bits_WIRE_62_tl_state_size}, {_r_bits_WIRE_61_tl_state_size}, {_r_bits_WIRE_60_tl_state_size}, {_r_bits_WIRE_59_tl_state_size}, {_r_bits_WIRE_58_tl_state_size}, {_r_bits_WIRE_57_tl_state_size}, {_r_bits_WIRE_56_tl_state_size}, {_r_bits_WIRE_55_tl_state_size}, {_r_bits_WIRE_54_tl_state_size}, {_r_bits_WIRE_53_tl_state_size}, {_r_bits_WIRE_52_tl_state_size}, {_r_bits_WIRE_51_tl_state_size}, {_r_bits_WIRE_50_tl_state_size}, {_r_bits_WIRE_49_tl_state_size}, {_r_bits_WIRE_48_tl_state_size}, {_r_bits_WIRE_47_tl_state_size}, {_r_bits_WIRE_46_tl_state_size}, {_r_bits_WIRE_45_tl_state_size}, {_r_bits_WIRE_44_tl_state_size}, {_r_bits_WIRE_43_tl_state_size}, {_r_bits_WIRE_42_tl_state_size}, {_r_bits_WIRE_41_tl_state_size}, {_r_bits_WIRE_40_tl_state_size}, {_r_bits_WIRE_39_tl_state_size}, {_r_bits_WIRE_38_tl_state_size}, {_r_bits_WIRE_37_tl_state_size}, {_r_bits_WIRE_36_tl_state_size}, {_r_bits_WIRE_35_tl_state_size}, {_r_bits_WIRE_34_tl_state_size}, {_r_bits_WIRE_33_tl_state_size}, {_r_bits_WIRE_32_tl_state_size}, {_r_bits_WIRE_31_tl_state_size}, {_r_bits_WIRE_30_tl_state_size}, {_r_bits_WIRE_29_tl_state_size}, {_r_bits_WIRE_28_tl_state_size}, {_r_bits_WIRE_27_tl_state_size}, {_r_bits_WIRE_26_tl_state_size}, {_r_bits_WIRE_25_tl_state_size}, {_r_bits_WIRE_24_tl_state_size}, {_r_bits_WIRE_23_tl_state_size}, {_r_bits_WIRE_22_tl_state_size}, {_r_bits_WIRE_21_tl_state_size}, {_r_bits_WIRE_20_tl_state_size}, {_r_bits_WIRE_19_tl_state_size}, {_r_bits_WIRE_18_tl_state_size}, {_r_bits_WIRE_17_tl_state_size}, {_r_bits_WIRE_16_tl_state_size}, {_r_bits_WIRE_15_tl_state_size}, {_r_bits_WIRE_14_tl_state_size}, {_r_bits_WIRE_13_tl_state_size}, {_r_bits_WIRE_12_tl_state_size}, {_r_bits_WIRE_11_tl_state_size}, {_r_bits_WIRE_10_tl_state_size}, {_r_bits_WIRE_9_tl_state_size}, {_r_bits_WIRE_8_tl_state_size}, {_r_bits_WIRE_7_tl_state_size}, {_r_bits_WIRE_6_tl_state_size}, {_r_bits_WIRE_5_tl_state_size}, {_r_bits_WIRE_4_tl_state_size}, {_r_bits_WIRE_3_tl_state_size}, {_r_bits_WIRE_2_tl_state_size}, {_r_bits_WIRE_1_tl_state_size}, {_r_bits_WIRE_0_tl_state_size}}; // @[UserYanker.scala:68:27, :73:22] assign nodeIn_r_bits_echo_tl_state_size = _GEN_0[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22] wire [7:0] _r_bits_WIRE_0_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_1_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_2_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_3_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_4_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_5_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_6_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_7_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_8_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_9_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_10_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_11_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_12_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_13_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_14_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_15_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_16_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_17_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_18_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_19_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_20_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_21_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_22_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_23_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_24_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_25_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_26_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_27_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_28_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_29_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_30_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_31_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_32_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_33_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_34_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_35_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_36_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_37_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_38_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_39_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_40_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_41_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_42_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_43_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_44_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_45_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_46_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_47_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_48_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_49_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_50_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_51_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_52_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_53_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_54_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_55_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_56_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_57_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_58_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_59_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_60_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_61_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_62_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_63_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_64_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_65_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_66_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_67_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_68_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_69_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_70_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_71_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_72_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_73_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_74_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_75_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_76_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_77_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_78_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_79_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_80_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_81_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_82_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_83_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_84_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_85_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_86_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_87_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_88_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_89_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_90_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_91_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_92_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_93_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_94_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_95_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_96_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_97_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_98_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_99_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_100_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_101_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_102_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_103_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_104_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_105_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_106_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_107_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_108_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_109_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_110_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_111_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_112_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_113_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_114_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_115_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_116_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_117_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_118_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_119_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_120_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_121_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_122_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_123_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_124_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_125_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_126_tl_state_source; // @[UserYanker.scala:68:27] wire [7:0] _r_bits_WIRE_127_tl_state_source; // @[UserYanker.scala:68:27] wire [127:0][7:0] _GEN_1 = {{_r_bits_WIRE_127_tl_state_source}, {_r_bits_WIRE_126_tl_state_source}, {_r_bits_WIRE_125_tl_state_source}, {_r_bits_WIRE_124_tl_state_source}, {_r_bits_WIRE_123_tl_state_source}, {_r_bits_WIRE_122_tl_state_source}, {_r_bits_WIRE_121_tl_state_source}, {_r_bits_WIRE_120_tl_state_source}, {_r_bits_WIRE_119_tl_state_source}, {_r_bits_WIRE_118_tl_state_source}, {_r_bits_WIRE_117_tl_state_source}, {_r_bits_WIRE_116_tl_state_source}, {_r_bits_WIRE_115_tl_state_source}, {_r_bits_WIRE_114_tl_state_source}, {_r_bits_WIRE_113_tl_state_source}, {_r_bits_WIRE_112_tl_state_source}, {_r_bits_WIRE_111_tl_state_source}, {_r_bits_WIRE_110_tl_state_source}, {_r_bits_WIRE_109_tl_state_source}, {_r_bits_WIRE_108_tl_state_source}, {_r_bits_WIRE_107_tl_state_source}, {_r_bits_WIRE_106_tl_state_source}, {_r_bits_WIRE_105_tl_state_source}, {_r_bits_WIRE_104_tl_state_source}, {_r_bits_WIRE_103_tl_state_source}, {_r_bits_WIRE_102_tl_state_source}, {_r_bits_WIRE_101_tl_state_source}, {_r_bits_WIRE_100_tl_state_source}, {_r_bits_WIRE_99_tl_state_source}, {_r_bits_WIRE_98_tl_state_source}, {_r_bits_WIRE_97_tl_state_source}, {_r_bits_WIRE_96_tl_state_source}, {_r_bits_WIRE_95_tl_state_source}, {_r_bits_WIRE_94_tl_state_source}, {_r_bits_WIRE_93_tl_state_source}, {_r_bits_WIRE_92_tl_state_source}, {_r_bits_WIRE_91_tl_state_source}, {_r_bits_WIRE_90_tl_state_source}, {_r_bits_WIRE_89_tl_state_source}, {_r_bits_WIRE_88_tl_state_source}, {_r_bits_WIRE_87_tl_state_source}, {_r_bits_WIRE_86_tl_state_source}, {_r_bits_WIRE_85_tl_state_source}, {_r_bits_WIRE_84_tl_state_source}, {_r_bits_WIRE_83_tl_state_source}, {_r_bits_WIRE_82_tl_state_source}, {_r_bits_WIRE_81_tl_state_source}, {_r_bits_WIRE_80_tl_state_source}, {_r_bits_WIRE_79_tl_state_source}, {_r_bits_WIRE_78_tl_state_source}, {_r_bits_WIRE_77_tl_state_source}, {_r_bits_WIRE_76_tl_state_source}, {_r_bits_WIRE_75_tl_state_source}, {_r_bits_WIRE_74_tl_state_source}, {_r_bits_WIRE_73_tl_state_source}, {_r_bits_WIRE_72_tl_state_source}, {_r_bits_WIRE_71_tl_state_source}, {_r_bits_WIRE_70_tl_state_source}, {_r_bits_WIRE_69_tl_state_source}, {_r_bits_WIRE_68_tl_state_source}, {_r_bits_WIRE_67_tl_state_source}, {_r_bits_WIRE_66_tl_state_source}, {_r_bits_WIRE_65_tl_state_source}, {_r_bits_WIRE_64_tl_state_source}, {_r_bits_WIRE_63_tl_state_source}, {_r_bits_WIRE_62_tl_state_source}, {_r_bits_WIRE_61_tl_state_source}, {_r_bits_WIRE_60_tl_state_source}, {_r_bits_WIRE_59_tl_state_source}, {_r_bits_WIRE_58_tl_state_source}, {_r_bits_WIRE_57_tl_state_source}, {_r_bits_WIRE_56_tl_state_source}, {_r_bits_WIRE_55_tl_state_source}, {_r_bits_WIRE_54_tl_state_source}, {_r_bits_WIRE_53_tl_state_source}, {_r_bits_WIRE_52_tl_state_source}, {_r_bits_WIRE_51_tl_state_source}, {_r_bits_WIRE_50_tl_state_source}, {_r_bits_WIRE_49_tl_state_source}, {_r_bits_WIRE_48_tl_state_source}, {_r_bits_WIRE_47_tl_state_source}, {_r_bits_WIRE_46_tl_state_source}, {_r_bits_WIRE_45_tl_state_source}, {_r_bits_WIRE_44_tl_state_source}, {_r_bits_WIRE_43_tl_state_source}, {_r_bits_WIRE_42_tl_state_source}, {_r_bits_WIRE_41_tl_state_source}, {_r_bits_WIRE_40_tl_state_source}, {_r_bits_WIRE_39_tl_state_source}, {_r_bits_WIRE_38_tl_state_source}, {_r_bits_WIRE_37_tl_state_source}, {_r_bits_WIRE_36_tl_state_source}, {_r_bits_WIRE_35_tl_state_source}, {_r_bits_WIRE_34_tl_state_source}, {_r_bits_WIRE_33_tl_state_source}, {_r_bits_WIRE_32_tl_state_source}, {_r_bits_WIRE_31_tl_state_source}, {_r_bits_WIRE_30_tl_state_source}, {_r_bits_WIRE_29_tl_state_source}, {_r_bits_WIRE_28_tl_state_source}, {_r_bits_WIRE_27_tl_state_source}, {_r_bits_WIRE_26_tl_state_source}, {_r_bits_WIRE_25_tl_state_source}, {_r_bits_WIRE_24_tl_state_source}, {_r_bits_WIRE_23_tl_state_source}, {_r_bits_WIRE_22_tl_state_source}, {_r_bits_WIRE_21_tl_state_source}, {_r_bits_WIRE_20_tl_state_source}, {_r_bits_WIRE_19_tl_state_source}, {_r_bits_WIRE_18_tl_state_source}, {_r_bits_WIRE_17_tl_state_source}, {_r_bits_WIRE_16_tl_state_source}, {_r_bits_WIRE_15_tl_state_source}, {_r_bits_WIRE_14_tl_state_source}, {_r_bits_WIRE_13_tl_state_source}, {_r_bits_WIRE_12_tl_state_source}, {_r_bits_WIRE_11_tl_state_source}, {_r_bits_WIRE_10_tl_state_source}, {_r_bits_WIRE_9_tl_state_source}, {_r_bits_WIRE_8_tl_state_source}, {_r_bits_WIRE_7_tl_state_source}, {_r_bits_WIRE_6_tl_state_source}, {_r_bits_WIRE_5_tl_state_source}, {_r_bits_WIRE_4_tl_state_source}, {_r_bits_WIRE_3_tl_state_source}, {_r_bits_WIRE_2_tl_state_source}, {_r_bits_WIRE_1_tl_state_source}, {_r_bits_WIRE_0_tl_state_source}}; // @[UserYanker.scala:68:27, :73:22] assign nodeIn_r_bits_echo_tl_state_source = _GEN_1[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22] wire _r_bits_WIRE_0_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_1_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_2_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_3_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_4_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_5_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_6_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_7_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_8_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_9_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_10_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_11_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_12_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_13_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_14_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_15_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_16_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_17_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_18_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_19_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_20_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_21_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_22_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_23_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_24_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_25_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_26_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_27_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_28_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_29_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_30_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_31_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_32_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_33_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_34_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_35_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_36_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_37_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_38_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_39_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_40_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_41_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_42_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_43_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_44_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_45_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_46_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_47_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_48_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_49_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_50_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_51_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_52_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_53_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_54_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_55_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_56_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_57_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_58_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_59_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_60_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_61_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_62_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_63_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_64_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_65_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_66_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_67_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_68_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_69_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_70_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_71_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_72_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_73_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_74_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_75_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_76_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_77_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_78_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_79_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_80_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_81_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_82_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_83_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_84_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_85_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_86_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_87_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_88_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_89_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_90_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_91_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_92_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_93_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_94_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_95_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_96_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_97_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_98_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_99_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_100_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_101_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_102_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_103_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_104_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_105_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_106_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_107_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_108_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_109_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_110_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_111_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_112_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_113_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_114_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_115_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_116_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_117_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_118_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_119_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_120_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_121_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_122_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_123_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_124_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_125_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_126_extra_id; // @[UserYanker.scala:68:27] wire _r_bits_WIRE_127_extra_id; // @[UserYanker.scala:68:27] wire [127:0] _GEN_2 = {{_r_bits_WIRE_127_extra_id}, {_r_bits_WIRE_126_extra_id}, {_r_bits_WIRE_125_extra_id}, {_r_bits_WIRE_124_extra_id}, {_r_bits_WIRE_123_extra_id}, {_r_bits_WIRE_122_extra_id}, {_r_bits_WIRE_121_extra_id}, {_r_bits_WIRE_120_extra_id}, {_r_bits_WIRE_119_extra_id}, {_r_bits_WIRE_118_extra_id}, {_r_bits_WIRE_117_extra_id}, {_r_bits_WIRE_116_extra_id}, {_r_bits_WIRE_115_extra_id}, {_r_bits_WIRE_114_extra_id}, {_r_bits_WIRE_113_extra_id}, {_r_bits_WIRE_112_extra_id}, {_r_bits_WIRE_111_extra_id}, {_r_bits_WIRE_110_extra_id}, {_r_bits_WIRE_109_extra_id}, {_r_bits_WIRE_108_extra_id}, {_r_bits_WIRE_107_extra_id}, {_r_bits_WIRE_106_extra_id}, {_r_bits_WIRE_105_extra_id}, {_r_bits_WIRE_104_extra_id}, {_r_bits_WIRE_103_extra_id}, {_r_bits_WIRE_102_extra_id}, {_r_bits_WIRE_101_extra_id}, {_r_bits_WIRE_100_extra_id}, {_r_bits_WIRE_99_extra_id}, {_r_bits_WIRE_98_extra_id}, {_r_bits_WIRE_97_extra_id}, {_r_bits_WIRE_96_extra_id}, {_r_bits_WIRE_95_extra_id}, {_r_bits_WIRE_94_extra_id}, {_r_bits_WIRE_93_extra_id}, {_r_bits_WIRE_92_extra_id}, {_r_bits_WIRE_91_extra_id}, {_r_bits_WIRE_90_extra_id}, {_r_bits_WIRE_89_extra_id}, {_r_bits_WIRE_88_extra_id}, {_r_bits_WIRE_87_extra_id}, {_r_bits_WIRE_86_extra_id}, {_r_bits_WIRE_85_extra_id}, {_r_bits_WIRE_84_extra_id}, {_r_bits_WIRE_83_extra_id}, {_r_bits_WIRE_82_extra_id}, {_r_bits_WIRE_81_extra_id}, {_r_bits_WIRE_80_extra_id}, {_r_bits_WIRE_79_extra_id}, {_r_bits_WIRE_78_extra_id}, {_r_bits_WIRE_77_extra_id}, {_r_bits_WIRE_76_extra_id}, {_r_bits_WIRE_75_extra_id}, {_r_bits_WIRE_74_extra_id}, {_r_bits_WIRE_73_extra_id}, {_r_bits_WIRE_72_extra_id}, {_r_bits_WIRE_71_extra_id}, {_r_bits_WIRE_70_extra_id}, {_r_bits_WIRE_69_extra_id}, {_r_bits_WIRE_68_extra_id}, {_r_bits_WIRE_67_extra_id}, {_r_bits_WIRE_66_extra_id}, {_r_bits_WIRE_65_extra_id}, {_r_bits_WIRE_64_extra_id}, {_r_bits_WIRE_63_extra_id}, {_r_bits_WIRE_62_extra_id}, {_r_bits_WIRE_61_extra_id}, {_r_bits_WIRE_60_extra_id}, {_r_bits_WIRE_59_extra_id}, {_r_bits_WIRE_58_extra_id}, {_r_bits_WIRE_57_extra_id}, {_r_bits_WIRE_56_extra_id}, {_r_bits_WIRE_55_extra_id}, {_r_bits_WIRE_54_extra_id}, {_r_bits_WIRE_53_extra_id}, {_r_bits_WIRE_52_extra_id}, {_r_bits_WIRE_51_extra_id}, {_r_bits_WIRE_50_extra_id}, {_r_bits_WIRE_49_extra_id}, {_r_bits_WIRE_48_extra_id}, {_r_bits_WIRE_47_extra_id}, {_r_bits_WIRE_46_extra_id}, {_r_bits_WIRE_45_extra_id}, {_r_bits_WIRE_44_extra_id}, {_r_bits_WIRE_43_extra_id}, {_r_bits_WIRE_42_extra_id}, {_r_bits_WIRE_41_extra_id}, {_r_bits_WIRE_40_extra_id}, {_r_bits_WIRE_39_extra_id}, {_r_bits_WIRE_38_extra_id}, {_r_bits_WIRE_37_extra_id}, {_r_bits_WIRE_36_extra_id}, {_r_bits_WIRE_35_extra_id}, {_r_bits_WIRE_34_extra_id}, {_r_bits_WIRE_33_extra_id}, {_r_bits_WIRE_32_extra_id}, {_r_bits_WIRE_31_extra_id}, {_r_bits_WIRE_30_extra_id}, {_r_bits_WIRE_29_extra_id}, {_r_bits_WIRE_28_extra_id}, {_r_bits_WIRE_27_extra_id}, {_r_bits_WIRE_26_extra_id}, {_r_bits_WIRE_25_extra_id}, {_r_bits_WIRE_24_extra_id}, {_r_bits_WIRE_23_extra_id}, {_r_bits_WIRE_22_extra_id}, {_r_bits_WIRE_21_extra_id}, {_r_bits_WIRE_20_extra_id}, {_r_bits_WIRE_19_extra_id}, {_r_bits_WIRE_18_extra_id}, {_r_bits_WIRE_17_extra_id}, {_r_bits_WIRE_16_extra_id}, {_r_bits_WIRE_15_extra_id}, {_r_bits_WIRE_14_extra_id}, {_r_bits_WIRE_13_extra_id}, {_r_bits_WIRE_12_extra_id}, {_r_bits_WIRE_11_extra_id}, {_r_bits_WIRE_10_extra_id}, {_r_bits_WIRE_9_extra_id}, {_r_bits_WIRE_8_extra_id}, {_r_bits_WIRE_7_extra_id}, {_r_bits_WIRE_6_extra_id}, {_r_bits_WIRE_5_extra_id}, {_r_bits_WIRE_4_extra_id}, {_r_bits_WIRE_3_extra_id}, {_r_bits_WIRE_2_extra_id}, {_r_bits_WIRE_1_extra_id}, {_r_bits_WIRE_0_extra_id}}; // @[UserYanker.scala:68:27, :73:22] assign nodeIn_r_bits_echo_extra_id = _GEN_2[nodeOut_r_bits_id]; // @[UserYanker.scala:73:22] wire [127:0] _arsel_T = 128'h1 << arsel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [127:0] _arsel_T_1 = _arsel_T; // @[OneHot.scala:65:{12,27}] wire arsel_0 = _arsel_T_1[0]; // @[OneHot.scala:65:27] wire arsel_1 = _arsel_T_1[1]; // @[OneHot.scala:65:27] wire arsel_2 = _arsel_T_1[2]; // @[OneHot.scala:65:27] wire arsel_3 = _arsel_T_1[3]; // @[OneHot.scala:65:27] wire arsel_4 = _arsel_T_1[4]; // @[OneHot.scala:65:27] wire arsel_5 = _arsel_T_1[5]; // @[OneHot.scala:65:27] wire arsel_6 = _arsel_T_1[6]; // @[OneHot.scala:65:27] wire arsel_7 = _arsel_T_1[7]; // @[OneHot.scala:65:27] wire arsel_8 = _arsel_T_1[8]; // @[OneHot.scala:65:27] wire arsel_9 = _arsel_T_1[9]; // @[OneHot.scala:65:27] wire arsel_10 = _arsel_T_1[10]; // @[OneHot.scala:65:27] wire arsel_11 = _arsel_T_1[11]; // @[OneHot.scala:65:27] wire arsel_12 = _arsel_T_1[12]; // @[OneHot.scala:65:27] wire arsel_13 = _arsel_T_1[13]; // @[OneHot.scala:65:27] wire arsel_14 = _arsel_T_1[14]; // @[OneHot.scala:65:27] wire arsel_15 = _arsel_T_1[15]; // @[OneHot.scala:65:27] wire arsel_16 = _arsel_T_1[16]; // @[OneHot.scala:65:27] wire arsel_17 = _arsel_T_1[17]; // @[OneHot.scala:65:27] wire arsel_18 = _arsel_T_1[18]; // @[OneHot.scala:65:27] wire arsel_19 = _arsel_T_1[19]; // @[OneHot.scala:65:27] wire arsel_20 = _arsel_T_1[20]; // @[OneHot.scala:65:27] wire arsel_21 = _arsel_T_1[21]; // @[OneHot.scala:65:27] wire arsel_22 = _arsel_T_1[22]; // @[OneHot.scala:65:27] wire arsel_23 = _arsel_T_1[23]; // @[OneHot.scala:65:27] wire arsel_24 = _arsel_T_1[24]; // @[OneHot.scala:65:27] wire arsel_25 = _arsel_T_1[25]; // @[OneHot.scala:65:27] wire arsel_26 = _arsel_T_1[26]; // @[OneHot.scala:65:27] wire arsel_27 = _arsel_T_1[27]; // @[OneHot.scala:65:27] wire arsel_28 = _arsel_T_1[28]; // @[OneHot.scala:65:27] wire arsel_29 = _arsel_T_1[29]; // @[OneHot.scala:65:27] wire arsel_30 = _arsel_T_1[30]; // @[OneHot.scala:65:27] wire arsel_31 = _arsel_T_1[31]; // @[OneHot.scala:65:27] wire arsel_32 = _arsel_T_1[32]; // @[OneHot.scala:65:27] wire arsel_33 = _arsel_T_1[33]; // @[OneHot.scala:65:27] wire arsel_34 = _arsel_T_1[34]; // @[OneHot.scala:65:27] wire arsel_35 = _arsel_T_1[35]; // @[OneHot.scala:65:27] wire arsel_36 = _arsel_T_1[36]; // @[OneHot.scala:65:27] wire arsel_37 = _arsel_T_1[37]; // @[OneHot.scala:65:27] wire arsel_38 = _arsel_T_1[38]; // @[OneHot.scala:65:27] wire arsel_39 = _arsel_T_1[39]; // @[OneHot.scala:65:27] wire arsel_40 = _arsel_T_1[40]; // @[OneHot.scala:65:27] wire arsel_41 = _arsel_T_1[41]; // @[OneHot.scala:65:27] wire arsel_42 = _arsel_T_1[42]; // @[OneHot.scala:65:27] wire arsel_43 = _arsel_T_1[43]; // @[OneHot.scala:65:27] wire arsel_44 = _arsel_T_1[44]; // @[OneHot.scala:65:27] wire arsel_45 = _arsel_T_1[45]; // @[OneHot.scala:65:27] wire arsel_46 = _arsel_T_1[46]; // @[OneHot.scala:65:27] wire arsel_47 = _arsel_T_1[47]; // @[OneHot.scala:65:27] wire arsel_48 = _arsel_T_1[48]; // @[OneHot.scala:65:27] wire arsel_49 = _arsel_T_1[49]; // @[OneHot.scala:65:27] wire arsel_50 = _arsel_T_1[50]; // @[OneHot.scala:65:27] wire arsel_51 = _arsel_T_1[51]; // @[OneHot.scala:65:27] wire arsel_52 = _arsel_T_1[52]; // @[OneHot.scala:65:27] wire arsel_53 = _arsel_T_1[53]; // @[OneHot.scala:65:27] wire arsel_54 = _arsel_T_1[54]; // @[OneHot.scala:65:27] wire arsel_55 = _arsel_T_1[55]; // @[OneHot.scala:65:27] wire arsel_56 = _arsel_T_1[56]; // @[OneHot.scala:65:27] wire arsel_57 = _arsel_T_1[57]; // @[OneHot.scala:65:27] wire arsel_58 = _arsel_T_1[58]; // @[OneHot.scala:65:27] wire arsel_59 = _arsel_T_1[59]; // @[OneHot.scala:65:27] wire arsel_60 = _arsel_T_1[60]; // @[OneHot.scala:65:27] wire arsel_61 = _arsel_T_1[61]; // @[OneHot.scala:65:27] wire arsel_62 = _arsel_T_1[62]; // @[OneHot.scala:65:27] wire arsel_63 = _arsel_T_1[63]; // @[OneHot.scala:65:27] wire arsel_64 = _arsel_T_1[64]; // @[OneHot.scala:65:27] wire arsel_65 = _arsel_T_1[65]; // @[OneHot.scala:65:27] wire arsel_66 = _arsel_T_1[66]; // @[OneHot.scala:65:27] wire arsel_67 = _arsel_T_1[67]; // @[OneHot.scala:65:27] wire arsel_68 = _arsel_T_1[68]; // @[OneHot.scala:65:27] wire arsel_69 = _arsel_T_1[69]; // @[OneHot.scala:65:27] wire arsel_70 = _arsel_T_1[70]; // @[OneHot.scala:65:27] wire arsel_71 = _arsel_T_1[71]; // @[OneHot.scala:65:27] wire arsel_72 = _arsel_T_1[72]; // @[OneHot.scala:65:27] wire arsel_73 = _arsel_T_1[73]; // @[OneHot.scala:65:27] wire arsel_74 = _arsel_T_1[74]; // @[OneHot.scala:65:27] wire arsel_75 = _arsel_T_1[75]; // @[OneHot.scala:65:27] wire arsel_76 = _arsel_T_1[76]; // @[OneHot.scala:65:27] wire arsel_77 = _arsel_T_1[77]; // @[OneHot.scala:65:27] wire arsel_78 = _arsel_T_1[78]; // @[OneHot.scala:65:27] wire arsel_79 = _arsel_T_1[79]; // @[OneHot.scala:65:27] wire arsel_80 = _arsel_T_1[80]; // @[OneHot.scala:65:27] wire arsel_81 = _arsel_T_1[81]; // @[OneHot.scala:65:27] wire arsel_82 = _arsel_T_1[82]; // @[OneHot.scala:65:27] wire arsel_83 = _arsel_T_1[83]; // @[OneHot.scala:65:27] wire arsel_84 = _arsel_T_1[84]; // @[OneHot.scala:65:27] wire arsel_85 = _arsel_T_1[85]; // @[OneHot.scala:65:27] wire arsel_86 = _arsel_T_1[86]; // @[OneHot.scala:65:27] wire arsel_87 = _arsel_T_1[87]; // @[OneHot.scala:65:27] wire arsel_88 = _arsel_T_1[88]; // @[OneHot.scala:65:27] wire arsel_89 = _arsel_T_1[89]; // @[OneHot.scala:65:27] wire arsel_90 = _arsel_T_1[90]; // @[OneHot.scala:65:27] wire arsel_91 = _arsel_T_1[91]; // @[OneHot.scala:65:27] wire arsel_92 = _arsel_T_1[92]; // @[OneHot.scala:65:27] wire arsel_93 = _arsel_T_1[93]; // @[OneHot.scala:65:27] wire arsel_94 = _arsel_T_1[94]; // @[OneHot.scala:65:27] wire arsel_95 = _arsel_T_1[95]; // @[OneHot.scala:65:27] wire arsel_96 = _arsel_T_1[96]; // @[OneHot.scala:65:27] wire arsel_97 = _arsel_T_1[97]; // @[OneHot.scala:65:27] wire arsel_98 = _arsel_T_1[98]; // @[OneHot.scala:65:27] wire arsel_99 = _arsel_T_1[99]; // @[OneHot.scala:65:27] wire arsel_100 = _arsel_T_1[100]; // @[OneHot.scala:65:27] wire arsel_101 = _arsel_T_1[101]; // @[OneHot.scala:65:27] wire arsel_102 = _arsel_T_1[102]; // @[OneHot.scala:65:27] wire arsel_103 = _arsel_T_1[103]; // @[OneHot.scala:65:27] wire arsel_104 = _arsel_T_1[104]; // @[OneHot.scala:65:27] wire arsel_105 = _arsel_T_1[105]; // @[OneHot.scala:65:27] wire arsel_106 = _arsel_T_1[106]; // @[OneHot.scala:65:27] wire arsel_107 = _arsel_T_1[107]; // @[OneHot.scala:65:27] wire arsel_108 = _arsel_T_1[108]; // @[OneHot.scala:65:27] wire arsel_109 = _arsel_T_1[109]; // @[OneHot.scala:65:27] wire arsel_110 = _arsel_T_1[110]; // @[OneHot.scala:65:27] wire arsel_111 = _arsel_T_1[111]; // @[OneHot.scala:65:27] wire arsel_112 = _arsel_T_1[112]; // @[OneHot.scala:65:27] wire arsel_113 = _arsel_T_1[113]; // @[OneHot.scala:65:27] wire arsel_114 = _arsel_T_1[114]; // @[OneHot.scala:65:27] wire arsel_115 = _arsel_T_1[115]; // @[OneHot.scala:65:27] wire arsel_116 = _arsel_T_1[116]; // @[OneHot.scala:65:27] wire arsel_117 = _arsel_T_1[117]; // @[OneHot.scala:65:27] wire arsel_118 = _arsel_T_1[118]; // @[OneHot.scala:65:27] wire arsel_119 = _arsel_T_1[119]; // @[OneHot.scala:65:27] wire arsel_120 = _arsel_T_1[120]; // @[OneHot.scala:65:27] wire arsel_121 = _arsel_T_1[121]; // @[OneHot.scala:65:27] wire arsel_122 = _arsel_T_1[122]; // @[OneHot.scala:65:27] wire arsel_123 = _arsel_T_1[123]; // @[OneHot.scala:65:27] wire arsel_124 = _arsel_T_1[124]; // @[OneHot.scala:65:27] wire arsel_125 = _arsel_T_1[125]; // @[OneHot.scala:65:27] wire arsel_126 = _arsel_T_1[126]; // @[OneHot.scala:65:27] wire arsel_127 = _arsel_T_1[127]; // @[OneHot.scala:65:27] wire [127:0] _rsel_T = 128'h1 << rsel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [127:0] _rsel_T_1 = _rsel_T; // @[OneHot.scala:65:{12,27}] wire rsel_0 = _rsel_T_1[0]; // @[OneHot.scala:65:27] wire rsel_1 = _rsel_T_1[1]; // @[OneHot.scala:65:27] wire rsel_2 = _rsel_T_1[2]; // @[OneHot.scala:65:27] wire rsel_3 = _rsel_T_1[3]; // @[OneHot.scala:65:27] wire rsel_4 = _rsel_T_1[4]; // @[OneHot.scala:65:27] wire rsel_5 = _rsel_T_1[5]; // @[OneHot.scala:65:27] wire rsel_6 = _rsel_T_1[6]; // @[OneHot.scala:65:27] wire rsel_7 = _rsel_T_1[7]; // @[OneHot.scala:65:27] wire rsel_8 = _rsel_T_1[8]; // @[OneHot.scala:65:27] wire rsel_9 = _rsel_T_1[9]; // @[OneHot.scala:65:27] wire rsel_10 = _rsel_T_1[10]; // @[OneHot.scala:65:27] wire rsel_11 = _rsel_T_1[11]; // @[OneHot.scala:65:27] wire rsel_12 = _rsel_T_1[12]; // @[OneHot.scala:65:27] wire rsel_13 = _rsel_T_1[13]; // @[OneHot.scala:65:27] wire rsel_14 = _rsel_T_1[14]; // @[OneHot.scala:65:27] wire rsel_15 = _rsel_T_1[15]; // @[OneHot.scala:65:27] wire rsel_16 = _rsel_T_1[16]; // @[OneHot.scala:65:27] wire rsel_17 = _rsel_T_1[17]; // @[OneHot.scala:65:27] wire rsel_18 = _rsel_T_1[18]; // @[OneHot.scala:65:27] wire rsel_19 = _rsel_T_1[19]; // @[OneHot.scala:65:27] wire rsel_20 = _rsel_T_1[20]; // @[OneHot.scala:65:27] wire rsel_21 = _rsel_T_1[21]; // @[OneHot.scala:65:27] wire rsel_22 = _rsel_T_1[22]; // @[OneHot.scala:65:27] wire rsel_23 = _rsel_T_1[23]; // @[OneHot.scala:65:27] wire rsel_24 = _rsel_T_1[24]; // @[OneHot.scala:65:27] wire rsel_25 = _rsel_T_1[25]; // @[OneHot.scala:65:27] wire rsel_26 = _rsel_T_1[26]; // @[OneHot.scala:65:27] wire rsel_27 = _rsel_T_1[27]; // @[OneHot.scala:65:27] wire rsel_28 = _rsel_T_1[28]; // @[OneHot.scala:65:27] wire rsel_29 = _rsel_T_1[29]; // @[OneHot.scala:65:27] wire rsel_30 = _rsel_T_1[30]; // @[OneHot.scala:65:27] wire rsel_31 = _rsel_T_1[31]; // @[OneHot.scala:65:27] wire rsel_32 = _rsel_T_1[32]; // @[OneHot.scala:65:27] wire rsel_33 = _rsel_T_1[33]; // @[OneHot.scala:65:27] wire rsel_34 = _rsel_T_1[34]; // @[OneHot.scala:65:27] wire rsel_35 = _rsel_T_1[35]; // @[OneHot.scala:65:27] wire rsel_36 = _rsel_T_1[36]; // @[OneHot.scala:65:27] wire rsel_37 = _rsel_T_1[37]; // @[OneHot.scala:65:27] wire rsel_38 = _rsel_T_1[38]; // @[OneHot.scala:65:27] wire rsel_39 = _rsel_T_1[39]; // @[OneHot.scala:65:27] wire rsel_40 = _rsel_T_1[40]; // @[OneHot.scala:65:27] wire rsel_41 = _rsel_T_1[41]; // @[OneHot.scala:65:27] wire rsel_42 = _rsel_T_1[42]; // @[OneHot.scala:65:27] wire rsel_43 = _rsel_T_1[43]; // @[OneHot.scala:65:27] wire rsel_44 = _rsel_T_1[44]; // @[OneHot.scala:65:27] wire rsel_45 = _rsel_T_1[45]; // @[OneHot.scala:65:27] wire rsel_46 = _rsel_T_1[46]; // @[OneHot.scala:65:27] wire rsel_47 = _rsel_T_1[47]; // @[OneHot.scala:65:27] wire rsel_48 = _rsel_T_1[48]; // @[OneHot.scala:65:27] wire rsel_49 = _rsel_T_1[49]; // @[OneHot.scala:65:27] wire rsel_50 = _rsel_T_1[50]; // @[OneHot.scala:65:27] wire rsel_51 = _rsel_T_1[51]; // @[OneHot.scala:65:27] wire rsel_52 = _rsel_T_1[52]; // @[OneHot.scala:65:27] wire rsel_53 = _rsel_T_1[53]; // @[OneHot.scala:65:27] wire rsel_54 = _rsel_T_1[54]; // @[OneHot.scala:65:27] wire rsel_55 = _rsel_T_1[55]; // @[OneHot.scala:65:27] wire rsel_56 = _rsel_T_1[56]; // @[OneHot.scala:65:27] wire rsel_57 = _rsel_T_1[57]; // @[OneHot.scala:65:27] wire rsel_58 = _rsel_T_1[58]; // @[OneHot.scala:65:27] wire rsel_59 = _rsel_T_1[59]; // @[OneHot.scala:65:27] wire rsel_60 = _rsel_T_1[60]; // @[OneHot.scala:65:27] wire rsel_61 = _rsel_T_1[61]; // @[OneHot.scala:65:27] wire rsel_62 = _rsel_T_1[62]; // @[OneHot.scala:65:27] wire rsel_63 = _rsel_T_1[63]; // @[OneHot.scala:65:27] wire rsel_64 = _rsel_T_1[64]; // @[OneHot.scala:65:27] wire rsel_65 = _rsel_T_1[65]; // @[OneHot.scala:65:27] wire rsel_66 = _rsel_T_1[66]; // @[OneHot.scala:65:27] wire rsel_67 = _rsel_T_1[67]; // @[OneHot.scala:65:27] wire rsel_68 = _rsel_T_1[68]; // @[OneHot.scala:65:27] wire rsel_69 = _rsel_T_1[69]; // @[OneHot.scala:65:27] wire rsel_70 = _rsel_T_1[70]; // @[OneHot.scala:65:27] wire rsel_71 = _rsel_T_1[71]; // @[OneHot.scala:65:27] wire rsel_72 = _rsel_T_1[72]; // @[OneHot.scala:65:27] wire rsel_73 = _rsel_T_1[73]; // @[OneHot.scala:65:27] wire rsel_74 = _rsel_T_1[74]; // @[OneHot.scala:65:27] wire rsel_75 = _rsel_T_1[75]; // @[OneHot.scala:65:27] wire rsel_76 = _rsel_T_1[76]; // @[OneHot.scala:65:27] wire rsel_77 = _rsel_T_1[77]; // @[OneHot.scala:65:27] wire rsel_78 = _rsel_T_1[78]; // @[OneHot.scala:65:27] wire rsel_79 = _rsel_T_1[79]; // @[OneHot.scala:65:27] wire rsel_80 = _rsel_T_1[80]; // @[OneHot.scala:65:27] wire rsel_81 = _rsel_T_1[81]; // @[OneHot.scala:65:27] wire rsel_82 = _rsel_T_1[82]; // @[OneHot.scala:65:27] wire rsel_83 = _rsel_T_1[83]; // @[OneHot.scala:65:27] wire rsel_84 = _rsel_T_1[84]; // @[OneHot.scala:65:27] wire rsel_85 = _rsel_T_1[85]; // @[OneHot.scala:65:27] wire rsel_86 = _rsel_T_1[86]; // @[OneHot.scala:65:27] wire rsel_87 = _rsel_T_1[87]; // @[OneHot.scala:65:27] wire rsel_88 = _rsel_T_1[88]; // @[OneHot.scala:65:27] wire rsel_89 = _rsel_T_1[89]; // @[OneHot.scala:65:27] wire rsel_90 = _rsel_T_1[90]; // @[OneHot.scala:65:27] wire rsel_91 = _rsel_T_1[91]; // @[OneHot.scala:65:27] wire rsel_92 = _rsel_T_1[92]; // @[OneHot.scala:65:27] wire rsel_93 = _rsel_T_1[93]; // @[OneHot.scala:65:27] wire rsel_94 = _rsel_T_1[94]; // @[OneHot.scala:65:27] wire rsel_95 = _rsel_T_1[95]; // @[OneHot.scala:65:27] wire rsel_96 = _rsel_T_1[96]; // @[OneHot.scala:65:27] wire rsel_97 = _rsel_T_1[97]; // @[OneHot.scala:65:27] wire rsel_98 = _rsel_T_1[98]; // @[OneHot.scala:65:27] wire rsel_99 = _rsel_T_1[99]; // @[OneHot.scala:65:27] wire rsel_100 = _rsel_T_1[100]; // @[OneHot.scala:65:27] wire rsel_101 = _rsel_T_1[101]; // @[OneHot.scala:65:27] wire rsel_102 = _rsel_T_1[102]; // @[OneHot.scala:65:27] wire rsel_103 = _rsel_T_1[103]; // @[OneHot.scala:65:27] wire rsel_104 = _rsel_T_1[104]; // @[OneHot.scala:65:27] wire rsel_105 = _rsel_T_1[105]; // @[OneHot.scala:65:27] wire rsel_106 = _rsel_T_1[106]; // @[OneHot.scala:65:27] wire rsel_107 = _rsel_T_1[107]; // @[OneHot.scala:65:27] wire rsel_108 = _rsel_T_1[108]; // @[OneHot.scala:65:27] wire rsel_109 = _rsel_T_1[109]; // @[OneHot.scala:65:27] wire rsel_110 = _rsel_T_1[110]; // @[OneHot.scala:65:27] wire rsel_111 = _rsel_T_1[111]; // @[OneHot.scala:65:27] wire rsel_112 = _rsel_T_1[112]; // @[OneHot.scala:65:27] wire rsel_113 = _rsel_T_1[113]; // @[OneHot.scala:65:27] wire rsel_114 = _rsel_T_1[114]; // @[OneHot.scala:65:27] wire rsel_115 = _rsel_T_1[115]; // @[OneHot.scala:65:27] wire rsel_116 = _rsel_T_1[116]; // @[OneHot.scala:65:27] wire rsel_117 = _rsel_T_1[117]; // @[OneHot.scala:65:27] wire rsel_118 = _rsel_T_1[118]; // @[OneHot.scala:65:27] wire rsel_119 = _rsel_T_1[119]; // @[OneHot.scala:65:27] wire rsel_120 = _rsel_T_1[120]; // @[OneHot.scala:65:27] wire rsel_121 = _rsel_T_1[121]; // @[OneHot.scala:65:27] wire rsel_122 = _rsel_T_1[122]; // @[OneHot.scala:65:27] wire rsel_123 = _rsel_T_1[123]; // @[OneHot.scala:65:27] wire rsel_124 = _rsel_T_1[124]; // @[OneHot.scala:65:27] wire rsel_125 = _rsel_T_1[125]; // @[OneHot.scala:65:27] wire rsel_126 = _rsel_T_1[126]; // @[OneHot.scala:65:27] wire rsel_127 = _rsel_T_1[127]; // @[OneHot.scala:65:27] wire _T_640 = nodeOut_r_valid & nodeIn_r_ready; // @[UserYanker.scala:78:37] wire _T_643 = nodeIn_ar_valid & nodeOut_ar_ready; // @[UserYanker.scala:81:37] wire _aw_ready_WIRE_0; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_1; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_2; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_3; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_4; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_5; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_6; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_7; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_8; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_9; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_10; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_11; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_12; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_13; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_14; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_15; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_16; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_17; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_18; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_19; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_20; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_21; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_22; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_23; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_24; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_25; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_26; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_27; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_28; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_29; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_30; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_31; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_32; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_33; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_34; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_35; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_36; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_37; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_38; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_39; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_40; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_41; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_42; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_43; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_44; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_45; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_46; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_47; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_48; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_49; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_50; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_51; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_52; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_53; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_54; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_55; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_56; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_57; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_58; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_59; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_60; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_61; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_62; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_63; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_64; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_65; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_66; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_67; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_68; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_69; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_70; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_71; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_72; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_73; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_74; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_75; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_76; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_77; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_78; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_79; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_80; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_81; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_82; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_83; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_84; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_85; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_86; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_87; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_88; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_89; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_90; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_91; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_92; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_93; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_94; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_95; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_96; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_97; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_98; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_99; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_100; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_101; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_102; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_103; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_104; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_105; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_106; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_107; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_108; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_109; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_110; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_111; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_112; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_113; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_114; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_115; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_116; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_117; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_118; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_119; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_120; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_121; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_122; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_123; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_124; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_125; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_126; // @[UserYanker.scala:88:29] wire _aw_ready_WIRE_127; // @[UserYanker.scala:88:29] wire [127:0] _GEN_3 = {{_aw_ready_WIRE_127}, {_aw_ready_WIRE_126}, {_aw_ready_WIRE_125}, {_aw_ready_WIRE_124}, {_aw_ready_WIRE_123}, {_aw_ready_WIRE_122}, {_aw_ready_WIRE_121}, {_aw_ready_WIRE_120}, {_aw_ready_WIRE_119}, {_aw_ready_WIRE_118}, {_aw_ready_WIRE_117}, {_aw_ready_WIRE_116}, {_aw_ready_WIRE_115}, {_aw_ready_WIRE_114}, {_aw_ready_WIRE_113}, {_aw_ready_WIRE_112}, {_aw_ready_WIRE_111}, {_aw_ready_WIRE_110}, {_aw_ready_WIRE_109}, {_aw_ready_WIRE_108}, {_aw_ready_WIRE_107}, {_aw_ready_WIRE_106}, {_aw_ready_WIRE_105}, {_aw_ready_WIRE_104}, {_aw_ready_WIRE_103}, {_aw_ready_WIRE_102}, {_aw_ready_WIRE_101}, {_aw_ready_WIRE_100}, {_aw_ready_WIRE_99}, {_aw_ready_WIRE_98}, {_aw_ready_WIRE_97}, {_aw_ready_WIRE_96}, {_aw_ready_WIRE_95}, {_aw_ready_WIRE_94}, {_aw_ready_WIRE_93}, {_aw_ready_WIRE_92}, {_aw_ready_WIRE_91}, {_aw_ready_WIRE_90}, {_aw_ready_WIRE_89}, {_aw_ready_WIRE_88}, {_aw_ready_WIRE_87}, {_aw_ready_WIRE_86}, {_aw_ready_WIRE_85}, {_aw_ready_WIRE_84}, {_aw_ready_WIRE_83}, {_aw_ready_WIRE_82}, {_aw_ready_WIRE_81}, {_aw_ready_WIRE_80}, {_aw_ready_WIRE_79}, {_aw_ready_WIRE_78}, {_aw_ready_WIRE_77}, {_aw_ready_WIRE_76}, {_aw_ready_WIRE_75}, {_aw_ready_WIRE_74}, {_aw_ready_WIRE_73}, {_aw_ready_WIRE_72}, {_aw_ready_WIRE_71}, {_aw_ready_WIRE_70}, {_aw_ready_WIRE_69}, {_aw_ready_WIRE_68}, {_aw_ready_WIRE_67}, {_aw_ready_WIRE_66}, {_aw_ready_WIRE_65}, {_aw_ready_WIRE_64}, {_aw_ready_WIRE_63}, {_aw_ready_WIRE_62}, {_aw_ready_WIRE_61}, {_aw_ready_WIRE_60}, {_aw_ready_WIRE_59}, {_aw_ready_WIRE_58}, {_aw_ready_WIRE_57}, {_aw_ready_WIRE_56}, {_aw_ready_WIRE_55}, {_aw_ready_WIRE_54}, {_aw_ready_WIRE_53}, {_aw_ready_WIRE_52}, {_aw_ready_WIRE_51}, {_aw_ready_WIRE_50}, {_aw_ready_WIRE_49}, {_aw_ready_WIRE_48}, {_aw_ready_WIRE_47}, {_aw_ready_WIRE_46}, {_aw_ready_WIRE_45}, {_aw_ready_WIRE_44}, {_aw_ready_WIRE_43}, {_aw_ready_WIRE_42}, {_aw_ready_WIRE_41}, {_aw_ready_WIRE_40}, {_aw_ready_WIRE_39}, {_aw_ready_WIRE_38}, {_aw_ready_WIRE_37}, {_aw_ready_WIRE_36}, {_aw_ready_WIRE_35}, {_aw_ready_WIRE_34}, {_aw_ready_WIRE_33}, {_aw_ready_WIRE_32}, {_aw_ready_WIRE_31}, {_aw_ready_WIRE_30}, {_aw_ready_WIRE_29}, {_aw_ready_WIRE_28}, {_aw_ready_WIRE_27}, {_aw_ready_WIRE_26}, {_aw_ready_WIRE_25}, {_aw_ready_WIRE_24}, {_aw_ready_WIRE_23}, {_aw_ready_WIRE_22}, {_aw_ready_WIRE_21}, {_aw_ready_WIRE_20}, {_aw_ready_WIRE_19}, {_aw_ready_WIRE_18}, {_aw_ready_WIRE_17}, {_aw_ready_WIRE_16}, {_aw_ready_WIRE_15}, {_aw_ready_WIRE_14}, {_aw_ready_WIRE_13}, {_aw_ready_WIRE_12}, {_aw_ready_WIRE_11}, {_aw_ready_WIRE_10}, {_aw_ready_WIRE_9}, {_aw_ready_WIRE_8}, {_aw_ready_WIRE_7}, {_aw_ready_WIRE_6}, {_aw_ready_WIRE_5}, {_aw_ready_WIRE_4}, {_aw_ready_WIRE_3}, {_aw_ready_WIRE_2}, {_aw_ready_WIRE_1}, {_aw_ready_WIRE_0}}; // @[UserYanker.scala:88:29, :89:36] assign _nodeIn_aw_ready_T = nodeOut_aw_ready & _GEN_3[nodeIn_aw_bits_id]; // @[UserYanker.scala:89:36] assign nodeIn_aw_ready = _nodeIn_aw_ready_T; // @[UserYanker.scala:89:36] assign _nodeOut_aw_valid_T = nodeIn_aw_valid & _GEN_3[nodeIn_aw_bits_id]; // @[UserYanker.scala:89:36, :90:36] assign nodeOut_aw_valid = _nodeOut_aw_valid_T; // @[UserYanker.scala:90:36] wire _r_valid_WIRE_0; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_1; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_2; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_3; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_4; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_5; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_6; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_7; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_8; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_9; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_10; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_11; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_12; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_13; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_14; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_15; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_16; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_17; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_18; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_19; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_20; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_21; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_22; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_23; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_24; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_25; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_26; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_27; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_28; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_29; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_30; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_31; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_32; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_33; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_34; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_35; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_36; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_37; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_38; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_39; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_40; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_41; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_42; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_43; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_44; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_45; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_46; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_47; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_48; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_49; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_50; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_51; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_52; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_53; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_54; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_55; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_56; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_57; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_58; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_59; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_60; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_61; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_62; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_63; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_64; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_65; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_66; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_67; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_68; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_69; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_70; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_71; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_72; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_73; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_74; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_75; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_76; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_77; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_78; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_79; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_80; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_81; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_82; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_83; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_84; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_85; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_86; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_87; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_88; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_89; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_90; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_91; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_92; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_93; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_94; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_95; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_96; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_97; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_98; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_99; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_100; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_101; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_102; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_103; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_104; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_105; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_106; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_107; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_108; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_109; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_110; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_111; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_112; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_113; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_114; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_115; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_116; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_117; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_118; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_119; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_120; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_121; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_122; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_123; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_124; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_125; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_126; // @[UserYanker.scala:67:28] wire _r_valid_WIRE_127; // @[UserYanker.scala:67:28] wire _b_valid_WIRE_0; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_1; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_2; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_3; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_4; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_5; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_6; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_7; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_8; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_9; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_10; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_11; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_12; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_13; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_14; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_15; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_16; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_17; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_18; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_19; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_20; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_21; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_22; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_23; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_24; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_25; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_26; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_27; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_28; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_29; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_30; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_31; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_32; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_33; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_34; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_35; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_36; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_37; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_38; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_39; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_40; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_41; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_42; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_43; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_44; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_45; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_46; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_47; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_48; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_49; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_50; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_51; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_52; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_53; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_54; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_55; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_56; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_57; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_58; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_59; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_60; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_61; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_62; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_63; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_64; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_65; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_66; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_67; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_68; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_69; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_70; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_71; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_72; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_73; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_74; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_75; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_76; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_77; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_78; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_79; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_80; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_81; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_82; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_83; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_84; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_85; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_86; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_87; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_88; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_89; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_90; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_91; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_92; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_93; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_94; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_95; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_96; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_97; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_98; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_99; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_100; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_101; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_102; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_103; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_104; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_105; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_106; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_107; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_108; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_109; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_110; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_111; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_112; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_113; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_114; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_115; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_116; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_117; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_118; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_119; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_120; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_121; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_122; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_123; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_124; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_125; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_126; // @[UserYanker.scala:96:28] wire _b_valid_WIRE_127; // @[UserYanker.scala:96:28]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_70 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 48, 48) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 47, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 74, 25) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0) node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0) node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0) node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1) node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2) node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0) node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1) node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4) node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0) node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1) node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19) node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 51, 51) node _notCDom_absSigSum_T = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17]) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24]) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19)) node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26) node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27) node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28) node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29) node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30) node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31) node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32) node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33) node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34) node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35) node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36) node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37) node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38) node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39) node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40) node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41) node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42) node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43) node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44) node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45) node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46) node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47) node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0) node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0) node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0) node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1) node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2) node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0) node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1) node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4) node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0) node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1) node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19) node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T	module MulAddRecFNToRaw_postMul_e8_s24_70( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = \|_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = \|_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = \|_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = \|_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = \|_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = \|_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = \|_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = \|_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = \|_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = \|_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = \|_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 \| CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 \| CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = \|_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = \|_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = \|_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = \|_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 \| notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _GEN_0 = io_fromPreMul_isInfA_0 \| io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49] wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49] assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49] wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36] assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36] assign notNaN_isInfOut = notNaN_isInfProd \| io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 \| io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32] wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 \| _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31] wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32] wire _io_invalidExc_T_3 = _io_invalidExc_T_1 \| _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61] wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35] assign _io_invalidExc_T_9 = _io_invalidExc_T_3 \| _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 \| io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14] wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}] assign _io_rawOut_isZero_T_2 = notNaN_addZeros \| _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T \| _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 \| _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 \| opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 \| _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [8:0] rawC_exp = 9'h0; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h0; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:25] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:122:68] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36] wire io_toPostMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _CIsDominant_T = 1'h0; // @[MulAddRecFN.scala:110:9] wire CIsDominant = 1'h0; // @[MulAddRecFN.scala:110:23] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[primitives.scala:118:30] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[primitives.scala:123:57] wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[common.scala:82:46] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire _doSubMags_T = signProd; // @[MulAddRecFN.scala:97:42, :102:30] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _sNatCAlignDist_T = {sExpAlignedProd[10], sExpAlignedProd}; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero \| rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T_1 = {25{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:13] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 \| _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6; // @[MulAddRecFN.scala:146:{32,58}] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN \| rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _sNatCAlignDist_T - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = _io_toPostMul_sExpSum_T_2; // @[MulAddRecFN.scala:158:{12,53}] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_46 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_46( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_154 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_154( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_7 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[6]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_14 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_7 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<4>(0hc), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0he), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<2>(0h3) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0hc), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0hb), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0hc), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0hc), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0he), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h10), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h3)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) node _T_16 = eq(UInt<3>(0h4), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_18 = and(route_q.io.enq.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_15 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_7 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_24 = and(vcalloc_q.io.enq.valid, _T_23) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = asUInt(reset) node _T_27 = eq(_T_26, UInt<1>(0h0)) when _T_27 : node _T_28 = eq(_T_25, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_25, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node c_lo = cat(c_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _c_T = cat(c_hi, c_lo) node _c_T_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_lo_hi_1 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node c_lo_1 = cat(c_lo_hi_1, io.out_credit_available.`0`[0]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_1 = cat(c_hi_hi_1, io.out_credit_available.`0`[3]) node _c_T_2 = cat(c_hi_1, c_lo_1) node _c_T_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_channel_oh_0 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 5, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_10 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_7( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hC; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 4'h9 : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 4'hA : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'hB : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hC : 4'h0); // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h3; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h3; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_71 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_88 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_71( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_88 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ResetCatchAndSync_d3_1 : input clock : Clock input reset : Reset output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}} node _post_psd_reset_T = asUInt(reset) node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T) inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_1 connect io_sync_reset_chain.clock, clock connect io_sync_reset_chain.reset, post_psd_reset connect io_sync_reset_chain.io.d, UInt<1>(0h1) wire _io_sync_reset_WIRE : UInt<1> connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q node _io_sync_reset_T = not(_io_sync_reset_WIRE) node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T) connect io.sync_reset, _io_sync_reset_T_1 extmodule ClockSourceAtFreqMHz : input power : UInt<1> input gate : UInt<1> output clk : Clock defname = ClockSourceAtFreqMHz parameter PERIOD = 1.0 extmodule ClockSourceAtFreqMHz_1 : input power : UInt<1> input gate : UInt<1> output clk : Clock defname = ClockSourceAtFreqMHz parameter PERIOD = 10.0	module ResetCatchAndSync_d3_1( // @[ResetCatchAndSync.scala:13:7] input clock, // @[ResetCatchAndSync.scala:13:7] input reset, // @[ResetCatchAndSync.scala:13:7] output io_sync_reset // @[ResetCatchAndSync.scala:17:14] ); wire _post_psd_reset_T = reset; // @[ResetCatchAndSync.scala:26:76] wire io_psd_test_mode = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire io_psd_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:28:25] wire io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7] wire post_psd_reset = _post_psd_reset_T; // @[ResetCatchAndSync.scala:26:{27,76}] wire _io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] wire _io_sync_reset_T = ~_io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] assign _io_sync_reset_T_1 = _io_sync_reset_T; // @[ResetCatchAndSync.scala:28:25, :29:7] assign io_sync_reset_0 = _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:13:7, :28:25] AsyncResetSynchronizerShiftReg_w1_d3_i0_1 io_sync_reset_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (post_psd_reset), // @[ResetCatchAndSync.scala:26:27] .io_q (_io_sync_reset_WIRE) ); // @[ShiftReg.scala:45:23] assign io_sync_reset = io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_118( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_4 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_141 = shr(io.in.a.bits.source, 3) node _T_142 = eq(_T_141, UInt<3>(0h4)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = or(_T_165, _T_170) node _T_172 = and(_T_160, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = and(_T_159, _T_173) node _T_175 = asUInt(reset) node _T_176 = eq(_T_175, UInt<1>(0h0)) when _T_176 : node _T_177 = eq(_T_174, UInt<1>(0h0)) when _T_177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_174, UInt<1>(0h1), "") : assert_2 node _T_178 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h0)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_10) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<1>(0h1)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_11) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h2)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_12) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<2>(0h3)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_13) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_202 = and(_T_200, _T_201) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_203 = shr(io.in.a.bits.source, 3) node _T_204 = eq(_T_203, UInt<3>(0h4)) node _T_205 = leq(UInt<1>(0h0), uncommonBits_14) node _T_206 = and(_T_204, _T_205) node _T_207 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_208 = and(_T_206, _T_207) node _T_209 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_210 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_211 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_178 connect _WIRE[1], _T_184 connect _WIRE[2], _T_190 connect _WIRE[3], _T_196 connect _WIRE[4], _T_202 connect _WIRE[5], _T_208 connect _WIRE[6], _T_209 connect _WIRE[7], _T_210 connect _WIRE[8], _T_211 node _T_212 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_213 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_217 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_218 = mux(_WIRE[5], _T_212, UInt<1>(0h0)) node _T_219 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_220 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_221 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_222 = or(_T_213, _T_214) node _T_223 = or(_T_222, _T_215) node _T_224 = or(_T_223, _T_216) node _T_225 = or(_T_224, _T_217) node _T_226 = or(_T_225, _T_218) node _T_227 = or(_T_226, _T_219) node _T_228 = or(_T_227, _T_220) node _T_229 = or(_T_228, _T_221) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_229 node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<13>(0h1000))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_240 = cvt(_T_239) node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000))) node _T_242 = asSInt(_T_241) node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0))) node _T_244 = or(_T_238, _T_243) node _T_245 = and(_T_233, _T_244) node _T_246 = or(UInt<1>(0h0), _T_245) node _T_247 = and(_WIRE_1, _T_246) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_247, UInt<1>(0h1), "") : assert_3 node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(source_ok, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_254 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_254, UInt<1>(0h1), "") : assert_5 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(is_aligned, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_261 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_T_261, UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_261, UInt<1>(0h1), "") : assert_7 node _T_265 = not(io.in.a.bits.mask) node _T_266 = eq(_T_265, UInt<1>(0h0)) node _T_267 = asUInt(reset) node _T_268 = eq(_T_267, UInt<1>(0h0)) when _T_268 : node _T_269 = eq(_T_266, UInt<1>(0h0)) when _T_269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_266, UInt<1>(0h1), "") : assert_8 node _T_270 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_270, UInt<1>(0h1), "") : assert_9 node _T_274 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_274 : node _T_275 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_276 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<1>(0h0)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_15) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<1>(0h1)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_16) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_291 = shr(io.in.a.bits.source, 2) node _T_292 = eq(_T_291, UInt<2>(0h2)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_17) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_296 = and(_T_294, _T_295) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_297 = shr(io.in.a.bits.source, 2) node _T_298 = eq(_T_297, UInt<2>(0h3)) node _T_299 = leq(UInt<1>(0h0), uncommonBits_18) node _T_300 = and(_T_298, _T_299) node _T_301 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_302 = and(_T_300, _T_301) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_303 = shr(io.in.a.bits.source, 3) node _T_304 = eq(_T_303, UInt<3>(0h4)) node _T_305 = leq(UInt<1>(0h0), uncommonBits_19) node _T_306 = and(_T_304, _T_305) node _T_307 = leq(uncommonBits_19, UInt<3>(0h4)) node _T_308 = and(_T_306, _T_307) node _T_309 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_310 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_311 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_312 = or(_T_278, _T_284) node _T_313 = or(_T_312, _T_290) node _T_314 = or(_T_313, _T_296) node _T_315 = or(_T_314, _T_302) node _T_316 = or(_T_315, _T_308) node _T_317 = or(_T_316, _T_309) node _T_318 = or(_T_317, _T_310) node _T_319 = or(_T_318, _T_311) node _T_320 = and(_T_277, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_323 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<13>(0h1000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = or(_T_327, _T_332) node _T_334 = and(_T_322, _T_333) node _T_335 = or(UInt<1>(0h0), _T_334) node _T_336 = and(_T_321, _T_335) node _T_337 = asUInt(reset) node _T_338 = eq(_T_337, UInt<1>(0h0)) when _T_338 : node _T_339 = eq(_T_336, UInt<1>(0h0)) when _T_339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_336, UInt<1>(0h1), "") : assert_10 node _T_340 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<1>(0h0)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_20) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_347 = shr(io.in.a.bits.source, 2) node _T_348 = eq(_T_347, UInt<1>(0h1)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_21) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_352 = and(_T_350, _T_351) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_353 = shr(io.in.a.bits.source, 2) node _T_354 = eq(_T_353, UInt<2>(0h2)) node _T_355 = leq(UInt<1>(0h0), uncommonBits_22) node _T_356 = and(_T_354, _T_355) node _T_357 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_359 = shr(io.in.a.bits.source, 2) node _T_360 = eq(_T_359, UInt<2>(0h3)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_23) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_364 = and(_T_362, _T_363) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_365 = shr(io.in.a.bits.source, 3) node _T_366 = eq(_T_365, UInt<3>(0h4)) node _T_367 = leq(UInt<1>(0h0), uncommonBits_24) node _T_368 = and(_T_366, _T_367) node _T_369 = leq(uncommonBits_24, UInt<3>(0h4)) node _T_370 = and(_T_368, _T_369) node _T_371 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_372 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_373 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_340 connect _WIRE_2[1], _T_346 connect _WIRE_2[2], _T_352 connect _WIRE_2[3], _T_358 connect _WIRE_2[4], _T_364 connect _WIRE_2[5], _T_370 connect _WIRE_2[6], _T_371 connect _WIRE_2[7], _T_372 connect _WIRE_2[8], _T_373 node _T_374 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_375 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_376 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_377 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_380 = mux(_WIRE_2[5], _T_374, UInt<1>(0h0)) node _T_381 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_383 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_384 = or(_T_375, _T_376) node _T_385 = or(_T_384, _T_377) node _T_386 = or(_T_385, _T_378) node _T_387 = or(_T_386, _T_379) node _T_388 = or(_T_387, _T_380) node _T_389 = or(_T_388, _T_381) node _T_390 = or(_T_389, _T_382) node _T_391 = or(_T_390, _T_383) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_391 node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = or(UInt<1>(0h0), _T_394) node _T_396 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_397 = cvt(_T_396) node _T_398 = and(_T_397, asSInt(UInt<13>(0h1000))) node _T_399 = asSInt(_T_398) node _T_400 = eq(_T_399, asSInt(UInt<1>(0h0))) node _T_401 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_402 = cvt(_T_401) node _T_403 = and(_T_402, asSInt(UInt<13>(0h1000))) node _T_404 = asSInt(_T_403) node _T_405 = eq(_T_404, asSInt(UInt<1>(0h0))) node _T_406 = or(_T_400, _T_405) node _T_407 = and(_T_395, _T_406) node _T_408 = or(UInt<1>(0h0), _T_407) node _T_409 = and(_WIRE_3, _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_409, UInt<1>(0h1), "") : assert_11 node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(source_ok, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_416 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_416, UInt<1>(0h1), "") : assert_13 node _T_420 = asUInt(reset) node _T_421 = eq(_T_420, UInt<1>(0h0)) when _T_421 : node _T_422 = eq(is_aligned, UInt<1>(0h0)) when _T_422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_423 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_424 = asUInt(reset) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(_T_423, UInt<1>(0h0)) when _T_426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_423, UInt<1>(0h1), "") : assert_15 node _T_427 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_427, UInt<1>(0h1), "") : assert_16 node _T_431 = not(io.in.a.bits.mask) node _T_432 = eq(_T_431, UInt<1>(0h0)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_432, UInt<1>(0h1), "") : assert_17 node _T_436 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_436, UInt<1>(0h1), "") : assert_18 node _T_440 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_440 : node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_443 = and(_T_441, _T_442) node _T_444 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_445 = shr(io.in.a.bits.source, 2) node _T_446 = eq(_T_445, UInt<1>(0h0)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_25) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_450 = and(_T_448, _T_449) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_451 = shr(io.in.a.bits.source, 2) node _T_452 = eq(_T_451, UInt<1>(0h1)) node _T_453 = leq(UInt<1>(0h0), uncommonBits_26) node _T_454 = and(_T_452, _T_453) node _T_455 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_456 = and(_T_454, _T_455) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_457 = shr(io.in.a.bits.source, 2) node _T_458 = eq(_T_457, UInt<2>(0h2)) node _T_459 = leq(UInt<1>(0h0), uncommonBits_27) node _T_460 = and(_T_458, _T_459) node _T_461 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_462 = and(_T_460, _T_461) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_463 = shr(io.in.a.bits.source, 2) node _T_464 = eq(_T_463, UInt<2>(0h3)) node _T_465 = leq(UInt<1>(0h0), uncommonBits_28) node _T_466 = and(_T_464, _T_465) node _T_467 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_468 = and(_T_466, _T_467) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_469 = shr(io.in.a.bits.source, 3) node _T_470 = eq(_T_469, UInt<3>(0h4)) node _T_471 = leq(UInt<1>(0h0), uncommonBits_29) node _T_472 = and(_T_470, _T_471) node _T_473 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_476 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_477 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_478 = or(_T_444, _T_450) node _T_479 = or(_T_478, _T_456) node _T_480 = or(_T_479, _T_462) node _T_481 = or(_T_480, _T_468) node _T_482 = or(_T_481, _T_474) node _T_483 = or(_T_482, _T_475) node _T_484 = or(_T_483, _T_476) node _T_485 = or(_T_484, _T_477) node _T_486 = and(_T_443, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_487, UInt<1>(0h1), "") : assert_19 node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_492 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_493 = and(_T_491, _T_492) node _T_494 = or(UInt<1>(0h0), _T_493) node _T_495 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_496 = cvt(_T_495) node _T_497 = and(_T_496, asSInt(UInt<13>(0h1000))) node _T_498 = asSInt(_T_497) node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0))) node _T_500 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_501 = cvt(_T_500) node _T_502 = and(_T_501, asSInt(UInt<13>(0h1000))) node _T_503 = asSInt(_T_502) node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0))) node _T_505 = or(_T_499, _T_504) node _T_506 = and(_T_494, _T_505) node _T_507 = or(UInt<1>(0h0), _T_506) node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_T_507, UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_507, UInt<1>(0h1), "") : assert_20 node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(source_ok, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(is_aligned, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_517 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_517, UInt<1>(0h1), "") : assert_23 node _T_521 = eq(io.in.a.bits.mask, mask) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_521, UInt<1>(0h1), "") : assert_24 node _T_525 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_526 = asUInt(reset) node _T_527 = eq(_T_526, UInt<1>(0h0)) when _T_527 : node _T_528 = eq(_T_525, UInt<1>(0h0)) when _T_528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_525, UInt<1>(0h1), "") : assert_25 node _T_529 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_529 : node _T_530 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_531 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_532 = and(_T_530, _T_531) node _T_533 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_534 = shr(io.in.a.bits.source, 2) node _T_535 = eq(_T_534, UInt<1>(0h0)) node _T_536 = leq(UInt<1>(0h0), uncommonBits_30) node _T_537 = and(_T_535, _T_536) node _T_538 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_539 = and(_T_537, _T_538) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_540 = shr(io.in.a.bits.source, 2) node _T_541 = eq(_T_540, UInt<1>(0h1)) node _T_542 = leq(UInt<1>(0h0), uncommonBits_31) node _T_543 = and(_T_541, _T_542) node _T_544 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_545 = and(_T_543, _T_544) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_546 = shr(io.in.a.bits.source, 2) node _T_547 = eq(_T_546, UInt<2>(0h2)) node _T_548 = leq(UInt<1>(0h0), uncommonBits_32) node _T_549 = and(_T_547, _T_548) node _T_550 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_551 = and(_T_549, _T_550) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_552 = shr(io.in.a.bits.source, 2) node _T_553 = eq(_T_552, UInt<2>(0h3)) node _T_554 = leq(UInt<1>(0h0), uncommonBits_33) node _T_555 = and(_T_553, _T_554) node _T_556 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_557 = and(_T_555, _T_556) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_558 = shr(io.in.a.bits.source, 3) node _T_559 = eq(_T_558, UInt<3>(0h4)) node _T_560 = leq(UInt<1>(0h0), uncommonBits_34) node _T_561 = and(_T_559, _T_560) node _T_562 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_563 = and(_T_561, _T_562) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_566 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_567 = or(_T_533, _T_539) node _T_568 = or(_T_567, _T_545) node _T_569 = or(_T_568, _T_551) node _T_570 = or(_T_569, _T_557) node _T_571 = or(_T_570, _T_563) node _T_572 = or(_T_571, _T_564) node _T_573 = or(_T_572, _T_565) node _T_574 = or(_T_573, _T_566) node _T_575 = and(_T_532, _T_574) node _T_576 = or(UInt<1>(0h0), _T_575) node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_578 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_579 = and(_T_577, _T_578) node _T_580 = or(UInt<1>(0h0), _T_579) node _T_581 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<13>(0h1000))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<13>(0h1000))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = or(_T_585, _T_590) node _T_592 = and(_T_580, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = and(_T_576, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_594, UInt<1>(0h1), "") : assert_26 node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(source_ok, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(is_aligned, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_604 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_604, UInt<1>(0h1), "") : assert_29 node _T_608 = eq(io.in.a.bits.mask, mask) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_608, UInt<1>(0h1), "") : assert_30 node _T_612 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_612 : node _T_613 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_614 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_615 = and(_T_613, _T_614) node _T_616 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_617 = shr(io.in.a.bits.source, 2) node _T_618 = eq(_T_617, UInt<1>(0h0)) node _T_619 = leq(UInt<1>(0h0), uncommonBits_35) node _T_620 = and(_T_618, _T_619) node _T_621 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_622 = and(_T_620, _T_621) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_623 = shr(io.in.a.bits.source, 2) node _T_624 = eq(_T_623, UInt<1>(0h1)) node _T_625 = leq(UInt<1>(0h0), uncommonBits_36) node _T_626 = and(_T_624, _T_625) node _T_627 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_629 = shr(io.in.a.bits.source, 2) node _T_630 = eq(_T_629, UInt<2>(0h2)) node _T_631 = leq(UInt<1>(0h0), uncommonBits_37) node _T_632 = and(_T_630, _T_631) node _T_633 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_634 = and(_T_632, _T_633) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_635 = shr(io.in.a.bits.source, 2) node _T_636 = eq(_T_635, UInt<2>(0h3)) node _T_637 = leq(UInt<1>(0h0), uncommonBits_38) node _T_638 = and(_T_636, _T_637) node _T_639 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_640 = and(_T_638, _T_639) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_641 = shr(io.in.a.bits.source, 3) node _T_642 = eq(_T_641, UInt<3>(0h4)) node _T_643 = leq(UInt<1>(0h0), uncommonBits_39) node _T_644 = and(_T_642, _T_643) node _T_645 = leq(uncommonBits_39, UInt<3>(0h4)) node _T_646 = and(_T_644, _T_645) node _T_647 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_648 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_649 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_650 = or(_T_616, _T_622) node _T_651 = or(_T_650, _T_628) node _T_652 = or(_T_651, _T_634) node _T_653 = or(_T_652, _T_640) node _T_654 = or(_T_653, _T_646) node _T_655 = or(_T_654, _T_647) node _T_656 = or(_T_655, _T_648) node _T_657 = or(_T_656, _T_649) node _T_658 = and(_T_615, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_661 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_662 = and(_T_660, _T_661) node _T_663 = or(UInt<1>(0h0), _T_662) node _T_664 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_665 = cvt(_T_664) node _T_666 = and(_T_665, asSInt(UInt<13>(0h1000))) node _T_667 = asSInt(_T_666) node _T_668 = eq(_T_667, asSInt(UInt<1>(0h0))) node _T_669 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_670 = cvt(_T_669) node _T_671 = and(_T_670, asSInt(UInt<13>(0h1000))) node _T_672 = asSInt(_T_671) node _T_673 = eq(_T_672, asSInt(UInt<1>(0h0))) node _T_674 = or(_T_668, _T_673) node _T_675 = and(_T_663, _T_674) node _T_676 = or(UInt<1>(0h0), _T_675) node _T_677 = and(_T_659, _T_676) node _T_678 = asUInt(reset) node _T_679 = eq(_T_678, UInt<1>(0h0)) when _T_679 : node _T_680 = eq(_T_677, UInt<1>(0h0)) when _T_680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_677, UInt<1>(0h1), "") : assert_31 node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(source_ok, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_684 = asUInt(reset) node _T_685 = eq(_T_684, UInt<1>(0h0)) when _T_685 : node _T_686 = eq(is_aligned, UInt<1>(0h0)) when _T_686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_687 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_688 = asUInt(reset) node _T_689 = eq(_T_688, UInt<1>(0h0)) when _T_689 : node _T_690 = eq(_T_687, UInt<1>(0h0)) when _T_690 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_687, UInt<1>(0h1), "") : assert_34 node _T_691 = not(mask) node _T_692 = and(io.in.a.bits.mask, _T_691) node _T_693 = eq(_T_692, UInt<1>(0h0)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_693, UInt<1>(0h1), "") : assert_35 node _T_697 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_697 : node _T_698 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_699 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_700 = and(_T_698, _T_699) node _T_701 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_702 = shr(io.in.a.bits.source, 2) node _T_703 = eq(_T_702, UInt<1>(0h0)) node _T_704 = leq(UInt<1>(0h0), uncommonBits_40) node _T_705 = and(_T_703, _T_704) node _T_706 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_707 = and(_T_705, _T_706) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_708 = shr(io.in.a.bits.source, 2) node _T_709 = eq(_T_708, UInt<1>(0h1)) node _T_710 = leq(UInt<1>(0h0), uncommonBits_41) node _T_711 = and(_T_709, _T_710) node _T_712 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_713 = and(_T_711, _T_712) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_714 = shr(io.in.a.bits.source, 2) node _T_715 = eq(_T_714, UInt<2>(0h2)) node _T_716 = leq(UInt<1>(0h0), uncommonBits_42) node _T_717 = and(_T_715, _T_716) node _T_718 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_719 = and(_T_717, _T_718) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_720 = shr(io.in.a.bits.source, 2) node _T_721 = eq(_T_720, UInt<2>(0h3)) node _T_722 = leq(UInt<1>(0h0), uncommonBits_43) node _T_723 = and(_T_721, _T_722) node _T_724 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_725 = and(_T_723, _T_724) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_726 = shr(io.in.a.bits.source, 3) node _T_727 = eq(_T_726, UInt<3>(0h4)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_44) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_44, UInt<3>(0h4)) node _T_731 = and(_T_729, _T_730) node _T_732 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_733 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_734 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_735 = or(_T_701, _T_707) node _T_736 = or(_T_735, _T_713) node _T_737 = or(_T_736, _T_719) node _T_738 = or(_T_737, _T_725) node _T_739 = or(_T_738, _T_731) node _T_740 = or(_T_739, _T_732) node _T_741 = or(_T_740, _T_733) node _T_742 = or(_T_741, _T_734) node _T_743 = and(_T_700, _T_742) node _T_744 = or(UInt<1>(0h0), _T_743) node _T_745 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_746 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<13>(0h1000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = or(_T_750, _T_755) node _T_757 = and(_T_745, _T_756) node _T_758 = or(UInt<1>(0h0), _T_757) node _T_759 = and(_T_744, _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_759, UInt<1>(0h1), "") : assert_36 node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(source_ok, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(is_aligned, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_769 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_769, UInt<1>(0h1), "") : assert_39 node _T_773 = eq(io.in.a.bits.mask, mask) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_773, UInt<1>(0h1), "") : assert_40 node _T_777 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_777 : node _T_778 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_779 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_780 = and(_T_778, _T_779) node _T_781 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_782 = shr(io.in.a.bits.source, 2) node _T_783 = eq(_T_782, UInt<1>(0h0)) node _T_784 = leq(UInt<1>(0h0), uncommonBits_45) node _T_785 = and(_T_783, _T_784) node _T_786 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_787 = and(_T_785, _T_786) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_788 = shr(io.in.a.bits.source, 2) node _T_789 = eq(_T_788, UInt<1>(0h1)) node _T_790 = leq(UInt<1>(0h0), uncommonBits_46) node _T_791 = and(_T_789, _T_790) node _T_792 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_794 = shr(io.in.a.bits.source, 2) node _T_795 = eq(_T_794, UInt<2>(0h2)) node _T_796 = leq(UInt<1>(0h0), uncommonBits_47) node _T_797 = and(_T_795, _T_796) node _T_798 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_799 = and(_T_797, _T_798) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_800 = shr(io.in.a.bits.source, 2) node _T_801 = eq(_T_800, UInt<2>(0h3)) node _T_802 = leq(UInt<1>(0h0), uncommonBits_48) node _T_803 = and(_T_801, _T_802) node _T_804 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_805 = and(_T_803, _T_804) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_806 = shr(io.in.a.bits.source, 3) node _T_807 = eq(_T_806, UInt<3>(0h4)) node _T_808 = leq(UInt<1>(0h0), uncommonBits_49) node _T_809 = and(_T_807, _T_808) node _T_810 = leq(uncommonBits_49, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_814 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_815 = or(_T_781, _T_787) node _T_816 = or(_T_815, _T_793) node _T_817 = or(_T_816, _T_799) node _T_818 = or(_T_817, _T_805) node _T_819 = or(_T_818, _T_811) node _T_820 = or(_T_819, _T_812) node _T_821 = or(_T_820, _T_813) node _T_822 = or(_T_821, _T_814) node _T_823 = and(_T_780, _T_822) node _T_824 = or(UInt<1>(0h0), _T_823) node _T_825 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_826 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<13>(0h1000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_832 = cvt(_T_831) node _T_833 = and(_T_832, asSInt(UInt<13>(0h1000))) node _T_834 = asSInt(_T_833) node _T_835 = eq(_T_834, asSInt(UInt<1>(0h0))) node _T_836 = or(_T_830, _T_835) node _T_837 = and(_T_825, _T_836) node _T_838 = or(UInt<1>(0h0), _T_837) node _T_839 = and(_T_824, _T_838) node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(_T_839, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_839, UInt<1>(0h1), "") : assert_41 node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(source_ok, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(is_aligned, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_849 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_849, UInt<1>(0h1), "") : assert_44 node _T_853 = eq(io.in.a.bits.mask, mask) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_853, UInt<1>(0h1), "") : assert_45 node _T_857 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_857 : node _T_858 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_859 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_860 = and(_T_858, _T_859) node _T_861 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_862 = shr(io.in.a.bits.source, 2) node _T_863 = eq(_T_862, UInt<1>(0h0)) node _T_864 = leq(UInt<1>(0h0), uncommonBits_50) node _T_865 = and(_T_863, _T_864) node _T_866 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_867 = and(_T_865, _T_866) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_868 = shr(io.in.a.bits.source, 2) node _T_869 = eq(_T_868, UInt<1>(0h1)) node _T_870 = leq(UInt<1>(0h0), uncommonBits_51) node _T_871 = and(_T_869, _T_870) node _T_872 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_873 = and(_T_871, _T_872) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_874 = shr(io.in.a.bits.source, 2) node _T_875 = eq(_T_874, UInt<2>(0h2)) node _T_876 = leq(UInt<1>(0h0), uncommonBits_52) node _T_877 = and(_T_875, _T_876) node _T_878 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<2>(0h3)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_53) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_886 = shr(io.in.a.bits.source, 3) node _T_887 = eq(_T_886, UInt<3>(0h4)) node _T_888 = leq(UInt<1>(0h0), uncommonBits_54) node _T_889 = and(_T_887, _T_888) node _T_890 = leq(uncommonBits_54, UInt<3>(0h4)) node _T_891 = and(_T_889, _T_890) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_895 = or(_T_861, _T_867) node _T_896 = or(_T_895, _T_873) node _T_897 = or(_T_896, _T_879) node _T_898 = or(_T_897, _T_885) node _T_899 = or(_T_898, _T_891) node _T_900 = or(_T_899, _T_892) node _T_901 = or(_T_900, _T_893) node _T_902 = or(_T_901, _T_894) node _T_903 = and(_T_860, _T_902) node _T_904 = or(UInt<1>(0h0), _T_903) node _T_905 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_906 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<13>(0h1000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = or(_T_910, _T_915) node _T_917 = and(_T_905, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = and(_T_904, _T_918) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_919, UInt<1>(0h1), "") : assert_46 node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(source_ok, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(is_aligned, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_929 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_929, UInt<1>(0h1), "") : assert_49 node _T_933 = eq(io.in.a.bits.mask, mask) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_933, UInt<1>(0h1), "") : assert_50 node _T_937 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_937, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_941 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_941, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 3) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<3>(0h4)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<3>(0h4)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_945 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_945 : node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok_1, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_949 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_949, UInt<1>(0h1), "") : assert_54 node _T_953 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_953, UInt<1>(0h1), "") : assert_55 node _T_957 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_957, UInt<1>(0h1), "") : assert_56 node _T_961 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_961, UInt<1>(0h1), "") : assert_57 node _T_965 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_965 : node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(source_ok_1, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(sink_ok, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_972 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_972, UInt<1>(0h1), "") : assert_60 node _T_976 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_976, UInt<1>(0h1), "") : assert_61 node _T_980 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_980, UInt<1>(0h1), "") : assert_62 node _T_984 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_984, UInt<1>(0h1), "") : assert_63 node _T_988 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_989 = or(UInt<1>(0h0), _T_988) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_989, UInt<1>(0h1), "") : assert_64 node _T_993 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_993 : node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(source_ok_1, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(sink_ok, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1000 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_67 node _T_1004 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_68 node _T_1008 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_69 node _T_1012 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1013 = or(_T_1012, io.in.d.bits.corrupt) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_70 node _T_1017 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1018 = or(UInt<1>(0h0), _T_1017) node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_T_1018, UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1018, UInt<1>(0h1), "") : assert_71 node _T_1022 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1022 : node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(source_ok_1, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1026 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_73 node _T_1030 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_74 node _T_1034 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1035 = or(UInt<1>(0h0), _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_75 node _T_1039 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1039 : node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(source_ok_1, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1043 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(_T_1043, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1043, UInt<1>(0h1), "") : assert_77 node _T_1047 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1048 = or(_T_1047, io.in.d.bits.corrupt) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_78 node _T_1052 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1053 = or(UInt<1>(0h0), _T_1052) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_79 node _T_1057 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1057 : node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(source_ok_1, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1061 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_81 node _T_1065 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_82 node _T_1069 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1070 = or(UInt<1>(0h0), _T_1069) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1074 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1078 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1082 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1086 = eq(a_first, UInt<1>(0h0)) node _T_1087 = and(io.in.a.valid, _T_1086) when _T_1087 : node _T_1088 = eq(io.in.a.bits.opcode, opcode) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_87 node _T_1092 = eq(io.in.a.bits.param, param) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_88 node _T_1096 = eq(io.in.a.bits.size, size) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_89 node _T_1100 = eq(io.in.a.bits.source, source) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_90 node _T_1104 = eq(io.in.a.bits.address, address) node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(_T_1104, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1104, UInt<1>(0h1), "") : assert_91 node _T_1108 = and(io.in.a.ready, io.in.a.valid) node _T_1109 = and(_T_1108, a_first) when _T_1109 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1110 = eq(d_first, UInt<1>(0h0)) node _T_1111 = and(io.in.d.valid, _T_1110) when _T_1111 : node _T_1112 = eq(io.in.d.bits.opcode, opcode_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_92 node _T_1116 = eq(io.in.d.bits.param, param_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_93 node _T_1120 = eq(io.in.d.bits.size, size_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_94 node _T_1124 = eq(io.in.d.bits.source, source_1) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_95 node _T_1128 = eq(io.in.d.bits.sink, sink) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_96 node _T_1132 = eq(io.in.d.bits.denied, denied) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_97 node _T_1136 = and(io.in.d.ready, io.in.d.valid) node _T_1137 = and(_T_1136, d_first) when _T_1137 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1138 = and(io.in.a.valid, a_first_1) node _T_1139 = and(_T_1138, UInt<1>(0h1)) when _T_1139 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1140 = and(io.in.a.ready, io.in.a.valid) node _T_1141 = and(_T_1140, a_first_1) node _T_1142 = and(_T_1141, UInt<1>(0h1)) when _T_1142 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1143 = dshr(inflight, io.in.a.bits.source) node _T_1144 = bits(_T_1143, 0, 0) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1149 = and(io.in.d.valid, d_first_1) node _T_1150 = and(_T_1149, UInt<1>(0h1)) node _T_1151 = eq(d_release_ack, UInt<1>(0h0)) node _T_1152 = and(_T_1150, _T_1151) when _T_1152 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1153 = and(io.in.d.ready, io.in.d.valid) node _T_1154 = and(_T_1153, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1158 = and(io.in.d.valid, d_first_1) node _T_1159 = and(_T_1158, UInt<1>(0h1)) node _T_1160 = eq(d_release_ack, UInt<1>(0h0)) node _T_1161 = and(_T_1159, _T_1160) when _T_1161 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1162 = dshr(inflight, io.in.d.bits.source) node _T_1163 = bits(_T_1162, 0, 0) node _T_1164 = or(_T_1163, same_cycle_resp) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1168 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1169 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1170 = or(_T_1168, _T_1169) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_100 node _T_1174 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1175 = asUInt(reset) node _T_1176 = eq(_T_1175, UInt<1>(0h0)) when _T_1176 : node _T_1177 = eq(_T_1174, UInt<1>(0h0)) when _T_1177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1174, UInt<1>(0h1), "") : assert_101 else : node _T_1178 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1179 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1180 = or(_T_1178, _T_1179) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_102 node _T_1184 = eq(io.in.d.bits.size, a_size_lookup) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_103 node _T_1188 = and(io.in.d.valid, d_first_1) node _T_1189 = and(_T_1188, a_first_1) node _T_1190 = and(_T_1189, io.in.a.valid) node _T_1191 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = eq(d_release_ack, UInt<1>(0h0)) node _T_1194 = and(_T_1192, _T_1193) when _T_1194 : node _T_1195 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1196 = or(_T_1195, io.in.a.ready) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_8 node _T_1200 = orr(inflight) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) node _T_1202 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1203 = or(_T_1201, _T_1202) node _T_1204 = lt(watchdog, plusarg_reader.out) node _T_1205 = or(_T_1203, _T_1204) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1209 = and(io.in.a.ready, io.in.a.valid) node _T_1210 = and(io.in.d.ready, io.in.d.valid) node _T_1211 = or(_T_1209, _T_1210) when _T_1211 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1212 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1213 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1214 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = and(_T_1212, _T_1215) when _T_1216 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1217 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1218 = and(_T_1217, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1219 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1220 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1221 = and(_T_1219, _T_1220) node _T_1222 = and(_T_1218, _T_1221) when _T_1222 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1223 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1224 = bits(_T_1223, 0, 0) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1229 = and(io.in.d.valid, d_first_2) node _T_1230 = and(_T_1229, UInt<1>(0h1)) node _T_1231 = and(_T_1230, d_release_ack_1) when _T_1231 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1232 = and(io.in.d.ready, io.in.d.valid) node _T_1233 = and(_T_1232, d_first_2) node _T_1234 = and(_T_1233, UInt<1>(0h1)) node _T_1235 = and(_T_1234, d_release_ack_1) when _T_1235 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1236 = and(io.in.d.valid, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1239 = dshr(inflight_1, io.in.d.bits.source) node _T_1240 = bits(_T_1239, 0, 0) node _T_1241 = or(_T_1240, same_cycle_resp_1) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1245 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_108 else : node _T_1249 = eq(io.in.d.bits.size, c_size_lookup) node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(_T_1249, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1249, UInt<1>(0h1), "") : assert_109 node _T_1253 = and(io.in.d.valid, d_first_2) node _T_1254 = and(_T_1253, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1255 = and(_T_1254, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1256 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1257 = and(_T_1255, _T_1256) node _T_1258 = and(_T_1257, d_release_ack_1) node _T_1259 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1260 = and(_T_1258, _T_1259) when _T_1260 : node _T_1261 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1262 = or(_T_1261, _WIRE_27.ready) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_9 node _T_1266 = orr(inflight_1) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) node _T_1268 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1269 = or(_T_1267, _T_1268) node _T_1270 = lt(watchdog_1, plusarg_reader_1.out) node _T_1271 = or(_T_1269, _T_1270) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1275 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1276 = and(io.in.d.ready, io.in.d.valid) node _T_1277 = or(_T_1275, _T_1276) when _T_1277 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_4( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_66 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_67 = _source_ok_T_66 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1209 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1209; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1209; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1277 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1277; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1277; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1277; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1142 = _T_1209 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1142 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1142 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1142 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1142 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1142 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1188 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1188 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1157 = _T_1277 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1157 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1157 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1157 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1253 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1253 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1235 = _T_1277 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1235 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1235 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1235 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_45 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_301 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_45( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_301 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_2 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg	module AsyncResetRegVec_w1_i0_2( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_11 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 55, 55) wire common_expOut : UInt<12> wire common_fractOut : UInt<52> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 11, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 11, 11) node roundMask_lsbs = bits(_roundMask_T_1, 10, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 10, 10) node roundMask_lsbs_1 = bits(roundMask_lsbs, 9, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 9, 9) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 8, 0) node roundMask_msb_3 = bits(roundMask_lsbs_2, 8, 8) node roundMask_lsbs_3 = bits(roundMask_lsbs_2, 7, 0) node roundMask_msb_4 = bits(roundMask_lsbs_3, 7, 7) node roundMask_lsbs_4 = bits(roundMask_lsbs_3, 6, 0) node roundMask_msb_5 = bits(roundMask_lsbs_4, 6, 6) node roundMask_lsbs_5 = bits(roundMask_lsbs_4, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_5) node _roundMask_T_2 = bits(roundMask_shift, 63, 13) node _roundMask_T_3 = bits(_roundMask_T_2, 31, 0) node _roundMask_T_4 = shl(UInt<16>(0hffff), 16) node _roundMask_T_5 = xor(UInt<32>(0hffffffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 16) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 15, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 16) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 23, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 8) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 8) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 23, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 8) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 27, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 4) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 4) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 27, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 4) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 29, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 2) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 2) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 29, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 2) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_35, 30, 0) node _roundMask_T_44 = shl(_roundMask_T_43, 1) node _roundMask_T_45 = xor(_roundMask_T_35, _roundMask_T_44) node _roundMask_T_46 = shr(_roundMask_T_42, 1) node _roundMask_T_47 = and(_roundMask_T_46, _roundMask_T_45) node _roundMask_T_48 = bits(_roundMask_T_42, 30, 0) node _roundMask_T_49 = shl(_roundMask_T_48, 1) node _roundMask_T_50 = not(_roundMask_T_45) node _roundMask_T_51 = and(_roundMask_T_49, _roundMask_T_50) node _roundMask_T_52 = or(_roundMask_T_47, _roundMask_T_51) node _roundMask_T_53 = bits(_roundMask_T_2, 50, 32) node _roundMask_T_54 = bits(_roundMask_T_53, 15, 0) node _roundMask_T_55 = shl(UInt<8>(0hff), 8) node _roundMask_T_56 = xor(UInt<16>(0hffff), _roundMask_T_55) node _roundMask_T_57 = shr(_roundMask_T_54, 8) node _roundMask_T_58 = and(_roundMask_T_57, _roundMask_T_56) node _roundMask_T_59 = bits(_roundMask_T_54, 7, 0) node _roundMask_T_60 = shl(_roundMask_T_59, 8) node _roundMask_T_61 = not(_roundMask_T_56) node _roundMask_T_62 = and(_roundMask_T_60, _roundMask_T_61) node _roundMask_T_63 = or(_roundMask_T_58, _roundMask_T_62) node _roundMask_T_64 = bits(_roundMask_T_56, 11, 0) node _roundMask_T_65 = shl(_roundMask_T_64, 4) node _roundMask_T_66 = xor(_roundMask_T_56, _roundMask_T_65) node _roundMask_T_67 = shr(_roundMask_T_63, 4) node _roundMask_T_68 = and(_roundMask_T_67, _roundMask_T_66) node _roundMask_T_69 = bits(_roundMask_T_63, 11, 0) node _roundMask_T_70 = shl(_roundMask_T_69, 4) node _roundMask_T_71 = not(_roundMask_T_66) node _roundMask_T_72 = and(_roundMask_T_70, _roundMask_T_71) node _roundMask_T_73 = or(_roundMask_T_68, _roundMask_T_72) node _roundMask_T_74 = bits(_roundMask_T_66, 13, 0) node _roundMask_T_75 = shl(_roundMask_T_74, 2) node _roundMask_T_76 = xor(_roundMask_T_66, _roundMask_T_75) node _roundMask_T_77 = shr(_roundMask_T_73, 2) node _roundMask_T_78 = and(_roundMask_T_77, _roundMask_T_76) node _roundMask_T_79 = bits(_roundMask_T_73, 13, 0) node _roundMask_T_80 = shl(_roundMask_T_79, 2) node _roundMask_T_81 = not(_roundMask_T_76) node _roundMask_T_82 = and(_roundMask_T_80, _roundMask_T_81) node _roundMask_T_83 = or(_roundMask_T_78, _roundMask_T_82) node _roundMask_T_84 = bits(_roundMask_T_76, 14, 0) node _roundMask_T_85 = shl(_roundMask_T_84, 1) node _roundMask_T_86 = xor(_roundMask_T_76, _roundMask_T_85) node _roundMask_T_87 = shr(_roundMask_T_83, 1) node _roundMask_T_88 = and(_roundMask_T_87, _roundMask_T_86) node _roundMask_T_89 = bits(_roundMask_T_83, 14, 0) node _roundMask_T_90 = shl(_roundMask_T_89, 1) node _roundMask_T_91 = not(_roundMask_T_86) node _roundMask_T_92 = and(_roundMask_T_90, _roundMask_T_91) node _roundMask_T_93 = or(_roundMask_T_88, _roundMask_T_92) node _roundMask_T_94 = bits(_roundMask_T_53, 18, 16) node _roundMask_T_95 = bits(_roundMask_T_94, 1, 0) node _roundMask_T_96 = bits(_roundMask_T_95, 0, 0) node _roundMask_T_97 = bits(_roundMask_T_95, 1, 1) node _roundMask_T_98 = cat(_roundMask_T_96, _roundMask_T_97) node _roundMask_T_99 = bits(_roundMask_T_94, 2, 2) node _roundMask_T_100 = cat(_roundMask_T_98, _roundMask_T_99) node _roundMask_T_101 = cat(_roundMask_T_93, _roundMask_T_100) node _roundMask_T_102 = cat(_roundMask_T_52, _roundMask_T_101) node _roundMask_T_103 = not(_roundMask_T_102) node _roundMask_T_104 = mux(roundMask_msb_5, UInt<1>(0h0), _roundMask_T_103) node _roundMask_T_105 = not(_roundMask_T_104) node _roundMask_T_106 = not(_roundMask_T_105) node _roundMask_T_107 = mux(roundMask_msb_4, UInt<1>(0h0), _roundMask_T_106) node _roundMask_T_108 = not(_roundMask_T_107) node _roundMask_T_109 = not(_roundMask_T_108) node _roundMask_T_110 = mux(roundMask_msb_3, UInt<1>(0h0), _roundMask_T_109) node _roundMask_T_111 = not(_roundMask_T_110) node _roundMask_T_112 = not(_roundMask_T_111) node _roundMask_T_113 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_112) node _roundMask_T_114 = not(_roundMask_T_113) node _roundMask_T_115 = cat(_roundMask_T_114, UInt<3>(0h7)) node roundMask_msb_6 = bits(roundMask_lsbs_1, 9, 9) node roundMask_lsbs_6 = bits(roundMask_lsbs_1, 8, 0) node roundMask_msb_7 = bits(roundMask_lsbs_6, 8, 8) node roundMask_lsbs_7 = bits(roundMask_lsbs_6, 7, 0) node roundMask_msb_8 = bits(roundMask_lsbs_7, 7, 7) node roundMask_lsbs_8 = bits(roundMask_lsbs_7, 6, 0) node roundMask_msb_9 = bits(roundMask_lsbs_8, 6, 6) node roundMask_lsbs_9 = bits(roundMask_lsbs_8, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_9) node _roundMask_T_116 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_117 = bits(_roundMask_T_116, 1, 0) node _roundMask_T_118 = bits(_roundMask_T_117, 0, 0) node _roundMask_T_119 = bits(_roundMask_T_117, 1, 1) node _roundMask_T_120 = cat(_roundMask_T_118, _roundMask_T_119) node _roundMask_T_121 = bits(_roundMask_T_116, 2, 2) node _roundMask_T_122 = cat(_roundMask_T_120, _roundMask_T_121) node _roundMask_T_123 = mux(roundMask_msb_9, _roundMask_T_122, UInt<1>(0h0)) node _roundMask_T_124 = mux(roundMask_msb_8, _roundMask_T_123, UInt<1>(0h0)) node _roundMask_T_125 = mux(roundMask_msb_7, _roundMask_T_124, UInt<1>(0h0)) node _roundMask_T_126 = mux(roundMask_msb_6, _roundMask_T_125, UInt<1>(0h0)) node _roundMask_T_127 = mux(roundMask_msb_1, _roundMask_T_115, _roundMask_T_126) node _roundMask_T_128 = mux(roundMask_msb, _roundMask_T_127, UInt<1>(0h0)) node _roundMask_T_129 = or(_roundMask_T_128, doShiftSigDown1) node roundMask = cat(_roundMask_T_129, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<55>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 53) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 11, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 52, 1) node _common_fractOut_T_1 = bits(roundedSig, 51, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 10) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<11>(0h3ce))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 54, 54) node _roundCarry_T_1 = bits(roundedSig, 53, 53) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 11) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<12>(0he00), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<12>(0h3ce)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<12>(0h400), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<12>(0h200), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<12>(0h3ce), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<12>(0hbff), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<12>(0hc00), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<12>(0he00), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<52>(0h8000000000000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<52>(0hfffffffffffff), UInt<52>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_11( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [31:0] _roundMask_T_5 = 32'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_4 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_10 = 32'hFFFF0000; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_13 = 24'hFFFF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_14 = 32'hFFFF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_15 = 32'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_20 = 32'hFF00FF00; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_23 = 28'hFF00FF; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_24 = 32'hFF00FF0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_25 = 32'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_30 = 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_33 = 30'hF0F0F0F; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_34 = 32'h3C3C3C3C; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_35 = 32'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_40 = 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_43 = 31'h33333333; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_44 = 32'h66666666; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_45 = 32'h55555555; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_50 = 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_56 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_55 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_61 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_64 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_65 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_66 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_71 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_74 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_75 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_76 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_81 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_84 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_85 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_86 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_91 = 16'hAAAA; // @[primitives.scala:77:20] wire [11:0] _expOut_T_4 = 12'hC31; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire [55:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [64:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[55]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [11:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [11:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [51:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [51:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [11:0] _roundMask_T = io_in_sExp_0[11:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [11:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[11]; // @[primitives.scala:52:21, :58:25] wire [10:0] roundMask_lsbs = _roundMask_T_1[10:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[10]; // @[primitives.scala:58:25, :59:26] wire [9:0] roundMask_lsbs_1 = roundMask_lsbs[9:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_6 = roundMask_lsbs_1[9]; // @[primitives.scala:58:25, :59:26] wire [8:0] roundMask_lsbs_2 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire [8:0] roundMask_lsbs_6 = roundMask_lsbs_1[8:0]; // @[primitives.scala:59:26] wire roundMask_msb_3 = roundMask_lsbs_2[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_3 = roundMask_lsbs_2[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_4 = roundMask_lsbs_3[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_4 = roundMask_lsbs_3[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_5 = roundMask_lsbs_4[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_5 = roundMask_lsbs_4[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_5); // @[primitives.scala:59:26, :76:56] wire [50:0] _roundMask_T_2 = roundMask_shift[63:13]; // @[primitives.scala:76:56, :78:22] wire [31:0] _roundMask_T_3 = _roundMask_T_2[31:0]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_6 = _roundMask_T_3[31:16]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_7 = {16'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_8 = _roundMask_T_3[15:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_9 = {_roundMask_T_8, 16'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_11 = _roundMask_T_9 & 32'hFFFF0000; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_16 = _roundMask_T_12[31:8]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_17 = {8'h0, _roundMask_T_16 & 24'hFF00FF}; // @[primitives.scala:77:20] wire [23:0] _roundMask_T_18 = _roundMask_T_12[23:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_19 = {_roundMask_T_18, 8'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_21 = _roundMask_T_19 & 32'hFF00FF00; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_26 = _roundMask_T_22[31:4]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_27 = {4'h0, _roundMask_T_26 & 28'hF0F0F0F}; // @[primitives.scala:77:20] wire [27:0] _roundMask_T_28 = _roundMask_T_22[27:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_29 = {_roundMask_T_28, 4'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_31 = _roundMask_T_29 & 32'hF0F0F0F0; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_36 = _roundMask_T_32[31:2]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_37 = {2'h0, _roundMask_T_36 & 30'h33333333}; // @[primitives.scala:77:20] wire [29:0] _roundMask_T_38 = _roundMask_T_32[29:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_39 = {_roundMask_T_38, 2'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_41 = _roundMask_T_39 & 32'hCCCCCCCC; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_46 = _roundMask_T_42[31:1]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_47 = {1'h0, _roundMask_T_46 & 31'h55555555}; // @[primitives.scala:77:20] wire [30:0] _roundMask_T_48 = _roundMask_T_42[30:0]; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_49 = {_roundMask_T_48, 1'h0}; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_51 = _roundMask_T_49 & 32'hAAAAAAAA; // @[primitives.scala:77:20] wire [31:0] _roundMask_T_52 = _roundMask_T_47 \| _roundMask_T_51; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_53 = _roundMask_T_2[50:32]; // @[primitives.scala:77:20, :78:22] wire [15:0] _roundMask_T_54 = _roundMask_T_53[15:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_57 = _roundMask_T_54[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_58 = {8'h0, _roundMask_T_57}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_59 = _roundMask_T_54[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_60 = {_roundMask_T_59, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_62 = _roundMask_T_60 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_63 = _roundMask_T_58 \| _roundMask_T_62; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_67 = _roundMask_T_63[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_68 = {4'h0, _roundMask_T_67 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_69 = _roundMask_T_63[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_70 = {_roundMask_T_69, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_72 = _roundMask_T_70 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_73 = _roundMask_T_68 \| _roundMask_T_72; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_77 = _roundMask_T_73[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_78 = {2'h0, _roundMask_T_77 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_79 = _roundMask_T_73[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_80 = {_roundMask_T_79, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_82 = _roundMask_T_80 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_83 = _roundMask_T_78 \| _roundMask_T_82; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_87 = _roundMask_T_83[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_88 = {1'h0, _roundMask_T_87 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_89 = _roundMask_T_83[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_90 = {_roundMask_T_89, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_92 = _roundMask_T_90 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_93 = _roundMask_T_88 \| _roundMask_T_92; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_94 = _roundMask_T_53[18:16]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_95 = _roundMask_T_94[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_96 = _roundMask_T_95[0]; // @[primitives.scala:77:20] wire _roundMask_T_97 = _roundMask_T_95[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_98 = {_roundMask_T_96, _roundMask_T_97}; // @[primitives.scala:77:20] wire _roundMask_T_99 = _roundMask_T_94[2]; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_100 = {_roundMask_T_98, _roundMask_T_99}; // @[primitives.scala:77:20] wire [18:0] _roundMask_T_101 = {_roundMask_T_93, _roundMask_T_100}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_102 = {_roundMask_T_52, _roundMask_T_101}; // @[primitives.scala:77:20] wire [50:0] _roundMask_T_103 = ~_roundMask_T_102; // @[primitives.scala:73:32, :77:20] wire [50:0] _roundMask_T_104 = roundMask_msb_5 ? 51'h0 : _roundMask_T_103; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_105 = ~_roundMask_T_104; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_106 = ~_roundMask_T_105; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_107 = roundMask_msb_4 ? 51'h0 : _roundMask_T_106; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_108 = ~_roundMask_T_107; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_109 = ~_roundMask_T_108; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_110 = roundMask_msb_3 ? 51'h0 : _roundMask_T_109; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_111 = ~_roundMask_T_110; // @[primitives.scala:73:{17,21}] wire [50:0] _roundMask_T_112 = ~_roundMask_T_111; // @[primitives.scala:73:{17,32}] wire [50:0] _roundMask_T_113 = roundMask_msb_2 ? 51'h0 : _roundMask_T_112; // @[primitives.scala:58:25, :73:{21,32}] wire [50:0] _roundMask_T_114 = ~_roundMask_T_113; // @[primitives.scala:73:{17,21}] wire [53:0] _roundMask_T_115 = {_roundMask_T_114, 3'h7}; // @[primitives.scala:68:58, :73:17] wire roundMask_msb_7 = roundMask_lsbs_6[8]; // @[primitives.scala:58:25, :59:26] wire [7:0] roundMask_lsbs_7 = roundMask_lsbs_6[7:0]; // @[primitives.scala:59:26] wire roundMask_msb_8 = roundMask_lsbs_7[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_8 = roundMask_lsbs_7[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_9 = roundMask_lsbs_8[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_9 = roundMask_lsbs_8[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_9); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_116 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_117 = _roundMask_T_116[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_118 = _roundMask_T_117[0]; // @[primitives.scala:77:20] wire _roundMask_T_119 = _roundMask_T_117[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_120 = {_roundMask_T_118, _roundMask_T_119}; // @[primitives.scala:77:20] wire _roundMask_T_121 = _roundMask_T_116[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_122 = {_roundMask_T_120, _roundMask_T_121}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_123 = roundMask_msb_9 ? _roundMask_T_122 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [2:0] _roundMask_T_124 = roundMask_msb_8 ? _roundMask_T_123 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_125 = roundMask_msb_7 ? _roundMask_T_124 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [2:0] _roundMask_T_126 = roundMask_msb_6 ? _roundMask_T_125 : 3'h0; // @[primitives.scala:58:25, :62:24] wire [53:0] _roundMask_T_127 = roundMask_msb_1 ? _roundMask_T_115 : {51'h0, _roundMask_T_126}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [53:0] _roundMask_T_128 = roundMask_msb ? _roundMask_T_127 : 54'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [53:0] _roundMask_T_129 = {_roundMask_T_128[53:1], _roundMask_T_128[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [55:0] roundMask = {_roundMask_T_129, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [56:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [55:0] shiftedRoundMask = _shiftedRoundMask_T[56:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [55:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [55:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [55:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [55:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [55:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [53:0] _roundedSig_T_1 = _roundedSig_T[55:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [54:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 55'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [54:0] _roundedSig_T_6 = roundMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [54:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [54:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [54:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [55:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [55:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [53:0] _roundedSig_T_12 = _roundedSig_T_11[55:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [54:0] _roundedSig_T_14 = roundPosMask[55:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [54:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 55'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [54:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [54:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[54:53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [13:0] sRoundedExp = {io_in_sExp_0[12], io_in_sExp_0} + {{11{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[11:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [51:0] _common_fractOut_T = roundedSig[52:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [51:0] _common_fractOut_T_1 = roundedSig[51:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[13:10]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 14'sh3CE; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[54]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[53]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[12:11]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire notNaN_isSpecialInfOut = io_infiniteExc_0 \| io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [11:0] _expOut_T_1 = _expOut_T ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [11:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [11:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [11:0] _expOut_T_5 = pegMinNonzeroMagOut ? 12'hC31 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [11:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [11:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [11:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 10'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [11:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [11:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [11:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [11:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [11:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [11:0] _expOut_T_14 = pegMinNonzeroMagOut ? 12'h3CE : 12'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [11:0] _expOut_T_15 = _expOut_T_13 \| _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [11:0] _expOut_T_16 = pegMaxFiniteMagOut ? 12'hBFF : 12'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [11:0] _expOut_T_17 = _expOut_T_15 \| _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [11:0] _expOut_T_18 = notNaN_isInfOut ? 12'hC00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [11:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [11:0] _expOut_T_20 = isNaNOut ? 12'hE00 : 12'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [11:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [51:0] _fractOut_T_2 = {isNaNOut, 51'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [51:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [51:0] _fractOut_T_4 = {52{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [51:0] fractOut = _fractOut_T_3 \| _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [12:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_14 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) wire _source_ok_WIRE : UInt<1>[5] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 node _source_ok_T_25 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_26 = or(_source_ok_T_25, _source_ok_WIRE[2]) node _source_ok_T_27 = or(_source_ok_T_26, _source_ok_WIRE[3]) node source_ok = or(_source_ok_T_27, _source_ok_WIRE[4]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = and(_T_11, _T_24) node _T_65 = and(_T_64, _T_37) node _T_66 = and(_T_65, _T_50) node _T_67 = and(_T_66, _T_63) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_67, UInt<1>(0h1), "") : assert_1 node _T_71 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_71 : node _T_72 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_73 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_76 = shr(io.in.a.bits.source, 2) node _T_77 = eq(_T_76, UInt<1>(0h0)) node _T_78 = leq(UInt<1>(0h0), uncommonBits_4) node _T_79 = and(_T_77, _T_78) node _T_80 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_81 = and(_T_79, _T_80) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_82 = shr(io.in.a.bits.source, 2) node _T_83 = eq(_T_82, UInt<1>(0h1)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_5) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_87 = and(_T_85, _T_86) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_88 = shr(io.in.a.bits.source, 2) node _T_89 = eq(_T_88, UInt<2>(0h2)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_6) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_93 = and(_T_91, _T_92) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_94 = shr(io.in.a.bits.source, 2) node _T_95 = eq(_T_94, UInt<2>(0h3)) node _T_96 = leq(UInt<1>(0h0), uncommonBits_7) node _T_97 = and(_T_95, _T_96) node _T_98 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(_T_75, _T_81) node _T_101 = or(_T_100, _T_87) node _T_102 = or(_T_101, _T_93) node _T_103 = or(_T_102, _T_99) node _T_104 = and(_T_74, _T_103) node _T_105 = or(UInt<1>(0h0), _T_104) node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<13>(0h1000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<18>(0h2f000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<13>(0h1000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<27>(0h4000000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<13>(0h1000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = or(_T_111, _T_116) node _T_148 = or(_T_147, _T_121) node _T_149 = or(_T_148, _T_126) node _T_150 = or(_T_149, _T_131) node _T_151 = or(_T_150, _T_136) node _T_152 = or(_T_151, _T_141) node _T_153 = or(_T_152, _T_146) node _T_154 = and(_T_106, _T_153) node _T_155 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_156 = or(UInt<1>(0h0), _T_155) node _T_157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<29>(0h10000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = and(_T_156, _T_167) node _T_169 = or(UInt<1>(0h0), _T_154) node _T_170 = or(_T_169, _T_168) node _T_171 = and(_T_105, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_171, UInt<1>(0h1), "") : assert_2 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<14>(0h2000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<13>(0h1000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<17>(0h10000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<18>(0h2f000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<13>(0h1000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<17>(0h10000))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<27>(0h4000000))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_220 = cvt(_T_219) node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000))) node _T_222 = asSInt(_T_221) node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0))) node _T_224 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_225 = cvt(_T_224) node _T_226 = and(_T_225, asSInt(UInt<29>(0h10000000))) node _T_227 = asSInt(_T_226) node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = or(_T_183, _T_188) node _T_230 = or(_T_229, _T_193) node _T_231 = or(_T_230, _T_198) node _T_232 = or(_T_231, _T_203) node _T_233 = or(_T_232, _T_208) node _T_234 = or(_T_233, _T_213) node _T_235 = or(_T_234, _T_218) node _T_236 = or(_T_235, _T_223) node _T_237 = or(_T_236, _T_228) node _T_238 = and(_T_178, _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = and(UInt<1>(0h0), _T_239) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_240, UInt<1>(0h1), "") : assert_3 node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(source_ok, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_247 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_247, UInt<1>(0h1), "") : assert_5 node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(is_aligned, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_254 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_254, UInt<1>(0h1), "") : assert_7 node _T_258 = not(io.in.a.bits.mask) node _T_259 = eq(_T_258, UInt<1>(0h0)) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_259, UInt<1>(0h1), "") : assert_8 node _T_263 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_263, UInt<1>(0h1), "") : assert_9 node _T_267 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_267 : node _T_268 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_269 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_8) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h1)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_9) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h2)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_10) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h3)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_11) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _T_296 = or(_T_271, _T_277) node _T_297 = or(_T_296, _T_283) node _T_298 = or(_T_297, _T_289) node _T_299 = or(_T_298, _T_295) node _T_300 = and(_T_270, _T_299) node _T_301 = or(UInt<1>(0h0), _T_300) node _T_302 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_303 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<14>(0h2000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<17>(0h10000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<18>(0h2f000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<27>(0h4000000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_307, _T_312) node _T_344 = or(_T_343, _T_317) node _T_345 = or(_T_344, _T_322) node _T_346 = or(_T_345, _T_327) node _T_347 = or(_T_346, _T_332) node _T_348 = or(_T_347, _T_337) node _T_349 = or(_T_348, _T_342) node _T_350 = and(_T_302, _T_349) node _T_351 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_359 = cvt(_T_358) node _T_360 = and(_T_359, asSInt(UInt<29>(0h10000000))) node _T_361 = asSInt(_T_360) node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) node _T_363 = or(_T_357, _T_362) node _T_364 = and(_T_352, _T_363) node _T_365 = or(UInt<1>(0h0), _T_350) node _T_366 = or(_T_365, _T_364) node _T_367 = and(_T_301, _T_366) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_367, UInt<1>(0h1), "") : assert_10 node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<14>(0h2000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_386 = cvt(_T_385) node _T_387 = and(_T_386, asSInt(UInt<17>(0h10000))) node _T_388 = asSInt(_T_387) node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0))) node _T_390 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_391 = cvt(_T_390) node _T_392 = and(_T_391, asSInt(UInt<18>(0h2f000))) node _T_393 = asSInt(_T_392) node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0))) node _T_395 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<17>(0h10000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<17>(0h10000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_411 = cvt(_T_410) node _T_412 = and(_T_411, asSInt(UInt<27>(0h4000000))) node _T_413 = asSInt(_T_412) node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0))) node _T_415 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_416 = cvt(_T_415) node _T_417 = and(_T_416, asSInt(UInt<13>(0h1000))) node _T_418 = asSInt(_T_417) node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0))) node _T_420 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_421 = cvt(_T_420) node _T_422 = and(_T_421, asSInt(UInt<29>(0h10000000))) node _T_423 = asSInt(_T_422) node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0))) node _T_425 = or(_T_379, _T_384) node _T_426 = or(_T_425, _T_389) node _T_427 = or(_T_426, _T_394) node _T_428 = or(_T_427, _T_399) node _T_429 = or(_T_428, _T_404) node _T_430 = or(_T_429, _T_409) node _T_431 = or(_T_430, _T_414) node _T_432 = or(_T_431, _T_419) node _T_433 = or(_T_432, _T_424) node _T_434 = and(_T_374, _T_433) node _T_435 = or(UInt<1>(0h0), _T_434) node _T_436 = and(UInt<1>(0h0), _T_435) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_436, UInt<1>(0h1), "") : assert_11 node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(source_ok, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_443 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_443, UInt<1>(0h1), "") : assert_13 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(is_aligned, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_450 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_450, UInt<1>(0h1), "") : assert_15 node _T_454 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_454, UInt<1>(0h1), "") : assert_16 node _T_458 = not(io.in.a.bits.mask) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_459, UInt<1>(0h1), "") : assert_17 node _T_463 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_463, UInt<1>(0h1), "") : assert_18 node _T_467 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_467 : node _T_468 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_469 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_470 = and(_T_468, _T_469) node _T_471 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_472 = shr(io.in.a.bits.source, 2) node _T_473 = eq(_T_472, UInt<1>(0h0)) node _T_474 = leq(UInt<1>(0h0), uncommonBits_12) node _T_475 = and(_T_473, _T_474) node _T_476 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_477 = and(_T_475, _T_476) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_478 = shr(io.in.a.bits.source, 2) node _T_479 = eq(_T_478, UInt<1>(0h1)) node _T_480 = leq(UInt<1>(0h0), uncommonBits_13) node _T_481 = and(_T_479, _T_480) node _T_482 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_483 = and(_T_481, _T_482) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<2>(0h2)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_14) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<2>(0h3)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_15) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(_T_471, _T_477) node _T_497 = or(_T_496, _T_483) node _T_498 = or(_T_497, _T_489) node _T_499 = or(_T_498, _T_495) node _T_500 = and(_T_470, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_501, UInt<1>(0h1), "") : assert_19 node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = or(UInt<1>(0h0), _T_507) node _T_509 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<13>(0h1000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = and(_T_508, _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<14>(0h2000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<17>(0h10000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<18>(0h2f000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<17>(0h10000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<17>(0h10000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<27>(0h4000000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<29>(0h10000000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = or(_T_523, _T_528) node _T_565 = or(_T_564, _T_533) node _T_566 = or(_T_565, _T_538) node _T_567 = or(_T_566, _T_543) node _T_568 = or(_T_567, _T_548) node _T_569 = or(_T_568, _T_553) node _T_570 = or(_T_569, _T_558) node _T_571 = or(_T_570, _T_563) node _T_572 = and(_T_518, _T_571) node _T_573 = or(UInt<1>(0h0), _T_514) node _T_574 = or(_T_573, _T_572) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_574, UInt<1>(0h1), "") : assert_20 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(source_ok, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(is_aligned, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_584 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_584, UInt<1>(0h1), "") : assert_23 node _T_588 = eq(io.in.a.bits.mask, mask) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_588, UInt<1>(0h1), "") : assert_24 node _T_592 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_593 = asUInt(reset) node _T_594 = eq(_T_593, UInt<1>(0h0)) when _T_594 : node _T_595 = eq(_T_592, UInt<1>(0h0)) when _T_595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_592, UInt<1>(0h1), "") : assert_25 node _T_596 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_596 : node _T_597 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_598 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_601 = shr(io.in.a.bits.source, 2) node _T_602 = eq(_T_601, UInt<1>(0h0)) node _T_603 = leq(UInt<1>(0h0), uncommonBits_16) node _T_604 = and(_T_602, _T_603) node _T_605 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_606 = and(_T_604, _T_605) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_607 = shr(io.in.a.bits.source, 2) node _T_608 = eq(_T_607, UInt<1>(0h1)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_17) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_613 = shr(io.in.a.bits.source, 2) node _T_614 = eq(_T_613, UInt<2>(0h2)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_18) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_619 = shr(io.in.a.bits.source, 2) node _T_620 = eq(_T_619, UInt<2>(0h3)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_19) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_624 = and(_T_622, _T_623) node _T_625 = or(_T_600, _T_606) node _T_626 = or(_T_625, _T_612) node _T_627 = or(_T_626, _T_618) node _T_628 = or(_T_627, _T_624) node _T_629 = and(_T_599, _T_628) node _T_630 = or(UInt<1>(0h0), _T_629) node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = and(_T_634, _T_639) node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_643 = and(_T_641, _T_642) node _T_644 = or(UInt<1>(0h0), _T_643) node _T_645 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<14>(0h2000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<18>(0h2f000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<17>(0h10000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<27>(0h4000000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<13>(0h1000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<29>(0h10000000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = or(_T_649, _T_654) node _T_686 = or(_T_685, _T_659) node _T_687 = or(_T_686, _T_664) node _T_688 = or(_T_687, _T_669) node _T_689 = or(_T_688, _T_674) node _T_690 = or(_T_689, _T_679) node _T_691 = or(_T_690, _T_684) node _T_692 = and(_T_644, _T_691) node _T_693 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<17>(0h10000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = and(_T_693, _T_698) node _T_700 = or(UInt<1>(0h0), _T_640) node _T_701 = or(_T_700, _T_692) node _T_702 = or(_T_701, _T_699) node _T_703 = and(_T_630, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_703, UInt<1>(0h1), "") : assert_26 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_713 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_713, UInt<1>(0h1), "") : assert_29 node _T_717 = eq(io.in.a.bits.mask, mask) node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(_T_717, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_717, UInt<1>(0h1), "") : assert_30 node _T_721 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_721 : node _T_722 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_723 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_726 = shr(io.in.a.bits.source, 2) node _T_727 = eq(_T_726, UInt<1>(0h0)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_20) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_731 = and(_T_729, _T_730) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_732 = shr(io.in.a.bits.source, 2) node _T_733 = eq(_T_732, UInt<1>(0h1)) node _T_734 = leq(UInt<1>(0h0), uncommonBits_21) node _T_735 = and(_T_733, _T_734) node _T_736 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_737 = and(_T_735, _T_736) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_738 = shr(io.in.a.bits.source, 2) node _T_739 = eq(_T_738, UInt<2>(0h2)) node _T_740 = leq(UInt<1>(0h0), uncommonBits_22) node _T_741 = and(_T_739, _T_740) node _T_742 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_743 = and(_T_741, _T_742) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_744 = shr(io.in.a.bits.source, 2) node _T_745 = eq(_T_744, UInt<2>(0h3)) node _T_746 = leq(UInt<1>(0h0), uncommonBits_23) node _T_747 = and(_T_745, _T_746) node _T_748 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(_T_725, _T_731) node _T_751 = or(_T_750, _T_737) node _T_752 = or(_T_751, _T_743) node _T_753 = or(_T_752, _T_749) node _T_754 = and(_T_724, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = and(_T_759, _T_764) node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_768 = and(_T_766, _T_767) node _T_769 = or(UInt<1>(0h0), _T_768) node _T_770 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<14>(0h2000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<18>(0h2f000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<13>(0h1000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<27>(0h4000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<29>(0h10000000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = or(_T_774, _T_779) node _T_811 = or(_T_810, _T_784) node _T_812 = or(_T_811, _T_789) node _T_813 = or(_T_812, _T_794) node _T_814 = or(_T_813, _T_799) node _T_815 = or(_T_814, _T_804) node _T_816 = or(_T_815, _T_809) node _T_817 = and(_T_769, _T_816) node _T_818 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_819 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<17>(0h10000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = and(_T_818, _T_823) node _T_825 = or(UInt<1>(0h0), _T_765) node _T_826 = or(_T_825, _T_817) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_828, UInt<1>(0h1), "") : assert_31 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(source_ok, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_838 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_838, UInt<1>(0h1), "") : assert_34 node _T_842 = not(mask) node _T_843 = and(io.in.a.bits.mask, _T_842) node _T_844 = eq(_T_843, UInt<1>(0h0)) node _T_845 = asUInt(reset) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(_T_844, UInt<1>(0h0)) when _T_847 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_844, UInt<1>(0h1), "") : assert_35 node _T_848 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_848 : node _T_849 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_850 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_851 = and(_T_849, _T_850) node _T_852 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h0)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_24) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<1>(0h1)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_25) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_865 = shr(io.in.a.bits.source, 2) node _T_866 = eq(_T_865, UInt<2>(0h2)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_26) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_870 = and(_T_868, _T_869) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_871 = shr(io.in.a.bits.source, 2) node _T_872 = eq(_T_871, UInt<2>(0h3)) node _T_873 = leq(UInt<1>(0h0), uncommonBits_27) node _T_874 = and(_T_872, _T_873) node _T_875 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_876 = and(_T_874, _T_875) node _T_877 = or(_T_852, _T_858) node _T_878 = or(_T_877, _T_864) node _T_879 = or(_T_878, _T_870) node _T_880 = or(_T_879, _T_876) node _T_881 = and(_T_851, _T_880) node _T_882 = or(UInt<1>(0h0), _T_881) node _T_883 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_884 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _T_886 = or(UInt<1>(0h0), _T_885) node _T_887 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_888 = cvt(_T_887) node _T_889 = and(_T_888, asSInt(UInt<14>(0h2000))) node _T_890 = asSInt(_T_889) node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0))) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<18>(0h2f000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<17>(0h10000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_908 = cvt(_T_907) node _T_909 = and(_T_908, asSInt(UInt<13>(0h1000))) node _T_910 = asSInt(_T_909) node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0))) node _T_912 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_913 = cvt(_T_912) node _T_914 = and(_T_913, asSInt(UInt<27>(0h4000000))) node _T_915 = asSInt(_T_914) node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0))) node _T_917 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = or(_T_891, _T_896) node _T_923 = or(_T_922, _T_901) node _T_924 = or(_T_923, _T_906) node _T_925 = or(_T_924, _T_911) node _T_926 = or(_T_925, _T_916) node _T_927 = or(_T_926, _T_921) node _T_928 = and(_T_886, _T_927) node _T_929 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_930 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_931 = cvt(_T_930) node _T_932 = and(_T_931, asSInt(UInt<17>(0h10000))) node _T_933 = asSInt(_T_932) node _T_934 = eq(_T_933, asSInt(UInt<1>(0h0))) node _T_935 = and(_T_929, _T_934) node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_938 = and(_T_936, _T_937) node _T_939 = or(UInt<1>(0h0), _T_938) node _T_940 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_941 = cvt(_T_940) node _T_942 = and(_T_941, asSInt(UInt<17>(0h10000))) node _T_943 = asSInt(_T_942) node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0))) node _T_945 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<29>(0h10000000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = or(_T_944, _T_949) node _T_951 = and(_T_939, _T_950) node _T_952 = or(UInt<1>(0h0), _T_928) node _T_953 = or(_T_952, _T_935) node _T_954 = or(_T_953, _T_951) node _T_955 = and(_T_882, _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_955, UInt<1>(0h1), "") : assert_36 node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(source_ok, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(is_aligned, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_965 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_965, UInt<1>(0h1), "") : assert_39 node _T_969 = eq(io.in.a.bits.mask, mask) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_969, UInt<1>(0h1), "") : assert_40 node _T_973 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_973 : node _T_974 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_975 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_976 = and(_T_974, _T_975) node _T_977 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_978 = shr(io.in.a.bits.source, 2) node _T_979 = eq(_T_978, UInt<1>(0h0)) node _T_980 = leq(UInt<1>(0h0), uncommonBits_28) node _T_981 = and(_T_979, _T_980) node _T_982 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_983 = and(_T_981, _T_982) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_984 = shr(io.in.a.bits.source, 2) node _T_985 = eq(_T_984, UInt<1>(0h1)) node _T_986 = leq(UInt<1>(0h0), uncommonBits_29) node _T_987 = and(_T_985, _T_986) node _T_988 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_989 = and(_T_987, _T_988) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_990 = shr(io.in.a.bits.source, 2) node _T_991 = eq(_T_990, UInt<2>(0h2)) node _T_992 = leq(UInt<1>(0h0), uncommonBits_30) node _T_993 = and(_T_991, _T_992) node _T_994 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_995 = and(_T_993, _T_994) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<2>(0h3)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_31) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _T_1002 = or(_T_977, _T_983) node _T_1003 = or(_T_1002, _T_989) node _T_1004 = or(_T_1003, _T_995) node _T_1005 = or(_T_1004, _T_1001) node _T_1006 = and(_T_976, _T_1005) node _T_1007 = or(UInt<1>(0h0), _T_1006) node _T_1008 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1009 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1010 = and(_T_1008, _T_1009) node _T_1011 = or(UInt<1>(0h0), _T_1010) node _T_1012 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<14>(0h2000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1023 = cvt(_T_1022) node _T_1024 = and(_T_1023, asSInt(UInt<18>(0h2f000))) node _T_1025 = asSInt(_T_1024) node _T_1026 = eq(_T_1025, asSInt(UInt<1>(0h0))) node _T_1027 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1028 = cvt(_T_1027) node _T_1029 = and(_T_1028, asSInt(UInt<17>(0h10000))) node _T_1030 = asSInt(_T_1029) node _T_1031 = eq(_T_1030, asSInt(UInt<1>(0h0))) node _T_1032 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1033 = cvt(_T_1032) node _T_1034 = and(_T_1033, asSInt(UInt<13>(0h1000))) node _T_1035 = asSInt(_T_1034) node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0))) node _T_1037 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1038 = cvt(_T_1037) node _T_1039 = and(_T_1038, asSInt(UInt<27>(0h4000000))) node _T_1040 = asSInt(_T_1039) node _T_1041 = eq(_T_1040, asSInt(UInt<1>(0h0))) node _T_1042 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1043 = cvt(_T_1042) node _T_1044 = and(_T_1043, asSInt(UInt<13>(0h1000))) node _T_1045 = asSInt(_T_1044) node _T_1046 = eq(_T_1045, asSInt(UInt<1>(0h0))) node _T_1047 = or(_T_1016, _T_1021) node _T_1048 = or(_T_1047, _T_1026) node _T_1049 = or(_T_1048, _T_1031) node _T_1050 = or(_T_1049, _T_1036) node _T_1051 = or(_T_1050, _T_1041) node _T_1052 = or(_T_1051, _T_1046) node _T_1053 = and(_T_1011, _T_1052) node _T_1054 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1055 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1056 = cvt(_T_1055) node _T_1057 = and(_T_1056, asSInt(UInt<17>(0h10000))) node _T_1058 = asSInt(_T_1057) node _T_1059 = eq(_T_1058, asSInt(UInt<1>(0h0))) node _T_1060 = and(_T_1054, _T_1059) node _T_1061 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1062 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = or(UInt<1>(0h0), _T_1063) node _T_1065 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1066 = cvt(_T_1065) node _T_1067 = and(_T_1066, asSInt(UInt<17>(0h10000))) node _T_1068 = asSInt(_T_1067) node _T_1069 = eq(_T_1068, asSInt(UInt<1>(0h0))) node _T_1070 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1071 = cvt(_T_1070) node _T_1072 = and(_T_1071, asSInt(UInt<29>(0h10000000))) node _T_1073 = asSInt(_T_1072) node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0))) node _T_1075 = or(_T_1069, _T_1074) node _T_1076 = and(_T_1064, _T_1075) node _T_1077 = or(UInt<1>(0h0), _T_1053) node _T_1078 = or(_T_1077, _T_1060) node _T_1079 = or(_T_1078, _T_1076) node _T_1080 = and(_T_1007, _T_1079) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_41 node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(source_ok, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(is_aligned, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1090 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_44 node _T_1094 = eq(io.in.a.bits.mask, mask) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_45 node _T_1098 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1098 : node _T_1099 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1101 = and(_T_1099, _T_1100) node _T_1102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1103 = shr(io.in.a.bits.source, 2) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) node _T_1105 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1108 = and(_T_1106, _T_1107) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1109 = shr(io.in.a.bits.source, 2) node _T_1110 = eq(_T_1109, UInt<1>(0h1)) node _T_1111 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1112 = and(_T_1110, _T_1111) node _T_1113 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1114 = and(_T_1112, _T_1113) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1115 = shr(io.in.a.bits.source, 2) node _T_1116 = eq(_T_1115, UInt<2>(0h2)) node _T_1117 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1120 = and(_T_1118, _T_1119) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1121 = shr(io.in.a.bits.source, 2) node _T_1122 = eq(_T_1121, UInt<2>(0h3)) node _T_1123 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1124 = and(_T_1122, _T_1123) node _T_1125 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1126 = and(_T_1124, _T_1125) node _T_1127 = or(_T_1102, _T_1108) node _T_1128 = or(_T_1127, _T_1114) node _T_1129 = or(_T_1128, _T_1120) node _T_1130 = or(_T_1129, _T_1126) node _T_1131 = and(_T_1101, _T_1130) node _T_1132 = or(UInt<1>(0h0), _T_1131) node _T_1133 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1134 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1135 = and(_T_1133, _T_1134) node _T_1136 = or(UInt<1>(0h0), _T_1135) node _T_1137 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<13>(0h1000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = and(_T_1136, _T_1141) node _T_1143 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1144 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<14>(0h2000))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1150 = cvt(_T_1149) node _T_1151 = and(_T_1150, asSInt(UInt<17>(0h10000))) node _T_1152 = asSInt(_T_1151) node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0))) node _T_1154 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1155 = cvt(_T_1154) node _T_1156 = and(_T_1155, asSInt(UInt<18>(0h2f000))) node _T_1157 = asSInt(_T_1156) node _T_1158 = eq(_T_1157, asSInt(UInt<1>(0h0))) node _T_1159 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1160 = cvt(_T_1159) node _T_1161 = and(_T_1160, asSInt(UInt<17>(0h10000))) node _T_1162 = asSInt(_T_1161) node _T_1163 = eq(_T_1162, asSInt(UInt<1>(0h0))) node _T_1164 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1165 = cvt(_T_1164) node _T_1166 = and(_T_1165, asSInt(UInt<13>(0h1000))) node _T_1167 = asSInt(_T_1166) node _T_1168 = eq(_T_1167, asSInt(UInt<1>(0h0))) node _T_1169 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1170 = cvt(_T_1169) node _T_1171 = and(_T_1170, asSInt(UInt<27>(0h4000000))) node _T_1172 = asSInt(_T_1171) node _T_1173 = eq(_T_1172, asSInt(UInt<1>(0h0))) node _T_1174 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1175 = cvt(_T_1174) node _T_1176 = and(_T_1175, asSInt(UInt<13>(0h1000))) node _T_1177 = asSInt(_T_1176) node _T_1178 = eq(_T_1177, asSInt(UInt<1>(0h0))) node _T_1179 = or(_T_1148, _T_1153) node _T_1180 = or(_T_1179, _T_1158) node _T_1181 = or(_T_1180, _T_1163) node _T_1182 = or(_T_1181, _T_1168) node _T_1183 = or(_T_1182, _T_1173) node _T_1184 = or(_T_1183, _T_1178) node _T_1185 = and(_T_1143, _T_1184) node _T_1186 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1187 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = or(UInt<1>(0h0), _T_1188) node _T_1190 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<17>(0h10000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<29>(0h10000000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = or(_T_1194, _T_1199) node _T_1201 = and(_T_1189, _T_1200) node _T_1202 = or(UInt<1>(0h0), _T_1142) node _T_1203 = or(_T_1202, _T_1185) node _T_1204 = or(_T_1203, _T_1201) node _T_1205 = and(_T_1132, _T_1204) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_46 node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(source_ok, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(is_aligned, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1215 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_49 node _T_1219 = eq(io.in.a.bits.mask, mask) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_50 node _T_1223 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1227 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_52 node _source_ok_T_28 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_29 = shr(io.in.d.bits.source, 2) node _source_ok_T_30 = eq(_source_ok_T_29, UInt<1>(0h0)) node _source_ok_T_31 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_T_33 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h1)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<2>(0h2)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h3)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) wire _source_ok_WIRE_1 : UInt<1>[5] connect _source_ok_WIRE_1[0], _source_ok_T_28 connect _source_ok_WIRE_1[1], _source_ok_T_34 connect _source_ok_WIRE_1[2], _source_ok_T_40 connect _source_ok_WIRE_1[3], _source_ok_T_46 connect _source_ok_WIRE_1[4], _source_ok_T_52 node _source_ok_T_53 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE_1[2]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE_1[3]) node source_ok_1 = or(_source_ok_T_55, _source_ok_WIRE_1[4]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1231 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1231 : node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(source_ok_1, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1235 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_54 node _T_1239 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_55 node _T_1243 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_56 node _T_1247 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_57 node _T_1251 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1251 : node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(source_ok_1, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(sink_ok, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1258 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_60 node _T_1262 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_61 node _T_1266 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_62 node _T_1270 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_63 node _T_1274 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1275 = or(UInt<1>(0h1), _T_1274) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_64 node _T_1279 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1279 : node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(source_ok_1, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(sink_ok, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1286 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_67 node _T_1290 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_68 node _T_1294 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_69 node _T_1298 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1299 = or(_T_1298, io.in.d.bits.corrupt) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_70 node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1304 = or(UInt<1>(0h1), _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_71 node _T_1308 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1308 : node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(source_ok_1, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1312 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_73 node _T_1316 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_74 node _T_1320 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1321 = or(UInt<1>(0h1), _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_75 node _T_1325 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1325 : node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(source_ok_1, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1329 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1330 = asUInt(reset) node _T_1331 = eq(_T_1330, UInt<1>(0h0)) when _T_1331 : node _T_1332 = eq(_T_1329, UInt<1>(0h0)) when _T_1332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1329, UInt<1>(0h1), "") : assert_77 node _T_1333 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1334 = or(_T_1333, io.in.d.bits.corrupt) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_78 node _T_1338 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1339 = or(UInt<1>(0h1), _T_1338) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_79 node _T_1343 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1343 : node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(source_ok_1, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1347 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_81 node _T_1351 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_82 node _T_1355 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1356 = or(UInt<1>(0h1), _T_1355) node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(_T_1356, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1356, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1360 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1364 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1368 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1372 = eq(a_first, UInt<1>(0h0)) node _T_1373 = and(io.in.a.valid, _T_1372) when _T_1373 : node _T_1374 = eq(io.in.a.bits.opcode, opcode) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_87 node _T_1378 = eq(io.in.a.bits.param, param) node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(_T_1378, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1378, UInt<1>(0h1), "") : assert_88 node _T_1382 = eq(io.in.a.bits.size, size) node _T_1383 = asUInt(reset) node _T_1384 = eq(_T_1383, UInt<1>(0h0)) when _T_1384 : node _T_1385 = eq(_T_1382, UInt<1>(0h0)) when _T_1385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1382, UInt<1>(0h1), "") : assert_89 node _T_1386 = eq(io.in.a.bits.source, source) node _T_1387 = asUInt(reset) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) when _T_1388 : node _T_1389 = eq(_T_1386, UInt<1>(0h0)) when _T_1389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1386, UInt<1>(0h1), "") : assert_90 node _T_1390 = eq(io.in.a.bits.address, address) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_91 node _T_1394 = and(io.in.a.ready, io.in.a.valid) node _T_1395 = and(_T_1394, a_first) when _T_1395 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1396 = eq(d_first, UInt<1>(0h0)) node _T_1397 = and(io.in.d.valid, _T_1396) when _T_1397 : node _T_1398 = eq(io.in.d.bits.opcode, opcode_1) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_92 node _T_1402 = eq(io.in.d.bits.param, param_1) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_93 node _T_1406 = eq(io.in.d.bits.size, size_1) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_94 node _T_1410 = eq(io.in.d.bits.source, source_1) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_95 node _T_1414 = eq(io.in.d.bits.sink, sink) node _T_1415 = asUInt(reset) node _T_1416 = eq(_T_1415, UInt<1>(0h0)) when _T_1416 : node _T_1417 = eq(_T_1414, UInt<1>(0h0)) when _T_1417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1414, UInt<1>(0h1), "") : assert_96 node _T_1418 = eq(io.in.d.bits.denied, denied) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_97 node _T_1422 = and(io.in.d.ready, io.in.d.valid) node _T_1423 = and(_T_1422, d_first) when _T_1423 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes : UInt<136>, clock, reset, UInt<136>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<17> connect a_set, UInt<17>(0h0) wire a_set_wo_ready : UInt<17> connect a_set_wo_ready, UInt<17>(0h0) wire a_opcodes_set : UInt<68> connect a_opcodes_set, UInt<68>(0h0) wire a_sizes_set : UInt<136> connect a_sizes_set, UInt<136>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1424 = and(io.in.a.valid, a_first_1) node _T_1425 = and(_T_1424, UInt<1>(0h1)) when _T_1425 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1426 = and(io.in.a.ready, io.in.a.valid) node _T_1427 = and(_T_1426, a_first_1) node _T_1428 = and(_T_1427, UInt<1>(0h1)) when _T_1428 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1429 = dshr(inflight, io.in.a.bits.source) node _T_1430 = bits(_T_1429, 0, 0) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<17> connect d_clr, UInt<17>(0h0) wire d_clr_wo_ready : UInt<17> connect d_clr_wo_ready, UInt<17>(0h0) wire d_opcodes_clr : UInt<68> connect d_opcodes_clr, UInt<68>(0h0) wire d_sizes_clr : UInt<136> connect d_sizes_clr, UInt<136>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1435 = and(io.in.d.valid, d_first_1) node _T_1436 = and(_T_1435, UInt<1>(0h1)) node _T_1437 = eq(d_release_ack, UInt<1>(0h0)) node _T_1438 = and(_T_1436, _T_1437) when _T_1438 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1439 = and(io.in.d.ready, io.in.d.valid) node _T_1440 = and(_T_1439, d_first_1) node _T_1441 = and(_T_1440, UInt<1>(0h1)) node _T_1442 = eq(d_release_ack, UInt<1>(0h0)) node _T_1443 = and(_T_1441, _T_1442) when _T_1443 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1444 = and(io.in.d.valid, d_first_1) node _T_1445 = and(_T_1444, UInt<1>(0h1)) node _T_1446 = eq(d_release_ack, UInt<1>(0h0)) node _T_1447 = and(_T_1445, _T_1446) when _T_1447 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1448 = dshr(inflight, io.in.d.bits.source) node _T_1449 = bits(_T_1448, 0, 0) node _T_1450 = or(_T_1449, same_cycle_resp) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1454 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1455 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1456 = or(_T_1454, _T_1455) node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(_T_1456, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1456, UInt<1>(0h1), "") : assert_100 node _T_1460 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_101 else : node _T_1464 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1465 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1466 = or(_T_1464, _T_1465) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_102 node _T_1470 = eq(io.in.d.bits.size, a_size_lookup) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_103 node _T_1474 = and(io.in.d.valid, d_first_1) node _T_1475 = and(_T_1474, a_first_1) node _T_1476 = and(_T_1475, io.in.a.valid) node _T_1477 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1478 = and(_T_1476, _T_1477) node _T_1479 = eq(d_release_ack, UInt<1>(0h0)) node _T_1480 = and(_T_1478, _T_1479) when _T_1480 : node _T_1481 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1482 = or(_T_1481, io.in.a.ready) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_104 node _T_1486 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1487 = orr(a_set_wo_ready) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) node _T_1489 = or(_T_1486, _T_1488) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_28 node _T_1493 = orr(inflight) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) node _T_1495 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1496 = or(_T_1494, _T_1495) node _T_1497 = lt(watchdog, plusarg_reader.out) node _T_1498 = or(_T_1496, _T_1497) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1502 = and(io.in.a.ready, io.in.a.valid) node _T_1503 = and(io.in.d.ready, io.in.d.valid) node _T_1504 = or(_T_1502, _T_1503) when _T_1504 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes_1 : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes_1 : UInt<136>, clock, reset, UInt<136>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<17> connect c_set, UInt<17>(0h0) wire c_set_wo_ready : UInt<17> connect c_set_wo_ready, UInt<17>(0h0) wire c_opcodes_set : UInt<68> connect c_opcodes_set, UInt<68>(0h0) wire c_sizes_set : UInt<136> connect c_sizes_set, UInt<136>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1505 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1506 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1507 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1508 = and(_T_1506, _T_1507) node _T_1509 = and(_T_1505, _T_1508) when _T_1509 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1510 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1511 = and(_T_1510, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1512 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1513 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1514 = and(_T_1512, _T_1513) node _T_1515 = and(_T_1511, _T_1514) when _T_1515 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1516 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1517 = bits(_T_1516, 0, 0) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(_T_1518, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1518, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<17> connect d_clr_1, UInt<17>(0h0) wire d_clr_wo_ready_1 : UInt<17> connect d_clr_wo_ready_1, UInt<17>(0h0) wire d_opcodes_clr_1 : UInt<68> connect d_opcodes_clr_1, UInt<68>(0h0) wire d_sizes_clr_1 : UInt<136> connect d_sizes_clr_1, UInt<136>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1522 = and(io.in.d.valid, d_first_2) node _T_1523 = and(_T_1522, UInt<1>(0h1)) node _T_1524 = and(_T_1523, d_release_ack_1) when _T_1524 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1525 = and(io.in.d.ready, io.in.d.valid) node _T_1526 = and(_T_1525, d_first_2) node _T_1527 = and(_T_1526, UInt<1>(0h1)) node _T_1528 = and(_T_1527, d_release_ack_1) when _T_1528 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1529 = and(io.in.d.valid, d_first_2) node _T_1530 = and(_T_1529, UInt<1>(0h1)) node _T_1531 = and(_T_1530, d_release_ack_1) when _T_1531 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1532 = dshr(inflight_1, io.in.d.bits.source) node _T_1533 = bits(_T_1532, 0, 0) node _T_1534 = or(_T_1533, same_cycle_resp_1) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1538 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_109 else : node _T_1542 = eq(io.in.d.bits.size, c_size_lookup) node _T_1543 = asUInt(reset) node _T_1544 = eq(_T_1543, UInt<1>(0h0)) when _T_1544 : node _T_1545 = eq(_T_1542, UInt<1>(0h0)) when _T_1545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1542, UInt<1>(0h1), "") : assert_110 node _T_1546 = and(io.in.d.valid, d_first_2) node _T_1547 = and(_T_1546, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1548 = and(_T_1547, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1549 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1550 = and(_T_1548, _T_1549) node _T_1551 = and(_T_1550, d_release_ack_1) node _T_1552 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1553 = and(_T_1551, _T_1552) when _T_1553 : node _T_1554 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1555 = or(_T_1554, _WIRE_23.ready) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_111 node _T_1559 = orr(c_set_wo_ready) when _T_1559 : node _T_1560 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1561 = asUInt(reset) node _T_1562 = eq(_T_1561, UInt<1>(0h0)) when _T_1562 : node _T_1563 = eq(_T_1560, UInt<1>(0h0)) when _T_1563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1560, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_29 node _T_1564 = orr(inflight_1) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) node _T_1566 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1567 = or(_T_1565, _T_1566) node _T_1568 = lt(watchdog_1, plusarg_reader_1.out) node _T_1569 = or(_T_1567, _T_1568) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1573 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1574 = and(io.in.d.ready, io.in.d.valid) node _T_1575 = or(_T_1573, _T_1574) when _T_1575 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_14( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_138 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_138( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget16 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_13 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleA_a29d128s7k1z4u connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonIn.a wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 127, 64) node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2) node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0)) node _repeat_limit_T = dshl(UInt<4>(0hf), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 3, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 3) regreset repeat_count : UInt<1>, clock, reset, UInt<1>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonOut.a.ready, anonOut.a.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) node repeat_sel = bits(cated.bits.address, 3, 3) node repeat_index = or(repeat_sel, repeat_count) connect anonOut.a.bits, cated.bits connect anonOut.a.valid, cated.valid connect cated.ready, anonOut.a.ready node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0) node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64) wire repeat_anonOut_a_bits_data_mux : UInt<64>[2] connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1 connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index] node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0) node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8) wire repeat_anonOut_a_bits_mask_mux : UInt<8>[2] connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1 connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 node hasData = bits(anonOut.d.bits.opcode, 0, 0) node _limit_T = dshl(UInt<4>(0hf), anonOut.d.bits.size) node _limit_T_1 = bits(_limit_T, 3, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 3) regreset count : UInt<1>, clock, reset, UInt<1>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg) node _T = and(anonOut.d.ready, anonOut.d.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonOut_d_ready_T = eq(last, UInt<1>(0h0)) node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T) connect anonOut.d.ready, _anonOut_d_ready_T_1 node _anonIn_d_valid_T = and(anonOut.d.valid, last) connect anonIn.d.valid, _anonIn_d_valid_T connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T) node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0)) node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1) wire anonIn_d_bits_data_odata_0 : UInt connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data wire anonIn_d_bits_data_odata_1 : UInt connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data reg anonIn_d_bits_data_rdata : UInt<64>[1], clock node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0]) node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonOut.d.bits.data) node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid) node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1) when _anonIn_d_bits_data_T_2 : connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1) connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0 node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0) connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3 connect anonIn.d.bits.corrupt, corrupt_out wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)	module TLWidthWidget16( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _repeated_repeater_io_enq_ready; // @[Repeater.scala:36:26] wire _repeated_repeater_io_deq_valid; // @[Repeater.scala:36:26] wire [2:0] _repeated_repeater_io_deq_bits_opcode; // @[Repeater.scala:36:26] wire [3:0] _repeated_repeater_io_deq_bits_size; // @[Repeater.scala:36:26] wire [28:0] _repeated_repeater_io_deq_bits_address; // @[Repeater.scala:36:26] wire [15:0] _repeated_repeater_io_deq_bits_mask; // @[Repeater.scala:36:26] wire [127:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire [18:0] _repeat_limit_T = 19'hF << _repeated_repeater_io_deq_bits_size; // @[package.scala:243:71] reg repeat_count; // @[WidthWidget.scala:105:26] wire repeat_last = repeat_count == ~(_repeat_limit_T[3]) \| _repeated_repeater_io_deq_bits_opcode[2]; // @[package.scala:243:{46,71,76}] wire repeat_index = _repeated_repeater_io_deq_bits_address[3] \| repeat_count; // @[Repeater.scala:36:26] wire [18:0] _limit_T = 19'hF << auto_anon_out_d_bits_size; // @[package.scala:243:71] reg count; // @[WidthWidget.scala:40:27] wire last = count == ~(_limit_T[3]) \| ~(auto_anon_out_d_bits_opcode[0]); // @[package.scala:243:{46,71,76}] reg corrupt_reg; // @[WidthWidget.scala:45:32] wire corrupt_out = auto_anon_out_d_bits_corrupt \| corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] wire anonOut_d_ready = auto_anon_in_d_ready \| ~last; // @[WidthWidget.scala:42:36, :76:{29,32}] wire anonIn_d_valid = auto_anon_out_d_valid & last; // @[WidthWidget.scala:42:36, :77:29] reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire anonIn_d_bits_data_masked_enable_0 = ~(count & ~(_limit_T[3])) \| ~anonIn_d_bits_data_rdata_written_once; // @[package.scala:243:{46,71,76}] reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24] wire _anonIn_d_bits_data_T = anonOut_d_ready & auto_anon_out_d_valid; // @[Decoupled.scala:51:35] wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & ~last; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] repeat_count <= 1'h0; // @[WidthWidget.scala:105:26] count <= 1'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] end else begin // @[WidthWidget.scala:27:9] if (auto_anon_out_a_ready & _repeated_repeater_io_deq_valid) // @[Decoupled.scala:51:35] repeat_count <= ~repeat_last & repeat_count - 1'h1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35] count <= ~last & count - 1'h1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23] end anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 \| anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] end if (_anonIn_d_bits_data_T_2 & anonIn_d_bits_data_masked_enable_0) // @[WidthWidget.scala:63:42, :66:24, :68:88, :69:{23,33}, :71:56] anonIn_d_bits_data_rdata_0 <= auto_anon_out_d_bits_data; // @[WidthWidget.scala:66:24] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_125 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_125( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_246 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_246( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_18 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_18( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_67 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_67( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<27>(0h4000000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = or(_T_38, _T_43) node _T_75 = or(_T_74, _T_48) node _T_76 = or(_T_75, _T_53) node _T_77 = or(_T_76, _T_58) node _T_78 = or(_T_77, _T_63) node _T_79 = or(_T_78, _T_68) node _T_80 = or(_T_79, _T_73) node _T_81 = and(_T_33, _T_80) node _T_82 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_83 = or(UInt<1>(0h0), _T_82) node _T_84 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<17>(0h10000))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<29>(0h10000000))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_88, _T_93) node _T_95 = and(_T_83, _T_94) node _T_96 = or(UInt<1>(0h0), _T_81) node _T_97 = or(_T_96, _T_95) node _T_98 = and(_T_32, _T_97) node _T_99 = asUInt(reset) node _T_100 = eq(_T_99, UInt<1>(0h0)) when _T_100 : node _T_101 = eq(_T_98, UInt<1>(0h0)) when _T_101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_98, UInt<1>(0h1), "") : assert_2 node _T_102 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_103 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_102 connect _WIRE[1], _T_103 node _T_104 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_105 = mux(_WIRE[0], _T_104, UInt<1>(0h0)) node _T_106 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = or(_T_105, _T_106) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_107 node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = or(UInt<1>(0h0), _T_110) node _T_112 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<14>(0h2000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<13>(0h1000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<17>(0h10000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<18>(0h2f000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<17>(0h10000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<13>(0h1000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<17>(0h10000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<27>(0h4000000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<29>(0h10000000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = or(_T_116, _T_121) node _T_163 = or(_T_162, _T_126) node _T_164 = or(_T_163, _T_131) node _T_165 = or(_T_164, _T_136) node _T_166 = or(_T_165, _T_141) node _T_167 = or(_T_166, _T_146) node _T_168 = or(_T_167, _T_151) node _T_169 = or(_T_168, _T_156) node _T_170 = or(_T_169, _T_161) node _T_171 = and(_T_111, _T_170) node _T_172 = or(UInt<1>(0h0), _T_171) node _T_173 = and(_WIRE_1, _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_173, UInt<1>(0h1), "") : assert_3 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(source_ok, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_180 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_180, UInt<1>(0h1), "") : assert_5 node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(is_aligned, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_187 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_187, UInt<1>(0h1), "") : assert_7 node _T_191 = not(io.in.a.bits.mask) node _T_192 = eq(_T_191, UInt<1>(0h0)) node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_T_192, UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_192, UInt<1>(0h1), "") : assert_8 node _T_196 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_197 = asUInt(reset) node _T_198 = eq(_T_197, UInt<1>(0h0)) when _T_198 : node _T_199 = eq(_T_196, UInt<1>(0h0)) when _T_199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_196, UInt<1>(0h1), "") : assert_9 node _T_200 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_200 : node _T_201 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_202 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_205 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_206 = or(_T_204, _T_205) node _T_207 = and(_T_203, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<14>(0h2000))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<17>(0h10000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_226 = cvt(_T_225) node _T_227 = and(_T_226, asSInt(UInt<18>(0h2f000))) node _T_228 = asSInt(_T_227) node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0))) node _T_230 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_231 = cvt(_T_230) node _T_232 = and(_T_231, asSInt(UInt<17>(0h10000))) node _T_233 = asSInt(_T_232) node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0))) node _T_235 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_236 = cvt(_T_235) node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000))) node _T_238 = asSInt(_T_237) node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0))) node _T_240 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<27>(0h4000000))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<13>(0h1000))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = or(_T_214, _T_219) node _T_251 = or(_T_250, _T_224) node _T_252 = or(_T_251, _T_229) node _T_253 = or(_T_252, _T_234) node _T_254 = or(_T_253, _T_239) node _T_255 = or(_T_254, _T_244) node _T_256 = or(_T_255, _T_249) node _T_257 = and(_T_209, _T_256) node _T_258 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_259 = or(UInt<1>(0h0), _T_258) node _T_260 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<17>(0h10000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_266 = cvt(_T_265) node _T_267 = and(_T_266, asSInt(UInt<29>(0h10000000))) node _T_268 = asSInt(_T_267) node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0))) node _T_270 = or(_T_264, _T_269) node _T_271 = and(_T_259, _T_270) node _T_272 = or(UInt<1>(0h0), _T_257) node _T_273 = or(_T_272, _T_271) node _T_274 = and(_T_208, _T_273) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_274, UInt<1>(0h1), "") : assert_10 node _T_278 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_278 connect _WIRE_2[1], _T_279 node _T_280 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_281 = mux(_WIRE_2[0], _T_280, UInt<1>(0h0)) node _T_282 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = or(_T_281, _T_282) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_283 node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_285 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_286 = and(_T_284, _T_285) node _T_287 = or(UInt<1>(0h0), _T_286) node _T_288 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<14>(0h2000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<13>(0h1000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<18>(0h2f000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<13>(0h1000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<17>(0h10000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<27>(0h4000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<29>(0h10000000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = or(_T_292, _T_297) node _T_339 = or(_T_338, _T_302) node _T_340 = or(_T_339, _T_307) node _T_341 = or(_T_340, _T_312) node _T_342 = or(_T_341, _T_317) node _T_343 = or(_T_342, _T_322) node _T_344 = or(_T_343, _T_327) node _T_345 = or(_T_344, _T_332) node _T_346 = or(_T_345, _T_337) node _T_347 = and(_T_287, _T_346) node _T_348 = or(UInt<1>(0h0), _T_347) node _T_349 = and(_WIRE_3, _T_348) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_349, UInt<1>(0h1), "") : assert_11 node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(source_ok, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_356 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_356, UInt<1>(0h1), "") : assert_13 node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(is_aligned, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_363 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_363, UInt<1>(0h1), "") : assert_15 node _T_367 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_367, UInt<1>(0h1), "") : assert_16 node _T_371 = not(io.in.a.bits.mask) node _T_372 = eq(_T_371, UInt<1>(0h0)) node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_T_372, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_372, UInt<1>(0h1), "") : assert_17 node _T_376 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_377 = asUInt(reset) node _T_378 = eq(_T_377, UInt<1>(0h0)) when _T_378 : node _T_379 = eq(_T_376, UInt<1>(0h0)) when _T_379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_376, UInt<1>(0h1), "") : assert_18 node _T_380 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_380 : node _T_381 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_382 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_383 = and(_T_381, _T_382) node _T_384 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_385 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_386 = or(_T_384, _T_385) node _T_387 = and(_T_383, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(_T_388, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_388, UInt<1>(0h1), "") : assert_19 node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = or(UInt<1>(0h0), _T_394) node _T_396 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_397 = cvt(_T_396) node _T_398 = and(_T_397, asSInt(UInt<13>(0h1000))) node _T_399 = asSInt(_T_398) node _T_400 = eq(_T_399, asSInt(UInt<1>(0h0))) node _T_401 = and(_T_395, _T_400) node _T_402 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_403 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_404 = and(_T_402, _T_403) node _T_405 = or(UInt<1>(0h0), _T_404) node _T_406 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_407 = cvt(_T_406) node _T_408 = and(_T_407, asSInt(UInt<14>(0h2000))) node _T_409 = asSInt(_T_408) node _T_410 = eq(_T_409, asSInt(UInt<1>(0h0))) node _T_411 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<17>(0h10000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_417 = cvt(_T_416) node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000))) node _T_419 = asSInt(_T_418) node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0))) node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_422 = cvt(_T_421) node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000))) node _T_424 = asSInt(_T_423) node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0))) node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<17>(0h10000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<27>(0h4000000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<29>(0h10000000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = or(_T_410, _T_415) node _T_452 = or(_T_451, _T_420) node _T_453 = or(_T_452, _T_425) node _T_454 = or(_T_453, _T_430) node _T_455 = or(_T_454, _T_435) node _T_456 = or(_T_455, _T_440) node _T_457 = or(_T_456, _T_445) node _T_458 = or(_T_457, _T_450) node _T_459 = and(_T_405, _T_458) node _T_460 = or(UInt<1>(0h0), _T_401) node _T_461 = or(_T_460, _T_459) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_461, UInt<1>(0h1), "") : assert_20 node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(source_ok, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(is_aligned, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_471 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_471, UInt<1>(0h1), "") : assert_23 node _T_475 = eq(io.in.a.bits.mask, mask) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_475, UInt<1>(0h1), "") : assert_24 node _T_479 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_479, UInt<1>(0h1), "") : assert_25 node _T_483 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_483 : node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_485 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_486 = and(_T_484, _T_485) node _T_487 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_488 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_489 = or(_T_487, _T_488) node _T_490 = and(_T_486, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_493 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_494 = and(_T_492, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<13>(0h1000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = and(_T_495, _T_500) node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_504 = and(_T_502, _T_503) node _T_505 = or(UInt<1>(0h0), _T_504) node _T_506 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<14>(0h2000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<18>(0h2f000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<27>(0h4000000))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<13>(0h1000))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_542 = cvt(_T_541) node _T_543 = and(_T_542, asSInt(UInt<29>(0h10000000))) node _T_544 = asSInt(_T_543) node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0))) node _T_546 = or(_T_510, _T_515) node _T_547 = or(_T_546, _T_520) node _T_548 = or(_T_547, _T_525) node _T_549 = or(_T_548, _T_530) node _T_550 = or(_T_549, _T_535) node _T_551 = or(_T_550, _T_540) node _T_552 = or(_T_551, _T_545) node _T_553 = and(_T_505, _T_552) node _T_554 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_555 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_556 = cvt(_T_555) node _T_557 = and(_T_556, asSInt(UInt<17>(0h10000))) node _T_558 = asSInt(_T_557) node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0))) node _T_560 = and(_T_554, _T_559) node _T_561 = or(UInt<1>(0h0), _T_501) node _T_562 = or(_T_561, _T_553) node _T_563 = or(_T_562, _T_560) node _T_564 = and(_T_491, _T_563) node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(_T_564, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_564, UInt<1>(0h1), "") : assert_26 node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(source_ok, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(is_aligned, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_574 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_574, UInt<1>(0h1), "") : assert_29 node _T_578 = eq(io.in.a.bits.mask, mask) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_578, UInt<1>(0h1), "") : assert_30 node _T_582 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_582 : node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_584 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_585 = and(_T_583, _T_584) node _T_586 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_587 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(_T_585, _T_588) node _T_590 = or(UInt<1>(0h0), _T_589) node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_593 = and(_T_591, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_596 = cvt(_T_595) node _T_597 = and(_T_596, asSInt(UInt<13>(0h1000))) node _T_598 = asSInt(_T_597) node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0))) node _T_600 = and(_T_594, _T_599) node _T_601 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_602 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_603 = and(_T_601, _T_602) node _T_604 = or(UInt<1>(0h0), _T_603) node _T_605 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_606 = cvt(_T_605) node _T_607 = and(_T_606, asSInt(UInt<14>(0h2000))) node _T_608 = asSInt(_T_607) node _T_609 = eq(_T_608, asSInt(UInt<1>(0h0))) node _T_610 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_611 = cvt(_T_610) node _T_612 = and(_T_611, asSInt(UInt<18>(0h2f000))) node _T_613 = asSInt(_T_612) node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0))) node _T_615 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<17>(0h10000))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_626 = cvt(_T_625) node _T_627 = and(_T_626, asSInt(UInt<17>(0h10000))) node _T_628 = asSInt(_T_627) node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0))) node _T_630 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<27>(0h4000000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<29>(0h10000000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = or(_T_609, _T_614) node _T_646 = or(_T_645, _T_619) node _T_647 = or(_T_646, _T_624) node _T_648 = or(_T_647, _T_629) node _T_649 = or(_T_648, _T_634) node _T_650 = or(_T_649, _T_639) node _T_651 = or(_T_650, _T_644) node _T_652 = and(_T_604, _T_651) node _T_653 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_654 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_655 = cvt(_T_654) node _T_656 = and(_T_655, asSInt(UInt<17>(0h10000))) node _T_657 = asSInt(_T_656) node _T_658 = eq(_T_657, asSInt(UInt<1>(0h0))) node _T_659 = and(_T_653, _T_658) node _T_660 = or(UInt<1>(0h0), _T_600) node _T_661 = or(_T_660, _T_652) node _T_662 = or(_T_661, _T_659) node _T_663 = and(_T_590, _T_662) node _T_664 = asUInt(reset) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(_T_663, UInt<1>(0h0)) when _T_666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_663, UInt<1>(0h1), "") : assert_31 node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(source_ok, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(is_aligned, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_673 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_673, UInt<1>(0h1), "") : assert_34 node _T_677 = not(mask) node _T_678 = and(io.in.a.bits.mask, _T_677) node _T_679 = eq(_T_678, UInt<1>(0h0)) node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(_T_679, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_679, UInt<1>(0h1), "") : assert_35 node _T_683 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_683 : node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_685 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_686 = and(_T_684, _T_685) node _T_687 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_688 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_689 = or(_T_687, _T_688) node _T_690 = and(_T_686, _T_689) node _T_691 = or(UInt<1>(0h0), _T_690) node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_693 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _T_695 = or(UInt<1>(0h0), _T_694) node _T_696 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<14>(0h2000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_702 = cvt(_T_701) node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000))) node _T_704 = asSInt(_T_703) node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0))) node _T_706 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<18>(0h2f000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<17>(0h10000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<13>(0h1000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<17>(0h10000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<27>(0h4000000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<29>(0h10000000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = or(_T_700, _T_705) node _T_742 = or(_T_741, _T_710) node _T_743 = or(_T_742, _T_715) node _T_744 = or(_T_743, _T_720) node _T_745 = or(_T_744, _T_725) node _T_746 = or(_T_745, _T_730) node _T_747 = or(_T_746, _T_735) node _T_748 = or(_T_747, _T_740) node _T_749 = and(_T_695, _T_748) node _T_750 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_751 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = and(_T_750, _T_755) node _T_757 = or(UInt<1>(0h0), _T_749) node _T_758 = or(_T_757, _T_756) node _T_759 = and(_T_691, _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_759, UInt<1>(0h1), "") : assert_36 node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(source_ok, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(is_aligned, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_769 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_769, UInt<1>(0h1), "") : assert_39 node _T_773 = eq(io.in.a.bits.mask, mask) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_773, UInt<1>(0h1), "") : assert_40 node _T_777 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_777 : node _T_778 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_779 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_780 = and(_T_778, _T_779) node _T_781 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_782 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_783 = or(_T_781, _T_782) node _T_784 = and(_T_780, _T_783) node _T_785 = or(UInt<1>(0h0), _T_784) node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_787 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<14>(0h2000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<13>(0h1000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<18>(0h2f000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<17>(0h10000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<17>(0h10000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<27>(0h4000000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<29>(0h10000000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = or(_T_794, _T_799) node _T_836 = or(_T_835, _T_804) node _T_837 = or(_T_836, _T_809) node _T_838 = or(_T_837, _T_814) node _T_839 = or(_T_838, _T_819) node _T_840 = or(_T_839, _T_824) node _T_841 = or(_T_840, _T_829) node _T_842 = or(_T_841, _T_834) node _T_843 = and(_T_789, _T_842) node _T_844 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_845 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<17>(0h10000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = and(_T_844, _T_849) node _T_851 = or(UInt<1>(0h0), _T_843) node _T_852 = or(_T_851, _T_850) node _T_853 = and(_T_785, _T_852) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_853, UInt<1>(0h1), "") : assert_41 node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(source_ok, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(is_aligned, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_863 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_863, UInt<1>(0h1), "") : assert_44 node _T_867 = eq(io.in.a.bits.mask, mask) node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(_T_867, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_867, UInt<1>(0h1), "") : assert_45 node _T_871 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_871 : node _T_872 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_873 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_874 = and(_T_872, _T_873) node _T_875 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_876 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_877 = or(_T_875, _T_876) node _T_878 = and(_T_874, _T_877) node _T_879 = or(UInt<1>(0h0), _T_878) node _T_880 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_881 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_882 = and(_T_880, _T_881) node _T_883 = or(UInt<1>(0h0), _T_882) node _T_884 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = and(_T_883, _T_888) node _T_890 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_891 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<14>(0h2000))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<17>(0h10000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<18>(0h2f000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<27>(0h4000000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<13>(0h1000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = or(_T_895, _T_900) node _T_927 = or(_T_926, _T_905) node _T_928 = or(_T_927, _T_910) node _T_929 = or(_T_928, _T_915) node _T_930 = or(_T_929, _T_920) node _T_931 = or(_T_930, _T_925) node _T_932 = and(_T_890, _T_931) node _T_933 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_934 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_935 = and(_T_933, _T_934) node _T_936 = or(UInt<1>(0h0), _T_935) node _T_937 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<29>(0h10000000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = or(_T_941, _T_946) node _T_948 = and(_T_936, _T_947) node _T_949 = or(UInt<1>(0h0), _T_889) node _T_950 = or(_T_949, _T_932) node _T_951 = or(_T_950, _T_948) node _T_952 = and(_T_879, _T_951) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_952, UInt<1>(0h1), "") : assert_46 node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(source_ok, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(is_aligned, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_962 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_962, UInt<1>(0h1), "") : assert_49 node _T_966 = eq(io.in.a.bits.mask, mask) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_966, UInt<1>(0h1), "") : assert_50 node _T_970 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_970, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_974 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_974, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20)) node _T_978 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_978 : node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(source_ok_1, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_982 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_982, UInt<1>(0h1), "") : assert_54 node _T_986 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_986, UInt<1>(0h1), "") : assert_55 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_990, UInt<1>(0h1), "") : assert_56 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_994, UInt<1>(0h1), "") : assert_57 node _T_998 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_998 : node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(source_ok_1, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(sink_ok, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_60 node _T_1009 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_61 node _T_1013 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_62 node _T_1017 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_63 node _T_1021 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1022 = or(UInt<1>(0h1), _T_1021) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_64 node _T_1026 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1026 : node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(source_ok_1, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(sink_ok, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1033 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_67 node _T_1037 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_68 node _T_1041 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_69 node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1046 = or(_T_1045, io.in.d.bits.corrupt) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_70 node _T_1050 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1051 = or(UInt<1>(0h1), _T_1050) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_71 node _T_1055 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1055 : node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(source_ok_1, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1059 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_73 node _T_1063 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_74 node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1068 = or(UInt<1>(0h1), _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_75 node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1072 : node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(source_ok_1, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_77 node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.d.bits.corrupt) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_78 node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1086 = or(UInt<1>(0h1), _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_79 node _T_1090 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1090 : node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok_1, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_81 node _T_1098 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_82 node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1103 = or(UInt<1>(0h1), _T_1102) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1107 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_84 node _T_1111 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) node _T_1113 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1114 = cvt(_T_1113) node _T_1115 = and(_T_1114, asSInt(UInt<1>(0h0))) node _T_1116 = asSInt(_T_1115) node _T_1117 = eq(_T_1116, asSInt(UInt<1>(0h0))) node _T_1118 = or(_T_1112, _T_1117) node _T_1119 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) node _T_1121 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = or(_T_1120, _T_1125) node _T_1127 = and(_T_1118, _T_1126) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h100c0))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0h8000040)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<17>(0h100c0))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<28>(0h8000080)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<17>(0h100c0))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<17>(0h100c0))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_61 = cvt(_address_ok_T_60) node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<27>(0h4000000))) node _address_ok_T_63 = asSInt(_address_ok_T_62) node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0))) node _address_ok_T_65 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_66 = cvt(_address_ok_T_65) node _address_ok_T_67 = and(_address_ok_T_66, asSInt(UInt<13>(0h1000))) node _address_ok_T_68 = asSInt(_address_ok_T_67) node _address_ok_T_69 = eq(_address_ok_T_68, asSInt(UInt<1>(0h0))) node _address_ok_T_70 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.b.bits.address, UInt<32>(0h80000040)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.b.bits.address, UInt<32>(0h80000080)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.b.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[18] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 connect _address_ok_WIRE[12], _address_ok_T_64 connect _address_ok_WIRE[13], _address_ok_T_69 connect _address_ok_WIRE[14], _address_ok_T_74 connect _address_ok_WIRE[15], _address_ok_T_79 connect _address_ok_WIRE[16], _address_ok_T_84 connect _address_ok_WIRE[17], _address_ok_T_89 node _address_ok_T_90 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_91 = or(_address_ok_T_90, _address_ok_WIRE[2]) node _address_ok_T_92 = or(_address_ok_T_91, _address_ok_WIRE[3]) node _address_ok_T_93 = or(_address_ok_T_92, _address_ok_WIRE[4]) node _address_ok_T_94 = or(_address_ok_T_93, _address_ok_WIRE[5]) node _address_ok_T_95 = or(_address_ok_T_94, _address_ok_WIRE[6]) node _address_ok_T_96 = or(_address_ok_T_95, _address_ok_WIRE[7]) node _address_ok_T_97 = or(_address_ok_T_96, _address_ok_WIRE[8]) node _address_ok_T_98 = or(_address_ok_T_97, _address_ok_WIRE[9]) node _address_ok_T_99 = or(_address_ok_T_98, _address_ok_WIRE[10]) node _address_ok_T_100 = or(_address_ok_T_99, _address_ok_WIRE[11]) node _address_ok_T_101 = or(_address_ok_T_100, _address_ok_WIRE[12]) node _address_ok_T_102 = or(_address_ok_T_101, _address_ok_WIRE[13]) node _address_ok_T_103 = or(_address_ok_T_102, _address_ok_WIRE[14]) node _address_ok_T_104 = or(_address_ok_T_103, _address_ok_WIRE[15]) node _address_ok_T_105 = or(_address_ok_T_104, _address_ok_WIRE[16]) node address_ok = or(_address_ok_T_105, _address_ok_WIRE[17]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3) wire _legal_source_WIRE_1 : UInt<1> connect _legal_source_WIRE_1, _legal_source_T_4 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1131 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1131 : node _T_1132 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1133 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1132 connect _WIRE_4[1], _T_1133 node _T_1134 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1135 = mux(_WIRE_4[0], _T_1134, UInt<1>(0h0)) node _T_1136 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1137 = or(_T_1135, _T_1136) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1137 node _T_1138 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1139 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1140 = and(_T_1138, _T_1139) node _T_1141 = or(UInt<1>(0h0), _T_1140) node _T_1142 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<14>(0h2000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1148 = cvt(_T_1147) node _T_1149 = and(_T_1148, asSInt(UInt<13>(0h1000))) node _T_1150 = asSInt(_T_1149) node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0))) node _T_1152 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<17>(0h10000))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1158 = cvt(_T_1157) node _T_1159 = and(_T_1158, asSInt(UInt<18>(0h2f000))) node _T_1160 = asSInt(_T_1159) node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0))) node _T_1162 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1163 = cvt(_T_1162) node _T_1164 = and(_T_1163, asSInt(UInt<17>(0h10000))) node _T_1165 = asSInt(_T_1164) node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0))) node _T_1167 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1168 = cvt(_T_1167) node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000))) node _T_1170 = asSInt(_T_1169) node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0))) node _T_1172 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1173 = cvt(_T_1172) node _T_1174 = and(_T_1173, asSInt(UInt<17>(0h10000))) node _T_1175 = asSInt(_T_1174) node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0))) node _T_1177 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1178 = cvt(_T_1177) node _T_1179 = and(_T_1178, asSInt(UInt<27>(0h4000000))) node _T_1180 = asSInt(_T_1179) node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1183 = cvt(_T_1182) node _T_1184 = and(_T_1183, asSInt(UInt<13>(0h1000))) node _T_1185 = asSInt(_T_1184) node _T_1186 = eq(_T_1185, asSInt(UInt<1>(0h0))) node _T_1187 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1188 = cvt(_T_1187) node _T_1189 = and(_T_1188, asSInt(UInt<29>(0h10000000))) node _T_1190 = asSInt(_T_1189) node _T_1191 = eq(_T_1190, asSInt(UInt<1>(0h0))) node _T_1192 = or(_T_1146, _T_1151) node _T_1193 = or(_T_1192, _T_1156) node _T_1194 = or(_T_1193, _T_1161) node _T_1195 = or(_T_1194, _T_1166) node _T_1196 = or(_T_1195, _T_1171) node _T_1197 = or(_T_1196, _T_1176) node _T_1198 = or(_T_1197, _T_1181) node _T_1199 = or(_T_1198, _T_1186) node _T_1200 = or(_T_1199, _T_1191) node _T_1201 = and(_T_1141, _T_1200) node _T_1202 = or(UInt<1>(0h0), _T_1201) node _T_1203 = and(_WIRE_5, _T_1202) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86 node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(address_ok, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(legal_source, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1216 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90 node _T_1220 = eq(io.in.b.bits.mask, mask_1) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91 node _T_1224 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92 node _T_1228 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1228 : node _T_1229 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1230 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1231 = and(_T_1229, _T_1230) node _T_1232 = or(UInt<1>(0h0), _T_1231) node _T_1233 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1234 = cvt(_T_1233) node _T_1235 = and(_T_1234, asSInt(UInt<14>(0h2000))) node _T_1236 = asSInt(_T_1235) node _T_1237 = eq(_T_1236, asSInt(UInt<1>(0h0))) node _T_1238 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<13>(0h1000))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<17>(0h10000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<18>(0h2f000))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<17>(0h10000))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<13>(0h1000))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<17>(0h10000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1269 = cvt(_T_1268) node _T_1270 = and(_T_1269, asSInt(UInt<27>(0h4000000))) node _T_1271 = asSInt(_T_1270) node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0))) node _T_1273 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1274 = cvt(_T_1273) node _T_1275 = and(_T_1274, asSInt(UInt<13>(0h1000))) node _T_1276 = asSInt(_T_1275) node _T_1277 = eq(_T_1276, asSInt(UInt<1>(0h0))) node _T_1278 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<29>(0h10000000))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = or(_T_1237, _T_1242) node _T_1284 = or(_T_1283, _T_1247) node _T_1285 = or(_T_1284, _T_1252) node _T_1286 = or(_T_1285, _T_1257) node _T_1287 = or(_T_1286, _T_1262) node _T_1288 = or(_T_1287, _T_1267) node _T_1289 = or(_T_1288, _T_1272) node _T_1290 = or(_T_1289, _T_1277) node _T_1291 = or(_T_1290, _T_1282) node _T_1292 = and(_T_1232, _T_1291) node _T_1293 = or(UInt<1>(0h0), _T_1292) node _T_1294 = and(UInt<1>(0h0), _T_1293) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_93 node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(address_ok, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(legal_source, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1307 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(_T_1307, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1307, UInt<1>(0h1), "") : assert_97 node _T_1311 = eq(io.in.b.bits.mask, mask_1) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_98 node _T_1315 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_99 node _T_1319 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1319 : node _T_1320 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1321 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = or(UInt<1>(0h0), _T_1322) node _T_1324 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<14>(0h2000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1330 = cvt(_T_1329) node _T_1331 = and(_T_1330, asSInt(UInt<13>(0h1000))) node _T_1332 = asSInt(_T_1331) node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0))) node _T_1334 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1335 = cvt(_T_1334) node _T_1336 = and(_T_1335, asSInt(UInt<17>(0h10000))) node _T_1337 = asSInt(_T_1336) node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0))) node _T_1339 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1340 = cvt(_T_1339) node _T_1341 = and(_T_1340, asSInt(UInt<18>(0h2f000))) node _T_1342 = asSInt(_T_1341) node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0))) node _T_1344 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1345 = cvt(_T_1344) node _T_1346 = and(_T_1345, asSInt(UInt<17>(0h10000))) node _T_1347 = asSInt(_T_1346) node _T_1348 = eq(_T_1347, asSInt(UInt<1>(0h0))) node _T_1349 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1350 = cvt(_T_1349) node _T_1351 = and(_T_1350, asSInt(UInt<13>(0h1000))) node _T_1352 = asSInt(_T_1351) node _T_1353 = eq(_T_1352, asSInt(UInt<1>(0h0))) node _T_1354 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1355 = cvt(_T_1354) node _T_1356 = and(_T_1355, asSInt(UInt<17>(0h10000))) node _T_1357 = asSInt(_T_1356) node _T_1358 = eq(_T_1357, asSInt(UInt<1>(0h0))) node _T_1359 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1360 = cvt(_T_1359) node _T_1361 = and(_T_1360, asSInt(UInt<27>(0h4000000))) node _T_1362 = asSInt(_T_1361) node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0))) node _T_1364 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1365 = cvt(_T_1364) node _T_1366 = and(_T_1365, asSInt(UInt<13>(0h1000))) node _T_1367 = asSInt(_T_1366) node _T_1368 = eq(_T_1367, asSInt(UInt<1>(0h0))) node _T_1369 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1370 = cvt(_T_1369) node _T_1371 = and(_T_1370, asSInt(UInt<29>(0h10000000))) node _T_1372 = asSInt(_T_1371) node _T_1373 = eq(_T_1372, asSInt(UInt<1>(0h0))) node _T_1374 = or(_T_1328, _T_1333) node _T_1375 = or(_T_1374, _T_1338) node _T_1376 = or(_T_1375, _T_1343) node _T_1377 = or(_T_1376, _T_1348) node _T_1378 = or(_T_1377, _T_1353) node _T_1379 = or(_T_1378, _T_1358) node _T_1380 = or(_T_1379, _T_1363) node _T_1381 = or(_T_1380, _T_1368) node _T_1382 = or(_T_1381, _T_1373) node _T_1383 = and(_T_1323, _T_1382) node _T_1384 = or(UInt<1>(0h0), _T_1383) node _T_1385 = and(UInt<1>(0h0), _T_1384) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_100 node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(address_ok, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1392 = asUInt(reset) node _T_1393 = eq(_T_1392, UInt<1>(0h0)) when _T_1393 : node _T_1394 = eq(legal_source, UInt<1>(0h0)) when _T_1394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1398 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_104 node _T_1402 = eq(io.in.b.bits.mask, mask_1) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_105 node _T_1406 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1406 : node _T_1407 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1408 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1409 = and(_T_1407, _T_1408) node _T_1410 = or(UInt<1>(0h0), _T_1409) node _T_1411 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1412 = cvt(_T_1411) node _T_1413 = and(_T_1412, asSInt(UInt<14>(0h2000))) node _T_1414 = asSInt(_T_1413) node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0))) node _T_1416 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<17>(0h10000))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1427 = cvt(_T_1426) node _T_1428 = and(_T_1427, asSInt(UInt<18>(0h2f000))) node _T_1429 = asSInt(_T_1428) node _T_1430 = eq(_T_1429, asSInt(UInt<1>(0h0))) node _T_1431 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1432 = cvt(_T_1431) node _T_1433 = and(_T_1432, asSInt(UInt<17>(0h10000))) node _T_1434 = asSInt(_T_1433) node _T_1435 = eq(_T_1434, asSInt(UInt<1>(0h0))) node _T_1436 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1437 = cvt(_T_1436) node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000))) node _T_1439 = asSInt(_T_1438) node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0))) node _T_1441 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1442 = cvt(_T_1441) node _T_1443 = and(_T_1442, asSInt(UInt<17>(0h10000))) node _T_1444 = asSInt(_T_1443) node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0))) node _T_1446 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1447 = cvt(_T_1446) node _T_1448 = and(_T_1447, asSInt(UInt<27>(0h4000000))) node _T_1449 = asSInt(_T_1448) node _T_1450 = eq(_T_1449, asSInt(UInt<1>(0h0))) node _T_1451 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1452 = cvt(_T_1451) node _T_1453 = and(_T_1452, asSInt(UInt<13>(0h1000))) node _T_1454 = asSInt(_T_1453) node _T_1455 = eq(_T_1454, asSInt(UInt<1>(0h0))) node _T_1456 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<29>(0h10000000))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = or(_T_1415, _T_1420) node _T_1462 = or(_T_1461, _T_1425) node _T_1463 = or(_T_1462, _T_1430) node _T_1464 = or(_T_1463, _T_1435) node _T_1465 = or(_T_1464, _T_1440) node _T_1466 = or(_T_1465, _T_1445) node _T_1467 = or(_T_1466, _T_1450) node _T_1468 = or(_T_1467, _T_1455) node _T_1469 = or(_T_1468, _T_1460) node _T_1470 = and(_T_1410, _T_1469) node _T_1471 = or(UInt<1>(0h0), _T_1470) node _T_1472 = and(UInt<1>(0h0), _T_1471) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_106 node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(address_ok, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(legal_source, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1485 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_110 node _T_1489 = not(mask_1) node _T_1490 = and(io.in.b.bits.mask, _T_1489) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_111 node _T_1495 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1495 : node _T_1496 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1497 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = or(UInt<1>(0h0), _T_1498) node _T_1500 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<14>(0h2000))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1506 = cvt(_T_1505) node _T_1507 = and(_T_1506, asSInt(UInt<13>(0h1000))) node _T_1508 = asSInt(_T_1507) node _T_1509 = eq(_T_1508, asSInt(UInt<1>(0h0))) node _T_1510 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1511 = cvt(_T_1510) node _T_1512 = and(_T_1511, asSInt(UInt<17>(0h10000))) node _T_1513 = asSInt(_T_1512) node _T_1514 = eq(_T_1513, asSInt(UInt<1>(0h0))) node _T_1515 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1516 = cvt(_T_1515) node _T_1517 = and(_T_1516, asSInt(UInt<18>(0h2f000))) node _T_1518 = asSInt(_T_1517) node _T_1519 = eq(_T_1518, asSInt(UInt<1>(0h0))) node _T_1520 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1521 = cvt(_T_1520) node _T_1522 = and(_T_1521, asSInt(UInt<17>(0h10000))) node _T_1523 = asSInt(_T_1522) node _T_1524 = eq(_T_1523, asSInt(UInt<1>(0h0))) node _T_1525 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1526 = cvt(_T_1525) node _T_1527 = and(_T_1526, asSInt(UInt<13>(0h1000))) node _T_1528 = asSInt(_T_1527) node _T_1529 = eq(_T_1528, asSInt(UInt<1>(0h0))) node _T_1530 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1531 = cvt(_T_1530) node _T_1532 = and(_T_1531, asSInt(UInt<17>(0h10000))) node _T_1533 = asSInt(_T_1532) node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0))) node _T_1535 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1536 = cvt(_T_1535) node _T_1537 = and(_T_1536, asSInt(UInt<27>(0h4000000))) node _T_1538 = asSInt(_T_1537) node _T_1539 = eq(_T_1538, asSInt(UInt<1>(0h0))) node _T_1540 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1541 = cvt(_T_1540) node _T_1542 = and(_T_1541, asSInt(UInt<13>(0h1000))) node _T_1543 = asSInt(_T_1542) node _T_1544 = eq(_T_1543, asSInt(UInt<1>(0h0))) node _T_1545 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1546 = cvt(_T_1545) node _T_1547 = and(_T_1546, asSInt(UInt<29>(0h10000000))) node _T_1548 = asSInt(_T_1547) node _T_1549 = eq(_T_1548, asSInt(UInt<1>(0h0))) node _T_1550 = or(_T_1504, _T_1509) node _T_1551 = or(_T_1550, _T_1514) node _T_1552 = or(_T_1551, _T_1519) node _T_1553 = or(_T_1552, _T_1524) node _T_1554 = or(_T_1553, _T_1529) node _T_1555 = or(_T_1554, _T_1534) node _T_1556 = or(_T_1555, _T_1539) node _T_1557 = or(_T_1556, _T_1544) node _T_1558 = or(_T_1557, _T_1549) node _T_1559 = and(_T_1499, _T_1558) node _T_1560 = or(UInt<1>(0h0), _T_1559) node _T_1561 = and(UInt<1>(0h0), _T_1560) node _T_1562 = asUInt(reset) node _T_1563 = eq(_T_1562, UInt<1>(0h0)) when _T_1563 : node _T_1564 = eq(_T_1561, UInt<1>(0h0)) when _T_1564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1561, UInt<1>(0h1), "") : assert_112 node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(address_ok, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(legal_source, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1571 = asUInt(reset) node _T_1572 = eq(_T_1571, UInt<1>(0h0)) when _T_1572 : node _T_1573 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1574 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1575 = asUInt(reset) node _T_1576 = eq(_T_1575, UInt<1>(0h0)) when _T_1576 : node _T_1577 = eq(_T_1574, UInt<1>(0h0)) when _T_1577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1574, UInt<1>(0h1), "") : assert_116 node _T_1578 = eq(io.in.b.bits.mask, mask_1) node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(_T_1578, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1578, UInt<1>(0h1), "") : assert_117 node _T_1582 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1582 : node _T_1583 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1584 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1585 = and(_T_1583, _T_1584) node _T_1586 = or(UInt<1>(0h0), _T_1585) node _T_1587 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1588 = cvt(_T_1587) node _T_1589 = and(_T_1588, asSInt(UInt<14>(0h2000))) node _T_1590 = asSInt(_T_1589) node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0))) node _T_1592 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1593 = cvt(_T_1592) node _T_1594 = and(_T_1593, asSInt(UInt<13>(0h1000))) node _T_1595 = asSInt(_T_1594) node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1598 = cvt(_T_1597) node _T_1599 = and(_T_1598, asSInt(UInt<17>(0h10000))) node _T_1600 = asSInt(_T_1599) node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0))) node _T_1602 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<18>(0h2f000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<17>(0h10000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<27>(0h4000000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<13>(0h1000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<29>(0h10000000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = or(_T_1591, _T_1596) node _T_1638 = or(_T_1637, _T_1601) node _T_1639 = or(_T_1638, _T_1606) node _T_1640 = or(_T_1639, _T_1611) node _T_1641 = or(_T_1640, _T_1616) node _T_1642 = or(_T_1641, _T_1621) node _T_1643 = or(_T_1642, _T_1626) node _T_1644 = or(_T_1643, _T_1631) node _T_1645 = or(_T_1644, _T_1636) node _T_1646 = and(_T_1586, _T_1645) node _T_1647 = or(UInt<1>(0h0), _T_1646) node _T_1648 = and(UInt<1>(0h0), _T_1647) node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(_T_1648, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1648, UInt<1>(0h1), "") : assert_118 node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(address_ok, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(legal_source, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1658 = asUInt(reset) node _T_1659 = eq(_T_1658, UInt<1>(0h0)) when _T_1659 : node _T_1660 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1661 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(_T_1661, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1661, UInt<1>(0h1), "") : assert_122 node _T_1665 = eq(io.in.b.bits.mask, mask_1) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_123 node _T_1669 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1669 : node _T_1670 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1671 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1672 = and(_T_1670, _T_1671) node _T_1673 = or(UInt<1>(0h0), _T_1672) node _T_1674 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1675 = cvt(_T_1674) node _T_1676 = and(_T_1675, asSInt(UInt<14>(0h2000))) node _T_1677 = asSInt(_T_1676) node _T_1678 = eq(_T_1677, asSInt(UInt<1>(0h0))) node _T_1679 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1680 = cvt(_T_1679) node _T_1681 = and(_T_1680, asSInt(UInt<13>(0h1000))) node _T_1682 = asSInt(_T_1681) node _T_1683 = eq(_T_1682, asSInt(UInt<1>(0h0))) node _T_1684 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1685 = cvt(_T_1684) node _T_1686 = and(_T_1685, asSInt(UInt<17>(0h10000))) node _T_1687 = asSInt(_T_1686) node _T_1688 = eq(_T_1687, asSInt(UInt<1>(0h0))) node _T_1689 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1690 = cvt(_T_1689) node _T_1691 = and(_T_1690, asSInt(UInt<18>(0h2f000))) node _T_1692 = asSInt(_T_1691) node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0))) node _T_1694 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1695 = cvt(_T_1694) node _T_1696 = and(_T_1695, asSInt(UInt<17>(0h10000))) node _T_1697 = asSInt(_T_1696) node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0))) node _T_1699 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1700 = cvt(_T_1699) node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000))) node _T_1702 = asSInt(_T_1701) node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0))) node _T_1704 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1705 = cvt(_T_1704) node _T_1706 = and(_T_1705, asSInt(UInt<17>(0h10000))) node _T_1707 = asSInt(_T_1706) node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0))) node _T_1709 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1710 = cvt(_T_1709) node _T_1711 = and(_T_1710, asSInt(UInt<27>(0h4000000))) node _T_1712 = asSInt(_T_1711) node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0))) node _T_1714 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1715 = cvt(_T_1714) node _T_1716 = and(_T_1715, asSInt(UInt<13>(0h1000))) node _T_1717 = asSInt(_T_1716) node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0))) node _T_1719 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1720 = cvt(_T_1719) node _T_1721 = and(_T_1720, asSInt(UInt<29>(0h10000000))) node _T_1722 = asSInt(_T_1721) node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0))) node _T_1724 = or(_T_1678, _T_1683) node _T_1725 = or(_T_1724, _T_1688) node _T_1726 = or(_T_1725, _T_1693) node _T_1727 = or(_T_1726, _T_1698) node _T_1728 = or(_T_1727, _T_1703) node _T_1729 = or(_T_1728, _T_1708) node _T_1730 = or(_T_1729, _T_1713) node _T_1731 = or(_T_1730, _T_1718) node _T_1732 = or(_T_1731, _T_1723) node _T_1733 = and(_T_1673, _T_1732) node _T_1734 = or(UInt<1>(0h0), _T_1733) node _T_1735 = and(UInt<1>(0h0), _T_1734) node _T_1736 = asUInt(reset) node _T_1737 = eq(_T_1736, UInt<1>(0h0)) when _T_1737 : node _T_1738 = eq(_T_1735, UInt<1>(0h0)) when _T_1738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1735, UInt<1>(0h1), "") : assert_124 node _T_1739 = asUInt(reset) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) when _T_1740 : node _T_1741 = eq(address_ok, UInt<1>(0h0)) when _T_1741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1742 = asUInt(reset) node _T_1743 = eq(_T_1742, UInt<1>(0h0)) when _T_1743 : node _T_1744 = eq(legal_source, UInt<1>(0h0)) when _T_1744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1745 = asUInt(reset) node _T_1746 = eq(_T_1745, UInt<1>(0h0)) when _T_1746 : node _T_1747 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1748 = eq(io.in.b.bits.mask, mask_1) node _T_1749 = asUInt(reset) node _T_1750 = eq(_T_1749, UInt<1>(0h0)) when _T_1750 : node _T_1751 = eq(_T_1748, UInt<1>(0h0)) when _T_1751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1748, UInt<1>(0h1), "") : assert_128 node _T_1752 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1756 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_130 node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_4 connect _source_ok_WIRE_2[1], _source_ok_T_5 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_106 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_107 = cvt(_address_ok_T_106) node _address_ok_T_108 = and(_address_ok_T_107, asSInt(UInt<13>(0h1000))) node _address_ok_T_109 = asSInt(_address_ok_T_108) node _address_ok_T_110 = eq(_address_ok_T_109, asSInt(UInt<1>(0h0))) node _address_ok_T_111 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_112 = cvt(_address_ok_T_111) node _address_ok_T_113 = and(_address_ok_T_112, asSInt(UInt<13>(0h1000))) node _address_ok_T_114 = asSInt(_address_ok_T_113) node _address_ok_T_115 = eq(_address_ok_T_114, asSInt(UInt<1>(0h0))) node _address_ok_T_116 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_117 = cvt(_address_ok_T_116) node _address_ok_T_118 = and(_address_ok_T_117, asSInt(UInt<13>(0h1000))) node _address_ok_T_119 = asSInt(_address_ok_T_118) node _address_ok_T_120 = eq(_address_ok_T_119, asSInt(UInt<1>(0h0))) node _address_ok_T_121 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_122 = cvt(_address_ok_T_121) node _address_ok_T_123 = and(_address_ok_T_122, asSInt(UInt<17>(0h10000))) node _address_ok_T_124 = asSInt(_address_ok_T_123) node _address_ok_T_125 = eq(_address_ok_T_124, asSInt(UInt<1>(0h0))) node _address_ok_T_126 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_127 = cvt(_address_ok_T_126) node _address_ok_T_128 = and(_address_ok_T_127, asSInt(UInt<13>(0h1000))) node _address_ok_T_129 = asSInt(_address_ok_T_128) node _address_ok_T_130 = eq(_address_ok_T_129, asSInt(UInt<1>(0h0))) node _address_ok_T_131 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_132 = cvt(_address_ok_T_131) node _address_ok_T_133 = and(_address_ok_T_132, asSInt(UInt<13>(0h1000))) node _address_ok_T_134 = asSInt(_address_ok_T_133) node _address_ok_T_135 = eq(_address_ok_T_134, asSInt(UInt<1>(0h0))) node _address_ok_T_136 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_137 = cvt(_address_ok_T_136) node _address_ok_T_138 = and(_address_ok_T_137, asSInt(UInt<17>(0h10000))) node _address_ok_T_139 = asSInt(_address_ok_T_138) node _address_ok_T_140 = eq(_address_ok_T_139, asSInt(UInt<1>(0h0))) node _address_ok_T_141 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_142 = cvt(_address_ok_T_141) node _address_ok_T_143 = and(_address_ok_T_142, asSInt(UInt<13>(0h1000))) node _address_ok_T_144 = asSInt(_address_ok_T_143) node _address_ok_T_145 = eq(_address_ok_T_144, asSInt(UInt<1>(0h0))) node _address_ok_T_146 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_147 = cvt(_address_ok_T_146) node _address_ok_T_148 = and(_address_ok_T_147, asSInt(UInt<17>(0h100c0))) node _address_ok_T_149 = asSInt(_address_ok_T_148) node _address_ok_T_150 = eq(_address_ok_T_149, asSInt(UInt<1>(0h0))) node _address_ok_T_151 = xor(io.in.c.bits.address, UInt<28>(0h8000040)) node _address_ok_T_152 = cvt(_address_ok_T_151) node _address_ok_T_153 = and(_address_ok_T_152, asSInt(UInt<17>(0h100c0))) node _address_ok_T_154 = asSInt(_address_ok_T_153) node _address_ok_T_155 = eq(_address_ok_T_154, asSInt(UInt<1>(0h0))) node _address_ok_T_156 = xor(io.in.c.bits.address, UInt<28>(0h8000080)) node _address_ok_T_157 = cvt(_address_ok_T_156) node _address_ok_T_158 = and(_address_ok_T_157, asSInt(UInt<17>(0h100c0))) node _address_ok_T_159 = asSInt(_address_ok_T_158) node _address_ok_T_160 = eq(_address_ok_T_159, asSInt(UInt<1>(0h0))) node _address_ok_T_161 = xor(io.in.c.bits.address, UInt<28>(0h80000c0)) node _address_ok_T_162 = cvt(_address_ok_T_161) node _address_ok_T_163 = and(_address_ok_T_162, asSInt(UInt<17>(0h100c0))) node _address_ok_T_164 = asSInt(_address_ok_T_163) node _address_ok_T_165 = eq(_address_ok_T_164, asSInt(UInt<1>(0h0))) node _address_ok_T_166 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_167 = cvt(_address_ok_T_166) node _address_ok_T_168 = and(_address_ok_T_167, asSInt(UInt<27>(0h4000000))) node _address_ok_T_169 = asSInt(_address_ok_T_168) node _address_ok_T_170 = eq(_address_ok_T_169, asSInt(UInt<1>(0h0))) node _address_ok_T_171 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_172 = cvt(_address_ok_T_171) node _address_ok_T_173 = and(_address_ok_T_172, asSInt(UInt<13>(0h1000))) node _address_ok_T_174 = asSInt(_address_ok_T_173) node _address_ok_T_175 = eq(_address_ok_T_174, asSInt(UInt<1>(0h0))) node _address_ok_T_176 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_177 = cvt(_address_ok_T_176) node _address_ok_T_178 = and(_address_ok_T_177, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_179 = asSInt(_address_ok_T_178) node _address_ok_T_180 = eq(_address_ok_T_179, asSInt(UInt<1>(0h0))) node _address_ok_T_181 = xor(io.in.c.bits.address, UInt<32>(0h80000040)) node _address_ok_T_182 = cvt(_address_ok_T_181) node _address_ok_T_183 = and(_address_ok_T_182, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_184 = asSInt(_address_ok_T_183) node _address_ok_T_185 = eq(_address_ok_T_184, asSInt(UInt<1>(0h0))) node _address_ok_T_186 = xor(io.in.c.bits.address, UInt<32>(0h80000080)) node _address_ok_T_187 = cvt(_address_ok_T_186) node _address_ok_T_188 = and(_address_ok_T_187, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_189 = asSInt(_address_ok_T_188) node _address_ok_T_190 = eq(_address_ok_T_189, asSInt(UInt<1>(0h0))) node _address_ok_T_191 = xor(io.in.c.bits.address, UInt<32>(0h800000c0)) node _address_ok_T_192 = cvt(_address_ok_T_191) node _address_ok_T_193 = and(_address_ok_T_192, asSInt(UInt<29>(0h100000c0))) node _address_ok_T_194 = asSInt(_address_ok_T_193) node _address_ok_T_195 = eq(_address_ok_T_194, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[18] connect _address_ok_WIRE_1[0], _address_ok_T_110 connect _address_ok_WIRE_1[1], _address_ok_T_115 connect _address_ok_WIRE_1[2], _address_ok_T_120 connect _address_ok_WIRE_1[3], _address_ok_T_125 connect _address_ok_WIRE_1[4], _address_ok_T_130 connect _address_ok_WIRE_1[5], _address_ok_T_135 connect _address_ok_WIRE_1[6], _address_ok_T_140 connect _address_ok_WIRE_1[7], _address_ok_T_145 connect _address_ok_WIRE_1[8], _address_ok_T_150 connect _address_ok_WIRE_1[9], _address_ok_T_155 connect _address_ok_WIRE_1[10], _address_ok_T_160 connect _address_ok_WIRE_1[11], _address_ok_T_165 connect _address_ok_WIRE_1[12], _address_ok_T_170 connect _address_ok_WIRE_1[13], _address_ok_T_175 connect _address_ok_WIRE_1[14], _address_ok_T_180 connect _address_ok_WIRE_1[15], _address_ok_T_185 connect _address_ok_WIRE_1[16], _address_ok_T_190 connect _address_ok_WIRE_1[17], _address_ok_T_195 node _address_ok_T_196 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_197 = or(_address_ok_T_196, _address_ok_WIRE_1[2]) node _address_ok_T_198 = or(_address_ok_T_197, _address_ok_WIRE_1[3]) node _address_ok_T_199 = or(_address_ok_T_198, _address_ok_WIRE_1[4]) node _address_ok_T_200 = or(_address_ok_T_199, _address_ok_WIRE_1[5]) node _address_ok_T_201 = or(_address_ok_T_200, _address_ok_WIRE_1[6]) node _address_ok_T_202 = or(_address_ok_T_201, _address_ok_WIRE_1[7]) node _address_ok_T_203 = or(_address_ok_T_202, _address_ok_WIRE_1[8]) node _address_ok_T_204 = or(_address_ok_T_203, _address_ok_WIRE_1[9]) node _address_ok_T_205 = or(_address_ok_T_204, _address_ok_WIRE_1[10]) node _address_ok_T_206 = or(_address_ok_T_205, _address_ok_WIRE_1[11]) node _address_ok_T_207 = or(_address_ok_T_206, _address_ok_WIRE_1[12]) node _address_ok_T_208 = or(_address_ok_T_207, _address_ok_WIRE_1[13]) node _address_ok_T_209 = or(_address_ok_T_208, _address_ok_WIRE_1[14]) node _address_ok_T_210 = or(_address_ok_T_209, _address_ok_WIRE_1[15]) node _address_ok_T_211 = or(_address_ok_T_210, _address_ok_WIRE_1[16]) node address_ok_1 = or(_address_ok_T_211, _address_ok_WIRE_1[17]) node _T_1760 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1761, _T_1766) node _T_1768 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1771 = cvt(_T_1770) node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = asSInt(_T_1772) node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0))) node _T_1775 = or(_T_1769, _T_1774) node _T_1776 = and(_T_1767, _T_1775) node _T_1777 = asUInt(reset) node _T_1778 = eq(_T_1777, UInt<1>(0h0)) when _T_1778 : node _T_1779 = eq(_T_1776, UInt<1>(0h0)) when _T_1779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1776, UInt<1>(0h1), "") : assert_131 node _T_1780 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1780 : node _T_1781 = asUInt(reset) node _T_1782 = eq(_T_1781, UInt<1>(0h0)) when _T_1782 : node _T_1783 = eq(address_ok_1, UInt<1>(0h0)) when _T_1783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1784 = asUInt(reset) node _T_1785 = eq(_T_1784, UInt<1>(0h0)) when _T_1785 : node _T_1786 = eq(source_ok_2, UInt<1>(0h0)) when _T_1786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1787 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_134 node _T_1791 = asUInt(reset) node _T_1792 = eq(_T_1791, UInt<1>(0h0)) when _T_1792 : node _T_1793 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1794 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_136 node _T_1798 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_137 node _T_1802 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1802 : node _T_1803 = asUInt(reset) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) when _T_1804 : node _T_1805 = eq(address_ok_1, UInt<1>(0h0)) when _T_1805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1806 = asUInt(reset) node _T_1807 = eq(_T_1806, UInt<1>(0h0)) when _T_1807 : node _T_1808 = eq(source_ok_2, UInt<1>(0h0)) when _T_1808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1809 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(_T_1809, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1809, UInt<1>(0h1), "") : assert_140 node _T_1813 = asUInt(reset) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) when _T_1814 : node _T_1815 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1816 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1817 = asUInt(reset) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(_T_1816, UInt<1>(0h0)) when _T_1819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1816, UInt<1>(0h1), "") : assert_142 node _T_1820 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1820 : node _T_1821 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1822 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1825 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1826 = or(_T_1824, _T_1825) node _T_1827 = and(_T_1823, _T_1826) node _T_1828 = or(UInt<1>(0h0), _T_1827) node _T_1829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1830 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1831 = cvt(_T_1830) node _T_1832 = and(_T_1831, asSInt(UInt<14>(0h2000))) node _T_1833 = asSInt(_T_1832) node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1836 = cvt(_T_1835) node _T_1837 = and(_T_1836, asSInt(UInt<13>(0h1000))) node _T_1838 = asSInt(_T_1837) node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0))) node _T_1840 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<17>(0h10000))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1846 = cvt(_T_1845) node _T_1847 = and(_T_1846, asSInt(UInt<18>(0h2f000))) node _T_1848 = asSInt(_T_1847) node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0))) node _T_1850 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1851 = cvt(_T_1850) node _T_1852 = and(_T_1851, asSInt(UInt<17>(0h10000))) node _T_1853 = asSInt(_T_1852) node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0))) node _T_1855 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1856 = cvt(_T_1855) node _T_1857 = and(_T_1856, asSInt(UInt<13>(0h1000))) node _T_1858 = asSInt(_T_1857) node _T_1859 = eq(_T_1858, asSInt(UInt<1>(0h0))) node _T_1860 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1861 = cvt(_T_1860) node _T_1862 = and(_T_1861, asSInt(UInt<27>(0h4000000))) node _T_1863 = asSInt(_T_1862) node _T_1864 = eq(_T_1863, asSInt(UInt<1>(0h0))) node _T_1865 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1866 = cvt(_T_1865) node _T_1867 = and(_T_1866, asSInt(UInt<13>(0h1000))) node _T_1868 = asSInt(_T_1867) node _T_1869 = eq(_T_1868, asSInt(UInt<1>(0h0))) node _T_1870 = or(_T_1834, _T_1839) node _T_1871 = or(_T_1870, _T_1844) node _T_1872 = or(_T_1871, _T_1849) node _T_1873 = or(_T_1872, _T_1854) node _T_1874 = or(_T_1873, _T_1859) node _T_1875 = or(_T_1874, _T_1864) node _T_1876 = or(_T_1875, _T_1869) node _T_1877 = and(_T_1829, _T_1876) node _T_1878 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1879 = or(UInt<1>(0h0), _T_1878) node _T_1880 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1881 = cvt(_T_1880) node _T_1882 = and(_T_1881, asSInt(UInt<17>(0h10000))) node _T_1883 = asSInt(_T_1882) node _T_1884 = eq(_T_1883, asSInt(UInt<1>(0h0))) node _T_1885 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<29>(0h10000000))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = and(_T_1879, _T_1890) node _T_1892 = or(UInt<1>(0h0), _T_1877) node _T_1893 = or(_T_1892, _T_1891) node _T_1894 = and(_T_1828, _T_1893) node _T_1895 = asUInt(reset) node _T_1896 = eq(_T_1895, UInt<1>(0h0)) when _T_1896 : node _T_1897 = eq(_T_1894, UInt<1>(0h0)) when _T_1897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1894, UInt<1>(0h1), "") : assert_143 node _T_1898 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1899 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_1898 connect _WIRE_6[1], _T_1899 node _T_1900 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1901 = mux(_WIRE_6[0], _T_1900, UInt<1>(0h0)) node _T_1902 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1903 = or(_T_1901, _T_1902) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1903 node _T_1904 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1905 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1906 = and(_T_1904, _T_1905) node _T_1907 = or(UInt<1>(0h0), _T_1906) node _T_1908 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<14>(0h2000))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1914 = cvt(_T_1913) node _T_1915 = and(_T_1914, asSInt(UInt<13>(0h1000))) node _T_1916 = asSInt(_T_1915) node _T_1917 = eq(_T_1916, asSInt(UInt<1>(0h0))) node _T_1918 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1919 = cvt(_T_1918) node _T_1920 = and(_T_1919, asSInt(UInt<17>(0h10000))) node _T_1921 = asSInt(_T_1920) node _T_1922 = eq(_T_1921, asSInt(UInt<1>(0h0))) node _T_1923 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1924 = cvt(_T_1923) node _T_1925 = and(_T_1924, asSInt(UInt<18>(0h2f000))) node _T_1926 = asSInt(_T_1925) node _T_1927 = eq(_T_1926, asSInt(UInt<1>(0h0))) node _T_1928 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1929 = cvt(_T_1928) node _T_1930 = and(_T_1929, asSInt(UInt<17>(0h10000))) node _T_1931 = asSInt(_T_1930) node _T_1932 = eq(_T_1931, asSInt(UInt<1>(0h0))) node _T_1933 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1934 = cvt(_T_1933) node _T_1935 = and(_T_1934, asSInt(UInt<13>(0h1000))) node _T_1936 = asSInt(_T_1935) node _T_1937 = eq(_T_1936, asSInt(UInt<1>(0h0))) node _T_1938 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1939 = cvt(_T_1938) node _T_1940 = and(_T_1939, asSInt(UInt<17>(0h10000))) node _T_1941 = asSInt(_T_1940) node _T_1942 = eq(_T_1941, asSInt(UInt<1>(0h0))) node _T_1943 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1944 = cvt(_T_1943) node _T_1945 = and(_T_1944, asSInt(UInt<27>(0h4000000))) node _T_1946 = asSInt(_T_1945) node _T_1947 = eq(_T_1946, asSInt(UInt<1>(0h0))) node _T_1948 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1949 = cvt(_T_1948) node _T_1950 = and(_T_1949, asSInt(UInt<13>(0h1000))) node _T_1951 = asSInt(_T_1950) node _T_1952 = eq(_T_1951, asSInt(UInt<1>(0h0))) node _T_1953 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1954 = cvt(_T_1953) node _T_1955 = and(_T_1954, asSInt(UInt<29>(0h10000000))) node _T_1956 = asSInt(_T_1955) node _T_1957 = eq(_T_1956, asSInt(UInt<1>(0h0))) node _T_1958 = or(_T_1912, _T_1917) node _T_1959 = or(_T_1958, _T_1922) node _T_1960 = or(_T_1959, _T_1927) node _T_1961 = or(_T_1960, _T_1932) node _T_1962 = or(_T_1961, _T_1937) node _T_1963 = or(_T_1962, _T_1942) node _T_1964 = or(_T_1963, _T_1947) node _T_1965 = or(_T_1964, _T_1952) node _T_1966 = or(_T_1965, _T_1957) node _T_1967 = and(_T_1907, _T_1966) node _T_1968 = or(UInt<1>(0h0), _T_1967) node _T_1969 = and(_WIRE_7, _T_1968) node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(_T_1969, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1969, UInt<1>(0h1), "") : assert_144 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(source_ok_2, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1976 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_146 node _T_1980 = asUInt(reset) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) when _T_1981 : node _T_1982 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1983 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_148 node _T_1987 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(_T_1987, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1987, UInt<1>(0h1), "") : assert_149 node _T_1991 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1991 : node _T_1992 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1993 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1994 = and(_T_1992, _T_1993) node _T_1995 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1996 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1997 = or(_T_1995, _T_1996) node _T_1998 = and(_T_1994, _T_1997) node _T_1999 = or(UInt<1>(0h0), _T_1998) node _T_2000 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2001 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2002 = cvt(_T_2001) node _T_2003 = and(_T_2002, asSInt(UInt<14>(0h2000))) node _T_2004 = asSInt(_T_2003) node _T_2005 = eq(_T_2004, asSInt(UInt<1>(0h0))) node _T_2006 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2007 = cvt(_T_2006) node _T_2008 = and(_T_2007, asSInt(UInt<13>(0h1000))) node _T_2009 = asSInt(_T_2008) node _T_2010 = eq(_T_2009, asSInt(UInt<1>(0h0))) node _T_2011 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2012 = cvt(_T_2011) node _T_2013 = and(_T_2012, asSInt(UInt<17>(0h10000))) node _T_2014 = asSInt(_T_2013) node _T_2015 = eq(_T_2014, asSInt(UInt<1>(0h0))) node _T_2016 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2017 = cvt(_T_2016) node _T_2018 = and(_T_2017, asSInt(UInt<18>(0h2f000))) node _T_2019 = asSInt(_T_2018) node _T_2020 = eq(_T_2019, asSInt(UInt<1>(0h0))) node _T_2021 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2022 = cvt(_T_2021) node _T_2023 = and(_T_2022, asSInt(UInt<17>(0h10000))) node _T_2024 = asSInt(_T_2023) node _T_2025 = eq(_T_2024, asSInt(UInt<1>(0h0))) node _T_2026 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2027 = cvt(_T_2026) node _T_2028 = and(_T_2027, asSInt(UInt<13>(0h1000))) node _T_2029 = asSInt(_T_2028) node _T_2030 = eq(_T_2029, asSInt(UInt<1>(0h0))) node _T_2031 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2032 = cvt(_T_2031) node _T_2033 = and(_T_2032, asSInt(UInt<27>(0h4000000))) node _T_2034 = asSInt(_T_2033) node _T_2035 = eq(_T_2034, asSInt(UInt<1>(0h0))) node _T_2036 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2037 = cvt(_T_2036) node _T_2038 = and(_T_2037, asSInt(UInt<13>(0h1000))) node _T_2039 = asSInt(_T_2038) node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0))) node _T_2041 = or(_T_2005, _T_2010) node _T_2042 = or(_T_2041, _T_2015) node _T_2043 = or(_T_2042, _T_2020) node _T_2044 = or(_T_2043, _T_2025) node _T_2045 = or(_T_2044, _T_2030) node _T_2046 = or(_T_2045, _T_2035) node _T_2047 = or(_T_2046, _T_2040) node _T_2048 = and(_T_2000, _T_2047) node _T_2049 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2050 = or(UInt<1>(0h0), _T_2049) node _T_2051 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2052 = cvt(_T_2051) node _T_2053 = and(_T_2052, asSInt(UInt<17>(0h10000))) node _T_2054 = asSInt(_T_2053) node _T_2055 = eq(_T_2054, asSInt(UInt<1>(0h0))) node _T_2056 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2057 = cvt(_T_2056) node _T_2058 = and(_T_2057, asSInt(UInt<29>(0h10000000))) node _T_2059 = asSInt(_T_2058) node _T_2060 = eq(_T_2059, asSInt(UInt<1>(0h0))) node _T_2061 = or(_T_2055, _T_2060) node _T_2062 = and(_T_2050, _T_2061) node _T_2063 = or(UInt<1>(0h0), _T_2048) node _T_2064 = or(_T_2063, _T_2062) node _T_2065 = and(_T_1999, _T_2064) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_150 node _T_2069 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2070 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2069 connect _WIRE_8[1], _T_2070 node _T_2071 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2072 = mux(_WIRE_8[0], _T_2071, UInt<1>(0h0)) node _T_2073 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2074 = or(_T_2072, _T_2073) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2074 node _T_2075 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2076 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2077 = and(_T_2075, _T_2076) node _T_2078 = or(UInt<1>(0h0), _T_2077) node _T_2079 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2080 = cvt(_T_2079) node _T_2081 = and(_T_2080, asSInt(UInt<14>(0h2000))) node _T_2082 = asSInt(_T_2081) node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0))) node _T_2084 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2090 = cvt(_T_2089) node _T_2091 = and(_T_2090, asSInt(UInt<17>(0h10000))) node _T_2092 = asSInt(_T_2091) node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0))) node _T_2094 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<18>(0h2f000))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2100 = cvt(_T_2099) node _T_2101 = and(_T_2100, asSInt(UInt<17>(0h10000))) node _T_2102 = asSInt(_T_2101) node _T_2103 = eq(_T_2102, asSInt(UInt<1>(0h0))) node _T_2104 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2105 = cvt(_T_2104) node _T_2106 = and(_T_2105, asSInt(UInt<13>(0h1000))) node _T_2107 = asSInt(_T_2106) node _T_2108 = eq(_T_2107, asSInt(UInt<1>(0h0))) node _T_2109 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2110 = cvt(_T_2109) node _T_2111 = and(_T_2110, asSInt(UInt<17>(0h10000))) node _T_2112 = asSInt(_T_2111) node _T_2113 = eq(_T_2112, asSInt(UInt<1>(0h0))) node _T_2114 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2115 = cvt(_T_2114) node _T_2116 = and(_T_2115, asSInt(UInt<27>(0h4000000))) node _T_2117 = asSInt(_T_2116) node _T_2118 = eq(_T_2117, asSInt(UInt<1>(0h0))) node _T_2119 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2120 = cvt(_T_2119) node _T_2121 = and(_T_2120, asSInt(UInt<13>(0h1000))) node _T_2122 = asSInt(_T_2121) node _T_2123 = eq(_T_2122, asSInt(UInt<1>(0h0))) node _T_2124 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2125 = cvt(_T_2124) node _T_2126 = and(_T_2125, asSInt(UInt<29>(0h10000000))) node _T_2127 = asSInt(_T_2126) node _T_2128 = eq(_T_2127, asSInt(UInt<1>(0h0))) node _T_2129 = or(_T_2083, _T_2088) node _T_2130 = or(_T_2129, _T_2093) node _T_2131 = or(_T_2130, _T_2098) node _T_2132 = or(_T_2131, _T_2103) node _T_2133 = or(_T_2132, _T_2108) node _T_2134 = or(_T_2133, _T_2113) node _T_2135 = or(_T_2134, _T_2118) node _T_2136 = or(_T_2135, _T_2123) node _T_2137 = or(_T_2136, _T_2128) node _T_2138 = and(_T_2078, _T_2137) node _T_2139 = or(UInt<1>(0h0), _T_2138) node _T_2140 = and(_WIRE_9, _T_2139) node _T_2141 = asUInt(reset) node _T_2142 = eq(_T_2141, UInt<1>(0h0)) when _T_2142 : node _T_2143 = eq(_T_2140, UInt<1>(0h0)) when _T_2143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2140, UInt<1>(0h1), "") : assert_151 node _T_2144 = asUInt(reset) node _T_2145 = eq(_T_2144, UInt<1>(0h0)) when _T_2145 : node _T_2146 = eq(source_ok_2, UInt<1>(0h0)) when _T_2146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2147 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2148 = asUInt(reset) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) when _T_2149 : node _T_2150 = eq(_T_2147, UInt<1>(0h0)) when _T_2150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2147, UInt<1>(0h1), "") : assert_153 node _T_2151 = asUInt(reset) node _T_2152 = eq(_T_2151, UInt<1>(0h0)) when _T_2152 : node _T_2153 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2154 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2155 = asUInt(reset) node _T_2156 = eq(_T_2155, UInt<1>(0h0)) when _T_2156 : node _T_2157 = eq(_T_2154, UInt<1>(0h0)) when _T_2157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2154, UInt<1>(0h1), "") : assert_155 node _T_2158 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2158 : node _T_2159 = asUInt(reset) node _T_2160 = eq(_T_2159, UInt<1>(0h0)) when _T_2160 : node _T_2161 = eq(address_ok_1, UInt<1>(0h0)) when _T_2161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(source_ok_2, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2165 = asUInt(reset) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2168 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2169 = asUInt(reset) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) when _T_2170 : node _T_2171 = eq(_T_2168, UInt<1>(0h0)) when _T_2171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2168, UInt<1>(0h1), "") : assert_159 node _T_2172 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2173 = asUInt(reset) node _T_2174 = eq(_T_2173, UInt<1>(0h0)) when _T_2174 : node _T_2175 = eq(_T_2172, UInt<1>(0h0)) when _T_2175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2172, UInt<1>(0h1), "") : assert_160 node _T_2176 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2176 : node _T_2177 = asUInt(reset) node _T_2178 = eq(_T_2177, UInt<1>(0h0)) when _T_2178 : node _T_2179 = eq(address_ok_1, UInt<1>(0h0)) when _T_2179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(source_ok_2, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2183 = asUInt(reset) node _T_2184 = eq(_T_2183, UInt<1>(0h0)) when _T_2184 : node _T_2185 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2186 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2187 = asUInt(reset) node _T_2188 = eq(_T_2187, UInt<1>(0h0)) when _T_2188 : node _T_2189 = eq(_T_2186, UInt<1>(0h0)) when _T_2189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2186, UInt<1>(0h1), "") : assert_164 node _T_2190 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2190 : node _T_2191 = asUInt(reset) node _T_2192 = eq(_T_2191, UInt<1>(0h0)) when _T_2192 : node _T_2193 = eq(address_ok_1, UInt<1>(0h0)) when _T_2193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2194 = asUInt(reset) node _T_2195 = eq(_T_2194, UInt<1>(0h0)) when _T_2195 : node _T_2196 = eq(source_ok_2, UInt<1>(0h0)) when _T_2196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2197 = asUInt(reset) node _T_2198 = eq(_T_2197, UInt<1>(0h0)) when _T_2198 : node _T_2199 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2200 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2201 = asUInt(reset) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(_T_2200, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2200, UInt<1>(0h1), "") : assert_168 node _T_2204 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2205 = asUInt(reset) node _T_2206 = eq(_T_2205, UInt<1>(0h0)) when _T_2206 : node _T_2207 = eq(_T_2204, UInt<1>(0h0)) when _T_2207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2204, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<6>(0h20)) node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2211 = eq(a_first, UInt<1>(0h0)) node _T_2212 = and(io.in.a.valid, _T_2211) when _T_2212 : node _T_2213 = eq(io.in.a.bits.opcode, opcode) node _T_2214 = asUInt(reset) node _T_2215 = eq(_T_2214, UInt<1>(0h0)) when _T_2215 : node _T_2216 = eq(_T_2213, UInt<1>(0h0)) when _T_2216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2213, UInt<1>(0h1), "") : assert_171 node _T_2217 = eq(io.in.a.bits.param, param) node _T_2218 = asUInt(reset) node _T_2219 = eq(_T_2218, UInt<1>(0h0)) when _T_2219 : node _T_2220 = eq(_T_2217, UInt<1>(0h0)) when _T_2220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2217, UInt<1>(0h1), "") : assert_172 node _T_2221 = eq(io.in.a.bits.size, size) node _T_2222 = asUInt(reset) node _T_2223 = eq(_T_2222, UInt<1>(0h0)) when _T_2223 : node _T_2224 = eq(_T_2221, UInt<1>(0h0)) when _T_2224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2221, UInt<1>(0h1), "") : assert_173 node _T_2225 = eq(io.in.a.bits.source, source) node _T_2226 = asUInt(reset) node _T_2227 = eq(_T_2226, UInt<1>(0h0)) when _T_2227 : node _T_2228 = eq(_T_2225, UInt<1>(0h0)) when _T_2228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2225, UInt<1>(0h1), "") : assert_174 node _T_2229 = eq(io.in.a.bits.address, address) node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : node _T_2232 = eq(_T_2229, UInt<1>(0h0)) when _T_2232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2229, UInt<1>(0h1), "") : assert_175 node _T_2233 = and(io.in.a.ready, io.in.a.valid) node _T_2234 = and(_T_2233, a_first) when _T_2234 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2235 = eq(d_first, UInt<1>(0h0)) node _T_2236 = and(io.in.d.valid, _T_2235) when _T_2236 : node _T_2237 = eq(io.in.d.bits.opcode, opcode_1) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_176 node _T_2241 = eq(io.in.d.bits.param, param_1) node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(_T_2241, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2241, UInt<1>(0h1), "") : assert_177 node _T_2245 = eq(io.in.d.bits.size, size_1) node _T_2246 = asUInt(reset) node _T_2247 = eq(_T_2246, UInt<1>(0h0)) when _T_2247 : node _T_2248 = eq(_T_2245, UInt<1>(0h0)) when _T_2248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2245, UInt<1>(0h1), "") : assert_178 node _T_2249 = eq(io.in.d.bits.source, source_1) node _T_2250 = asUInt(reset) node _T_2251 = eq(_T_2250, UInt<1>(0h0)) when _T_2251 : node _T_2252 = eq(_T_2249, UInt<1>(0h0)) when _T_2252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2249, UInt<1>(0h1), "") : assert_179 node _T_2253 = eq(io.in.d.bits.sink, sink) node _T_2254 = asUInt(reset) node _T_2255 = eq(_T_2254, UInt<1>(0h0)) when _T_2255 : node _T_2256 = eq(_T_2253, UInt<1>(0h0)) when _T_2256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2253, UInt<1>(0h1), "") : assert_180 node _T_2257 = eq(io.in.d.bits.denied, denied) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_181 node _T_2261 = and(io.in.d.ready, io.in.d.valid) node _T_2262 = and(_T_2261, d_first) when _T_2262 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2263 = eq(b_first, UInt<1>(0h0)) node _T_2264 = and(io.in.b.valid, _T_2263) when _T_2264 : node _T_2265 = eq(io.in.b.bits.opcode, opcode_2) node _T_2266 = asUInt(reset) node _T_2267 = eq(_T_2266, UInt<1>(0h0)) when _T_2267 : node _T_2268 = eq(_T_2265, UInt<1>(0h0)) when _T_2268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2265, UInt<1>(0h1), "") : assert_182 node _T_2269 = eq(io.in.b.bits.param, param_2) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(_T_2269, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2269, UInt<1>(0h1), "") : assert_183 node _T_2273 = eq(io.in.b.bits.size, size_2) node _T_2274 = asUInt(reset) node _T_2275 = eq(_T_2274, UInt<1>(0h0)) when _T_2275 : node _T_2276 = eq(_T_2273, UInt<1>(0h0)) when _T_2276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2273, UInt<1>(0h1), "") : assert_184 node _T_2277 = eq(io.in.b.bits.source, source_2) node _T_2278 = asUInt(reset) node _T_2279 = eq(_T_2278, UInt<1>(0h0)) when _T_2279 : node _T_2280 = eq(_T_2277, UInt<1>(0h0)) when _T_2280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2277, UInt<1>(0h1), "") : assert_185 node _T_2281 = eq(io.in.b.bits.address, address_1) node _T_2282 = asUInt(reset) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : node _T_2284 = eq(_T_2281, UInt<1>(0h0)) when _T_2284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2281, UInt<1>(0h1), "") : assert_186 node _T_2285 = and(io.in.b.ready, io.in.b.valid) node _T_2286 = and(_T_2285, b_first) when _T_2286 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2287 = eq(c_first, UInt<1>(0h0)) node _T_2288 = and(io.in.c.valid, _T_2287) when _T_2288 : node _T_2289 = eq(io.in.c.bits.opcode, opcode_3) node _T_2290 = asUInt(reset) node _T_2291 = eq(_T_2290, UInt<1>(0h0)) when _T_2291 : node _T_2292 = eq(_T_2289, UInt<1>(0h0)) when _T_2292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2289, UInt<1>(0h1), "") : assert_187 node _T_2293 = eq(io.in.c.bits.param, param_3) node _T_2294 = asUInt(reset) node _T_2295 = eq(_T_2294, UInt<1>(0h0)) when _T_2295 : node _T_2296 = eq(_T_2293, UInt<1>(0h0)) when _T_2296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2293, UInt<1>(0h1), "") : assert_188 node _T_2297 = eq(io.in.c.bits.size, size_3) node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : node _T_2300 = eq(_T_2297, UInt<1>(0h0)) when _T_2300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2297, UInt<1>(0h1), "") : assert_189 node _T_2301 = eq(io.in.c.bits.source, source_3) node _T_2302 = asUInt(reset) node _T_2303 = eq(_T_2302, UInt<1>(0h0)) when _T_2303 : node _T_2304 = eq(_T_2301, UInt<1>(0h0)) when _T_2304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2301, UInt<1>(0h1), "") : assert_190 node _T_2305 = eq(io.in.c.bits.address, address_2) node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : node _T_2308 = eq(_T_2305, UInt<1>(0h0)) when _T_2308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2305, UInt<1>(0h1), "") : assert_191 node _T_2309 = and(io.in.c.ready, io.in.c.valid) node _T_2310 = and(_T_2309, c_first) when _T_2310 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2311 = and(io.in.a.valid, a_first_1) node _T_2312 = and(_T_2311, UInt<1>(0h1)) when _T_2312 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2313 = and(io.in.a.ready, io.in.a.valid) node _T_2314 = and(_T_2313, a_first_1) node _T_2315 = and(_T_2314, UInt<1>(0h1)) when _T_2315 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2316 = dshr(inflight, io.in.a.bits.source) node _T_2317 = bits(_T_2316, 0, 0) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) node _T_2319 = asUInt(reset) node _T_2320 = eq(_T_2319, UInt<1>(0h0)) when _T_2320 : node _T_2321 = eq(_T_2318, UInt<1>(0h0)) when _T_2321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2318, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2322 = and(io.in.d.valid, d_first_1) node _T_2323 = and(_T_2322, UInt<1>(0h1)) node _T_2324 = eq(d_release_ack, UInt<1>(0h0)) node _T_2325 = and(_T_2323, _T_2324) when _T_2325 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2326 = and(io.in.d.ready, io.in.d.valid) node _T_2327 = and(_T_2326, d_first_1) node _T_2328 = and(_T_2327, UInt<1>(0h1)) node _T_2329 = eq(d_release_ack, UInt<1>(0h0)) node _T_2330 = and(_T_2328, _T_2329) when _T_2330 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2331 = and(io.in.d.valid, d_first_1) node _T_2332 = and(_T_2331, UInt<1>(0h1)) node _T_2333 = eq(d_release_ack, UInt<1>(0h0)) node _T_2334 = and(_T_2332, _T_2333) when _T_2334 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2335 = dshr(inflight, io.in.d.bits.source) node _T_2336 = bits(_T_2335, 0, 0) node _T_2337 = or(_T_2336, same_cycle_resp) node _T_2338 = asUInt(reset) node _T_2339 = eq(_T_2338, UInt<1>(0h0)) when _T_2339 : node _T_2340 = eq(_T_2337, UInt<1>(0h0)) when _T_2340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2337, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2341 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2342 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2343 = or(_T_2341, _T_2342) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_194 node _T_2347 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2348 = asUInt(reset) node _T_2349 = eq(_T_2348, UInt<1>(0h0)) when _T_2349 : node _T_2350 = eq(_T_2347, UInt<1>(0h0)) when _T_2350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2347, UInt<1>(0h1), "") : assert_195 else : node _T_2351 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2352 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2353 = or(_T_2351, _T_2352) node _T_2354 = asUInt(reset) node _T_2355 = eq(_T_2354, UInt<1>(0h0)) when _T_2355 : node _T_2356 = eq(_T_2353, UInt<1>(0h0)) when _T_2356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2353, UInt<1>(0h1), "") : assert_196 node _T_2357 = eq(io.in.d.bits.size, a_size_lookup) node _T_2358 = asUInt(reset) node _T_2359 = eq(_T_2358, UInt<1>(0h0)) when _T_2359 : node _T_2360 = eq(_T_2357, UInt<1>(0h0)) when _T_2360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2357, UInt<1>(0h1), "") : assert_197 node _T_2361 = and(io.in.d.valid, d_first_1) node _T_2362 = and(_T_2361, a_first_1) node _T_2363 = and(_T_2362, io.in.a.valid) node _T_2364 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2365 = and(_T_2363, _T_2364) node _T_2366 = eq(d_release_ack, UInt<1>(0h0)) node _T_2367 = and(_T_2365, _T_2366) when _T_2367 : node _T_2368 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2369 = or(_T_2368, io.in.a.ready) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(_T_2369, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2369, UInt<1>(0h1), "") : assert_198 node _T_2373 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2374 = orr(a_set_wo_ready) node _T_2375 = eq(_T_2374, UInt<1>(0h0)) node _T_2376 = or(_T_2373, _T_2375) node _T_2377 = asUInt(reset) node _T_2378 = eq(_T_2377, UInt<1>(0h0)) when _T_2378 : node _T_2379 = eq(_T_2376, UInt<1>(0h0)) when _T_2379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2376, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_121 node _T_2380 = orr(inflight) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) node _T_2382 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2383 = or(_T_2381, _T_2382) node _T_2384 = lt(watchdog, plusarg_reader.out) node _T_2385 = or(_T_2383, _T_2384) node _T_2386 = asUInt(reset) node _T_2387 = eq(_T_2386, UInt<1>(0h0)) when _T_2387 : node _T_2388 = eq(_T_2385, UInt<1>(0h0)) when _T_2388 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2385, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2389 = and(io.in.a.ready, io.in.a.valid) node _T_2390 = and(io.in.d.ready, io.in.d.valid) node _T_2391 = or(_T_2389, _T_2390) when _T_2391 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2392 = and(io.in.c.valid, c_first_1) node _T_2393 = bits(io.in.c.bits.opcode, 2, 2) node _T_2394 = bits(io.in.c.bits.opcode, 1, 1) node _T_2395 = and(_T_2393, _T_2394) node _T_2396 = and(_T_2392, _T_2395) when _T_2396 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2397 = and(io.in.c.ready, io.in.c.valid) node _T_2398 = and(_T_2397, c_first_1) node _T_2399 = bits(io.in.c.bits.opcode, 2, 2) node _T_2400 = bits(io.in.c.bits.opcode, 1, 1) node _T_2401 = and(_T_2399, _T_2400) node _T_2402 = and(_T_2398, _T_2401) when _T_2402 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2403 = dshr(inflight_1, io.in.c.bits.source) node _T_2404 = bits(_T_2403, 0, 0) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2409 = and(io.in.d.valid, d_first_2) node _T_2410 = and(_T_2409, UInt<1>(0h1)) node _T_2411 = and(_T_2410, d_release_ack_1) when _T_2411 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2412 = and(io.in.d.ready, io.in.d.valid) node _T_2413 = and(_T_2412, d_first_2) node _T_2414 = and(_T_2413, UInt<1>(0h1)) node _T_2415 = and(_T_2414, d_release_ack_1) when _T_2415 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2416 = and(io.in.d.valid, d_first_2) node _T_2417 = and(_T_2416, UInt<1>(0h1)) node _T_2418 = and(_T_2417, d_release_ack_1) when _T_2418 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2419 = dshr(inflight_1, io.in.d.bits.source) node _T_2420 = bits(_T_2419, 0, 0) node _T_2421 = or(_T_2420, same_cycle_resp_1) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2425 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(_T_2425, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2425, UInt<1>(0h1), "") : assert_203 else : node _T_2429 = eq(io.in.d.bits.size, c_size_lookup) node _T_2430 = asUInt(reset) node _T_2431 = eq(_T_2430, UInt<1>(0h0)) when _T_2431 : node _T_2432 = eq(_T_2429, UInt<1>(0h0)) when _T_2432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2429, UInt<1>(0h1), "") : assert_204 node _T_2433 = and(io.in.d.valid, d_first_2) node _T_2434 = and(_T_2433, c_first_1) node _T_2435 = and(_T_2434, io.in.c.valid) node _T_2436 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2437 = and(_T_2435, _T_2436) node _T_2438 = and(_T_2437, d_release_ack_1) node _T_2439 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2440 = and(_T_2438, _T_2439) when _T_2440 : node _T_2441 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2442 = or(_T_2441, io.in.c.ready) node _T_2443 = asUInt(reset) node _T_2444 = eq(_T_2443, UInt<1>(0h0)) when _T_2444 : node _T_2445 = eq(_T_2442, UInt<1>(0h0)) when _T_2445 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2442, UInt<1>(0h1), "") : assert_205 node _T_2446 = orr(c_set_wo_ready) when _T_2446 : node _T_2447 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_122 node _T_2451 = orr(inflight_1) node _T_2452 = eq(_T_2451, UInt<1>(0h0)) node _T_2453 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2454 = or(_T_2452, _T_2453) node _T_2455 = lt(watchdog_1, plusarg_reader_1.out) node _T_2456 = or(_T_2454, _T_2455) node _T_2457 = asUInt(reset) node _T_2458 = eq(_T_2457, UInt<1>(0h0)) when _T_2458 : node _T_2459 = eq(_T_2456, UInt<1>(0h0)) when _T_2459 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2456, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2460 = and(io.in.c.ready, io.in.c.valid) node _T_2461 = and(io.in.d.ready, io.in.d.valid) node _T_2462 = or(_T_2460, _T_2461) when _T_2462 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<32>, clock, reset, UInt<32>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<32> connect d_set, UInt<32>(0h0) node _T_2463 = and(io.in.d.ready, io.in.d.valid) node _T_2464 = and(_T_2463, d_first_3) node _T_2465 = bits(io.in.d.bits.opcode, 2, 2) node _T_2466 = bits(io.in.d.bits.opcode, 1, 1) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = and(_T_2465, _T_2467) node _T_2469 = and(_T_2464, _T_2468) when _T_2469 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2470 = dshr(inflight_2, io.in.d.bits.sink) node _T_2471 = bits(_T_2470, 0, 0) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) node _T_2473 = asUInt(reset) node _T_2474 = eq(_T_2473, UInt<1>(0h0)) when _T_2474 : node _T_2475 = eq(_T_2472, UInt<1>(0h0)) when _T_2475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2472, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<32> connect e_clr, UInt<32>(0h0) node _T_2476 = and(io.in.e.ready, io.in.e.valid) node _T_2477 = and(_T_2476, UInt<1>(0h1)) node _T_2478 = and(_T_2477, UInt<1>(0h1)) when _T_2478 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2479 = or(d_set, inflight_2) node _T_2480 = dshr(_T_2479, io.in.e.bits.sink) node _T_2481 = bits(_T_2480, 0, 0) node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(_T_2481, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2481, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_123 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_124 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [4:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [4:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [8:0] b_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [8:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire [1:0] _GEN_1 = {1'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [1:0] _GEN_6 = {1'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [31:0] inflight_2; // @[Monitor.scala:828:27] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [31:0] _GEN_9 = {27'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [31:0] d_set = _GEN_8 ? 32'h1 << _GEN_9 : 32'h0; // @[OneHot.scala:58:35] wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35] wire [31:0] _GEN_11 = {27'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module CoherenceManagerWrapper : output auto : { coupler_to_bus_named_mbus_bus_xing_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_mbus_bus_xing_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_mbus_bus_xing_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_mbus_bus_xing_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coherent_jbar_anon_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coherent_jbar_anon_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coherent_jbar_anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip coherent_jbar_anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip l2_ctrls_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip coh_clock_groups_in : { member : { coh_0 : { clock : Clock, reset : Reset}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst coh_clock_groups of ClockGroupAggregator_coh inst clockGroup of ClockGroup_5 inst fixedClockNode of FixedClockBroadcast_1 inst broadcast of BundleBridgeNexus_NoOutput_5 inst l2 of InclusiveCache connect l2.clock, childClock connect l2.reset, childReset inst filter of TLFilter connect filter.clock, childClock connect filter.reset, childReset inst InclusiveCache_inner_TLBuffer of TLBuffer_a32d64s6k3z3c connect InclusiveCache_inner_TLBuffer.clock, childClock connect InclusiveCache_inner_TLBuffer.reset, childReset inst InclusiveCache_outer_TLBuffer of TLBuffer_a32d64s3k3z3c connect InclusiveCache_outer_TLBuffer.clock, childClock connect InclusiveCache_outer_TLBuffer.reset, childReset inst cork of TLCacheCork connect cork.clock, childClock connect cork.reset, childReset inst coherent_jbar of TLJbar connect coherent_jbar.clock, childClock connect coherent_jbar.reset, childReset inst binder of BankBinder connect binder.clock, childClock connect binder.reset, childReset inst coupler_to_bus_named_mbus of TLInterconnectCoupler_coh_to_bus_named_mbus connect coupler_to_bus_named_mbus.clock, childClock connect coupler_to_bus_named_mbus.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock connect clockGroup.auto.in, coh_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out connect InclusiveCache_outer_TLBuffer.auto.in_0, l2.auto.out_0 connect InclusiveCache_outer_TLBuffer.auto.in_1, l2.auto.out_1 connect InclusiveCache_outer_TLBuffer.auto.in_2, l2.auto.out_2 connect InclusiveCache_outer_TLBuffer.auto.in_3, l2.auto.out_3 connect InclusiveCache_inner_TLBuffer.auto.in_0, filter.auto.anon_out_0 connect InclusiveCache_inner_TLBuffer.auto.in_1, filter.auto.anon_out_1 connect InclusiveCache_inner_TLBuffer.auto.in_2, filter.auto.anon_out_2 connect InclusiveCache_inner_TLBuffer.auto.in_3, filter.auto.anon_out_3 connect l2.auto.in_0, InclusiveCache_inner_TLBuffer.auto.out_0 connect l2.auto.in_1, InclusiveCache_inner_TLBuffer.auto.out_1 connect l2.auto.in_2, InclusiveCache_inner_TLBuffer.auto.out_2 connect l2.auto.in_3, InclusiveCache_inner_TLBuffer.auto.out_3 connect cork.auto.in_0, InclusiveCache_outer_TLBuffer.auto.out_0 connect cork.auto.in_1, InclusiveCache_outer_TLBuffer.auto.out_1 connect cork.auto.in_2, InclusiveCache_outer_TLBuffer.auto.out_2 connect cork.auto.in_3, InclusiveCache_outer_TLBuffer.auto.out_3 connect binder.auto.in_0, cork.auto.out_0 connect binder.auto.in_1, cork.auto.out_1 connect binder.auto.in_2, cork.auto.out_2 connect binder.auto.in_3, cork.auto.out_3 connect filter.auto.anon_in_0, coherent_jbar.auto.anon_out_0 connect filter.auto.anon_in_1, coherent_jbar.auto.anon_out_1 connect filter.auto.anon_in_2, coherent_jbar.auto.anon_out_2 connect filter.auto.anon_in_3, coherent_jbar.auto.anon_out_3 connect coupler_to_bus_named_mbus.auto.widget_anon_in_0, binder.auto.out_0 connect coupler_to_bus_named_mbus.auto.widget_anon_in_1, binder.auto.out_1 connect coupler_to_bus_named_mbus.auto.widget_anon_in_2, binder.auto.out_2 connect coupler_to_bus_named_mbus.auto.widget_anon_in_3, binder.auto.out_3 connect coh_clock_groups.auto.in, auto.coh_clock_groups_in connect l2.auto.ctrls_ctrl_in, auto.l2_ctrls_ctrl_in connect coherent_jbar.auto.anon_in_0, auto.coherent_jbar_anon_in_0 connect coherent_jbar.auto.anon_in_1, auto.coherent_jbar_anon_in_1 connect coherent_jbar.auto.anon_in_2, auto.coherent_jbar_anon_in_2 connect coherent_jbar.auto.anon_in_3, auto.coherent_jbar_anon_in_3 connect coupler_to_bus_named_mbus.auto.bus_xing_out_0.d, auto.coupler_to_bus_named_mbus_bus_xing_out_0.d connect auto.coupler_to_bus_named_mbus_bus_xing_out_0.a.bits, coupler_to_bus_named_mbus.auto.bus_xing_out_0.a.bits connect auto.coupler_to_bus_named_mbus_bus_xing_out_0.a.valid, coupler_to_bus_named_mbus.auto.bus_xing_out_0.a.valid connect coupler_to_bus_named_mbus.auto.bus_xing_out_0.a.ready, auto.coupler_to_bus_named_mbus_bus_xing_out_0.a.ready connect coupler_to_bus_named_mbus.auto.bus_xing_out_1.d, auto.coupler_to_bus_named_mbus_bus_xing_out_1.d connect auto.coupler_to_bus_named_mbus_bus_xing_out_1.a.bits, coupler_to_bus_named_mbus.auto.bus_xing_out_1.a.bits connect auto.coupler_to_bus_named_mbus_bus_xing_out_1.a.valid, coupler_to_bus_named_mbus.auto.bus_xing_out_1.a.valid connect coupler_to_bus_named_mbus.auto.bus_xing_out_1.a.ready, auto.coupler_to_bus_named_mbus_bus_xing_out_1.a.ready connect coupler_to_bus_named_mbus.auto.bus_xing_out_2.d, auto.coupler_to_bus_named_mbus_bus_xing_out_2.d connect auto.coupler_to_bus_named_mbus_bus_xing_out_2.a.bits, coupler_to_bus_named_mbus.auto.bus_xing_out_2.a.bits connect auto.coupler_to_bus_named_mbus_bus_xing_out_2.a.valid, coupler_to_bus_named_mbus.auto.bus_xing_out_2.a.valid connect coupler_to_bus_named_mbus.auto.bus_xing_out_2.a.ready, auto.coupler_to_bus_named_mbus_bus_xing_out_2.a.ready connect coupler_to_bus_named_mbus.auto.bus_xing_out_3.d, auto.coupler_to_bus_named_mbus_bus_xing_out_3.d connect auto.coupler_to_bus_named_mbus_bus_xing_out_3.a.bits, coupler_to_bus_named_mbus.auto.bus_xing_out_3.a.bits connect auto.coupler_to_bus_named_mbus_bus_xing_out_3.a.valid, coupler_to_bus_named_mbus.auto.bus_xing_out_3.a.valid connect coupler_to_bus_named_mbus.auto.bus_xing_out_3.a.ready, auto.coupler_to_bus_named_mbus_bus_xing_out_3.a.ready connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset extmodule plusarg_reader_121 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_122 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module CoherenceManagerWrapper( // @[ClockDomain.scala:14:9] input auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coherent_jbar_anon_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coherent_jbar_anon_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coherent_jbar_anon_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_3_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_3_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coherent_jbar_anon_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coherent_jbar_anon_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_3_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_3_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coherent_jbar_anon_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coherent_jbar_anon_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coherent_jbar_anon_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coherent_jbar_anon_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_3_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coherent_jbar_anon_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coherent_jbar_anon_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coherent_jbar_anon_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_2_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_2_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coherent_jbar_anon_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coherent_jbar_anon_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_2_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_2_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coherent_jbar_anon_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coherent_jbar_anon_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coherent_jbar_anon_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coherent_jbar_anon_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_2_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coherent_jbar_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coherent_jbar_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coherent_jbar_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coherent_jbar_anon_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coherent_jbar_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coherent_jbar_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coherent_jbar_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coherent_jbar_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coherent_jbar_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coherent_jbar_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_coherent_jbar_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coherent_jbar_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coherent_jbar_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coherent_jbar_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_coherent_jbar_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coherent_jbar_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_coherent_jbar_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coherent_jbar_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_l2_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_l2_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_l2_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_l2_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_l2_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_l2_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_l2_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_l2_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_l2_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_l2_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coh_clock_groups_in_member_coh_0_clock, // @[LazyModuleImp.scala:107:25] input auto_coh_clock_groups_in_member_coh_0_reset // @[LazyModuleImp.scala:107:25] ); wire _binder_auto_in_3_a_ready; // @[BankBinder.scala:71:28] wire _binder_auto_in_3_d_valid; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_3_d_bits_opcode; // @[BankBinder.scala:71:28] wire [1:0] _binder_auto_in_3_d_bits_param; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_3_d_bits_size; // @[BankBinder.scala:71:28] wire [3:0] _binder_auto_in_3_d_bits_source; // @[BankBinder.scala:71:28] wire _binder_auto_in_3_d_bits_denied; // @[BankBinder.scala:71:28] wire [63:0] _binder_auto_in_3_d_bits_data; // @[BankBinder.scala:71:28] wire _binder_auto_in_3_d_bits_corrupt; // @[BankBinder.scala:71:28] wire _binder_auto_in_2_a_ready; // @[BankBinder.scala:71:28] wire _binder_auto_in_2_d_valid; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_2_d_bits_opcode; // @[BankBinder.scala:71:28] wire [1:0] _binder_auto_in_2_d_bits_param; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_2_d_bits_size; // @[BankBinder.scala:71:28] wire [3:0] _binder_auto_in_2_d_bits_source; // @[BankBinder.scala:71:28] wire _binder_auto_in_2_d_bits_denied; // @[BankBinder.scala:71:28] wire [63:0] _binder_auto_in_2_d_bits_data; // @[BankBinder.scala:71:28] wire _binder_auto_in_2_d_bits_corrupt; // @[BankBinder.scala:71:28] wire _binder_auto_in_1_a_ready; // @[BankBinder.scala:71:28] wire _binder_auto_in_1_d_valid; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_1_d_bits_opcode; // @[BankBinder.scala:71:28] wire [1:0] _binder_auto_in_1_d_bits_param; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_1_d_bits_size; // @[BankBinder.scala:71:28] wire [3:0] _binder_auto_in_1_d_bits_source; // @[BankBinder.scala:71:28] wire _binder_auto_in_1_d_bits_denied; // @[BankBinder.scala:71:28] wire [63:0] _binder_auto_in_1_d_bits_data; // @[BankBinder.scala:71:28] wire _binder_auto_in_1_d_bits_corrupt; // @[BankBinder.scala:71:28] wire _binder_auto_in_0_a_ready; // @[BankBinder.scala:71:28] wire _binder_auto_in_0_d_valid; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_0_d_bits_opcode; // @[BankBinder.scala:71:28] wire [1:0] _binder_auto_in_0_d_bits_param; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_0_d_bits_size; // @[BankBinder.scala:71:28] wire [3:0] _binder_auto_in_0_d_bits_source; // @[BankBinder.scala:71:28] wire _binder_auto_in_0_d_bits_denied; // @[BankBinder.scala:71:28] wire [63:0] _binder_auto_in_0_d_bits_data; // @[BankBinder.scala:71:28] wire _binder_auto_in_0_d_bits_corrupt; // @[BankBinder.scala:71:28] wire _cork_auto_in_3_a_ready; // @[Configs.scala:120:26] wire _cork_auto_in_3_c_ready; // @[Configs.scala:120:26] wire _cork_auto_in_3_d_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_3_d_bits_opcode; // @[Configs.scala:120:26] wire [1:0] _cork_auto_in_3_d_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_3_d_bits_size; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_3_d_bits_source; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_3_d_bits_sink; // @[Configs.scala:120:26] wire _cork_auto_in_3_d_bits_denied; // @[Configs.scala:120:26] wire [63:0] _cork_auto_in_3_d_bits_data; // @[Configs.scala:120:26] wire _cork_auto_in_3_d_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_in_2_a_ready; // @[Configs.scala:120:26] wire _cork_auto_in_2_c_ready; // @[Configs.scala:120:26] wire _cork_auto_in_2_d_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_2_d_bits_opcode; // @[Configs.scala:120:26] wire [1:0] _cork_auto_in_2_d_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_2_d_bits_size; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_2_d_bits_source; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_2_d_bits_sink; // @[Configs.scala:120:26] wire _cork_auto_in_2_d_bits_denied; // @[Configs.scala:120:26] wire [63:0] _cork_auto_in_2_d_bits_data; // @[Configs.scala:120:26] wire _cork_auto_in_2_d_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_in_1_a_ready; // @[Configs.scala:120:26] wire _cork_auto_in_1_c_ready; // @[Configs.scala:120:26] wire _cork_auto_in_1_d_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_1_d_bits_opcode; // @[Configs.scala:120:26] wire [1:0] _cork_auto_in_1_d_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_1_d_bits_size; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_1_d_bits_source; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_1_d_bits_sink; // @[Configs.scala:120:26] wire _cork_auto_in_1_d_bits_denied; // @[Configs.scala:120:26] wire [63:0] _cork_auto_in_1_d_bits_data; // @[Configs.scala:120:26] wire _cork_auto_in_1_d_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_in_0_a_ready; // @[Configs.scala:120:26] wire _cork_auto_in_0_c_ready; // @[Configs.scala:120:26] wire _cork_auto_in_0_d_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_0_d_bits_opcode; // @[Configs.scala:120:26] wire [1:0] _cork_auto_in_0_d_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_0_d_bits_size; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_0_d_bits_source; // @[Configs.scala:120:26] wire [2:0] _cork_auto_in_0_d_bits_sink; // @[Configs.scala:120:26] wire _cork_auto_in_0_d_bits_denied; // @[Configs.scala:120:26] wire [63:0] _cork_auto_in_0_d_bits_data; // @[Configs.scala:120:26] wire _cork_auto_in_0_d_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_out_3_a_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_3_a_bits_opcode; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_3_a_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_3_a_bits_size; // @[Configs.scala:120:26] wire [3:0] _cork_auto_out_3_a_bits_source; // @[Configs.scala:120:26] wire [31:0] _cork_auto_out_3_a_bits_address; // @[Configs.scala:120:26] wire [7:0] _cork_auto_out_3_a_bits_mask; // @[Configs.scala:120:26] wire [63:0] _cork_auto_out_3_a_bits_data; // @[Configs.scala:120:26] wire _cork_auto_out_3_a_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_out_3_d_ready; // @[Configs.scala:120:26] wire _cork_auto_out_2_a_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_2_a_bits_opcode; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_2_a_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_2_a_bits_size; // @[Configs.scala:120:26] wire [3:0] _cork_auto_out_2_a_bits_source; // @[Configs.scala:120:26] wire [31:0] _cork_auto_out_2_a_bits_address; // @[Configs.scala:120:26] wire [7:0] _cork_auto_out_2_a_bits_mask; // @[Configs.scala:120:26] wire [63:0] _cork_auto_out_2_a_bits_data; // @[Configs.scala:120:26] wire _cork_auto_out_2_a_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_out_2_d_ready; // @[Configs.scala:120:26] wire _cork_auto_out_1_a_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_1_a_bits_opcode; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_1_a_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_1_a_bits_size; // @[Configs.scala:120:26] wire [3:0] _cork_auto_out_1_a_bits_source; // @[Configs.scala:120:26] wire [31:0] _cork_auto_out_1_a_bits_address; // @[Configs.scala:120:26] wire [7:0] _cork_auto_out_1_a_bits_mask; // @[Configs.scala:120:26] wire [63:0] _cork_auto_out_1_a_bits_data; // @[Configs.scala:120:26] wire _cork_auto_out_1_a_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_out_1_d_ready; // @[Configs.scala:120:26] wire _cork_auto_out_0_a_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_0_a_bits_opcode; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_0_a_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_0_a_bits_size; // @[Configs.scala:120:26] wire [3:0] _cork_auto_out_0_a_bits_source; // @[Configs.scala:120:26] wire [31:0] _cork_auto_out_0_a_bits_address; // @[Configs.scala:120:26] wire [7:0] _cork_auto_out_0_a_bits_mask; // @[Configs.scala:120:26] wire [63:0] _cork_auto_out_0_a_bits_data; // @[Configs.scala:120:26] wire _cork_auto_out_0_a_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_out_0_d_ready; // @[Configs.scala:120:26] wire _InclusiveCache_inner_TLBuffer_auto_out_3_a_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_size; // @[Parameters.scala:56:69] wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_address; // @[Parameters.scala:56:69] wire [7:0] _InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_mask; // @[Parameters.scala:56:69] wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_3_b_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_3_c_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_size; // @[Parameters.scala:56:69] wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_address; // @[Parameters.scala:56:69] wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_3_d_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_3_e_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_3_e_bits_sink; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_2_a_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_size; // @[Parameters.scala:56:69] wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_address; // @[Parameters.scala:56:69] wire [7:0] _InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_mask; // @[Parameters.scala:56:69] wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_2_b_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_2_c_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_size; // @[Parameters.scala:56:69] wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_address; // @[Parameters.scala:56:69] wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_2_d_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_2_e_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_2_e_bits_sink; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_1_a_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_size; // @[Parameters.scala:56:69] wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_address; // @[Parameters.scala:56:69] wire [7:0] _InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_mask; // @[Parameters.scala:56:69] wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_1_b_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_1_c_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_size; // @[Parameters.scala:56:69] wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_address; // @[Parameters.scala:56:69] wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_1_d_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_1_e_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_1_e_bits_sink; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_0_a_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_size; // @[Parameters.scala:56:69] wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_address; // @[Parameters.scala:56:69] wire [7:0] _InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_mask; // @[Parameters.scala:56:69] wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_0_b_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_0_c_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_size; // @[Parameters.scala:56:69] wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_address; // @[Parameters.scala:56:69] wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_0_d_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_0_e_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_0_e_bits_sink; // @[Parameters.scala:56:69] wire _l2_auto_in_3_a_ready; // @[Configs.scala:93:24] wire _l2_auto_in_3_b_valid; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_3_b_bits_param; // @[Configs.scala:93:24] wire [5:0] _l2_auto_in_3_b_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_in_3_b_bits_address; // @[Configs.scala:93:24] wire _l2_auto_in_3_c_ready; // @[Configs.scala:93:24] wire _l2_auto_in_3_d_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_3_d_bits_opcode; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_3_d_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_3_d_bits_size; // @[Configs.scala:93:24] wire [5:0] _l2_auto_in_3_d_bits_source; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_3_d_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_in_3_d_bits_denied; // @[Configs.scala:93:24] wire [63:0] _l2_auto_in_3_d_bits_data; // @[Configs.scala:93:24] wire _l2_auto_in_3_d_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_in_2_a_ready; // @[Configs.scala:93:24] wire _l2_auto_in_2_b_valid; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_2_b_bits_param; // @[Configs.scala:93:24] wire [5:0] _l2_auto_in_2_b_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_in_2_b_bits_address; // @[Configs.scala:93:24] wire _l2_auto_in_2_c_ready; // @[Configs.scala:93:24] wire _l2_auto_in_2_d_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_2_d_bits_opcode; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_2_d_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_2_d_bits_size; // @[Configs.scala:93:24] wire [5:0] _l2_auto_in_2_d_bits_source; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_2_d_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_in_2_d_bits_denied; // @[Configs.scala:93:24] wire [63:0] _l2_auto_in_2_d_bits_data; // @[Configs.scala:93:24] wire _l2_auto_in_2_d_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_in_1_a_ready; // @[Configs.scala:93:24] wire _l2_auto_in_1_b_valid; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_1_b_bits_param; // @[Configs.scala:93:24] wire [5:0] _l2_auto_in_1_b_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_in_1_b_bits_address; // @[Configs.scala:93:24] wire _l2_auto_in_1_c_ready; // @[Configs.scala:93:24] wire _l2_auto_in_1_d_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_1_d_bits_opcode; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_1_d_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_1_d_bits_size; // @[Configs.scala:93:24] wire [5:0] _l2_auto_in_1_d_bits_source; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_1_d_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_in_1_d_bits_denied; // @[Configs.scala:93:24] wire [63:0] _l2_auto_in_1_d_bits_data; // @[Configs.scala:93:24] wire _l2_auto_in_1_d_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_in_0_a_ready; // @[Configs.scala:93:24] wire _l2_auto_in_0_b_valid; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_0_b_bits_param; // @[Configs.scala:93:24] wire [5:0] _l2_auto_in_0_b_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_in_0_b_bits_address; // @[Configs.scala:93:24] wire _l2_auto_in_0_c_ready; // @[Configs.scala:93:24] wire _l2_auto_in_0_d_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_0_d_bits_opcode; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_0_d_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_0_d_bits_size; // @[Configs.scala:93:24] wire [5:0] _l2_auto_in_0_d_bits_source; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_0_d_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_in_0_d_bits_denied; // @[Configs.scala:93:24] wire [63:0] _l2_auto_in_0_d_bits_data; // @[Configs.scala:93:24] wire _l2_auto_in_0_d_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_out_3_a_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_3_a_bits_opcode; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_3_a_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_3_a_bits_size; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_3_a_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_out_3_a_bits_address; // @[Configs.scala:93:24] wire [7:0] _l2_auto_out_3_a_bits_mask; // @[Configs.scala:93:24] wire [63:0] _l2_auto_out_3_a_bits_data; // @[Configs.scala:93:24] wire _l2_auto_out_3_a_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_out_3_c_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_3_c_bits_opcode; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_3_c_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_3_c_bits_size; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_3_c_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_out_3_c_bits_address; // @[Configs.scala:93:24] wire [63:0] _l2_auto_out_3_c_bits_data; // @[Configs.scala:93:24] wire _l2_auto_out_3_c_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_out_3_d_ready; // @[Configs.scala:93:24] wire _l2_auto_out_3_e_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_3_e_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_out_2_a_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_2_a_bits_opcode; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_2_a_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_2_a_bits_size; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_2_a_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_out_2_a_bits_address; // @[Configs.scala:93:24] wire [7:0] _l2_auto_out_2_a_bits_mask; // @[Configs.scala:93:24] wire [63:0] _l2_auto_out_2_a_bits_data; // @[Configs.scala:93:24] wire _l2_auto_out_2_a_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_out_2_c_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_2_c_bits_opcode; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_2_c_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_2_c_bits_size; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_2_c_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_out_2_c_bits_address; // @[Configs.scala:93:24] wire [63:0] _l2_auto_out_2_c_bits_data; // @[Configs.scala:93:24] wire _l2_auto_out_2_c_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_out_2_d_ready; // @[Configs.scala:93:24] wire _l2_auto_out_2_e_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_2_e_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_out_1_a_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_1_a_bits_opcode; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_1_a_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_1_a_bits_size; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_1_a_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_out_1_a_bits_address; // @[Configs.scala:93:24] wire [7:0] _l2_auto_out_1_a_bits_mask; // @[Configs.scala:93:24] wire [63:0] _l2_auto_out_1_a_bits_data; // @[Configs.scala:93:24] wire _l2_auto_out_1_a_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_out_1_c_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_1_c_bits_opcode; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_1_c_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_1_c_bits_size; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_1_c_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_out_1_c_bits_address; // @[Configs.scala:93:24] wire [63:0] _l2_auto_out_1_c_bits_data; // @[Configs.scala:93:24] wire _l2_auto_out_1_c_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_out_1_d_ready; // @[Configs.scala:93:24] wire _l2_auto_out_1_e_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_1_e_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_out_0_a_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_0_a_bits_opcode; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_0_a_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_0_a_bits_size; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_0_a_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_out_0_a_bits_address; // @[Configs.scala:93:24] wire [7:0] _l2_auto_out_0_a_bits_mask; // @[Configs.scala:93:24] wire [63:0] _l2_auto_out_0_a_bits_data; // @[Configs.scala:93:24] wire _l2_auto_out_0_a_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_out_0_c_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_0_c_bits_opcode; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_0_c_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_0_c_bits_size; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_0_c_bits_source; // @[Configs.scala:93:24] wire [31:0] _l2_auto_out_0_c_bits_address; // @[Configs.scala:93:24] wire [63:0] _l2_auto_out_0_c_bits_data; // @[Configs.scala:93:24] wire _l2_auto_out_0_c_bits_corrupt; // @[Configs.scala:93:24] wire _l2_auto_out_0_d_ready; // @[Configs.scala:93:24] wire _l2_auto_out_0_e_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_out_0_e_bits_sink; // @[Configs.scala:93:24] InclusiveCache l2 ( // @[Configs.scala:93:24] .clock (auto_coh_clock_groups_in_member_coh_0_clock), .reset (auto_coh_clock_groups_in_member_coh_0_reset), .auto_ctrls_ctrl_in_a_ready (auto_l2_ctrls_ctrl_in_a_ready), .auto_ctrls_ctrl_in_a_valid (auto_l2_ctrls_ctrl_in_a_valid), .auto_ctrls_ctrl_in_a_bits_opcode (auto_l2_ctrls_ctrl_in_a_bits_opcode), .auto_ctrls_ctrl_in_a_bits_param (auto_l2_ctrls_ctrl_in_a_bits_param), .auto_ctrls_ctrl_in_a_bits_size (auto_l2_ctrls_ctrl_in_a_bits_size), .auto_ctrls_ctrl_in_a_bits_source (auto_l2_ctrls_ctrl_in_a_bits_source), .auto_ctrls_ctrl_in_a_bits_address (auto_l2_ctrls_ctrl_in_a_bits_address), .auto_ctrls_ctrl_in_a_bits_mask (auto_l2_ctrls_ctrl_in_a_bits_mask), .auto_ctrls_ctrl_in_a_bits_data (auto_l2_ctrls_ctrl_in_a_bits_data), .auto_ctrls_ctrl_in_a_bits_corrupt (auto_l2_ctrls_ctrl_in_a_bits_corrupt), .auto_ctrls_ctrl_in_d_ready (auto_l2_ctrls_ctrl_in_d_ready), .auto_ctrls_ctrl_in_d_valid (auto_l2_ctrls_ctrl_in_d_valid), .auto_ctrls_ctrl_in_d_bits_opcode (auto_l2_ctrls_ctrl_in_d_bits_opcode), .auto_ctrls_ctrl_in_d_bits_size (auto_l2_ctrls_ctrl_in_d_bits_size), .auto_ctrls_ctrl_in_d_bits_source (auto_l2_ctrls_ctrl_in_d_bits_source), .auto_ctrls_ctrl_in_d_bits_data (auto_l2_ctrls_ctrl_in_d_bits_data), .auto_in_3_a_ready (_l2_auto_in_3_a_ready), .auto_in_3_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_3_a_valid), // @[Parameters.scala:56:69] .auto_in_3_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_opcode), // @[Parameters.scala:56:69] .auto_in_3_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_param), // @[Parameters.scala:56:69] .auto_in_3_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_size), // @[Parameters.scala:56:69] .auto_in_3_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_source), // @[Parameters.scala:56:69] .auto_in_3_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_address), // @[Parameters.scala:56:69] .auto_in_3_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_mask), // @[Parameters.scala:56:69] .auto_in_3_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_data), // @[Parameters.scala:56:69] .auto_in_3_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_3_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_3_b_ready), // @[Parameters.scala:56:69] .auto_in_3_b_valid (_l2_auto_in_3_b_valid), .auto_in_3_b_bits_param (_l2_auto_in_3_b_bits_param), .auto_in_3_b_bits_source (_l2_auto_in_3_b_bits_source), .auto_in_3_b_bits_address (_l2_auto_in_3_b_bits_address), .auto_in_3_c_ready (_l2_auto_in_3_c_ready), .auto_in_3_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_3_c_valid), // @[Parameters.scala:56:69] .auto_in_3_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_opcode), // @[Parameters.scala:56:69] .auto_in_3_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_param), // @[Parameters.scala:56:69] .auto_in_3_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_size), // @[Parameters.scala:56:69] .auto_in_3_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_source), // @[Parameters.scala:56:69] .auto_in_3_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_address), // @[Parameters.scala:56:69] .auto_in_3_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_data), // @[Parameters.scala:56:69] .auto_in_3_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_3_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_3_d_ready), // @[Parameters.scala:56:69] .auto_in_3_d_valid (_l2_auto_in_3_d_valid), .auto_in_3_d_bits_opcode (_l2_auto_in_3_d_bits_opcode), .auto_in_3_d_bits_param (_l2_auto_in_3_d_bits_param), .auto_in_3_d_bits_size (_l2_auto_in_3_d_bits_size), .auto_in_3_d_bits_source (_l2_auto_in_3_d_bits_source), .auto_in_3_d_bits_sink (_l2_auto_in_3_d_bits_sink), .auto_in_3_d_bits_denied (_l2_auto_in_3_d_bits_denied), .auto_in_3_d_bits_data (_l2_auto_in_3_d_bits_data), .auto_in_3_d_bits_corrupt (_l2_auto_in_3_d_bits_corrupt), .auto_in_3_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_3_e_valid), // @[Parameters.scala:56:69] .auto_in_3_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_3_e_bits_sink), // @[Parameters.scala:56:69] .auto_in_2_a_ready (_l2_auto_in_2_a_ready), .auto_in_2_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_2_a_valid), // @[Parameters.scala:56:69] .auto_in_2_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_opcode), // @[Parameters.scala:56:69] .auto_in_2_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_param), // @[Parameters.scala:56:69] .auto_in_2_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_size), // @[Parameters.scala:56:69] .auto_in_2_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_source), // @[Parameters.scala:56:69] .auto_in_2_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_address), // @[Parameters.scala:56:69] .auto_in_2_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_mask), // @[Parameters.scala:56:69] .auto_in_2_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_data), // @[Parameters.scala:56:69] .auto_in_2_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_2_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_2_b_ready), // @[Parameters.scala:56:69] .auto_in_2_b_valid (_l2_auto_in_2_b_valid), .auto_in_2_b_bits_param (_l2_auto_in_2_b_bits_param), .auto_in_2_b_bits_source (_l2_auto_in_2_b_bits_source), .auto_in_2_b_bits_address (_l2_auto_in_2_b_bits_address), .auto_in_2_c_ready (_l2_auto_in_2_c_ready), .auto_in_2_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_2_c_valid), // @[Parameters.scala:56:69] .auto_in_2_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_opcode), // @[Parameters.scala:56:69] .auto_in_2_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_param), // @[Parameters.scala:56:69] .auto_in_2_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_size), // @[Parameters.scala:56:69] .auto_in_2_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_source), // @[Parameters.scala:56:69] .auto_in_2_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_address), // @[Parameters.scala:56:69] .auto_in_2_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_data), // @[Parameters.scala:56:69] .auto_in_2_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_2_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_2_d_ready), // @[Parameters.scala:56:69] .auto_in_2_d_valid (_l2_auto_in_2_d_valid), .auto_in_2_d_bits_opcode (_l2_auto_in_2_d_bits_opcode), .auto_in_2_d_bits_param (_l2_auto_in_2_d_bits_param), .auto_in_2_d_bits_size (_l2_auto_in_2_d_bits_size), .auto_in_2_d_bits_source (_l2_auto_in_2_d_bits_source), .auto_in_2_d_bits_sink (_l2_auto_in_2_d_bits_sink), .auto_in_2_d_bits_denied (_l2_auto_in_2_d_bits_denied), .auto_in_2_d_bits_data (_l2_auto_in_2_d_bits_data), .auto_in_2_d_bits_corrupt (_l2_auto_in_2_d_bits_corrupt), .auto_in_2_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_2_e_valid), // @[Parameters.scala:56:69] .auto_in_2_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_2_e_bits_sink), // @[Parameters.scala:56:69] .auto_in_1_a_ready (_l2_auto_in_1_a_ready), .auto_in_1_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_1_a_valid), // @[Parameters.scala:56:69] .auto_in_1_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_opcode), // @[Parameters.scala:56:69] .auto_in_1_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_param), // @[Parameters.scala:56:69] .auto_in_1_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_size), // @[Parameters.scala:56:69] .auto_in_1_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_source), // @[Parameters.scala:56:69] .auto_in_1_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_address), // @[Parameters.scala:56:69] .auto_in_1_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_mask), // @[Parameters.scala:56:69] .auto_in_1_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_data), // @[Parameters.scala:56:69] .auto_in_1_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_1_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_1_b_ready), // @[Parameters.scala:56:69] .auto_in_1_b_valid (_l2_auto_in_1_b_valid), .auto_in_1_b_bits_param (_l2_auto_in_1_b_bits_param), .auto_in_1_b_bits_source (_l2_auto_in_1_b_bits_source), .auto_in_1_b_bits_address (_l2_auto_in_1_b_bits_address), .auto_in_1_c_ready (_l2_auto_in_1_c_ready), .auto_in_1_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_1_c_valid), // @[Parameters.scala:56:69] .auto_in_1_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_opcode), // @[Parameters.scala:56:69] .auto_in_1_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_param), // @[Parameters.scala:56:69] .auto_in_1_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_size), // @[Parameters.scala:56:69] .auto_in_1_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_source), // @[Parameters.scala:56:69] .auto_in_1_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_address), // @[Parameters.scala:56:69] .auto_in_1_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_data), // @[Parameters.scala:56:69] .auto_in_1_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_1_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_1_d_ready), // @[Parameters.scala:56:69] .auto_in_1_d_valid (_l2_auto_in_1_d_valid), .auto_in_1_d_bits_opcode (_l2_auto_in_1_d_bits_opcode), .auto_in_1_d_bits_param (_l2_auto_in_1_d_bits_param), .auto_in_1_d_bits_size (_l2_auto_in_1_d_bits_size), .auto_in_1_d_bits_source (_l2_auto_in_1_d_bits_source), .auto_in_1_d_bits_sink (_l2_auto_in_1_d_bits_sink), .auto_in_1_d_bits_denied (_l2_auto_in_1_d_bits_denied), .auto_in_1_d_bits_data (_l2_auto_in_1_d_bits_data), .auto_in_1_d_bits_corrupt (_l2_auto_in_1_d_bits_corrupt), .auto_in_1_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_1_e_valid), // @[Parameters.scala:56:69] .auto_in_1_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_1_e_bits_sink), // @[Parameters.scala:56:69] .auto_in_0_a_ready (_l2_auto_in_0_a_ready), .auto_in_0_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_0_a_valid), // @[Parameters.scala:56:69] .auto_in_0_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_opcode), // @[Parameters.scala:56:69] .auto_in_0_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_param), // @[Parameters.scala:56:69] .auto_in_0_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_size), // @[Parameters.scala:56:69] .auto_in_0_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_source), // @[Parameters.scala:56:69] .auto_in_0_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_address), // @[Parameters.scala:56:69] .auto_in_0_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_mask), // @[Parameters.scala:56:69] .auto_in_0_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_data), // @[Parameters.scala:56:69] .auto_in_0_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_0_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_0_b_ready), // @[Parameters.scala:56:69] .auto_in_0_b_valid (_l2_auto_in_0_b_valid), .auto_in_0_b_bits_param (_l2_auto_in_0_b_bits_param), .auto_in_0_b_bits_source (_l2_auto_in_0_b_bits_source), .auto_in_0_b_bits_address (_l2_auto_in_0_b_bits_address), .auto_in_0_c_ready (_l2_auto_in_0_c_ready), .auto_in_0_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_0_c_valid), // @[Parameters.scala:56:69] .auto_in_0_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_opcode), // @[Parameters.scala:56:69] .auto_in_0_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_param), // @[Parameters.scala:56:69] .auto_in_0_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_size), // @[Parameters.scala:56:69] .auto_in_0_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_source), // @[Parameters.scala:56:69] .auto_in_0_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_address), // @[Parameters.scala:56:69] .auto_in_0_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_data), // @[Parameters.scala:56:69] .auto_in_0_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_0_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_0_d_ready), // @[Parameters.scala:56:69] .auto_in_0_d_valid (_l2_auto_in_0_d_valid), .auto_in_0_d_bits_opcode (_l2_auto_in_0_d_bits_opcode), .auto_in_0_d_bits_param (_l2_auto_in_0_d_bits_param), .auto_in_0_d_bits_size (_l2_auto_in_0_d_bits_size), .auto_in_0_d_bits_source (_l2_auto_in_0_d_bits_source), .auto_in_0_d_bits_sink (_l2_auto_in_0_d_bits_sink), .auto_in_0_d_bits_denied (_l2_auto_in_0_d_bits_denied), .auto_in_0_d_bits_data (_l2_auto_in_0_d_bits_data), .auto_in_0_d_bits_corrupt (_l2_auto_in_0_d_bits_corrupt), .auto_in_0_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_0_e_valid), // @[Parameters.scala:56:69] .auto_in_0_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_0_e_bits_sink), // @[Parameters.scala:56:69] .auto_out_3_a_ready (_cork_auto_in_3_a_ready), // @[Configs.scala:120:26] .auto_out_3_a_valid (_l2_auto_out_3_a_valid), .auto_out_3_a_bits_opcode (_l2_auto_out_3_a_bits_opcode), .auto_out_3_a_bits_param (_l2_auto_out_3_a_bits_param), .auto_out_3_a_bits_size (_l2_auto_out_3_a_bits_size), .auto_out_3_a_bits_source (_l2_auto_out_3_a_bits_source), .auto_out_3_a_bits_address (_l2_auto_out_3_a_bits_address), .auto_out_3_a_bits_mask (_l2_auto_out_3_a_bits_mask), .auto_out_3_a_bits_data (_l2_auto_out_3_a_bits_data), .auto_out_3_a_bits_corrupt (_l2_auto_out_3_a_bits_corrupt), .auto_out_3_c_ready (_cork_auto_in_3_c_ready), // @[Configs.scala:120:26] .auto_out_3_c_valid (_l2_auto_out_3_c_valid), .auto_out_3_c_bits_opcode (_l2_auto_out_3_c_bits_opcode), .auto_out_3_c_bits_param (_l2_auto_out_3_c_bits_param), .auto_out_3_c_bits_size (_l2_auto_out_3_c_bits_size), .auto_out_3_c_bits_source (_l2_auto_out_3_c_bits_source), .auto_out_3_c_bits_address (_l2_auto_out_3_c_bits_address), .auto_out_3_c_bits_data (_l2_auto_out_3_c_bits_data), .auto_out_3_c_bits_corrupt (_l2_auto_out_3_c_bits_corrupt), .auto_out_3_d_ready (_l2_auto_out_3_d_ready), .auto_out_3_d_valid (_cork_auto_in_3_d_valid), // @[Configs.scala:120:26] .auto_out_3_d_bits_opcode (_cork_auto_in_3_d_bits_opcode), // @[Configs.scala:120:26] .auto_out_3_d_bits_param (_cork_auto_in_3_d_bits_param), // @[Configs.scala:120:26] .auto_out_3_d_bits_size (_cork_auto_in_3_d_bits_size), // @[Configs.scala:120:26] .auto_out_3_d_bits_source (_cork_auto_in_3_d_bits_source), // @[Configs.scala:120:26] .auto_out_3_d_bits_sink (_cork_auto_in_3_d_bits_sink), // @[Configs.scala:120:26] .auto_out_3_d_bits_denied (_cork_auto_in_3_d_bits_denied), // @[Configs.scala:120:26] .auto_out_3_d_bits_data (_cork_auto_in_3_d_bits_data), // @[Configs.scala:120:26] .auto_out_3_d_bits_corrupt (_cork_auto_in_3_d_bits_corrupt), // @[Configs.scala:120:26] .auto_out_3_e_valid (_l2_auto_out_3_e_valid), .auto_out_3_e_bits_sink (_l2_auto_out_3_e_bits_sink), .auto_out_2_a_ready (_cork_auto_in_2_a_ready), // @[Configs.scala:120:26] .auto_out_2_a_valid (_l2_auto_out_2_a_valid), .auto_out_2_a_bits_opcode (_l2_auto_out_2_a_bits_opcode), .auto_out_2_a_bits_param (_l2_auto_out_2_a_bits_param), .auto_out_2_a_bits_size (_l2_auto_out_2_a_bits_size), .auto_out_2_a_bits_source (_l2_auto_out_2_a_bits_source), .auto_out_2_a_bits_address (_l2_auto_out_2_a_bits_address), .auto_out_2_a_bits_mask (_l2_auto_out_2_a_bits_mask), .auto_out_2_a_bits_data (_l2_auto_out_2_a_bits_data), .auto_out_2_a_bits_corrupt (_l2_auto_out_2_a_bits_corrupt), .auto_out_2_c_ready (_cork_auto_in_2_c_ready), // @[Configs.scala:120:26] .auto_out_2_c_valid (_l2_auto_out_2_c_valid), .auto_out_2_c_bits_opcode (_l2_auto_out_2_c_bits_opcode), .auto_out_2_c_bits_param (_l2_auto_out_2_c_bits_param), .auto_out_2_c_bits_size (_l2_auto_out_2_c_bits_size), .auto_out_2_c_bits_source (_l2_auto_out_2_c_bits_source), .auto_out_2_c_bits_address (_l2_auto_out_2_c_bits_address), .auto_out_2_c_bits_data (_l2_auto_out_2_c_bits_data), .auto_out_2_c_bits_corrupt (_l2_auto_out_2_c_bits_corrupt), .auto_out_2_d_ready (_l2_auto_out_2_d_ready), .auto_out_2_d_valid (_cork_auto_in_2_d_valid), // @[Configs.scala:120:26] .auto_out_2_d_bits_opcode (_cork_auto_in_2_d_bits_opcode), // @[Configs.scala:120:26] .auto_out_2_d_bits_param (_cork_auto_in_2_d_bits_param), // @[Configs.scala:120:26] .auto_out_2_d_bits_size (_cork_auto_in_2_d_bits_size), // @[Configs.scala:120:26] .auto_out_2_d_bits_source (_cork_auto_in_2_d_bits_source), // @[Configs.scala:120:26] .auto_out_2_d_bits_sink (_cork_auto_in_2_d_bits_sink), // @[Configs.scala:120:26] .auto_out_2_d_bits_denied (_cork_auto_in_2_d_bits_denied), // @[Configs.scala:120:26] .auto_out_2_d_bits_data (_cork_auto_in_2_d_bits_data), // @[Configs.scala:120:26] .auto_out_2_d_bits_corrupt (_cork_auto_in_2_d_bits_corrupt), // @[Configs.scala:120:26] .auto_out_2_e_valid (_l2_auto_out_2_e_valid), .auto_out_2_e_bits_sink (_l2_auto_out_2_e_bits_sink), .auto_out_1_a_ready (_cork_auto_in_1_a_ready), // @[Configs.scala:120:26] .auto_out_1_a_valid (_l2_auto_out_1_a_valid), .auto_out_1_a_bits_opcode (_l2_auto_out_1_a_bits_opcode), .auto_out_1_a_bits_param (_l2_auto_out_1_a_bits_param), .auto_out_1_a_bits_size (_l2_auto_out_1_a_bits_size), .auto_out_1_a_bits_source (_l2_auto_out_1_a_bits_source), .auto_out_1_a_bits_address (_l2_auto_out_1_a_bits_address), .auto_out_1_a_bits_mask (_l2_auto_out_1_a_bits_mask), .auto_out_1_a_bits_data (_l2_auto_out_1_a_bits_data), .auto_out_1_a_bits_corrupt (_l2_auto_out_1_a_bits_corrupt), .auto_out_1_c_ready (_cork_auto_in_1_c_ready), // @[Configs.scala:120:26] .auto_out_1_c_valid (_l2_auto_out_1_c_valid), .auto_out_1_c_bits_opcode (_l2_auto_out_1_c_bits_opcode), .auto_out_1_c_bits_param (_l2_auto_out_1_c_bits_param), .auto_out_1_c_bits_size (_l2_auto_out_1_c_bits_size), .auto_out_1_c_bits_source (_l2_auto_out_1_c_bits_source), .auto_out_1_c_bits_address (_l2_auto_out_1_c_bits_address), .auto_out_1_c_bits_data (_l2_auto_out_1_c_bits_data), .auto_out_1_c_bits_corrupt (_l2_auto_out_1_c_bits_corrupt), .auto_out_1_d_ready (_l2_auto_out_1_d_ready), .auto_out_1_d_valid (_cork_auto_in_1_d_valid), // @[Configs.scala:120:26] .auto_out_1_d_bits_opcode (_cork_auto_in_1_d_bits_opcode), // @[Configs.scala:120:26] .auto_out_1_d_bits_param (_cork_auto_in_1_d_bits_param), // @[Configs.scala:120:26] .auto_out_1_d_bits_size (_cork_auto_in_1_d_bits_size), // @[Configs.scala:120:26] .auto_out_1_d_bits_source (_cork_auto_in_1_d_bits_source), // @[Configs.scala:120:26] .auto_out_1_d_bits_sink (_cork_auto_in_1_d_bits_sink), // @[Configs.scala:120:26] .auto_out_1_d_bits_denied (_cork_auto_in_1_d_bits_denied), // @[Configs.scala:120:26] .auto_out_1_d_bits_data (_cork_auto_in_1_d_bits_data), // @[Configs.scala:120:26] .auto_out_1_d_bits_corrupt (_cork_auto_in_1_d_bits_corrupt), // @[Configs.scala:120:26] .auto_out_1_e_valid (_l2_auto_out_1_e_valid), .auto_out_1_e_bits_sink (_l2_auto_out_1_e_bits_sink), .auto_out_0_a_ready (_cork_auto_in_0_a_ready), // @[Configs.scala:120:26] .auto_out_0_a_valid (_l2_auto_out_0_a_valid), .auto_out_0_a_bits_opcode (_l2_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param (_l2_auto_out_0_a_bits_param), .auto_out_0_a_bits_size (_l2_auto_out_0_a_bits_size), .auto_out_0_a_bits_source (_l2_auto_out_0_a_bits_source), .auto_out_0_a_bits_address (_l2_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask (_l2_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data (_l2_auto_out_0_a_bits_data), .auto_out_0_a_bits_corrupt (_l2_auto_out_0_a_bits_corrupt), .auto_out_0_c_ready (_cork_auto_in_0_c_ready), // @[Configs.scala:120:26] .auto_out_0_c_valid (_l2_auto_out_0_c_valid), .auto_out_0_c_bits_opcode (_l2_auto_out_0_c_bits_opcode), .auto_out_0_c_bits_param (_l2_auto_out_0_c_bits_param), .auto_out_0_c_bits_size (_l2_auto_out_0_c_bits_size), .auto_out_0_c_bits_source (_l2_auto_out_0_c_bits_source), .auto_out_0_c_bits_address (_l2_auto_out_0_c_bits_address), .auto_out_0_c_bits_data (_l2_auto_out_0_c_bits_data), .auto_out_0_c_bits_corrupt (_l2_auto_out_0_c_bits_corrupt), .auto_out_0_d_ready (_l2_auto_out_0_d_ready), .auto_out_0_d_valid (_cork_auto_in_0_d_valid), // @[Configs.scala:120:26] .auto_out_0_d_bits_opcode (_cork_auto_in_0_d_bits_opcode), // @[Configs.scala:120:26] .auto_out_0_d_bits_param (_cork_auto_in_0_d_bits_param), // @[Configs.scala:120:26] .auto_out_0_d_bits_size (_cork_auto_in_0_d_bits_size), // @[Configs.scala:120:26] .auto_out_0_d_bits_source (_cork_auto_in_0_d_bits_source), // @[Configs.scala:120:26] .auto_out_0_d_bits_sink (_cork_auto_in_0_d_bits_sink), // @[Configs.scala:120:26] .auto_out_0_d_bits_denied (_cork_auto_in_0_d_bits_denied), // @[Configs.scala:120:26] .auto_out_0_d_bits_data (_cork_auto_in_0_d_bits_data), // @[Configs.scala:120:26] .auto_out_0_d_bits_corrupt (_cork_auto_in_0_d_bits_corrupt), // @[Configs.scala:120:26] .auto_out_0_e_valid (_l2_auto_out_0_e_valid), .auto_out_0_e_bits_sink (_l2_auto_out_0_e_bits_sink) ); // @[Configs.scala:93:24] TLBuffer_a32d64s6k3z3c InclusiveCache_inner_TLBuffer ( // @[Parameters.scala:56:69] .clock (auto_coh_clock_groups_in_member_coh_0_clock), .reset (auto_coh_clock_groups_in_member_coh_0_reset), .auto_in_3_a_ready (auto_coherent_jbar_anon_in_3_a_ready), .auto_in_3_a_valid (auto_coherent_jbar_anon_in_3_a_valid), .auto_in_3_a_bits_opcode (auto_coherent_jbar_anon_in_3_a_bits_opcode), .auto_in_3_a_bits_param (auto_coherent_jbar_anon_in_3_a_bits_param), .auto_in_3_a_bits_size (auto_coherent_jbar_anon_in_3_a_bits_size), .auto_in_3_a_bits_source (auto_coherent_jbar_anon_in_3_a_bits_source), .auto_in_3_a_bits_address (auto_coherent_jbar_anon_in_3_a_bits_address), .auto_in_3_a_bits_mask (auto_coherent_jbar_anon_in_3_a_bits_mask), .auto_in_3_a_bits_data (auto_coherent_jbar_anon_in_3_a_bits_data), .auto_in_3_a_bits_corrupt (auto_coherent_jbar_anon_in_3_a_bits_corrupt), .auto_in_3_b_ready (auto_coherent_jbar_anon_in_3_b_ready), .auto_in_3_b_valid (auto_coherent_jbar_anon_in_3_b_valid), .auto_in_3_b_bits_param (auto_coherent_jbar_anon_in_3_b_bits_param), .auto_in_3_b_bits_source (auto_coherent_jbar_anon_in_3_b_bits_source), .auto_in_3_b_bits_address (auto_coherent_jbar_anon_in_3_b_bits_address), .auto_in_3_c_ready (auto_coherent_jbar_anon_in_3_c_ready), .auto_in_3_c_valid (auto_coherent_jbar_anon_in_3_c_valid), .auto_in_3_c_bits_opcode (auto_coherent_jbar_anon_in_3_c_bits_opcode), .auto_in_3_c_bits_param (auto_coherent_jbar_anon_in_3_c_bits_param), .auto_in_3_c_bits_size (auto_coherent_jbar_anon_in_3_c_bits_size), .auto_in_3_c_bits_source (auto_coherent_jbar_anon_in_3_c_bits_source), .auto_in_3_c_bits_address (auto_coherent_jbar_anon_in_3_c_bits_address), .auto_in_3_c_bits_data (auto_coherent_jbar_anon_in_3_c_bits_data), .auto_in_3_c_bits_corrupt (auto_coherent_jbar_anon_in_3_c_bits_corrupt), .auto_in_3_d_ready (auto_coherent_jbar_anon_in_3_d_ready), .auto_in_3_d_valid (auto_coherent_jbar_anon_in_3_d_valid), .auto_in_3_d_bits_opcode (auto_coherent_jbar_anon_in_3_d_bits_opcode), .auto_in_3_d_bits_param (auto_coherent_jbar_anon_in_3_d_bits_param), .auto_in_3_d_bits_size (auto_coherent_jbar_anon_in_3_d_bits_size), .auto_in_3_d_bits_source (auto_coherent_jbar_anon_in_3_d_bits_source), .auto_in_3_d_bits_sink (auto_coherent_jbar_anon_in_3_d_bits_sink), .auto_in_3_d_bits_denied (auto_coherent_jbar_anon_in_3_d_bits_denied), .auto_in_3_d_bits_data (auto_coherent_jbar_anon_in_3_d_bits_data), .auto_in_3_d_bits_corrupt (auto_coherent_jbar_anon_in_3_d_bits_corrupt), .auto_in_3_e_valid (auto_coherent_jbar_anon_in_3_e_valid), .auto_in_3_e_bits_sink (auto_coherent_jbar_anon_in_3_e_bits_sink), .auto_in_2_a_ready (auto_coherent_jbar_anon_in_2_a_ready), .auto_in_2_a_valid (auto_coherent_jbar_anon_in_2_a_valid), .auto_in_2_a_bits_opcode (auto_coherent_jbar_anon_in_2_a_bits_opcode), .auto_in_2_a_bits_param (auto_coherent_jbar_anon_in_2_a_bits_param), .auto_in_2_a_bits_size (auto_coherent_jbar_anon_in_2_a_bits_size), .auto_in_2_a_bits_source (auto_coherent_jbar_anon_in_2_a_bits_source), .auto_in_2_a_bits_address (auto_coherent_jbar_anon_in_2_a_bits_address), .auto_in_2_a_bits_mask (auto_coherent_jbar_anon_in_2_a_bits_mask), .auto_in_2_a_bits_data (auto_coherent_jbar_anon_in_2_a_bits_data), .auto_in_2_a_bits_corrupt (auto_coherent_jbar_anon_in_2_a_bits_corrupt), .auto_in_2_b_ready (auto_coherent_jbar_anon_in_2_b_ready), .auto_in_2_b_valid (auto_coherent_jbar_anon_in_2_b_valid), .auto_in_2_b_bits_param (auto_coherent_jbar_anon_in_2_b_bits_param), .auto_in_2_b_bits_source (auto_coherent_jbar_anon_in_2_b_bits_source), .auto_in_2_b_bits_address (auto_coherent_jbar_anon_in_2_b_bits_address), .auto_in_2_c_ready (auto_coherent_jbar_anon_in_2_c_ready), .auto_in_2_c_valid (auto_coherent_jbar_anon_in_2_c_valid), .auto_in_2_c_bits_opcode (auto_coherent_jbar_anon_in_2_c_bits_opcode), .auto_in_2_c_bits_param (auto_coherent_jbar_anon_in_2_c_bits_param), .auto_in_2_c_bits_size (auto_coherent_jbar_anon_in_2_c_bits_size), .auto_in_2_c_bits_source (auto_coherent_jbar_anon_in_2_c_bits_source), .auto_in_2_c_bits_address (auto_coherent_jbar_anon_in_2_c_bits_address), .auto_in_2_c_bits_data (auto_coherent_jbar_anon_in_2_c_bits_data), .auto_in_2_c_bits_corrupt (auto_coherent_jbar_anon_in_2_c_bits_corrupt), .auto_in_2_d_ready (auto_coherent_jbar_anon_in_2_d_ready), .auto_in_2_d_valid (auto_coherent_jbar_anon_in_2_d_valid), .auto_in_2_d_bits_opcode (auto_coherent_jbar_anon_in_2_d_bits_opcode), .auto_in_2_d_bits_param (auto_coherent_jbar_anon_in_2_d_bits_param), .auto_in_2_d_bits_size (auto_coherent_jbar_anon_in_2_d_bits_size), .auto_in_2_d_bits_source (auto_coherent_jbar_anon_in_2_d_bits_source), .auto_in_2_d_bits_sink (auto_coherent_jbar_anon_in_2_d_bits_sink), .auto_in_2_d_bits_denied (auto_coherent_jbar_anon_in_2_d_bits_denied), .auto_in_2_d_bits_data (auto_coherent_jbar_anon_in_2_d_bits_data), .auto_in_2_d_bits_corrupt (auto_coherent_jbar_anon_in_2_d_bits_corrupt), .auto_in_2_e_valid (auto_coherent_jbar_anon_in_2_e_valid), .auto_in_2_e_bits_sink (auto_coherent_jbar_anon_in_2_e_bits_sink), .auto_in_1_a_ready (auto_coherent_jbar_anon_in_1_a_ready), .auto_in_1_a_valid (auto_coherent_jbar_anon_in_1_a_valid), .auto_in_1_a_bits_opcode (auto_coherent_jbar_anon_in_1_a_bits_opcode), .auto_in_1_a_bits_param (auto_coherent_jbar_anon_in_1_a_bits_param), .auto_in_1_a_bits_size (auto_coherent_jbar_anon_in_1_a_bits_size), .auto_in_1_a_bits_source (auto_coherent_jbar_anon_in_1_a_bits_source), .auto_in_1_a_bits_address (auto_coherent_jbar_anon_in_1_a_bits_address), .auto_in_1_a_bits_mask (auto_coherent_jbar_anon_in_1_a_bits_mask), .auto_in_1_a_bits_data (auto_coherent_jbar_anon_in_1_a_bits_data), .auto_in_1_a_bits_corrupt (auto_coherent_jbar_anon_in_1_a_bits_corrupt), .auto_in_1_b_ready (auto_coherent_jbar_anon_in_1_b_ready), .auto_in_1_b_valid (auto_coherent_jbar_anon_in_1_b_valid), .auto_in_1_b_bits_param (auto_coherent_jbar_anon_in_1_b_bits_param), .auto_in_1_b_bits_source (auto_coherent_jbar_anon_in_1_b_bits_source), .auto_in_1_b_bits_address (auto_coherent_jbar_anon_in_1_b_bits_address), .auto_in_1_c_ready (auto_coherent_jbar_anon_in_1_c_ready), .auto_in_1_c_valid (auto_coherent_jbar_anon_in_1_c_valid), .auto_in_1_c_bits_opcode (auto_coherent_jbar_anon_in_1_c_bits_opcode), .auto_in_1_c_bits_param (auto_coherent_jbar_anon_in_1_c_bits_param), .auto_in_1_c_bits_size (auto_coherent_jbar_anon_in_1_c_bits_size), .auto_in_1_c_bits_source (auto_coherent_jbar_anon_in_1_c_bits_source), .auto_in_1_c_bits_address (auto_coherent_jbar_anon_in_1_c_bits_address), .auto_in_1_c_bits_data (auto_coherent_jbar_anon_in_1_c_bits_data), .auto_in_1_c_bits_corrupt (auto_coherent_jbar_anon_in_1_c_bits_corrupt), .auto_in_1_d_ready (auto_coherent_jbar_anon_in_1_d_ready), .auto_in_1_d_valid (auto_coherent_jbar_anon_in_1_d_valid), .auto_in_1_d_bits_opcode (auto_coherent_jbar_anon_in_1_d_bits_opcode), .auto_in_1_d_bits_param (auto_coherent_jbar_anon_in_1_d_bits_param), .auto_in_1_d_bits_size (auto_coherent_jbar_anon_in_1_d_bits_size), .auto_in_1_d_bits_source (auto_coherent_jbar_anon_in_1_d_bits_source), .auto_in_1_d_bits_sink (auto_coherent_jbar_anon_in_1_d_bits_sink), .auto_in_1_d_bits_denied (auto_coherent_jbar_anon_in_1_d_bits_denied), .auto_in_1_d_bits_data (auto_coherent_jbar_anon_in_1_d_bits_data), .auto_in_1_d_bits_corrupt (auto_coherent_jbar_anon_in_1_d_bits_corrupt), .auto_in_1_e_valid (auto_coherent_jbar_anon_in_1_e_valid), .auto_in_1_e_bits_sink (auto_coherent_jbar_anon_in_1_e_bits_sink), .auto_in_0_a_ready (auto_coherent_jbar_anon_in_0_a_ready), .auto_in_0_a_valid (auto_coherent_jbar_anon_in_0_a_valid), .auto_in_0_a_bits_opcode (auto_coherent_jbar_anon_in_0_a_bits_opcode), .auto_in_0_a_bits_param (auto_coherent_jbar_anon_in_0_a_bits_param), .auto_in_0_a_bits_size (auto_coherent_jbar_anon_in_0_a_bits_size), .auto_in_0_a_bits_source (auto_coherent_jbar_anon_in_0_a_bits_source), .auto_in_0_a_bits_address (auto_coherent_jbar_anon_in_0_a_bits_address), .auto_in_0_a_bits_mask (auto_coherent_jbar_anon_in_0_a_bits_mask), .auto_in_0_a_bits_data (auto_coherent_jbar_anon_in_0_a_bits_data), .auto_in_0_a_bits_corrupt (auto_coherent_jbar_anon_in_0_a_bits_corrupt), .auto_in_0_b_ready (auto_coherent_jbar_anon_in_0_b_ready), .auto_in_0_b_valid (auto_coherent_jbar_anon_in_0_b_valid), .auto_in_0_b_bits_param (auto_coherent_jbar_anon_in_0_b_bits_param), .auto_in_0_b_bits_source (auto_coherent_jbar_anon_in_0_b_bits_source), .auto_in_0_b_bits_address (auto_coherent_jbar_anon_in_0_b_bits_address), .auto_in_0_c_ready (auto_coherent_jbar_anon_in_0_c_ready), .auto_in_0_c_valid (auto_coherent_jbar_anon_in_0_c_valid), .auto_in_0_c_bits_opcode (auto_coherent_jbar_anon_in_0_c_bits_opcode), .auto_in_0_c_bits_param (auto_coherent_jbar_anon_in_0_c_bits_param), .auto_in_0_c_bits_size (auto_coherent_jbar_anon_in_0_c_bits_size), .auto_in_0_c_bits_source (auto_coherent_jbar_anon_in_0_c_bits_source), .auto_in_0_c_bits_address (auto_coherent_jbar_anon_in_0_c_bits_address), .auto_in_0_c_bits_data (auto_coherent_jbar_anon_in_0_c_bits_data), .auto_in_0_c_bits_corrupt (auto_coherent_jbar_anon_in_0_c_bits_corrupt), .auto_in_0_d_ready (auto_coherent_jbar_anon_in_0_d_ready), .auto_in_0_d_valid (auto_coherent_jbar_anon_in_0_d_valid), .auto_in_0_d_bits_opcode (auto_coherent_jbar_anon_in_0_d_bits_opcode), .auto_in_0_d_bits_param (auto_coherent_jbar_anon_in_0_d_bits_param), .auto_in_0_d_bits_size (auto_coherent_jbar_anon_in_0_d_bits_size), .auto_in_0_d_bits_source (auto_coherent_jbar_anon_in_0_d_bits_source), .auto_in_0_d_bits_sink (auto_coherent_jbar_anon_in_0_d_bits_sink), .auto_in_0_d_bits_denied (auto_coherent_jbar_anon_in_0_d_bits_denied), .auto_in_0_d_bits_data (auto_coherent_jbar_anon_in_0_d_bits_data), .auto_in_0_d_bits_corrupt (auto_coherent_jbar_anon_in_0_d_bits_corrupt), .auto_in_0_e_valid (auto_coherent_jbar_anon_in_0_e_valid), .auto_in_0_e_bits_sink (auto_coherent_jbar_anon_in_0_e_bits_sink), .auto_out_3_a_ready (_l2_auto_in_3_a_ready), // @[Configs.scala:93:24] .auto_out_3_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_3_a_valid), .auto_out_3_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_opcode), .auto_out_3_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_param), .auto_out_3_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_size), .auto_out_3_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_source), .auto_out_3_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_address), .auto_out_3_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_mask), .auto_out_3_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_data), .auto_out_3_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_3_a_bits_corrupt), .auto_out_3_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_3_b_ready), .auto_out_3_b_valid (_l2_auto_in_3_b_valid), // @[Configs.scala:93:24] .auto_out_3_b_bits_param (_l2_auto_in_3_b_bits_param), // @[Configs.scala:93:24] .auto_out_3_b_bits_source (_l2_auto_in_3_b_bits_source), // @[Configs.scala:93:24] .auto_out_3_b_bits_address (_l2_auto_in_3_b_bits_address), // @[Configs.scala:93:24] .auto_out_3_c_ready (_l2_auto_in_3_c_ready), // @[Configs.scala:93:24] .auto_out_3_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_3_c_valid), .auto_out_3_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_opcode), .auto_out_3_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_param), .auto_out_3_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_size), .auto_out_3_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_source), .auto_out_3_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_address), .auto_out_3_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_data), .auto_out_3_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_3_c_bits_corrupt), .auto_out_3_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_3_d_ready), .auto_out_3_d_valid (_l2_auto_in_3_d_valid), // @[Configs.scala:93:24] .auto_out_3_d_bits_opcode (_l2_auto_in_3_d_bits_opcode), // @[Configs.scala:93:24] .auto_out_3_d_bits_param (_l2_auto_in_3_d_bits_param), // @[Configs.scala:93:24] .auto_out_3_d_bits_size (_l2_auto_in_3_d_bits_size), // @[Configs.scala:93:24] .auto_out_3_d_bits_source (_l2_auto_in_3_d_bits_source), // @[Configs.scala:93:24] .auto_out_3_d_bits_sink (_l2_auto_in_3_d_bits_sink), // @[Configs.scala:93:24] .auto_out_3_d_bits_denied (_l2_auto_in_3_d_bits_denied), // @[Configs.scala:93:24] .auto_out_3_d_bits_data (_l2_auto_in_3_d_bits_data), // @[Configs.scala:93:24] .auto_out_3_d_bits_corrupt (_l2_auto_in_3_d_bits_corrupt), // @[Configs.scala:93:24] .auto_out_3_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_3_e_valid), .auto_out_3_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_3_e_bits_sink), .auto_out_2_a_ready (_l2_auto_in_2_a_ready), // @[Configs.scala:93:24] .auto_out_2_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_2_a_valid), .auto_out_2_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_opcode), .auto_out_2_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_param), .auto_out_2_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_size), .auto_out_2_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_source), .auto_out_2_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_address), .auto_out_2_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_mask), .auto_out_2_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_data), .auto_out_2_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_2_a_bits_corrupt), .auto_out_2_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_2_b_ready), .auto_out_2_b_valid (_l2_auto_in_2_b_valid), // @[Configs.scala:93:24] .auto_out_2_b_bits_param (_l2_auto_in_2_b_bits_param), // @[Configs.scala:93:24] .auto_out_2_b_bits_source (_l2_auto_in_2_b_bits_source), // @[Configs.scala:93:24] .auto_out_2_b_bits_address (_l2_auto_in_2_b_bits_address), // @[Configs.scala:93:24] .auto_out_2_c_ready (_l2_auto_in_2_c_ready), // @[Configs.scala:93:24] .auto_out_2_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_2_c_valid), .auto_out_2_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_opcode), .auto_out_2_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_param), .auto_out_2_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_size), .auto_out_2_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_source), .auto_out_2_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_address), .auto_out_2_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_data), .auto_out_2_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_2_c_bits_corrupt), .auto_out_2_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_2_d_ready), .auto_out_2_d_valid (_l2_auto_in_2_d_valid), // @[Configs.scala:93:24] .auto_out_2_d_bits_opcode (_l2_auto_in_2_d_bits_opcode), // @[Configs.scala:93:24] .auto_out_2_d_bits_param (_l2_auto_in_2_d_bits_param), // @[Configs.scala:93:24] .auto_out_2_d_bits_size (_l2_auto_in_2_d_bits_size), // @[Configs.scala:93:24] .auto_out_2_d_bits_source (_l2_auto_in_2_d_bits_source), // @[Configs.scala:93:24] .auto_out_2_d_bits_sink (_l2_auto_in_2_d_bits_sink), // @[Configs.scala:93:24] .auto_out_2_d_bits_denied (_l2_auto_in_2_d_bits_denied), // @[Configs.scala:93:24] .auto_out_2_d_bits_data (_l2_auto_in_2_d_bits_data), // @[Configs.scala:93:24] .auto_out_2_d_bits_corrupt (_l2_auto_in_2_d_bits_corrupt), // @[Configs.scala:93:24] .auto_out_2_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_2_e_valid), .auto_out_2_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_2_e_bits_sink), .auto_out_1_a_ready (_l2_auto_in_1_a_ready), // @[Configs.scala:93:24] .auto_out_1_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_1_a_valid), .auto_out_1_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_opcode), .auto_out_1_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_param), .auto_out_1_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_size), .auto_out_1_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_source), .auto_out_1_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_address), .auto_out_1_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_mask), .auto_out_1_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_data), .auto_out_1_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_1_a_bits_corrupt), .auto_out_1_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_1_b_ready), .auto_out_1_b_valid (_l2_auto_in_1_b_valid), // @[Configs.scala:93:24] .auto_out_1_b_bits_param (_l2_auto_in_1_b_bits_param), // @[Configs.scala:93:24] .auto_out_1_b_bits_source (_l2_auto_in_1_b_bits_source), // @[Configs.scala:93:24] .auto_out_1_b_bits_address (_l2_auto_in_1_b_bits_address), // @[Configs.scala:93:24] .auto_out_1_c_ready (_l2_auto_in_1_c_ready), // @[Configs.scala:93:24] .auto_out_1_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_1_c_valid), .auto_out_1_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_opcode), .auto_out_1_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_param), .auto_out_1_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_size), .auto_out_1_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_source), .auto_out_1_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_address), .auto_out_1_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_data), .auto_out_1_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_1_c_bits_corrupt), .auto_out_1_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_1_d_ready), .auto_out_1_d_valid (_l2_auto_in_1_d_valid), // @[Configs.scala:93:24] .auto_out_1_d_bits_opcode (_l2_auto_in_1_d_bits_opcode), // @[Configs.scala:93:24] .auto_out_1_d_bits_param (_l2_auto_in_1_d_bits_param), // @[Configs.scala:93:24] .auto_out_1_d_bits_size (_l2_auto_in_1_d_bits_size), // @[Configs.scala:93:24] .auto_out_1_d_bits_source (_l2_auto_in_1_d_bits_source), // @[Configs.scala:93:24] .auto_out_1_d_bits_sink (_l2_auto_in_1_d_bits_sink), // @[Configs.scala:93:24] .auto_out_1_d_bits_denied (_l2_auto_in_1_d_bits_denied), // @[Configs.scala:93:24] .auto_out_1_d_bits_data (_l2_auto_in_1_d_bits_data), // @[Configs.scala:93:24] .auto_out_1_d_bits_corrupt (_l2_auto_in_1_d_bits_corrupt), // @[Configs.scala:93:24] .auto_out_1_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_1_e_valid), .auto_out_1_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_1_e_bits_sink), .auto_out_0_a_ready (_l2_auto_in_0_a_ready), // @[Configs.scala:93:24] .auto_out_0_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_0_a_valid), .auto_out_0_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_param), .auto_out_0_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_size), .auto_out_0_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_source), .auto_out_0_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_data), .auto_out_0_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_0_a_bits_corrupt), .auto_out_0_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_0_b_ready), .auto_out_0_b_valid (_l2_auto_in_0_b_valid), // @[Configs.scala:93:24] .auto_out_0_b_bits_param (_l2_auto_in_0_b_bits_param), // @[Configs.scala:93:24] .auto_out_0_b_bits_source (_l2_auto_in_0_b_bits_source), // @[Configs.scala:93:24] .auto_out_0_b_bits_address (_l2_auto_in_0_b_bits_address), // @[Configs.scala:93:24] .auto_out_0_c_ready (_l2_auto_in_0_c_ready), // @[Configs.scala:93:24] .auto_out_0_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_0_c_valid), .auto_out_0_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_opcode), .auto_out_0_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_param), .auto_out_0_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_size), .auto_out_0_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_source), .auto_out_0_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_address), .auto_out_0_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_data), .auto_out_0_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_0_c_bits_corrupt), .auto_out_0_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_0_d_ready), .auto_out_0_d_valid (_l2_auto_in_0_d_valid), // @[Configs.scala:93:24] .auto_out_0_d_bits_opcode (_l2_auto_in_0_d_bits_opcode), // @[Configs.scala:93:24] .auto_out_0_d_bits_param (_l2_auto_in_0_d_bits_param), // @[Configs.scala:93:24] .auto_out_0_d_bits_size (_l2_auto_in_0_d_bits_size), // @[Configs.scala:93:24] .auto_out_0_d_bits_source (_l2_auto_in_0_d_bits_source), // @[Configs.scala:93:24] .auto_out_0_d_bits_sink (_l2_auto_in_0_d_bits_sink), // @[Configs.scala:93:24] .auto_out_0_d_bits_denied (_l2_auto_in_0_d_bits_denied), // @[Configs.scala:93:24] .auto_out_0_d_bits_data (_l2_auto_in_0_d_bits_data), // @[Configs.scala:93:24] .auto_out_0_d_bits_corrupt (_l2_auto_in_0_d_bits_corrupt), // @[Configs.scala:93:24] .auto_out_0_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_0_e_valid), .auto_out_0_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_0_e_bits_sink) ); // @[Parameters.scala:56:69] TLCacheCork cork ( // @[Configs.scala:120:26] .clock (auto_coh_clock_groups_in_member_coh_0_clock), .reset (auto_coh_clock_groups_in_member_coh_0_reset), .auto_in_3_a_ready (_cork_auto_in_3_a_ready), .auto_in_3_a_valid (_l2_auto_out_3_a_valid), // @[Configs.scala:93:24] .auto_in_3_a_bits_opcode (_l2_auto_out_3_a_bits_opcode), // @[Configs.scala:93:24] .auto_in_3_a_bits_param (_l2_auto_out_3_a_bits_param), // @[Configs.scala:93:24] .auto_in_3_a_bits_size (_l2_auto_out_3_a_bits_size), // @[Configs.scala:93:24] .auto_in_3_a_bits_source (_l2_auto_out_3_a_bits_source), // @[Configs.scala:93:24] .auto_in_3_a_bits_address (_l2_auto_out_3_a_bits_address), // @[Configs.scala:93:24] .auto_in_3_a_bits_mask (_l2_auto_out_3_a_bits_mask), // @[Configs.scala:93:24] .auto_in_3_a_bits_data (_l2_auto_out_3_a_bits_data), // @[Configs.scala:93:24] .auto_in_3_a_bits_corrupt (_l2_auto_out_3_a_bits_corrupt), // @[Configs.scala:93:24] .auto_in_3_c_ready (_cork_auto_in_3_c_ready), .auto_in_3_c_valid (_l2_auto_out_3_c_valid), // @[Configs.scala:93:24] .auto_in_3_c_bits_opcode (_l2_auto_out_3_c_bits_opcode), // @[Configs.scala:93:24] .auto_in_3_c_bits_param (_l2_auto_out_3_c_bits_param), // @[Configs.scala:93:24] .auto_in_3_c_bits_size (_l2_auto_out_3_c_bits_size), // @[Configs.scala:93:24] .auto_in_3_c_bits_source (_l2_auto_out_3_c_bits_source), // @[Configs.scala:93:24] .auto_in_3_c_bits_address (_l2_auto_out_3_c_bits_address), // @[Configs.scala:93:24] .auto_in_3_c_bits_data (_l2_auto_out_3_c_bits_data), // @[Configs.scala:93:24] .auto_in_3_c_bits_corrupt (_l2_auto_out_3_c_bits_corrupt), // @[Configs.scala:93:24] .auto_in_3_d_ready (_l2_auto_out_3_d_ready), // @[Configs.scala:93:24] .auto_in_3_d_valid (_cork_auto_in_3_d_valid), .auto_in_3_d_bits_opcode (_cork_auto_in_3_d_bits_opcode), .auto_in_3_d_bits_param (_cork_auto_in_3_d_bits_param), .auto_in_3_d_bits_size (_cork_auto_in_3_d_bits_size), .auto_in_3_d_bits_source (_cork_auto_in_3_d_bits_source), .auto_in_3_d_bits_sink (_cork_auto_in_3_d_bits_sink), .auto_in_3_d_bits_denied (_cork_auto_in_3_d_bits_denied), .auto_in_3_d_bits_data (_cork_auto_in_3_d_bits_data), .auto_in_3_d_bits_corrupt (_cork_auto_in_3_d_bits_corrupt), .auto_in_3_e_valid (_l2_auto_out_3_e_valid), // @[Configs.scala:93:24] .auto_in_3_e_bits_sink (_l2_auto_out_3_e_bits_sink), // @[Configs.scala:93:24] .auto_in_2_a_ready (_cork_auto_in_2_a_ready), .auto_in_2_a_valid (_l2_auto_out_2_a_valid), // @[Configs.scala:93:24] .auto_in_2_a_bits_opcode (_l2_auto_out_2_a_bits_opcode), // @[Configs.scala:93:24] .auto_in_2_a_bits_param (_l2_auto_out_2_a_bits_param), // @[Configs.scala:93:24] .auto_in_2_a_bits_size (_l2_auto_out_2_a_bits_size), // @[Configs.scala:93:24] .auto_in_2_a_bits_source (_l2_auto_out_2_a_bits_source), // @[Configs.scala:93:24] .auto_in_2_a_bits_address (_l2_auto_out_2_a_bits_address), // @[Configs.scala:93:24] .auto_in_2_a_bits_mask (_l2_auto_out_2_a_bits_mask), // @[Configs.scala:93:24] .auto_in_2_a_bits_data (_l2_auto_out_2_a_bits_data), // @[Configs.scala:93:24] .auto_in_2_a_bits_corrupt (_l2_auto_out_2_a_bits_corrupt), // @[Configs.scala:93:24] .auto_in_2_c_ready (_cork_auto_in_2_c_ready), .auto_in_2_c_valid (_l2_auto_out_2_c_valid), // @[Configs.scala:93:24] .auto_in_2_c_bits_opcode (_l2_auto_out_2_c_bits_opcode), // @[Configs.scala:93:24] .auto_in_2_c_bits_param (_l2_auto_out_2_c_bits_param), // @[Configs.scala:93:24] .auto_in_2_c_bits_size (_l2_auto_out_2_c_bits_size), // @[Configs.scala:93:24] .auto_in_2_c_bits_source (_l2_auto_out_2_c_bits_source), // @[Configs.scala:93:24] .auto_in_2_c_bits_address (_l2_auto_out_2_c_bits_address), // @[Configs.scala:93:24] .auto_in_2_c_bits_data (_l2_auto_out_2_c_bits_data), // @[Configs.scala:93:24] .auto_in_2_c_bits_corrupt (_l2_auto_out_2_c_bits_corrupt), // @[Configs.scala:93:24] .auto_in_2_d_ready (_l2_auto_out_2_d_ready), // @[Configs.scala:93:24] .auto_in_2_d_valid (_cork_auto_in_2_d_valid), .auto_in_2_d_bits_opcode (_cork_auto_in_2_d_bits_opcode), .auto_in_2_d_bits_param (_cork_auto_in_2_d_bits_param), .auto_in_2_d_bits_size (_cork_auto_in_2_d_bits_size), .auto_in_2_d_bits_source (_cork_auto_in_2_d_bits_source), .auto_in_2_d_bits_sink (_cork_auto_in_2_d_bits_sink), .auto_in_2_d_bits_denied (_cork_auto_in_2_d_bits_denied), .auto_in_2_d_bits_data (_cork_auto_in_2_d_bits_data), .auto_in_2_d_bits_corrupt (_cork_auto_in_2_d_bits_corrupt), .auto_in_2_e_valid (_l2_auto_out_2_e_valid), // @[Configs.scala:93:24] .auto_in_2_e_bits_sink (_l2_auto_out_2_e_bits_sink), // @[Configs.scala:93:24] .auto_in_1_a_ready (_cork_auto_in_1_a_ready), .auto_in_1_a_valid (_l2_auto_out_1_a_valid), // @[Configs.scala:93:24] .auto_in_1_a_bits_opcode (_l2_auto_out_1_a_bits_opcode), // @[Configs.scala:93:24] .auto_in_1_a_bits_param (_l2_auto_out_1_a_bits_param), // @[Configs.scala:93:24] .auto_in_1_a_bits_size (_l2_auto_out_1_a_bits_size), // @[Configs.scala:93:24] .auto_in_1_a_bits_source (_l2_auto_out_1_a_bits_source), // @[Configs.scala:93:24] .auto_in_1_a_bits_address (_l2_auto_out_1_a_bits_address), // @[Configs.scala:93:24] .auto_in_1_a_bits_mask (_l2_auto_out_1_a_bits_mask), // @[Configs.scala:93:24] .auto_in_1_a_bits_data (_l2_auto_out_1_a_bits_data), // @[Configs.scala:93:24] .auto_in_1_a_bits_corrupt (_l2_auto_out_1_a_bits_corrupt), // @[Configs.scala:93:24] .auto_in_1_c_ready (_cork_auto_in_1_c_ready), .auto_in_1_c_valid (_l2_auto_out_1_c_valid), // @[Configs.scala:93:24] .auto_in_1_c_bits_opcode (_l2_auto_out_1_c_bits_opcode), // @[Configs.scala:93:24] .auto_in_1_c_bits_param (_l2_auto_out_1_c_bits_param), // @[Configs.scala:93:24] .auto_in_1_c_bits_size (_l2_auto_out_1_c_bits_size), // @[Configs.scala:93:24] .auto_in_1_c_bits_source (_l2_auto_out_1_c_bits_source), // @[Configs.scala:93:24] .auto_in_1_c_bits_address (_l2_auto_out_1_c_bits_address), // @[Configs.scala:93:24] .auto_in_1_c_bits_data (_l2_auto_out_1_c_bits_data), // @[Configs.scala:93:24] .auto_in_1_c_bits_corrupt (_l2_auto_out_1_c_bits_corrupt), // @[Configs.scala:93:24] .auto_in_1_d_ready (_l2_auto_out_1_d_ready), // @[Configs.scala:93:24] .auto_in_1_d_valid (_cork_auto_in_1_d_valid), .auto_in_1_d_bits_opcode (_cork_auto_in_1_d_bits_opcode), .auto_in_1_d_bits_param (_cork_auto_in_1_d_bits_param), .auto_in_1_d_bits_size (_cork_auto_in_1_d_bits_size), .auto_in_1_d_bits_source (_cork_auto_in_1_d_bits_source), .auto_in_1_d_bits_sink (_cork_auto_in_1_d_bits_sink), .auto_in_1_d_bits_denied (_cork_auto_in_1_d_bits_denied), .auto_in_1_d_bits_data (_cork_auto_in_1_d_bits_data), .auto_in_1_d_bits_corrupt (_cork_auto_in_1_d_bits_corrupt), .auto_in_1_e_valid (_l2_auto_out_1_e_valid), // @[Configs.scala:93:24] .auto_in_1_e_bits_sink (_l2_auto_out_1_e_bits_sink), // @[Configs.scala:93:24] .auto_in_0_a_ready (_cork_auto_in_0_a_ready), .auto_in_0_a_valid (_l2_auto_out_0_a_valid), // @[Configs.scala:93:24] .auto_in_0_a_bits_opcode (_l2_auto_out_0_a_bits_opcode), // @[Configs.scala:93:24] .auto_in_0_a_bits_param (_l2_auto_out_0_a_bits_param), // @[Configs.scala:93:24] .auto_in_0_a_bits_size (_l2_auto_out_0_a_bits_size), // @[Configs.scala:93:24] .auto_in_0_a_bits_source (_l2_auto_out_0_a_bits_source), // @[Configs.scala:93:24] .auto_in_0_a_bits_address (_l2_auto_out_0_a_bits_address), // @[Configs.scala:93:24] .auto_in_0_a_bits_mask (_l2_auto_out_0_a_bits_mask), // @[Configs.scala:93:24] .auto_in_0_a_bits_data (_l2_auto_out_0_a_bits_data), // @[Configs.scala:93:24] .auto_in_0_a_bits_corrupt (_l2_auto_out_0_a_bits_corrupt), // @[Configs.scala:93:24] .auto_in_0_c_ready (_cork_auto_in_0_c_ready), .auto_in_0_c_valid (_l2_auto_out_0_c_valid), // @[Configs.scala:93:24] .auto_in_0_c_bits_opcode (_l2_auto_out_0_c_bits_opcode), // @[Configs.scala:93:24] .auto_in_0_c_bits_param (_l2_auto_out_0_c_bits_param), // @[Configs.scala:93:24] .auto_in_0_c_bits_size (_l2_auto_out_0_c_bits_size), // @[Configs.scala:93:24] .auto_in_0_c_bits_source (_l2_auto_out_0_c_bits_source), // @[Configs.scala:93:24] .auto_in_0_c_bits_address (_l2_auto_out_0_c_bits_address), // @[Configs.scala:93:24] .auto_in_0_c_bits_data (_l2_auto_out_0_c_bits_data), // @[Configs.scala:93:24] .auto_in_0_c_bits_corrupt (_l2_auto_out_0_c_bits_corrupt), // @[Configs.scala:93:24] .auto_in_0_d_ready (_l2_auto_out_0_d_ready), // @[Configs.scala:93:24] .auto_in_0_d_valid (_cork_auto_in_0_d_valid), .auto_in_0_d_bits_opcode (_cork_auto_in_0_d_bits_opcode), .auto_in_0_d_bits_param (_cork_auto_in_0_d_bits_param), .auto_in_0_d_bits_size (_cork_auto_in_0_d_bits_size), .auto_in_0_d_bits_source (_cork_auto_in_0_d_bits_source), .auto_in_0_d_bits_sink (_cork_auto_in_0_d_bits_sink), .auto_in_0_d_bits_denied (_cork_auto_in_0_d_bits_denied), .auto_in_0_d_bits_data (_cork_auto_in_0_d_bits_data), .auto_in_0_d_bits_corrupt (_cork_auto_in_0_d_bits_corrupt), .auto_in_0_e_valid (_l2_auto_out_0_e_valid), // @[Configs.scala:93:24] .auto_in_0_e_bits_sink (_l2_auto_out_0_e_bits_sink), // @[Configs.scala:93:24] .auto_out_3_a_ready (_binder_auto_in_3_a_ready), // @[BankBinder.scala:71:28] .auto_out_3_a_valid (_cork_auto_out_3_a_valid), .auto_out_3_a_bits_opcode (_cork_auto_out_3_a_bits_opcode), .auto_out_3_a_bits_param (_cork_auto_out_3_a_bits_param), .auto_out_3_a_bits_size (_cork_auto_out_3_a_bits_size), .auto_out_3_a_bits_source (_cork_auto_out_3_a_bits_source), .auto_out_3_a_bits_address (_cork_auto_out_3_a_bits_address), .auto_out_3_a_bits_mask (_cork_auto_out_3_a_bits_mask), .auto_out_3_a_bits_data (_cork_auto_out_3_a_bits_data), .auto_out_3_a_bits_corrupt (_cork_auto_out_3_a_bits_corrupt), .auto_out_3_d_ready (_cork_auto_out_3_d_ready), .auto_out_3_d_valid (_binder_auto_in_3_d_valid), // @[BankBinder.scala:71:28] .auto_out_3_d_bits_opcode (_binder_auto_in_3_d_bits_opcode), // @[BankBinder.scala:71:28] .auto_out_3_d_bits_param (_binder_auto_in_3_d_bits_param), // @[BankBinder.scala:71:28] .auto_out_3_d_bits_size (_binder_auto_in_3_d_bits_size), // @[BankBinder.scala:71:28] .auto_out_3_d_bits_source (_binder_auto_in_3_d_bits_source), // @[BankBinder.scala:71:28] .auto_out_3_d_bits_denied (_binder_auto_in_3_d_bits_denied), // @[BankBinder.scala:71:28] .auto_out_3_d_bits_data (_binder_auto_in_3_d_bits_data), // @[BankBinder.scala:71:28] .auto_out_3_d_bits_corrupt (_binder_auto_in_3_d_bits_corrupt), // @[BankBinder.scala:71:28] .auto_out_2_a_ready (_binder_auto_in_2_a_ready), // @[BankBinder.scala:71:28] .auto_out_2_a_valid (_cork_auto_out_2_a_valid), .auto_out_2_a_bits_opcode (_cork_auto_out_2_a_bits_opcode), .auto_out_2_a_bits_param (_cork_auto_out_2_a_bits_param), .auto_out_2_a_bits_size (_cork_auto_out_2_a_bits_size), .auto_out_2_a_bits_source (_cork_auto_out_2_a_bits_source), .auto_out_2_a_bits_address (_cork_auto_out_2_a_bits_address), .auto_out_2_a_bits_mask (_cork_auto_out_2_a_bits_mask), .auto_out_2_a_bits_data (_cork_auto_out_2_a_bits_data), .auto_out_2_a_bits_corrupt (_cork_auto_out_2_a_bits_corrupt), .auto_out_2_d_ready (_cork_auto_out_2_d_ready), .auto_out_2_d_valid (_binder_auto_in_2_d_valid), // @[BankBinder.scala:71:28] .auto_out_2_d_bits_opcode (_binder_auto_in_2_d_bits_opcode), // @[BankBinder.scala:71:28] .auto_out_2_d_bits_param (_binder_auto_in_2_d_bits_param), // @[BankBinder.scala:71:28] .auto_out_2_d_bits_size (_binder_auto_in_2_d_bits_size), // @[BankBinder.scala:71:28] .auto_out_2_d_bits_source (_binder_auto_in_2_d_bits_source), // @[BankBinder.scala:71:28] .auto_out_2_d_bits_denied (_binder_auto_in_2_d_bits_denied), // @[BankBinder.scala:71:28] .auto_out_2_d_bits_data (_binder_auto_in_2_d_bits_data), // @[BankBinder.scala:71:28] .auto_out_2_d_bits_corrupt (_binder_auto_in_2_d_bits_corrupt), // @[BankBinder.scala:71:28] .auto_out_1_a_ready (_binder_auto_in_1_a_ready), // @[BankBinder.scala:71:28] .auto_out_1_a_valid (_cork_auto_out_1_a_valid), .auto_out_1_a_bits_opcode (_cork_auto_out_1_a_bits_opcode), .auto_out_1_a_bits_param (_cork_auto_out_1_a_bits_param), .auto_out_1_a_bits_size (_cork_auto_out_1_a_bits_size), .auto_out_1_a_bits_source (_cork_auto_out_1_a_bits_source), .auto_out_1_a_bits_address (_cork_auto_out_1_a_bits_address), .auto_out_1_a_bits_mask (_cork_auto_out_1_a_bits_mask), .auto_out_1_a_bits_data (_cork_auto_out_1_a_bits_data), .auto_out_1_a_bits_corrupt (_cork_auto_out_1_a_bits_corrupt), .auto_out_1_d_ready (_cork_auto_out_1_d_ready), .auto_out_1_d_valid (_binder_auto_in_1_d_valid), // @[BankBinder.scala:71:28] .auto_out_1_d_bits_opcode (_binder_auto_in_1_d_bits_opcode), // @[BankBinder.scala:71:28] .auto_out_1_d_bits_param (_binder_auto_in_1_d_bits_param), // @[BankBinder.scala:71:28] .auto_out_1_d_bits_size (_binder_auto_in_1_d_bits_size), // @[BankBinder.scala:71:28] .auto_out_1_d_bits_source (_binder_auto_in_1_d_bits_source), // @[BankBinder.scala:71:28] .auto_out_1_d_bits_denied (_binder_auto_in_1_d_bits_denied), // @[BankBinder.scala:71:28] .auto_out_1_d_bits_data (_binder_auto_in_1_d_bits_data), // @[BankBinder.scala:71:28] .auto_out_1_d_bits_corrupt (_binder_auto_in_1_d_bits_corrupt), // @[BankBinder.scala:71:28] .auto_out_0_a_ready (_binder_auto_in_0_a_ready), // @[BankBinder.scala:71:28] .auto_out_0_a_valid (_cork_auto_out_0_a_valid), .auto_out_0_a_bits_opcode (_cork_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param (_cork_auto_out_0_a_bits_param), .auto_out_0_a_bits_size (_cork_auto_out_0_a_bits_size), .auto_out_0_a_bits_source (_cork_auto_out_0_a_bits_source), .auto_out_0_a_bits_address (_cork_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask (_cork_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data (_cork_auto_out_0_a_bits_data), .auto_out_0_a_bits_corrupt (_cork_auto_out_0_a_bits_corrupt), .auto_out_0_d_ready (_cork_auto_out_0_d_ready), .auto_out_0_d_valid (_binder_auto_in_0_d_valid), // @[BankBinder.scala:71:28] .auto_out_0_d_bits_opcode (_binder_auto_in_0_d_bits_opcode), // @[BankBinder.scala:71:28] .auto_out_0_d_bits_param (_binder_auto_in_0_d_bits_param), // @[BankBinder.scala:71:28] .auto_out_0_d_bits_size (_binder_auto_in_0_d_bits_size), // @[BankBinder.scala:71:28] .auto_out_0_d_bits_source (_binder_auto_in_0_d_bits_source), // @[BankBinder.scala:71:28] .auto_out_0_d_bits_denied (_binder_auto_in_0_d_bits_denied), // @[BankBinder.scala:71:28] .auto_out_0_d_bits_data (_binder_auto_in_0_d_bits_data), // @[BankBinder.scala:71:28] .auto_out_0_d_bits_corrupt (_binder_auto_in_0_d_bits_corrupt) // @[BankBinder.scala:71:28] ); // @[Configs.scala:120:26] BankBinder binder ( // @[BankBinder.scala:71:28] .clock (auto_coh_clock_groups_in_member_coh_0_clock), .reset (auto_coh_clock_groups_in_member_coh_0_reset), .auto_in_3_a_ready (_binder_auto_in_3_a_ready), .auto_in_3_a_valid (_cork_auto_out_3_a_valid), // @[Configs.scala:120:26] .auto_in_3_a_bits_opcode (_cork_auto_out_3_a_bits_opcode), // @[Configs.scala:120:26] .auto_in_3_a_bits_param (_cork_auto_out_3_a_bits_param), // @[Configs.scala:120:26] .auto_in_3_a_bits_size (_cork_auto_out_3_a_bits_size), // @[Configs.scala:120:26] .auto_in_3_a_bits_source (_cork_auto_out_3_a_bits_source), // @[Configs.scala:120:26] .auto_in_3_a_bits_address (_cork_auto_out_3_a_bits_address), // @[Configs.scala:120:26] .auto_in_3_a_bits_mask (_cork_auto_out_3_a_bits_mask), // @[Configs.scala:120:26] .auto_in_3_a_bits_data (_cork_auto_out_3_a_bits_data), // @[Configs.scala:120:26] .auto_in_3_a_bits_corrupt (_cork_auto_out_3_a_bits_corrupt), // @[Configs.scala:120:26] .auto_in_3_d_ready (_cork_auto_out_3_d_ready), // @[Configs.scala:120:26] .auto_in_3_d_valid (_binder_auto_in_3_d_valid), .auto_in_3_d_bits_opcode (_binder_auto_in_3_d_bits_opcode), .auto_in_3_d_bits_param (_binder_auto_in_3_d_bits_param), .auto_in_3_d_bits_size (_binder_auto_in_3_d_bits_size), .auto_in_3_d_bits_source (_binder_auto_in_3_d_bits_source), .auto_in_3_d_bits_denied (_binder_auto_in_3_d_bits_denied), .auto_in_3_d_bits_data (_binder_auto_in_3_d_bits_data), .auto_in_3_d_bits_corrupt (_binder_auto_in_3_d_bits_corrupt), .auto_in_2_a_ready (_binder_auto_in_2_a_ready), .auto_in_2_a_valid (_cork_auto_out_2_a_valid), // @[Configs.scala:120:26] .auto_in_2_a_bits_opcode (_cork_auto_out_2_a_bits_opcode), // @[Configs.scala:120:26] .auto_in_2_a_bits_param (_cork_auto_out_2_a_bits_param), // @[Configs.scala:120:26] .auto_in_2_a_bits_size (_cork_auto_out_2_a_bits_size), // @[Configs.scala:120:26] .auto_in_2_a_bits_source (_cork_auto_out_2_a_bits_source), // @[Configs.scala:120:26] .auto_in_2_a_bits_address (_cork_auto_out_2_a_bits_address), // @[Configs.scala:120:26] .auto_in_2_a_bits_mask (_cork_auto_out_2_a_bits_mask), // @[Configs.scala:120:26] .auto_in_2_a_bits_data (_cork_auto_out_2_a_bits_data), // @[Configs.scala:120:26] .auto_in_2_a_bits_corrupt (_cork_auto_out_2_a_bits_corrupt), // @[Configs.scala:120:26] .auto_in_2_d_ready (_cork_auto_out_2_d_ready), // @[Configs.scala:120:26] .auto_in_2_d_valid (_binder_auto_in_2_d_valid), .auto_in_2_d_bits_opcode (_binder_auto_in_2_d_bits_opcode), .auto_in_2_d_bits_param (_binder_auto_in_2_d_bits_param), .auto_in_2_d_bits_size (_binder_auto_in_2_d_bits_size), .auto_in_2_d_bits_source (_binder_auto_in_2_d_bits_source), .auto_in_2_d_bits_denied (_binder_auto_in_2_d_bits_denied), .auto_in_2_d_bits_data (_binder_auto_in_2_d_bits_data), .auto_in_2_d_bits_corrupt (_binder_auto_in_2_d_bits_corrupt), .auto_in_1_a_ready (_binder_auto_in_1_a_ready), .auto_in_1_a_valid (_cork_auto_out_1_a_valid), // @[Configs.scala:120:26] .auto_in_1_a_bits_opcode (_cork_auto_out_1_a_bits_opcode), // @[Configs.scala:120:26] .auto_in_1_a_bits_param (_cork_auto_out_1_a_bits_param), // @[Configs.scala:120:26] .auto_in_1_a_bits_size (_cork_auto_out_1_a_bits_size), // @[Configs.scala:120:26] .auto_in_1_a_bits_source (_cork_auto_out_1_a_bits_source), // @[Configs.scala:120:26] .auto_in_1_a_bits_address (_cork_auto_out_1_a_bits_address), // @[Configs.scala:120:26] .auto_in_1_a_bits_mask (_cork_auto_out_1_a_bits_mask), // @[Configs.scala:120:26] .auto_in_1_a_bits_data (_cork_auto_out_1_a_bits_data), // @[Configs.scala:120:26] .auto_in_1_a_bits_corrupt (_cork_auto_out_1_a_bits_corrupt), // @[Configs.scala:120:26] .auto_in_1_d_ready (_cork_auto_out_1_d_ready), // @[Configs.scala:120:26] .auto_in_1_d_valid (_binder_auto_in_1_d_valid), .auto_in_1_d_bits_opcode (_binder_auto_in_1_d_bits_opcode), .auto_in_1_d_bits_param (_binder_auto_in_1_d_bits_param), .auto_in_1_d_bits_size (_binder_auto_in_1_d_bits_size), .auto_in_1_d_bits_source (_binder_auto_in_1_d_bits_source), .auto_in_1_d_bits_denied (_binder_auto_in_1_d_bits_denied), .auto_in_1_d_bits_data (_binder_auto_in_1_d_bits_data), .auto_in_1_d_bits_corrupt (_binder_auto_in_1_d_bits_corrupt), .auto_in_0_a_ready (_binder_auto_in_0_a_ready), .auto_in_0_a_valid (_cork_auto_out_0_a_valid), // @[Configs.scala:120:26] .auto_in_0_a_bits_opcode (_cork_auto_out_0_a_bits_opcode), // @[Configs.scala:120:26] .auto_in_0_a_bits_param (_cork_auto_out_0_a_bits_param), // @[Configs.scala:120:26] .auto_in_0_a_bits_size (_cork_auto_out_0_a_bits_size), // @[Configs.scala:120:26] .auto_in_0_a_bits_source (_cork_auto_out_0_a_bits_source), // @[Configs.scala:120:26] .auto_in_0_a_bits_address (_cork_auto_out_0_a_bits_address), // @[Configs.scala:120:26] .auto_in_0_a_bits_mask (_cork_auto_out_0_a_bits_mask), // @[Configs.scala:120:26] .auto_in_0_a_bits_data (_cork_auto_out_0_a_bits_data), // @[Configs.scala:120:26] .auto_in_0_a_bits_corrupt (_cork_auto_out_0_a_bits_corrupt), // @[Configs.scala:120:26] .auto_in_0_d_ready (_cork_auto_out_0_d_ready), // @[Configs.scala:120:26] .auto_in_0_d_valid (_binder_auto_in_0_d_valid), .auto_in_0_d_bits_opcode (_binder_auto_in_0_d_bits_opcode), .auto_in_0_d_bits_param (_binder_auto_in_0_d_bits_param), .auto_in_0_d_bits_size (_binder_auto_in_0_d_bits_size), .auto_in_0_d_bits_source (_binder_auto_in_0_d_bits_source), .auto_in_0_d_bits_denied (_binder_auto_in_0_d_bits_denied), .auto_in_0_d_bits_data (_binder_auto_in_0_d_bits_data), .auto_in_0_d_bits_corrupt (_binder_auto_in_0_d_bits_corrupt), .auto_out_3_a_ready (auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_ready), .auto_out_3_a_valid (auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_valid), .auto_out_3_a_bits_opcode (auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_opcode), .auto_out_3_a_bits_param (auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_param), .auto_out_3_a_bits_size (auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_size), .auto_out_3_a_bits_source (auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_source), .auto_out_3_a_bits_address (auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_address), .auto_out_3_a_bits_mask (auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_mask), .auto_out_3_a_bits_data (auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_data), .auto_out_3_a_bits_corrupt (auto_coupler_to_bus_named_mbus_bus_xing_out_3_a_bits_corrupt), .auto_out_3_d_ready (auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_ready), .auto_out_3_d_valid (auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_valid), .auto_out_3_d_bits_opcode (auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_opcode), .auto_out_3_d_bits_param (auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_param), .auto_out_3_d_bits_size (auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_size), .auto_out_3_d_bits_source (auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_source), .auto_out_3_d_bits_sink (auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_sink), .auto_out_3_d_bits_denied (auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_denied), .auto_out_3_d_bits_data (auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_data), .auto_out_3_d_bits_corrupt (auto_coupler_to_bus_named_mbus_bus_xing_out_3_d_bits_corrupt), .auto_out_2_a_ready (auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_ready), .auto_out_2_a_valid (auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_valid), .auto_out_2_a_bits_opcode (auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_opcode), .auto_out_2_a_bits_param (auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_param), .auto_out_2_a_bits_size (auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_size), .auto_out_2_a_bits_source (auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_source), .auto_out_2_a_bits_address (auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_address), .auto_out_2_a_bits_mask (auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_mask), .auto_out_2_a_bits_data (auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_data), .auto_out_2_a_bits_corrupt (auto_coupler_to_bus_named_mbus_bus_xing_out_2_a_bits_corrupt), .auto_out_2_d_ready (auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_ready), .auto_out_2_d_valid (auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_valid), .auto_out_2_d_bits_opcode (auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_opcode), .auto_out_2_d_bits_param (auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_param), .auto_out_2_d_bits_size (auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_size), .auto_out_2_d_bits_source (auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_source), .auto_out_2_d_bits_sink (auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_sink), .auto_out_2_d_bits_denied (auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_denied), .auto_out_2_d_bits_data (auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_data), .auto_out_2_d_bits_corrupt (auto_coupler_to_bus_named_mbus_bus_xing_out_2_d_bits_corrupt), .auto_out_1_a_ready (auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_ready), .auto_out_1_a_valid (auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_valid), .auto_out_1_a_bits_opcode (auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_opcode), .auto_out_1_a_bits_param (auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_param), .auto_out_1_a_bits_size (auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_size), .auto_out_1_a_bits_source (auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_source), .auto_out_1_a_bits_address (auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_address), .auto_out_1_a_bits_mask (auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_mask), .auto_out_1_a_bits_data (auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_data), .auto_out_1_a_bits_corrupt (auto_coupler_to_bus_named_mbus_bus_xing_out_1_a_bits_corrupt), .auto_out_1_d_ready (auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_ready), .auto_out_1_d_valid (auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_valid), .auto_out_1_d_bits_opcode (auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_opcode), .auto_out_1_d_bits_param (auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_param), .auto_out_1_d_bits_size (auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_size), .auto_out_1_d_bits_source (auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_source), .auto_out_1_d_bits_sink (auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_sink), .auto_out_1_d_bits_denied (auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_denied), .auto_out_1_d_bits_data (auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_data), .auto_out_1_d_bits_corrupt (auto_coupler_to_bus_named_mbus_bus_xing_out_1_d_bits_corrupt), .auto_out_0_a_ready (auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_ready), .auto_out_0_a_valid (auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_valid), .auto_out_0_a_bits_opcode (auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_opcode), .auto_out_0_a_bits_param (auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_param), .auto_out_0_a_bits_size (auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_size), .auto_out_0_a_bits_source (auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_source), .auto_out_0_a_bits_address (auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_address), .auto_out_0_a_bits_mask (auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_mask), .auto_out_0_a_bits_data (auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_data), .auto_out_0_a_bits_corrupt (auto_coupler_to_bus_named_mbus_bus_xing_out_0_a_bits_corrupt), .auto_out_0_d_ready (auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_ready), .auto_out_0_d_valid (auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_valid), .auto_out_0_d_bits_opcode (auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_opcode), .auto_out_0_d_bits_param (auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_param), .auto_out_0_d_bits_size (auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_size), .auto_out_0_d_bits_source (auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_source), .auto_out_0_d_bits_sink (auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_sink), .auto_out_0_d_bits_denied (auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_denied), .auto_out_0_d_bits_data (auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_data), .auto_out_0_d_bits_corrupt (auto_coupler_to_bus_named_mbus_bus_xing_out_0_d_bits_corrupt) ); // @[BankBinder.scala:71:28] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_89 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RecFNToRecFN_89( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BreakpointUnit_3 : input clock : Clock input reset : Reset output io : { flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip pc : UInt<39>, flip ea : UInt<39>, flip mcontext : UInt<0>, flip scontext : UInt<0>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[0]} connect io.xcpt_if, UInt<1>(0h0) connect io.xcpt_ld, UInt<1>(0h0) connect io.xcpt_st, UInt<1>(0h0) connect io.debug_if, UInt<1>(0h0) connect io.debug_ld, UInt<1>(0h0) connect io.debug_st, UInt<1>(0h0)	module BreakpointUnit_3( // @[Breakpoint.scala:79:7] input clock, // @[Breakpoint.scala:79:7] input reset, // @[Breakpoint.scala:79:7] input io_status_debug, // @[Breakpoint.scala:80:14] input io_status_cease, // @[Breakpoint.scala:80:14] input io_status_wfi, // @[Breakpoint.scala:80:14] input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14] input io_status_dv, // @[Breakpoint.scala:80:14] input [1:0] io_status_prv, // @[Breakpoint.scala:80:14] input io_status_v, // @[Breakpoint.scala:80:14] input io_status_sd, // @[Breakpoint.scala:80:14] input io_status_mpv, // @[Breakpoint.scala:80:14] input io_status_gva, // @[Breakpoint.scala:80:14] input io_status_tsr, // @[Breakpoint.scala:80:14] input io_status_tw, // @[Breakpoint.scala:80:14] input io_status_tvm, // @[Breakpoint.scala:80:14] input io_status_mxr, // @[Breakpoint.scala:80:14] input io_status_sum, // @[Breakpoint.scala:80:14] input io_status_mprv, // @[Breakpoint.scala:80:14] input [1:0] io_status_fs, // @[Breakpoint.scala:80:14] input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14] input io_status_spp, // @[Breakpoint.scala:80:14] input io_status_mpie, // @[Breakpoint.scala:80:14] input io_status_spie, // @[Breakpoint.scala:80:14] input io_status_mie, // @[Breakpoint.scala:80:14] input io_status_sie, // @[Breakpoint.scala:80:14] input [38:0] io_pc // @[Breakpoint.scala:80:14] ); wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7] wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7] wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7] wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7] wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7] wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7] wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7] wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7] wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7] wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7] wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7] wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7] wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7] wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7] wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7] wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7] wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7] wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7] wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7] wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7] wire [38:0] io_ea = 39'h0; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14] wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14] wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14] wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7] wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7] wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7] wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7] wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7] wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7] wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7] wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7] wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14] wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c_3 : input clock : Clock input reset : Reset output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate anonIn.e.bits.sink invalidate anonIn.e.valid invalidate anonIn.e.ready invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.c.bits.corrupt invalidate anonIn.c.bits.data invalidate anonIn.c.bits.address invalidate anonIn.c.bits.source invalidate anonIn.c.bits.size invalidate anonIn.c.bits.param invalidate anonIn.c.bits.opcode invalidate anonIn.c.valid invalidate anonIn.c.ready invalidate anonIn.b.bits.corrupt invalidate anonIn.b.bits.data invalidate anonIn.b.bits.mask invalidate anonIn.b.bits.address invalidate anonIn.b.bits.source invalidate anonIn.b.bits.size invalidate anonIn.b.bits.param invalidate anonIn.b.bits.opcode invalidate anonIn.b.valid invalidate anonIn.b.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready inst monitor of TLMonitor_52 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, anonIn.e.bits.sink connect monitor.io.in.e.valid, anonIn.e.valid connect monitor.io.in.e.ready, anonIn.e.ready connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.c.bits.corrupt, anonIn.c.bits.corrupt connect monitor.io.in.c.bits.data, anonIn.c.bits.data connect monitor.io.in.c.bits.address, anonIn.c.bits.address connect monitor.io.in.c.bits.source, anonIn.c.bits.source connect monitor.io.in.c.bits.size, anonIn.c.bits.size connect monitor.io.in.c.bits.param, anonIn.c.bits.param connect monitor.io.in.c.bits.opcode, anonIn.c.bits.opcode connect monitor.io.in.c.valid, anonIn.c.valid connect monitor.io.in.c.ready, anonIn.c.ready connect monitor.io.in.b.bits.corrupt, anonIn.b.bits.corrupt connect monitor.io.in.b.bits.data, anonIn.b.bits.data connect monitor.io.in.b.bits.mask, anonIn.b.bits.mask connect monitor.io.in.b.bits.address, anonIn.b.bits.address connect monitor.io.in.b.bits.source, anonIn.b.bits.source connect monitor.io.in.b.bits.size, anonIn.b.bits.size connect monitor.io.in.b.bits.param, anonIn.b.bits.param connect monitor.io.in.b.bits.opcode, anonIn.b.bits.opcode connect monitor.io.in.b.valid, anonIn.b.valid connect monitor.io.in.b.ready, anonIn.b.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_53 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate anonOut.e.bits.sink invalidate anonOut.e.valid invalidate anonOut.e.ready invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.c.bits.corrupt invalidate anonOut.c.bits.data invalidate anonOut.c.bits.address invalidate anonOut.c.bits.source invalidate anonOut.c.bits.size invalidate anonOut.c.bits.param invalidate anonOut.c.bits.opcode invalidate anonOut.c.valid invalidate anonOut.c.ready invalidate anonOut.b.bits.corrupt invalidate anonOut.b.bits.data invalidate anonOut.b.bits.mask invalidate anonOut.b.bits.address invalidate anonOut.b.bits.source invalidate anonOut.b.bits.size invalidate anonOut.b.bits.param invalidate anonOut.b.bits.opcode invalidate anonOut.b.valid invalidate anonOut.b.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2] connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) connect in[0].a.bits.source, _in_0_a_bits_source_T connect anonIn.b.bits.corrupt, in[0].b.bits.corrupt connect anonIn.b.bits.data, in[0].b.bits.data connect anonIn.b.bits.mask, in[0].b.bits.mask connect anonIn.b.bits.address, in[0].b.bits.address connect anonIn.b.bits.source, in[0].b.bits.source connect anonIn.b.bits.size, in[0].b.bits.size connect anonIn.b.bits.param, in[0].b.bits.param connect anonIn.b.bits.opcode, in[0].b.bits.opcode connect anonIn.b.valid, in[0].b.valid connect in[0].b.ready, anonIn.b.ready node _anonIn_b_bits_source_T = bits(in[0].b.bits.source, 0, 0) connect anonIn.b.bits.source, _anonIn_b_bits_source_T connect in[0].c.bits.corrupt, anonIn.c.bits.corrupt connect in[0].c.bits.data, anonIn.c.bits.data connect in[0].c.bits.address, anonIn.c.bits.address connect in[0].c.bits.source, anonIn.c.bits.source connect in[0].c.bits.size, anonIn.c.bits.size connect in[0].c.bits.param, anonIn.c.bits.param connect in[0].c.bits.opcode, anonIn.c.bits.opcode connect in[0].c.valid, anonIn.c.valid connect anonIn.c.ready, in[0].c.ready node _in_0_c_bits_source_T = or(anonIn.c.bits.source, UInt<1>(0h0)) connect in[0].c.bits.source, _in_0_c_bits_source_T connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 0, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T connect in[0].e.bits.sink, anonIn.e.bits.sink connect in[0].e.valid, anonIn.e.valid connect anonIn.e.ready, in[0].e.ready connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<2>(0h2)) connect in[1].a.bits.source, _in_1_a_bits_source_T invalidate in[1].b.bits.corrupt invalidate in[1].b.bits.data invalidate in[1].b.bits.mask invalidate in[1].b.bits.address invalidate in[1].b.bits.source invalidate in[1].b.bits.size invalidate in[1].b.bits.param invalidate in[1].b.bits.opcode invalidate in[1].b.valid invalidate in[1].b.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready connect in[1].b.ready, UInt<1>(0h1) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) invalidate in[1].c.bits.corrupt invalidate in[1].c.bits.data invalidate in[1].c.bits.address invalidate in[1].c.bits.source invalidate in[1].c.bits.size invalidate in[1].c.bits.param invalidate in[1].c.bits.opcode invalidate in[1].c.valid invalidate in[1].c.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<1>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<3>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready invalidate _WIRE_5.bits.corrupt invalidate _WIRE_5.bits.data invalidate _WIRE_5.bits.address invalidate _WIRE_5.bits.source invalidate _WIRE_5.bits.size invalidate _WIRE_5.bits.param invalidate _WIRE_5.bits.opcode invalidate _WIRE_5.valid invalidate _WIRE_5.ready connect in[1].c.valid, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready connect anonIn_1.d.bits.source, UInt<1>(0h0) invalidate in[1].e.bits.sink invalidate in[1].e.valid invalidate in[1].e.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_8.bits.sink, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.sink invalidate _WIRE_9.valid invalidate _WIRE_9.ready connect in[1].e.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[1] connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready connect out[0].b.bits.corrupt, anonOut.b.bits.corrupt connect out[0].b.bits.data, anonOut.b.bits.data connect out[0].b.bits.mask, anonOut.b.bits.mask connect out[0].b.bits.address, anonOut.b.bits.address connect out[0].b.bits.source, anonOut.b.bits.source connect out[0].b.bits.size, anonOut.b.bits.size connect out[0].b.bits.param, anonOut.b.bits.param connect out[0].b.bits.opcode, anonOut.b.bits.opcode connect out[0].b.valid, anonOut.b.valid connect anonOut.b.ready, out[0].b.ready connect anonOut.c.bits.corrupt, out[0].c.bits.corrupt connect anonOut.c.bits.data, out[0].c.bits.data connect anonOut.c.bits.address, out[0].c.bits.address connect anonOut.c.bits.source, out[0].c.bits.source connect anonOut.c.bits.size, out[0].c.bits.size connect anonOut.c.bits.param, out[0].c.bits.param connect anonOut.c.bits.opcode, out[0].c.bits.opcode connect anonOut.c.valid, out[0].c.valid connect out[0].c.ready, anonOut.c.ready connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T connect anonOut.e.bits.sink, out[0].e.bits.sink connect anonOut.e.valid, out[0].e.valid connect out[0].e.ready, anonOut.e.ready node _anonOut_e_bits_sink_T = bits(out[0].e.bits.sink, 2, 0) connect anonOut.e.bits.sink, _anonOut_e_bits_sink_T node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(in[1].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<1>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 0, 0) node _requestBOI_T = shr(out[0].b.bits.source, 1) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<1>(0h1)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) node requestBOI_0_1 = eq(out[0].b.bits.source, UInt<2>(0h2)) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<1>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 0, 0) node _requestDOI_T = shr(out[0].d.bits.source, 1) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<1>(0h1)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<2>(0h2)) node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0) node _requestEIO_T = shr(in[0].e.bits.sink, 3) node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7)) node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4) node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0) node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3) node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7)) node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9) node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0) node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0)) node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0) node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect in[0].a.ready, portsAOI_filtered[0].ready wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect in[1].a.ready, portsAOI_filtered_1[0].ready wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[0].bits.data, out[0].b.bits.data connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[0].bits.address, out[0].b.bits.address connect portsBIO_filtered[0].bits.source, out[0].b.bits.source connect portsBIO_filtered[0].bits.size, out[0].b.bits.size connect portsBIO_filtered[0].bits.param, out[0].b.bits.param connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[1].bits.data, out[0].b.bits.data connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[1].bits.address, out[0].b.bits.address connect portsBIO_filtered[1].bits.source, out[0].b.bits.source connect portsBIO_filtered[1].bits.size, out[0].b.bits.size connect portsBIO_filtered[1].bits.param, out[0].b.bits.param connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_2 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1) wire _portsBIO_out_0_b_ready_WIRE : UInt<1> connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_2 connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered[0].bits, in[0].c.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect in[0].c.ready, portsCOI_filtered[0].ready wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1] connect portsCOI_filtered_1[0].bits, in[1].c.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect in[1].c.ready, portsCOI_filtered_1[0].ready wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1] connect portsEOI_filtered[0].bits, in[0].e.bits node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect in[0].e.ready, portsEOI_filtered[0].ready wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[1] connect portsEOI_filtered_1[0].bits, in[1].e.bits node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1)) node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect in[1].e.ready, portsEOI_filtered_1[0].ready regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) node readys_valid = bits(_readys_T, 1, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) node _readys_unready_T_4 = shl(readys_mask, 2) node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) node _readys_readys_T = shr(readys_unready, 2) node _readys_readys_T_1 = bits(readys_unready, 1, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) connect readys_mask, _readys_mask_T_4 node _readys_T_7 = bits(readys_readys, 1, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = and(_T_2, _T_5) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_6, UInt<1>(0h1), "") : assert node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = or(winner[0], winner[1]) node _T_13 = or(_T_11, _T_12) node _T_14 = asUInt(reset) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : node _T_16 = eq(_T_13, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_13, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_4 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) wire _out_0_a_bits_WIRE_2 : UInt<64> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) wire _out_0_a_bits_WIRE_3 : UInt<8> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { } connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) wire _out_0_a_bits_WIRE_6 : UInt<32> connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) wire _out_0_a_bits_WIRE_7 : UInt<2> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) wire _out_0_a_bits_WIRE_8 : UInt<4> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) wire _out_0_a_bits_WIRE_9 : UInt<3> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_10 : UInt<3> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode connect out[0].c, portsCOI_filtered[0] connect out[0].e, portsEOI_filtered[0] connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) connect in[0].b, portsBIO_filtered[0] connect in[0].d, portsDIO_filtered[0] invalidate in[1].b.bits.corrupt invalidate in[1].b.bits.data invalidate in[1].b.bits.mask invalidate in[1].b.bits.address invalidate in[1].b.bits.source invalidate in[1].b.bits.size invalidate in[1].b.bits.param invalidate in[1].b.bits.opcode connect in[1].d, portsDIO_filtered[1] connect portsBIO_filtered[1].ready, UInt<1>(0h0)	module TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s2k3z4c_3( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_e_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire [2:0] out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [1:0] in_0_c_bits_source; // @[Xbar.scala:159:18] wire [1:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_ready_0 = auto_anon_in_0_b_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_valid_0 = auto_anon_in_0_c_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_opcode_0 = auto_anon_in_0_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_c_bits_param_0 = auto_anon_in_0_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_c_bits_size_0 = auto_anon_in_0_c_bits_size; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_bits_source_0 = auto_anon_in_0_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_c_bits_address_0 = auto_anon_in_0_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_c_bits_data_0 = auto_anon_in_0_c_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_valid_0 = auto_anon_in_0_e_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_e_bits_sink_0 = auto_anon_in_0_e_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_b_valid_0 = auto_anon_out_b_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_b_bits_opcode_0 = auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_b_bits_param_0 = auto_anon_out_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_b_bits_size_0 = auto_anon_out_b_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_b_bits_source_0 = auto_anon_out_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_b_bits_address_0 = auto_anon_out_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_b_bits_mask_0 = auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_b_bits_data_0 = auto_anon_out_b_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_b_bits_corrupt_0 = auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_c_ready_0 = auto_anon_out_c_ready; // @[Xbar.scala:74:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_e_ready_0 = auto_anon_out_e_ready; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire auto_anon_in_1_d_ready = 1'h1; // @[Xbar.scala:74:9] wire anonIn_1_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire in_1_b_ready = 1'h1; // @[Xbar.scala:159:18] wire in_1_d_ready = 1'h1; // @[Xbar.scala:159:18] wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _beatsAI_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire portsDIO_filtered_1_ready = 1'h1; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [2:0] auto_anon_in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_opcode = 3'h4; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_opcode = 3'h4; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_1_0_bits_opcode = 3'h4; // @[Xbar.scala:352:24] wire [2:0] auto_anon_in_1_a_bits_param = 3'h0; // @[Xbar.scala:74:9] wire [2:0] anonIn_1_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] in_1_a_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_b_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_opcode = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_c_bits_param = 3'h0; // @[Xbar.scala:159:18] wire [2:0] in_1_e_bits_sink = 3'h0; // @[Xbar.scala:159:18] wire [2:0] _requestEIO_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestEIO_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] portsAOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_1_0_bits_sink = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _out_0_a_bits_T_19 = 3'h0; // @[Mux.scala:30:73] wire [3:0] auto_anon_in_1_a_bits_size = 4'h6; // @[Xbar.scala:74:9] wire [3:0] anonIn_1_a_bits_size = 4'h6; // @[MixedNode.scala:551:17] wire [3:0] in_1_a_bits_size = 4'h6; // @[Xbar.scala:159:18] wire [3:0] portsAOI_filtered_1_0_bits_size = 4'h6; // @[Xbar.scala:352:24] wire auto_anon_in_1_a_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_valid = 1'h0; // @[Xbar.scala:159:18] wire in_1_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_ready = 1'h0; // @[Xbar.scala:159:18] wire in_1_e_valid = 1'h0; // @[Xbar.scala:159:18] wire out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10] wire beatsAI_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36] wire portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsAOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_out_0_b_ready_T_1 = 1'h0; // @[Mux.scala:30:73] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _out_0_a_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _out_0_a_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire [7:0] auto_anon_in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:74:9] wire [7:0] anonIn_1_a_bits_mask = 8'hFF; // @[MixedNode.scala:551:17] wire [7:0] in_1_a_bits_mask = 8'hFF; // @[Xbar.scala:159:18] wire [7:0] portsAOI_filtered_1_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24] wire [63:0] auto_anon_in_1_a_bits_data = 64'h0; // @[Xbar.scala:74:9] wire [63:0] anonIn_1_a_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] in_1_a_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_1_b_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] in_1_c_bits_data = 64'h0; // @[Xbar.scala:159:18] wire [63:0] portsAOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _out_0_a_bits_T_4 = 64'h0; // @[Mux.scala:30:73] wire [8:0] beatsAI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59] wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] maskedBeats_1 = 9'h0; // @[Arbiter.scala:82:69] wire [31:0] in_1_b_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] in_1_c_bits_address = 32'h0; // @[Xbar.scala:159:18] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [1:0] in_1_b_bits_param = 2'h0; // @[Xbar.scala:159:18] wire [1:0] in_1_b_bits_source = 2'h0; // @[Xbar.scala:159:18] wire [1:0] in_1_c_bits_source = 2'h0; // @[Xbar.scala:159:18] wire [1:0] portsCOI_filtered_1_0_bits_source = 2'h0; // @[Xbar.scala:352:24] wire [3:0] in_1_b_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] in_1_c_bits_size = 4'h0; // @[Xbar.scala:159:18] wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24] wire [1:0] in_1_a_bits_source = 2'h2; // @[Xbar.scala:159:18] wire [1:0] _in_1_a_bits_source_T = 2'h2; // @[Xbar.scala:166:55] wire [1:0] portsAOI_filtered_1_0_bits_source = 2'h2; // @[Xbar.scala:352:24] wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46] wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71] wire [8:0] beatsAI_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] _beatsAI_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _beatsAI_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _beatsAI_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire [7:0] in_1_b_bits_mask = 8'h0; // @[Xbar.scala:159:18] wire anonIn_1_a_ready; // @[MixedNode.scala:551:17] wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9] wire anonIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_b_ready = auto_anon_in_0_b_ready_0; // @[Xbar.scala:74:9] wire anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_c_ready; // @[MixedNode.scala:551:17] wire anonIn_c_valid = auto_anon_in_0_c_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_opcode = auto_anon_in_0_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_c_bits_param = auto_anon_in_0_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonIn_c_bits_size = auto_anon_in_0_c_bits_size_0; // @[Xbar.scala:74:9] wire anonIn_c_bits_source = auto_anon_in_0_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_c_bits_address = auto_anon_in_0_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_c_bits_data = auto_anon_in_0_c_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonIn_e_ready; // @[MixedNode.scala:551:17] wire anonIn_e_valid = auto_anon_in_0_e_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_e_bits_sink = auto_anon_in_0_e_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_b_ready; // @[MixedNode.scala:542:17] wire anonOut_b_valid = auto_anon_out_b_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_b_bits_opcode = auto_anon_out_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_b_bits_param = auto_anon_out_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_b_bits_size = auto_anon_out_b_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_b_bits_source = auto_anon_out_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonOut_b_bits_address = auto_anon_out_b_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonOut_b_bits_mask = auto_anon_out_b_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_b_bits_data = auto_anon_out_b_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_b_bits_corrupt = auto_anon_out_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_c_ready = auto_anon_out_c_ready_0; // @[Xbar.scala:74:9] wire anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_e_ready = auto_anon_out_e_ready_0; // @[Xbar.scala:74:9] wire anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_b_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_b_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_b_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_0_b_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_0_b_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_b_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_b_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_c_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9] wire auto_anon_in_0_e_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_b_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_c_bits_param_0; // @[Xbar.scala:74:9] wire [3:0] auto_anon_out_c_bits_size_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_c_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_c_bits_address_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_c_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_c_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_e_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_out_e_valid_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_b_ready = anonIn_b_ready; // @[Xbar.scala:159:18] wire in_0_b_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_valid_0 = anonIn_b_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_b_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_opcode_0 = anonIn_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_b_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_param_0 = anonIn_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_b_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_size_0 = anonIn_b_bits_size; // @[Xbar.scala:74:9] wire _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_b_bits_source_0 = anonIn_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] in_0_b_bits_address; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_address_0 = anonIn_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] in_0_b_bits_mask; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_mask_0 = anonIn_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] in_0_b_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_data_0 = anonIn_b_bits_data; // @[Xbar.scala:74:9] wire in_0_b_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_b_bits_corrupt_0 = anonIn_b_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_c_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_c_ready_0 = anonIn_c_ready; // @[Xbar.scala:74:9] wire in_0_c_valid = anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_opcode = anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_c_bits_param = anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] in_0_c_bits_size = anonIn_c_bits_size; // @[Xbar.scala:159:18] wire _in_0_c_bits_source_T = anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] in_0_c_bits_address = anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [63:0] in_0_c_bits_data = anonIn_c_bits_data; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire in_0_e_ready; // @[Xbar.scala:159:18] assign auto_anon_in_0_e_ready_0 = anonIn_e_ready; // @[Xbar.scala:74:9] wire in_0_e_valid = anonIn_e_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_e_bits_sink = anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire in_1_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9] wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18] wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18] wire in_1_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] in_1_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9] wire in_1_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9] wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [1:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_b_ready; // @[Xbar.scala:216:19] assign auto_anon_out_b_ready_0 = anonOut_b_ready; // @[Xbar.scala:74:9] wire out_0_b_valid = anonOut_b_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_b_bits_opcode = anonOut_b_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_b_bits_param = anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_b_bits_size = anonOut_b_bits_size; // @[Xbar.scala:216:19] wire [1:0] out_0_b_bits_source = anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] out_0_b_bits_address = anonOut_b_bits_address; // @[Xbar.scala:216:19] wire [7:0] out_0_b_bits_mask = anonOut_b_bits_mask; // @[Xbar.scala:216:19] wire [63:0] out_0_b_bits_data = anonOut_b_bits_data; // @[Xbar.scala:216:19] wire out_0_b_bits_corrupt = anonOut_b_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_c_ready = anonOut_c_ready; // @[Xbar.scala:216:19] wire out_0_c_valid; // @[Xbar.scala:216:19] assign auto_anon_out_c_valid_0 = anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_opcode_0 = anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_c_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_param_0 = anonOut_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] out_0_c_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_size_0 = anonOut_c_bits_size; // @[Xbar.scala:74:9] wire [1:0] out_0_c_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_source_0 = anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_c_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_address_0 = anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] out_0_c_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_c_bits_data_0 = anonOut_c_bits_data; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [1:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_0_e_ready = anonOut_e_ready; // @[Xbar.scala:216:19] wire out_0_e_valid; // @[Xbar.scala:216:19] assign auto_anon_out_e_valid_0 = anonOut_e_valid; // @[Xbar.scala:74:9] wire [2:0] _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign auto_anon_out_e_bits_sink_0 = anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [1:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_ready = in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_b_valid = in_0_b_valid; // @[Xbar.scala:159:18] wire [2:0] portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_b_bits_opcode = in_0_b_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_b_bits_param = in_0_b_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_b_bits_size = in_0_b_bits_size; // @[Xbar.scala:159:18] wire [1:0] portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [31:0] portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign anonIn_b_bits_address = in_0_b_bits_address; // @[Xbar.scala:159:18] wire [7:0] portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24] assign anonIn_b_bits_mask = in_0_b_bits_mask; // @[Xbar.scala:159:18] wire [63:0] portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_b_bits_data = in_0_b_bits_data; // @[Xbar.scala:159:18] wire portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_b_bits_corrupt = in_0_b_bits_corrupt; // @[Xbar.scala:159:18] wire portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_c_ready = in_0_c_ready; // @[Xbar.scala:159:18] wire _portsCOI_filtered_0_valid_T_1 = in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] portsCOI_filtered_0_bits_opcode = in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsCOI_filtered_0_bits_param = in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] portsCOI_filtered_0_bits_size = in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [1:0] portsCOI_filtered_0_bits_source = in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestCIO_T = in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsCOI_filtered_0_bits_address = in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsCOI_filtered_0_bits_data = in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] wire [2:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire portsEOI_filtered_0_ready; // @[Xbar.scala:352:24] assign anonIn_e_ready = in_0_e_ready; // @[Xbar.scala:159:18] wire _portsEOI_filtered_0_valid_T_1 = in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] _requestEIO_uncommonBits_T = in_0_e_bits_sink; // @[Xbar.scala:159:18] wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24] wire [2:0] portsEOI_filtered_0_bits_sink = in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18] wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40] wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24] assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18] wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18] wire [1:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24] wire [2:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18] wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24] assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18] wire [1:0] in_0_b_bits_source; // @[Xbar.scala:159:18] wire [1:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [1:0] in_1_d_bits_source; // @[Xbar.scala:159:18] assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}] assign _anonIn_b_bits_source_T = in_0_b_bits_source[0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_b_bits_source = _anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign in_0_c_bits_source = {1'h0, _in_0_c_bits_source_T}; // @[Xbar.scala:159:18, :187:{29,55}] assign _anonIn_d_bits_source_T = in_0_d_bits_source[0]; // @[Xbar.scala:156:69, :159:18] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] wire [1:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] wire _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_b_ready = out_0_b_ready; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsBIO_filtered_1_bits_opcode = out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsBIO_filtered_1_bits_param = out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [3:0] portsBIO_filtered_1_bits_size = out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire [1:0] _requestBOI_uncommonBits_T = out_0_b_bits_source; // @[Xbar.scala:216:19] assign portsBIO_filtered_0_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsBIO_filtered_1_bits_source = out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] wire [31:0] portsBIO_filtered_1_bits_address = out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] wire [7:0] portsBIO_filtered_1_bits_mask = out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsBIO_filtered_1_bits_data = out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsBIO_filtered_0_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsBIO_filtered_1_bits_corrupt = out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_ready = out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_c_valid = out_0_c_valid; // @[Xbar.scala:216:19] assign anonOut_c_bits_opcode = out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_c_bits_param = out_0_c_bits_param; // @[Xbar.scala:216:19] assign anonOut_c_bits_size = out_0_c_bits_size; // @[Xbar.scala:216:19] assign anonOut_c_bits_source = out_0_c_bits_source; // @[Xbar.scala:216:19] assign anonOut_c_bits_address = out_0_c_bits_address; // @[Xbar.scala:216:19] assign anonOut_c_bits_data = out_0_c_bits_data; // @[Xbar.scala:216:19] wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [1:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_ready = out_0_e_ready; // @[Xbar.scala:216:19, :352:24] wire portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_e_valid = out_0_e_valid; // @[Xbar.scala:216:19] assign _anonOut_e_bits_sink_T = out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign anonOut_e_bits_sink = _anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestCIO_T_1 = {1'h0, _requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire requestBOI_uncommonBits = _requestBOI_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire _requestBOI_T = out_0_b_bits_source[1]; // @[Xbar.scala:216:19] wire _requestBOI_T_1 = ~_requestBOI_T; // @[Parameters.scala:54:{10,32}] wire _requestBOI_T_3 = _requestBOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestBOI_0_0 = _requestBOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsBIO_filtered_0_valid_T = requestBOI_0_0; // @[Xbar.scala:355:54] wire requestBOI_0_1 = out_0_b_bits_source == 2'h2; // @[Xbar.scala:216:19] wire _portsBIO_filtered_1_valid_T = requestBOI_0_1; // @[Xbar.scala:355:54] wire requestDOI_uncommonBits = _requestDOI_uncommonBits_T[0]; // @[Parameters.scala:52:{29,56}] wire _requestDOI_T = out_0_d_bits_source[1]; // @[Xbar.scala:216:19] wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}] wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}] wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48] wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54] wire requestDOI_0_1 = out_0_d_bits_source == 2'h2; // @[Xbar.scala:216:19] wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54] wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1; // @[Mux.scala:30:73] wire [2:0] requestEIO_uncommonBits = _requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] _beatsBO_decode_T = 27'hFFF << out_0_b_bits_size; // @[package.scala:243:71] wire [11:0] _beatsBO_decode_T_1 = _beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsBO_decode_T_2 = ~_beatsBO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsBO_decode = _beatsBO_decode_T_2[11:3]; // @[package.scala:243:46] wire _beatsBO_opdata_T = out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19] wire beatsBO_opdata = ~_beatsBO_opdata_T; // @[Edges.scala:97:{28,37}] wire [26:0] _beatsCI_decode_T = 27'hFFF << in_0_c_bits_size; // @[package.scala:243:71] wire [11:0] _beatsCI_decode_T_1 = _beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsCI_decode_T_2 = ~_beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsCI_decode = _beatsCI_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsCI_opdata = in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [8:0] beatsCI_0 = beatsCI_opdata ? beatsCI_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_b_valid = portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_opcode = portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_param = portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_size = portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_source = portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_address = portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_mask = portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_data = portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_b_bits_corrupt = portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] wire portsBIO_filtered_1_valid; // @[Xbar.scala:352:24] assign _portsBIO_filtered_0_valid_T_1 = out_0_b_valid & _portsBIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_0_valid = _portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsBIO_filtered_1_valid_T_1 = out_0_b_valid & _portsBIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsBIO_filtered_1_valid = _portsBIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsBIO_out_0_b_ready_T = requestBOI_0_0 & portsBIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsBIO_out_0_b_ready_T_2 = _portsBIO_out_0_b_ready_T; // @[Mux.scala:30:73] assign _portsBIO_out_0_b_ready_WIRE = _portsBIO_out_0_b_ready_T_2; // @[Mux.scala:30:73] assign out_0_b_ready = _portsBIO_out_0_b_ready_WIRE; // @[Mux.scala:30:73] assign in_0_c_ready = portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_c_valid = portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_opcode = portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_param = portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_size = portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_source = portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_address = portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_c_bits_data = portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign portsCOI_filtered_0_valid = _portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24] assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}] assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73] wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T \| _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73] assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73] assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73] assign in_0_e_ready = portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign out_0_e_valid = portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_e_bits_sink = portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign portsEOI_filtered_0_valid = _portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19] wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _out_0_a_valid_T = portsAOI_filtered_0_valid \| portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_67 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_134 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_67 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<2>(0h3), io.in.bits.egress_id) node _T_1 = eq(_T, UInt<1>(0h0)) node _T_2 = and(io.in.valid, _T_1) node _T_3 = eq(_T_2, UInt<1>(0h0)) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<2>(0h3) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<2>(0h3), io.in.bits.egress_id) connect route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h2) node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<2>(0h3), io.in.bits.egress_id) connect route_buffer.io.enq.bits.flow.egress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h3)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_7 = and(io.in.ready, io.in.valid) node _T_8 = and(_T_7, io.in.bits.head) node _T_9 = and(_T_8, at_dest) when _T_9 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_10 = eq(UInt<4>(0hb), io.in.bits.egress_id) when _T_10 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_11 = eq(UInt<4>(0hc), io.in.bits.egress_id) when _T_11 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_12 = eq(UInt<4>(0hd), io.in.bits.egress_id) when _T_12 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_13 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_14 = and(route_q.io.enq.valid, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_135 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_67 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_19 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_20 = and(vcalloc_q.io.enq.valid, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_21, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_1 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_2 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_1 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_15 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_16 = or(_out_bundle_bits_out_virt_channel_T_15, _out_bundle_bits_out_virt_channel_T_13) node _out_bundle_bits_out_virt_channel_T_17 = or(_out_bundle_bits_out_virt_channel_T_16, _out_bundle_bits_out_virt_channel_T_14) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_17 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_67( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [2:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire io_router_req_valid = io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head; // @[IngressUnit.scala:26:28, :58:{38,67}] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module Tile_23 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_279 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_23( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_279 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_106 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_362 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_106( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_362 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_42 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1) node _T_51 = and(io.wakeup_ports[3].valid, _T_50) when _T_51 : connect p1, UInt<1>(0h1) node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2) node _T_53 = and(io.wakeup_ports[3].valid, _T_52) when _T_53 : connect p2, UInt<1>(0h1) node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3) node _T_55 = and(io.wakeup_ports[3].valid, _T_54) when _T_55 : connect p3, UInt<1>(0h1) node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1) node _T_57 = and(io.wakeup_ports[4].valid, _T_56) when _T_57 : connect p1, UInt<1>(0h1) node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2) node _T_59 = and(io.wakeup_ports[4].valid, _T_58) when _T_59 : connect p2, UInt<1>(0h1) node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3) node _T_61 = and(io.wakeup_ports[4].valid, _T_60) when _T_61 : connect p3, UInt<1>(0h1) node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1) node _T_63 = and(io.wakeup_ports[5].valid, _T_62) when _T_63 : connect p1, UInt<1>(0h1) node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2) node _T_65 = and(io.wakeup_ports[5].valid, _T_64) when _T_65 : connect p2, UInt<1>(0h1) node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3) node _T_67 = and(io.wakeup_ports[5].valid, _T_66) when _T_67 : connect p3, UInt<1>(0h1) node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1) node _T_69 = and(io.wakeup_ports[6].valid, _T_68) when _T_69 : connect p1, UInt<1>(0h1) node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2) node _T_71 = and(io.wakeup_ports[6].valid, _T_70) when _T_71 : connect p2, UInt<1>(0h1) node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3) node _T_73 = and(io.wakeup_ports[6].valid, _T_72) when _T_73 : connect p3, UInt<1>(0h1) node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_75 = and(io.pred_wakeup_port.valid, _T_74) when _T_75 : connect ppred, UInt<1>(0h1) node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3 node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82) node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_85 = and(_T_83, _T_84) when _T_85 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_86, UInt<1>(0h1), "") : assert_4 node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90) node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_93 = and(_T_91, _T_92) when _T_93 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_94, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_99 = neq(_T_98, UInt<1>(0h0)) when _T_99 : connect next_state, UInt<2>(0h0) node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_100 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_101 = eq(state, UInt<2>(0h1)) when _T_101 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_102 = eq(state, UInt<2>(0h2)) when _T_102 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_103 = eq(state, UInt<2>(0h2)) when _T_103 : node _T_104 = and(p1, p2) node _T_105 = and(_T_104, ppred) when _T_105 : skip else : node _T_106 = and(p1, ppred) when _T_106 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_107 = and(p2, ppred) when _T_107 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_42( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned \| p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 \| ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 \| ~_GEN \| p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i64_e11_s53_5 : output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 63, 63) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32) node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33) node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34) node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35) node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36) node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37) node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38) node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39) node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40) node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41) node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42) node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43) node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44) node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45) node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46) node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47) node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48) node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49) node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50) node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51) node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52) node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53) node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54) node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55) node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56) node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57) node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58) node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59) node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60) node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61) node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62) node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63) node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f)) node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64) node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65) node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66) node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67) node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68) node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69) node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70) node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71) node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72) node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73) node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74) node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75) node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76) node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77) node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78) node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79) node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80) node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81) node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82) node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83) node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84) node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85) node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86) node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87) node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88) node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89) node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90) node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91) node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92) node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93) node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94) node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95) node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96) node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97) node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98) node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99) node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100) node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101) node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102) node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103) node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104) node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105) node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106) node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107) node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108) node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109) node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110) node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111) node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112) node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113) node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114) node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115) node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116) node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117) node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118) node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119) node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120) node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121) node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122) node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123) node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_5 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i64_e11_s53_5( // @[INToRecFN.scala:43:7] input io_signedIn, // @[INToRecFN.scala:46:16] input [63:0] io_in, // @[INToRecFN.scala:46:16] input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16] output [64:0] io_out, // @[INToRecFN.scala:46:16] output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16] ); wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7] wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [64:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31] wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53] wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70] wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70] wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_5 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_156 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_272 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_156( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_272 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Router_31 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_74 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn.flit.bits.egress_id invalidate ingressNodesIn.flit.bits.payload invalidate ingressNodesIn.flit.bits.tail invalidate ingressNodesIn.flit.bits.head invalidate ingressNodesIn.flit.valid invalidate ingressNodesIn.flit.ready wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} invalidate ingressNodesIn_1.flit.bits.egress_id invalidate ingressNodesIn_1.flit.bits.payload invalidate ingressNodesIn_1.flit.bits.tail invalidate ingressNodesIn_1.flit.bits.head invalidate ingressNodesIn_1.flit.valid invalidate ingressNodesIn_1.flit.ready wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut.flit.bits.ingress_id invalidate egressNodesOut.flit.bits.payload invalidate egressNodesOut.flit.bits.tail invalidate egressNodesOut.flit.bits.head invalidate egressNodesOut.flit.valid invalidate egressNodesOut.flit.ready wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut_1.flit.bits.ingress_id invalidate egressNodesOut_1.flit.bits.payload invalidate egressNodesOut_1.flit.bits.tail invalidate egressNodesOut_1.flit.bits.head invalidate egressNodesOut_1.flit.valid invalidate egressNodesOut_1.flit.ready wire egressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} invalidate egressNodesOut_2.flit.bits.ingress_id invalidate egressNodesOut_2.flit.bits.payload invalidate egressNodesOut_2.flit.bits.tail invalidate egressNodesOut_2.flit.bits.head invalidate egressNodesOut_2.flit.valid invalidate egressNodesOut_2.flit.ready wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] connect destNodesIn, auto.dest_nodes_in connect auto.source_nodes_out, sourceNodesOut connect ingressNodesIn, auto.ingress_nodes_in_0 connect ingressNodesIn_1, auto.ingress_nodes_in_1 connect auto.egress_nodes_out_0, egressNodesOut connect auto.egress_nodes_out_1, egressNodesOut_1 connect auto.egress_nodes_out_2, egressNodesOut_2 connect auto.debug_out, debugNodeOut inst input_unit_0_from_11 of InputUnit_74 connect input_unit_0_from_11.clock, clock connect input_unit_0_from_11.reset, reset inst ingress_unit_1_from_5 of IngressUnit_42 connect ingress_unit_1_from_5.clock, clock connect ingress_unit_1_from_5.reset, reset inst ingress_unit_2_from_6 of IngressUnit_43 connect ingress_unit_2_from_6.clock, clock connect ingress_unit_2_from_6.reset, reset inst output_unit_0_to_11 of OutputUnit_74 connect output_unit_0_to_11.clock, clock connect output_unit_0_to_11.reset, reset inst egress_unit_1_to_5 of EgressUnit_38 connect egress_unit_1_to_5.clock, clock connect egress_unit_1_to_5.reset, reset inst egress_unit_2_to_6 of EgressUnit_39 connect egress_unit_2_to_6.clock, clock connect egress_unit_2_to_6.reset, reset inst egress_unit_3_to_7 of EgressUnit_40 connect egress_unit_3_to_7.clock, clock connect egress_unit_3_to_7.reset, reset inst switch of Switch_31 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_31 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_31 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_31 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2) node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0) node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4) node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) wire fires_count : UInt connect fires_count, _fires_count_T_6 connect input_unit_0_from_11.io.in, destNodesIn connect ingress_unit_1_from_5.io.in, ingressNodesIn.flit connect ingress_unit_2_from_6.io.in, ingressNodesIn_1.flit connect output_unit_0_to_11.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_11.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_11.io.out.flit connect egressNodesOut.flit.bits, egress_unit_1_to_5.io.out.bits connect egressNodesOut.flit.valid, egress_unit_1_to_5.io.out.valid connect egress_unit_1_to_5.io.out.ready, egressNodesOut.flit.ready connect egressNodesOut_1.flit.bits, egress_unit_2_to_6.io.out.bits connect egressNodesOut_1.flit.valid, egress_unit_2_to_6.io.out.valid connect egress_unit_2_to_6.io.out.ready, egressNodesOut_1.flit.ready connect egressNodesOut_2.flit.bits, egress_unit_3_to_7.io.out.bits connect egressNodesOut_2.flit.valid, egress_unit_3_to_7.io.out.valid connect egress_unit_3_to_7.io.out.ready, egressNodesOut_2.flit.ready connect route_computer.io.req.`0`, input_unit_0_from_11.io.router_req connect route_computer.io.req.`1`, ingress_unit_1_from_5.io.router_req connect route_computer.io.req.`2`, ingress_unit_2_from_6.io.router_req connect input_unit_0_from_11.io.router_resp, route_computer.io.resp.`0` connect ingress_unit_1_from_5.io.router_resp, route_computer.io.resp.`1` connect ingress_unit_2_from_6.io.router_resp, route_computer.io.resp.`2` connect vc_allocator.io.req.`0`, input_unit_0_from_11.io.vcalloc_req connect vc_allocator.io.req.`1`, ingress_unit_1_from_5.io.vcalloc_req connect vc_allocator.io.req.`2`, ingress_unit_2_from_6.io.vcalloc_req connect input_unit_0_from_11.io.vcalloc_resp, vc_allocator.io.resp.`0` connect ingress_unit_1_from_5.io.vcalloc_resp, vc_allocator.io.resp.`1` connect ingress_unit_2_from_6.io.vcalloc_resp, vc_allocator.io.resp.`2` connect output_unit_0_to_11.io.allocs, vc_allocator.io.out_allocs.`0` connect egress_unit_1_to_5.io.allocs, vc_allocator.io.out_allocs.`1` connect egress_unit_2_to_6.io.allocs, vc_allocator.io.out_allocs.`2` connect egress_unit_3_to_7.io.allocs, vc_allocator.io.out_allocs.`3` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_11.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_11.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_11.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_11.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_11.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_11.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_11.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_11.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_11.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_11.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_11.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_11.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_11.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_11.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_11.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_11.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_11.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_11.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_11.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_11.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_11.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_11.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_11.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_11.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_11.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_11.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_5.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_5.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_5.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_5.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_5.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_5.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_6.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_6.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_6.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_6.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_6.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_6.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_7.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_7.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_7.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_7.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_7.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_7.io.channel_status[0].occupied connect input_unit_0_from_11.io.out_credit_available.`0`[0], output_unit_0_to_11.io.credit_available[0] connect input_unit_0_from_11.io.out_credit_available.`0`[1], output_unit_0_to_11.io.credit_available[1] connect input_unit_0_from_11.io.out_credit_available.`0`[2], output_unit_0_to_11.io.credit_available[2] connect input_unit_0_from_11.io.out_credit_available.`0`[3], output_unit_0_to_11.io.credit_available[3] connect input_unit_0_from_11.io.out_credit_available.`0`[4], output_unit_0_to_11.io.credit_available[4] connect input_unit_0_from_11.io.out_credit_available.`1`[0], egress_unit_1_to_5.io.credit_available[0] connect input_unit_0_from_11.io.out_credit_available.`2`[0], egress_unit_2_to_6.io.credit_available[0] connect input_unit_0_from_11.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect ingress_unit_1_from_5.io.out_credit_available.`0`[0], output_unit_0_to_11.io.credit_available[0] connect ingress_unit_1_from_5.io.out_credit_available.`0`[1], output_unit_0_to_11.io.credit_available[1] connect ingress_unit_1_from_5.io.out_credit_available.`0`[2], output_unit_0_to_11.io.credit_available[2] connect ingress_unit_1_from_5.io.out_credit_available.`0`[3], output_unit_0_to_11.io.credit_available[3] connect ingress_unit_1_from_5.io.out_credit_available.`0`[4], output_unit_0_to_11.io.credit_available[4] connect ingress_unit_1_from_5.io.out_credit_available.`1`[0], egress_unit_1_to_5.io.credit_available[0] connect ingress_unit_1_from_5.io.out_credit_available.`2`[0], egress_unit_2_to_6.io.credit_available[0] connect ingress_unit_1_from_5.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect ingress_unit_2_from_6.io.out_credit_available.`0`[0], output_unit_0_to_11.io.credit_available[0] connect ingress_unit_2_from_6.io.out_credit_available.`0`[1], output_unit_0_to_11.io.credit_available[1] connect ingress_unit_2_from_6.io.out_credit_available.`0`[2], output_unit_0_to_11.io.credit_available[2] connect ingress_unit_2_from_6.io.out_credit_available.`0`[3], output_unit_0_to_11.io.credit_available[3] connect ingress_unit_2_from_6.io.out_credit_available.`0`[4], output_unit_0_to_11.io.credit_available[4] connect ingress_unit_2_from_6.io.out_credit_available.`1`[0], egress_unit_1_to_5.io.credit_available[0] connect ingress_unit_2_from_6.io.out_credit_available.`2`[0], egress_unit_2_to_6.io.credit_available[0] connect ingress_unit_2_from_6.io.out_credit_available.`3`[0], egress_unit_3_to_7.io.credit_available[0] connect switch_allocator.io.req.`0`[0], input_unit_0_from_11.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_5.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_6.io.salloc_req[0] connect output_unit_0_to_11.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_11.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_11.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_11.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_11.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_11.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_11.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_11.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_11.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_11.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect egress_unit_1_to_5.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect egress_unit_1_to_5.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect egress_unit_2_to_6.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect egress_unit_2_to_6.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect egress_unit_3_to_7.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail connect egress_unit_3_to_7.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc connect switch.io.in.`0`[0], input_unit_0_from_11.io.out[0] connect switch.io.in.`1`[0], ingress_unit_1_from_5.io.out[0] connect switch.io.in.`2`[0], ingress_unit_2_from_6.io.out[0] connect output_unit_0_to_11.io.in, switch.io.out.`0` connect egress_unit_1_to_5.io.in, switch.io.out.`1` connect egress_unit_2_to_6.io.in, switch.io.out.`2` connect egress_unit_3_to_7.io.in, switch.io.out.`3` reg REG : { `3` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect switch.io.sel.`3`[0].`0`[0], REG.`3`[0].`0`[0] connect switch.io.sel.`3`[0].`1`[0], REG.`3`[0].`1`[0] connect switch.io.sel.`3`[0].`2`[0], REG.`3`[0].`2`[0] connect input_unit_0_from_11.io.block, UInt<1>(0h0) connect ingress_unit_1_from_5.io.block, UInt<1>(0h0) connect ingress_unit_2_from_6.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_11.io.debug.va_stall connect debugNodeOut.va_stall[1], ingress_unit_1_from_5.io.debug.va_stall connect debugNodeOut.va_stall[2], ingress_unit_2_from_6.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_11.io.debug.sa_stall connect debugNodeOut.sa_stall[1], ingress_unit_1_from_5.io.debug.sa_stall connect debugNodeOut.sa_stall[2], ingress_unit_2_from_6.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_79 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 11 2 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, _T_11) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, _T_11) connect fired_1, _fired_T_1 node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_14 = tail(_T_13, 1) node _T_15 = eq(debug_sample, _T_14) node _T_16 = and(_T_12, _T_15) node _T_17 = and(_T_16, fired_1) when _T_17 : node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "nocsample %d i5 2 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, _T_11 node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, _T_20) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, _T_20) connect fired_2, _fired_T_2 node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_23 = tail(_T_22, 1) node _T_24 = eq(debug_sample, _T_23) node _T_25 = and(_T_21, _T_24) node _T_26 = and(_T_25, fired_2) when _T_26 : node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "nocsample %d i6 2 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, _T_20 node _T_29 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, _T_29) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, _T_29) connect fired_3, _fired_T_3 node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_32 = tail(_T_31, 1) node _T_33 = eq(debug_sample, _T_32) node _T_34 = and(_T_30, _T_33) node _T_35 = and(_T_34, fired_3) when _T_35 : node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "nocsample %d 2 e5 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, _T_29 node _T_38 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid) regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, _T_38) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, _T_38) connect fired_4, _fired_T_4 node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_41 = tail(_T_40, 1) node _T_42 = eq(debug_sample, _T_41) node _T_43 = and(_T_39, _T_42) node _T_44 = and(_T_43, fired_4) when _T_44 : node _T_45 = asUInt(reset) node _T_46 = eq(_T_45, UInt<1>(0h0)) when _T_46 : printf(clock, UInt<1>(0h1), "nocsample %d 2 e6 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, _T_38 node _T_47 = and(egressNodesOut_2.flit.ready, egressNodesOut_2.flit.valid) regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_10 = add(util_ctr_5, _T_47) node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) connect util_ctr_5, _util_ctr_T_11 node _fired_T_5 = or(fired_5, _T_47) connect fired_5, _fired_T_5 node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_50 = tail(_T_49, 1) node _T_51 = eq(debug_sample, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = and(_T_52, fired_5) when _T_53 : node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "nocsample %d 2 e7 %d\n", debug_tsc, util_ctr_5) : printf_5 connect fired_5, _T_47	module Router_31( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [4:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [4:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_3_to_7_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_3_to_7_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_3_to_7_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_2_to_6_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_2_to_6_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_2_to_6_io_out_valid; // @[Router.scala:125:13] wire _egress_unit_1_to_5_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_5_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_5_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_11_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_11_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _ingress_unit_2_from_6_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [72:0] _ingress_unit_2_from_6_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_6_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_6_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_6_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [4:0] _ingress_unit_2_from_6_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire [1:0] _ingress_unit_2_from_6_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [2:0] _ingress_unit_2_from_6_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_2_from_6_io_in_ready; // @[Router.scala:116:13] wire _input_unit_0_from_11_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_11_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_11_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_11_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_6_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_11_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_3_0_2_0; // @[Router.scala:178:14] reg REG_3_0_0_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (\|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_5; // @[Router.scala:203:29] reg fired_5; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_142 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_142( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_225 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_225( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_434 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_434( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1 : output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : { sync : UInt<1>[1]} invalidate nodeIn.sync[0] wire nodeOut : UInt<1>[1] invalidate nodeOut[0] connect auto.out, nodeOut connect nodeIn, auto.in connect nodeOut, nodeIn.sync	module IntSyncSyncCrossingSink_n1x1( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_25 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_25 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i1_e8_s24_25(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_25 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMasterToNoC_3 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}} inst a of TLAToNoC_3 connect a.clock, clock connect a.reset, reset inst b of TLBFromNoC_3 connect b.clock, clock connect b.reset, reset inst c of TLCToNoC_3 connect c.clock, clock connect c.reset, reset inst d of TLDFromNoC_3 connect d.clock, clock connect d.reset, reset inst e of TLEToNoC_3 connect e.clock, clock connect e.reset, reset connect a.io.protocol, io.tilelink.a connect io.tilelink.b.bits, b.io.protocol.bits connect io.tilelink.b.valid, b.io.protocol.valid connect b.io.protocol.ready, io.tilelink.b.ready connect c.io.protocol, io.tilelink.c connect io.tilelink.d.bits, d.io.protocol.bits connect io.tilelink.d.valid, d.io.protocol.valid connect d.io.protocol.ready, io.tilelink.d.ready connect e.io.protocol, io.tilelink.e connect io.flits.a.bits, a.io.flit.bits connect io.flits.a.valid, a.io.flit.valid connect a.io.flit.ready, io.flits.a.ready connect b.io.flit, io.flits.b connect io.flits.c.bits, c.io.flit.bits connect io.flits.c.valid, c.io.flit.valid connect c.io.flit.ready, io.flits.c.ready connect d.io.flit, io.flits.d connect io.flits.e.bits, e.io.flit.bits connect io.flits.e.valid, e.io.flit.valid connect e.io.flit.ready, io.flits.e.ready	module TLMasterToNoC_3( // @[Tilelink.scala:37:7] input clock, // @[Tilelink.scala:37:7] input reset, // @[Tilelink.scala:37:7] output io_tilelink_a_ready, // @[Tilelink.scala:44:14] input io_tilelink_a_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14] input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_b_ready, // @[Tilelink.scala:44:14] output io_tilelink_b_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_b_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_b_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:44:14] output [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:44:14] output [7:0] io_tilelink_b_bits_mask, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_b_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_b_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_c_ready, // @[Tilelink.scala:44:14] input io_tilelink_c_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_d_ready, // @[Tilelink.scala:44:14] output io_tilelink_d_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14] output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_e_ready, // @[Tilelink.scala:44:14] input io_tilelink_e_valid, // @[Tilelink.scala:44:14] input [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:44:14] input io_flits_a_ready, // @[Tilelink.scala:44:14] output io_flits_a_valid, // @[Tilelink.scala:44:14] output io_flits_a_bits_head, // @[Tilelink.scala:44:14] output io_flits_a_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_b_ready, // @[Tilelink.scala:44:14] input io_flits_b_valid, // @[Tilelink.scala:44:14] input io_flits_b_bits_head, // @[Tilelink.scala:44:14] input io_flits_b_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:44:14] input io_flits_c_ready, // @[Tilelink.scala:44:14] output io_flits_c_valid, // @[Tilelink.scala:44:14] output io_flits_c_bits_head, // @[Tilelink.scala:44:14] output io_flits_c_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_d_ready, // @[Tilelink.scala:44:14] input io_flits_d_valid, // @[Tilelink.scala:44:14] input io_flits_d_bits_head, // @[Tilelink.scala:44:14] input io_flits_d_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:44:14] input io_flits_e_ready, // @[Tilelink.scala:44:14] output io_flits_e_valid, // @[Tilelink.scala:44:14] output io_flits_e_bits_head, // @[Tilelink.scala:44:14] output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_e_bits_egress_id // @[Tilelink.scala:44:14] ); wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:58:17] wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:56:17] TLAToNoC_3 a ( // @[Tilelink.scala:54:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:54:17] TLBFromNoC_1 b ( // @[Tilelink.scala:55:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_opcode (io_tilelink_b_bits_opcode), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_size (io_tilelink_b_bits_size), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_protocol_bits_mask (io_tilelink_b_bits_mask), .io_protocol_bits_data (io_tilelink_b_bits_data), .io_protocol_bits_corrupt (io_tilelink_b_bits_corrupt), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload) ); // @[Tilelink.scala:55:17] TLCToNoC_3 c ( // @[Tilelink.scala:56:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:56:17] TLDFromNoC_1 d ( // @[Tilelink.scala:57:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14] ); // @[Tilelink.scala:57:17] TLEToNoC e ( // @[Tilelink.scala:58:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_e_ready), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_payload (_e_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_e_bits_egress_id) ); // @[Tilelink.scala:58:17] assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :56:17, :67:14] assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :58:17, :69:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_39 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_78 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_79 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v3/common/tile.scala:140:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_39( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] a_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] a_first_beats1_1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] a_first_count_1 = 9'h0; // @[Edges.scala:234:25] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [7:0] io_in_a_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_a_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [8:0] a_first_beats1_decode = 9'h7; // @[Edges.scala:220:59] wire [8:0] a_first_beats1_decode_1 = 9'h7; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T = a_first ? 9'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] _a_first_counter_T_1 = a_first_1 ? 9'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_78 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_78 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_78( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_78 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_36 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T	module MulAddRecFNToRaw_preMul_e8_s24_36( // @[MulAddRecFN.scala:71:7] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25] wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49] wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T \| _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign \| _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = \|_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = \|_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = \|_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = \|_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = \|_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = \|_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = \|_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = \|_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = \|_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 \| reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 \| _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule

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